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1. general description the SSTUM32865 is a 1.8 v 28-bit 1 : 2 register speci?cally designed for use on two rank by four (2r 4) and similar high-density double data rate 2 (ddr2) memory modules. it is similar in function to the jedec-standard 14-bit ddr2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density dual in-line memory module (dimm) designs. the SSTUM32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the d-inputs and indicates whether a parity error has occurred on its open-drain ptyerr pin (active low). it further offers added features over the jedec standard register in that it is permanently con?gured for high output drive strength. this allows use in high density designs with heavier than normal net loading conditions. furthermore, the SSTUM32865 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. both added features (drive strength and chip selects) are fully backward compatible to the jedec standard register. the SSTUM32865 is packaged in a 160-ball, 12 18 grid, 0.65 mm ball pitch, thin pro?le ?ne-pitch ball grid array (tfbga) package, which, while requiring a minimum 9mm 13 mm of board space, allows for adequate signal routing and escape using conventional card technology. 2. features n 28-bit data register supporting ddr2 n fully compliant to jedec standard for sstub32865 n supports 2 rank by 4 dimm density by integrating equivalent functionality of two jedec-standard ddr2 registers (that is, 2 sstub32864 or 2 sstub32866) n parity checking function across 22 input data bits n parity out signal n controlled multi-impedance output impedance drivers enable optimal signal integrity and speed n meets or exceeds sstub32865 jedec standard speed performance n supports up to 450 mhz clock frequency of operation n permanently con?gured for high output drive n optimized pinout for high-density ddr2 module design n chip-selects minimize power consumption by gating data outputs from changing state n two additional chip select inputs allow optional ?exible enabling and disabling SSTUM32865 1.8 v 28-bit 1 : 2 registered buffer with parity for ddr2-800 rdimm applications rev. 01 19 september 2007 product data sheet
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 2 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity n supports stub series terminated logic sstl_18 data inputs n differential clock (ck and ck) inputs n supports lvcmos switching levels on the control and reset inputs n single 1.8 v supply operation (1.7 v to 2.0 v) n available in 160-ball 9 mm 13 mm, 0.65 mm ball pitch tfbga package 3. applications n 400 mt/s to 800 mt/s high-density (for example, 2 rank by 4) ddr2 registered dimms n ddr2 registered dimms (rdimm) desiring parity checking functionality 4. ordering information 4.1 ordering options table 1. ordering information type number solder process package name description version SSTUM32865et/g pb-free (snagcu solder ball compound) tfbga160 plastic thin ?ne-pitch ball grid array package; 160 balls; body 9 13 0.7 mm sot802-2 SSTUM32865et/s pb-free (snagcu solder ball compound) tfbga160 plastic thin ?ne-pitch ball grid array package; 160 balls; body 9 13 0.7 mm sot802-2 table 2. ordering options type number topside mark temperature range SSTUM32865et/g SSTUM32865et t amb = 0 c to +70 c SSTUM32865et/s SSTUM32865ets t amb = 0 c to +85 c
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 3 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 5. functional diagram fig 1. functional diagram of SSTUM32865 dq r dq r dq r dq r dq r dq r dq r parin d0 d21 vref (cs active) dcs0 dcs1 dcke0, dcke1 dodt0, dodt1 csgateen reset ck ck parity generator and checker q0a q0b q21a q21b qcs0a qcs0b qcs1a qcs1b qcke0a, qcke1a qcke0b, qcke1b qodt0a, qodt1a qodt0b, qodt1b ptyerr 002aac647 2 2 2 2 22 SSTUM32865 dcs2 dcs3
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 4 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 6. pinning information 6.1 pinning fig 2. pin con?guration for tfbga160 002aac648 transparent top view ball a1 index area v u t r p n l j m k h g f e d b c a 24681012 1357911 SSTUM32865et/g SSTUM32865et/s
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 5 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 160-ball, 12 18 grid; top view. an empty cell indicates no ball is populated at that grid point. n.c. denotes a no-connect (ball present but not connected to the die). mcl denotes a pin that must be connected low. mch denotes a pin that must be connected high. fig 3. ball mapping vref n.c. parin n.c. n.c. qcke1a 1 234 5 6 d1 d2 n.c. n.c. n.c. qcke1b a b d3 d4 c d6 d5 vddl gnd n.c. d d7 d8 vddl gnd vddl e d11 d9 vddl gnd f d18 d12 vddl gnd g csgateen d15 dcs2 gnd h ck dcs0 gnd gnd j ck dcs1 vddl k d14 gnd gnd l d0 d10 gnd gnd m d17 d16 vddl vddl n d19 d21 gnd vddl vddl p d13 d20 gnd vddl vddl r dodt1 dodt0 t 002aac650 qcke0a q21a q19a q18a q17b q17a 789101112 qcke0b q21b q19b q18b qodt0b qodt0a qodt1b qodt1a n.c. gnd gnd q20b q20a vddr gnd gnd q16b q16a vddr vddr q1b q1a vddr vddr q2b q2a gnd gnd q5b q5a vddr vddr qcs0b qcs0a gnd gnd qcs1b qcs1a vddr vddr q6b q6a gnd gnd q10b q10a vddr vddr q9b q9a vddr vddr gnd q11b q11a gnd gnd gnd q15b q15a q14b q14a dcke0 dcke1 mcl ptyerr mch q3b u vref mcl mcl n.c. mch q3a v q12b q7b q4b q13b q0b q8b q12a q7a q4a q13a q0a q8a reset dcs3
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 6 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 6.2 pin description table 3. pin description symbol pin type description ungated inputs dcke0, dcke1 u1, u2 sstl_18 dram function pins not associated with chip select. dodt0, dodt1 t2, t1 chip select gated inputs d0 to d21 m1, b1, b2, c1, c2, d2, d1, e1, e2, f2, m2, f1, g2, r1, l2, h2, n2, n1, g1, p1, r2, p2 sstl_18 dram inputs, re-driven only when chip select is low. chip select inputs dcs0, dcs1, dcs2, dcs3 [1] j2, k2, h4, k4 sstl_18 dram chip select signals. these pins initiate dram address/command decodes, and as such at least one will be low when a valid address/command is present. the register can be programmed to re-drive all d-inputs only (csgateen = high) when at least one chip select input is low. dcs2 and dcs3 are not re-driven and can be left open-circuit to default high by means of its internal pull-up resistors. re-driven outputs q0a to q21a v11, f12, g12, v6, v9, h12, l12, v8, v12, n12, m12, p12, v7, v10, t12, r12, e12, a12, a10, a9, d12, a8 sstl_18 outputs of the register, valid after the speci?ed clock count and immediately following a rising edge of the clock. q0b to q21b u11, f11, g11, u6, u9, h11, l11, u8, u12, n11, m11, p11, u7, u10, t11, r11, e11, a11, b10, b9, d11, b8 qcs0a, qds1a, qcs0b, qcs1b j12, k12, j11, k11 qcke0a, qcke1a, qcke0b, qcke1b a7, a6, b7, b6 qodt0a, qodt1a, qodt0b, qodt1b b12, c12, b11, c11 parity input parin a3 sstl_18 parity input for the d0 to d21 inputs. arrives one clock cycle after the corresponding data input. parity error ptyerr u4 open-drain when low, this output indicates that a parity error was identi?ed associated with the address and/or command inputs. ptyerr will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with ?nal parity out timing on the industry-standard ddr2 register with parity (in jedec de?nition).
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 7 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity [1] if application does not require dcs2 and dcs3, it is allowed to connect h4 and k4 to v dd . program inputs csgateen h1 1.8 v lvcmos with weak pull-up chip select gate enable. when high, the d0 to d21 inputs will be latched only when at least one chip select input is low during the rising edge of the clock. when low, the d0 to d21 inputs will be latched and redriven on every rising edge of the clock. clock inputs ck, ck j1, k1 sstl_18 differential master clock input pair to the register. the register operation is triggered by a rising edge on the positive clock input (ck). miscellaneous inputs mcl u3, v2, v3 must be connected to a logic low. mch u5, v5 must be connected to a logic high. reset l1 1.8 v lvcmos with weak pull-up asynchronous reset input. when low, it causes a reset of the internal latches, thereby forcing the outputs low. reset also resets the ptyerr signal. vref a1, v1 0.9 v nominal input reference voltage for the sstl_18 inputs. two pins (internally tied together) are used for increased reliability. vddl d4, e4, e6, f4, g4, k5, n4, n5, p5, p6, r5, r6 power supply voltage. vddr e7, f8, f9, g8, g9, j8, j9, l8, l9, n8, n9, p7, p8 power supply voltage. gnd d5, d8, d9, e5, e8, e9, f5, g5, h5, h8, h9, j4, j5, k8, k9, l4, l5, m4, m5, m8, m9, p4, p9, r4, r7, r8, r9 ground. n.c. a2, a4, a5, b3, b4, b5, d6, d7, v4 ball present but not connected to die. table 3. pin description continued symbol pin type description
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 8 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 7. functional description 7.1 function table [1] q 0 is the previous state of the associated output. [2] dcs2 and dcs3 operate identically to dcs0 and dcs1, except they do not have corresponding re-driven (qcs) outputs. table 4. function table (each ?ip-?op) inputs outputs [1] reset dcs0 [2] dcs1 [2] csgateen ck ck dn, dodtn, dcken qn qcs0 qcs1 qodtn, qcken hll x - lllll hll x - hhllh h l l x l or h l or h x q 0 q 0 q 0 q 0 hlh x - lllhl hlh x - hhlhh h l h x l or h l or h x q 0 q 0 q 0 q 0 hhl x - llhll hhl x - hhhlh h h l x l or h l or h x q 0 q 0 q 0 q 0 hhh l - llhhl hhh l - hhhhh h h h l l or h l or h x q 0 q 0 q 0 q 0 hhh h - lq 0 hh l hhh h - hq 0 hh h h h h h l or h l or h x q 0 q 0 q 0 q 0 l x or ?oating x or ?oating x or ?oating x or ?oating x or ?oating x or ?oating l l l l table 5. parity and standby function table inputs output reset dcs0 [1] dcs1 [1] ck ck ? of inputs = h (d0 to d21) parin [2] ptyerr [3] [4] hl h - even l h hl h - odd l l hl h - even h l hl h - odd h h hh l - even l h hh l - odd l l hh l - even h l hh l - odd h h hh h - xx ptyerr 0 h x x l or h l or h x x ptyerr 0 l x or ?oating x or ?oating x or ?oating x or ?oating x or ?oating x or ?oating h
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 9 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity [1] dcs2 and dcs3 operate identically to dcs0 and dcs1 with regard to the parity function. [2] parin arrives one clock cycle after the data to which it applies. all dn inputs must be driven to a known state for parity to be calculated correctly. [3] this condition assumes ptyerr is high at the crossing of ck going high and ck going low. if ptyerr is low, it stays latched low for two clock cycles or until reset is driven low. csgateen is dont care for ptyerr. [4] ptyerr 0 is the previous state of output ptyerr. 7.2 functional information this 28-bit 1 : 2 registered buffer with parity is designed for 1.7 v to 2.0 v v dd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8 v cmos drivers that have been optimized to drive the ddr2 dimm load. the SSTUM32865 operates from a differential clock (ck and ck). data are registered at the crossing of ck going high, and ck going low. the device supports low-power standby operation. when the reset input ( reset) is low, the differential input receivers are disabled, and undriven (?oating) data, clock and reference voltage (vref) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs except ptyerr are forced low. the lvcmos reset input must always be held at a valid logic high or low level. to ensure de?ned outputs from the register before a stable clock has been supplied, reset must be held in the low state during power-up. in the ddr2 rdimm application, reset is speci?ed to be completely asynchronous with respect to ck and ck. therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the data outputs will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of reset until the input receivers are fully enabled, the design of the SSTUM32865 ensures that the outputs remain low, thus ensuring no glitches on the output. the device monitors dcs0, dcs1, dcs2 and dcs3 inputs and will gate the qn outputs from changing states when all dcsn inputs are high. if dcsn input is low, the qn outputs will function normally. the reset input has priority over the dcsn control and will force the qn outputs low and the ptyerr output high. if the dcsn-control functionality is not desired, then the csgateen input can be hardwired to ground, in which case, the set-up time requirement for dcsn would be the same as for the other dn data inputs. the SSTUM32865 includes a parity checking function. the SSTUM32865 accepts a parity bit from the memory controller at its input pin parin, compares it with the data received on the dn inputs (with either dcsn inputs active) and indicates whether a parity error has occurred on its open-drain ptyerr pin (active low).
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 10 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 7.3 functional differences to sstu32864 the SSTUM32865 for its basic register functionality, signal de?nition and performance is based upon the industry-standard sstu32864, but provides key operational features which differ (at least in part) from the industry-standard register in the following aspects: 7.3.1 chip select (cs) gating of key inputs ( dcs0, dcs1, dcs2, dcs3, csgateen) as a means to reduce device power, the internal latches will only be updated when one or more of the cs inputs are active (low) and csgateen high at the rising edge of the clock. the 22 chip-select-gated input signals associated with this function include addresses (addr0 to addr15, ba0 to ba2), and ras, cas, we, with the remaining signals (cs, cke, odt) continuously re-driven at the rising edge of every clock as they are independent of cs. the cs gating function can be disabled by tying csgateen low, enabling all internal latches to be updated on every rising edge of the clock. 7.3.2 parity error checking and reporting the SSTUM32865 incorporates a parity function, whereby the signal received on input pin parin is received as parity to the register, one clock cycle later than the cs-gated inputs. the received parity bit is then compared to the parity calculated across these same inputs by the register parity logic to verify that the information has not been corrupted. the 22 cs-gated input signals will be latched and re-driven on the ?rst clock, and any error will be reported one clock cycle later via the ptyerr output pin (driven low for two consecutive clock cycles). ptyerr is an open-drain output, allowing multiple modules to share a common signal pin for reporting the occurrence of a parity error during a valid command cycle (coincident with the re-driven signals). this output is driven low for two consecutive clock cycles to allow the memory controller suf?cient time to sense and capture the error even. a low state on ptyerr indicates that a parity error has occurred. 7.3.3 reset ( reset) similar to the reset pin on the industry-standard sstu32864, this pin is used to clear all internal latches and all outputs will be driven low quickly except the ptyerr output, which will be ?oated (and will normally default high by their external pull-up). 7.3.4 power-up sequence the reset function for the SSTUM32865 is similar to that of the sstu32864 except that the ptyerr signal is also cleared and will be held clear (high) for three consecutive clock cycles. table 6. chip select gating mode mode signal name description gating csgateen high registers only re-drive signals to the drams when chip select inputs are low. non-gating csgateen low registers always re-drive signals on every clock cycle, independent of the state of the chip select inputs.
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 11 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity (1) after reset is switched from low to high, all data and parin input signals must be set and held low for a minimum time of t act(max) to avoid false error. fig 4. reset switches from low to high ck dn (1) qn t su 002aaa983 ck m m + 1 m + 2 m + 3 m + 4 dcsn reset t act t h t pdm , t pdmss ck to q parin t su t h t phl , t plh ck to ptyerr t phl ck to ptyerr ptyerr high, low, or don't care high or low
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 12 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity fig 5. reset being held high ck dn (1) qn t su 002aaa984 ck mm + 1m + 2m + 3m + 4 dcsn reset t h t pdm , t pdmss ck to q parin t h t phl , t plh ck to ptyerr ptyerr output signal is dependent on the prior unknown event high or low unknown input event t su
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 13 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity (1) after reset is switched from high to low, all data and clock input signals must be set and held at valid logic levels (not ?oating) for a minimum time of t inact(max) . fig 6. reset switches from high to low ck (1) dcsn reset t inact t phl reset to q parin (1) t plh reset to ptyerr ptyerr high, low, or don't care high or low ck (1) dn (1) qn 002aac649
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 14 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity (1) this function holds the error for two cycles. for details, see section 7 functional descr iption and figure 4 reset s witches from lo w to high . fig 7. parity logic diagram d d d latching and reset function (1) ptyerr d qna qnb dn parin clock q 002aaa417 22 22
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 15 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 8. limiting values [1] the input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. [2] pins vddl or vddr. 9. recommended operating conditions [1] the differential inputs must not be ?oating, unless reset is low. [2] the reset input of the device must be held at valid logic levels (not ?oating) to ensure proper device operation. table 7. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +2.5 v v i input voltage receiver [1] - 0.5 +2.5 v v o output voltage driver [1] - 0.5 v dd + 0.5 v i ik input clamping current v i < 0 v or v i >v dd - - 50 ma i ok output clamping current v o < 0 v or v o >v dd - 50 ma i o output current continuous; 0 v < v o < v dd - 50 ma i ddc continuous current through each v dd [2] or gnd pin - 100 ma t stg storage temperature - 65 +150 c v esd electrostatic discharge voltage human body model (hbm); 1.5 k w ; 100 pf 2 - kv machine model (mm); 0 w ; 200 pf 150 - v table 8. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 1.7 - 2.0 v v ref reference voltage 0.49 v dd 0.50 v dd 0.51 v dd v v t termination voltage v ref - 0.040 v ref v ref + 0.040 v v i input voltage 0 - v dd v v ih(ac) ac high-level input voltage data inputs (dn) [1] v ref + 0.250 - - v v il(ac) ac low-level input voltage data inputs (dn) [1] --v ref - 0.250 v v ih(dc) dc high-level input voltage data inputs (dn) [1] v ref + 0.125 - - v v il(dc) dc low-level input voltage data inputs (dn) [1] --v ref - 0.125 v v ih high-level input voltage reset [2] 0.65 v dd -- v v il low-level input voltage reset [2] - - 0.35 v dd v v icr common mode input voltage range ck, ck 0.675 - 1.125 v v id differential input voltage ck, ck 600 - - mv i oh high-level output current - - - 8ma i ol low-level output current - - 8 ma t amb ambient temperature operating in free air SSTUM32865et/g 0 - +70 c SSTUM32865et/s 0 - +85 c
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 16 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 10. characteristics [1] instantaneous is de?ned as within < 2 ns following the output data transition edge. table 9. characteristics over recommended operating conditions, unless otherwise noted. symbol parameter conditions min typ max unit v oh high-level output voltage i oh = - 6 ma; v dd = 1.7 v 1.2 - - v v ol low-level output voltage i ol = 6 ma; v dd = 1.7 v - - 0.5 v i i input current all inputs; v i =v dd or gnd; v dd = 2.0 v -- 5 m a i dd supply current static standby current; reset = gnd; v dd = 2.0 v -- 2ma static operating current; reset = v dd ; v dd = 2.0 v; v i =v ih(ac) or v il(ac) - - 40 ma i ddd dynamic operating current per mhz clock only; reset = v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50 % duty cycle. i o = 0 ma; v dd = 1.8 v -16- m a per each data input; reset = v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50 % duty cycle. one data input switching at half clock frequency, 50 % duty cycle. i o = 0 ma; v dd = 1.8 v -19- m a c i input capacitance data inputs; v i =v ref 250 mv; v dd = 1.8 v 2.5 - 3.5 pf ck and ck; v icr = 0.9 v; v id = 600 mv; v dd = 1.8 v 2- 3pf reset; v i =v dd or gnd; v dd = 1.8 v 3- 5pf z o output impedance instantaneous [1] -7- w steady-state - 53 - w
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 17 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity [1] this parameter is not necessarily production tested. [2] data inputs must be active below a minimum time of t act(max) after reset is taken high. [3] data and clock inputs must be held at valid levels (not ?oating) a minimum time of t inact(max) after reset is taken low. [1] includes 350 ps of test-load transmission line delay. [2] this parameter is not necessarily production tested. table 10. timing requirements over recommended operating conditions, unless otherwise noted. symbol parameter conditions min typ max unit f clock clock frequency - - 450 mhz t w pulse width ck, ck high or low 1 - - ns t act differential inputs active time [1] [2] --10ns t inact differential inputs inactive time [1] [3] --15ns t su set-up time chip select; dcs0, dcs1 valid before clock switching 0.6 - - ns data; dn valid before clock switching 0.5 - - ns parin; parin before ck and ck 0.5 - - ns t h hold time input to remain valid after clock switching 0.4 - - ns parin after ck and ck 0.4 - - ns table 11. switching characteristics over recommended operating conditions, unless otherwise noted. symbol parameter conditions min typ max unit f max maximum input clock frequency 450 - - mhz t pdm peak propagation delay ck and ck to output [1] 1.0 - 1.4 ns t lh low to high delay time ck and ck to ptyerr 1.2 - 3 ns t hl high to low delay time ck and ck to ptyerr 1 - 3 ns t plh low-to-high propagation delay from reset to ptyerr - - 3 ns t pdmss simultaneous switching peak propagation delay ck and ck to output [1] [2] - - 1.5 ns t phl high-to-low propagation delay reset to output - - 3 ns table 12. output edge rates over recommended operating conditions, unless otherwise noted. symbol parameter conditions min typ max unit dv/dt_r rising edge slew rate 1 - 4 v/ns dv/dt_f falling edge slew rate 1 - 4 v/ns dv/dt_ d absolute difference between dv/dt_r and dv/dt_f - - 1 v/ns
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 18 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 11. test information 11.1 test circuit all input pulses are supplied by generators having the following characteristics: pulse repetition rate (prr) 10 mhz; z 0 =50 w ; input slew rat e = 1 v/ns 20 %, unless otherwise speci?ed. the outputs are measured one at a time with one transition per measurement. (1) c l includes probe and jig capacitance. fig 8. load circuit (1) i dd tested with clock and data inputs held at v dd or gnd, and i o = 0 ma. fig 9. voltage and current waveforms; inputs active and inactive times v id = 600 mv. v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 10. voltage waveforms; pulse duration r l = 100 w r l = 1000 w v dd 50 w ck inputs ck ck out dut test point 002aaa371 test point delay = 350 ps z o = 50 w r l = 1000 w c l = 30 pf (1) lvcmos reset 10 % i dd (1) t inact v dd 0.5v dd t act 90 % 0 v 002aaa372 0.5v dd v icr v icr v ih v il input t w v id 002aaa373
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 19 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity v id = 600 mv. v ref = 0.5v dd . v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 11. voltage waveforms; set-up and hold times t plh and t phl are the same as t pd . fig 12. voltage waveforms; propagation delay times (clock to output) t plh and t phl are the same as t pd . v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 13. voltage waveforms; propagation delay times (reset to output) t su v ih v il v id t h ck ck input v ref v ref v icr 002aaa374 v oh v ol output t plh 002aaa375 v t v icr v icr t phl ck ck v i(p-p) t phl 002aaa376 lvcmos reset output v t 0.5v dd v ih v il v oh v ol
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 20 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 11.2 output slew rate measurement v dd = 1.8 v 0.1 v. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; input slew rat e = 1 v/ns 20 %, unless otherwise speci?ed. (1) c l includes probe and jig capacitance. fig 14. load circuit, high-to-low slew measurement fig 15. voltage waveforms, high-to-low slew rate measurement (1) c l includes probe and jig capacitance. fig 16. load circuit, low-to-high slew measurement fig 17. voltage waveforms, low-to-high slew rate measurement c l = 10 pf (1) v dd out dut test point r l = 50 w 002aaa377 v oh v ol output 80 % 20 % dv_f dt_f 002aaa378 c l = 10 pf (1) out dut test point r l = 50 w 002aaa379 v oh v ol 80 % 20 % dv_r dt_r output 002aaa380
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 21 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 11.3 error output load circuit and voltage measurement v dd = 1.8 v 0.1 v. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; input slew rat e = 1 v/ns 20 %, unless otherwise speci?ed. (1) c l includes probe and jig capacitance. fig 18. load circuit, error output measurements fig 19. voltage waveforms, open-drain output low-to-high transition time with respect to reset input fig 20. voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs c l = 10 pf (1) v dd out dut test point r l = 1 k w 002aaa500 0.5v dd t plh v dd 0 v 0.15 v v oh 0 v output waveform 2 reset 002aaa501 lvcmos v icr t hl 0.5v dd v dd v ol timing inputs output waveform 1 v i(p-p) v icr 002aaa502
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 22 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity fig 21. voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs v icr t lh v oh 0 v timing inputs output waveform 2 v i(p-p) v icr 0.15 v 002aaa503
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 23 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 12. package outline fig 22. package outline sot802-2 (tfbga160) references outline version european projection issue date iec jedec jeita sot802-2 sot802-2 05-06-21 05-07-13 unit a max mm 1.15 0.35 0.25 0.80 0.65 9.1 8.9 a 1 dimensions (mm are the original dimensions) tfbga160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.7 mm 0 5 10 mm scale a 2 d 13.1 12.9 e 0.45 0.35 b e 2 11.05 e 0.65 e 1 7.15 y v 0.15 w 0.08 0.1 - - - - - - - - - y 1 0.1 b ball a1 index area a b c d e f h k g l j m n p r t u v 24681012 1357911 e 2 e 1 e e 1/2 e 1/2 e a c b ? v m c ? w m c y c y 1 x ball a1 index area b a d e detail x a a 2 a 1
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 24 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 13. soldering this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus pbsn soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 25 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 13.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 23 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 13 and 14 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 23 . table 13. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 14. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 26 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 14. abbreviations 15. revision history msl: moisture sensitivity level fig 23. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 15. abbreviations acronym description cmos complementary metal oxide semiconductor ddr2 double data rate 2 dimm dual in-line memory module dram dynamic random access memory lvcmos low voltage complementary metal oxide semiconductor mt/s mega transfers per second rdimm registered dual in-line memory module sstl stub series terminated logic sstl_18 stub series terminated logic for 1.8 v table 16. revision history document id release date data sheet status change notice supersedes SSTUM32865_1 20070919 product data sheet - -
SSTUM32865_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 19 september 2007 27 of 28 nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 17. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors SSTUM32865 1.8 v ddr2-800 registered buffer with parity ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 19 september 2007 document identifier: SSTUM32865_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . . 8 7.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 functional information . . . . . . . . . . . . . . . . . . . 9 7.3 functional differences to sstu32864 . . . . . . 10 7.3.1 chip select (cs) gating of key inputs ( dcs0, dcs1, dcs2, dcs3, csgateen) . . . . . . . . 10 7.3.2 parity error checking and reporting. . . . . . . . . 10 7.3.3 reset ( reset) . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.4 power-up sequence . . . . . . . . . . . . . . . . . . . . 10 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 9 recommended operating conditions. . . . . . . 15 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 16 11 test information . . . . . . . . . . . . . . . . . . . . . . . . 18 11.1 test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.2 output slew rate measurement. . . . . . . . . . . . 20 11.3 error output load circuit and voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . 21 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 24 13.2 wave and re?ow soldering . . . . . . . . . . . . . . . 24 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24 13.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 25 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 27 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17 contact information. . . . . . . . . . . . . . . . . . . . . 27 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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