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| ds07-13734-3ea fujitsu microelectronics data sheet ?check sheet? is seen at the following support page url : http://edevice.fujitsu.com/micom/en-support/ ?check sheet? lists the minimal requirement items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest caut ions on development. copyright?2004-2008 fujitsu microelec tronics limited all rights reserved 2007.11 16-bit microcontroller cmos f 2 mc-16lx mb90330a series mb90333a/f334a/mb90v330a description the mb90330a series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require usb communications. the usb feature supports not only 12-mbps function operation but also mini-host operation. it is equip ped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support usb communications. while inheriting the at architecture of the f 2 mc family, the instruction set supports the c language and extended addressing modes and contains enhanced signed multiplicat ion and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, long word processing is now available by intro- ducing a 32-bit accumulator. note : f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ? clock built-in oscillation circuit and pll clock frequency multiplication circuit oscillation clock the main clock is the oscillation clock divi ded into 2 (for oscilla tion 6 mhz : 3 mhz) clock for usb is 48 mhz machine clock frequency of 6 mhz, 12 mhz, or 24 mhz selectable minimum execution time of instruction : 41.6 ns (6 mhz oscillation clock, 4-time multiplied : machine clock 24 mhz and at operating v cc = 3.3 v. ? the maximum memory space : 16 mbytes ? 24-bit addressing (continued)
mb90330a series 2 (continued) ? bank addressing ? instruction system data types : bit, byte, word and long word addressing mode (23 types) enhanced high-precision computing with 32-bit accumulator enhanced multiply/divide instructions with sign an d the reti instruction ? instruction system compatible with high-level language (c language) and multi-task employing system stack pointer instruction set symmetry and barrel shift instructions ? program patch function (2 address pointer) ? 4-byte instruction queue ? interrupt function priority levels are programmable 32 interrupts function ? data transfer function extended intelligent i/o service function (ei 2 os) : maximum of 16 channels dmac : maximum 16 channels ? low power consumption mode sleep mode (with the cpu operating clock stopped) time-base timer mode (wit h the oscillator clock and time-base timer operating) stop mode (with the os cillator clock stopped) cpu intermittent operation mode (with the cpu operating at fixed intervals of set cycles) watch mode (with 32 khz oscillato r clock and watch timer operating) ? package lqfp-120p (fpt-120p-m05 : 0.40 mm pin pitch) lqfp-120p (fpt-120p-m21 : 0.50 mm pin pitch) ? process : cmos technology ? operation guaranteed temperature : ? 40 c to + 85 c (0 c to + 70 c when usb is in use) mb90330a series 3 internal peripheral function (resource) ? i/o port : max 94 ports ? time-base timer : 1 channel ? watchdog timer : 1 channel ? watch timer : 1 channel ? 16-bit reload timer : 3 channels ? multi-functional timer 16-bit free run timer : 1 channel output compare : 4 channels an interrupt request can be output when the 16-bit free-run timer value matches the compare register value. input capture : 4 channels upon detection of the effective edge of the signal input to the external input pin, the input capture unit sets the input capture data register to the 16-bit free-run timer value to output an interrupt request. 8/16-bit ppg timer (8-bit 6 channels or 16-bit 3 channels) the period and duty of the output pulse can be set by the program. 16-bit pwc timer : 1 channel timer function and pulse width measurement function ? uart : 4 channels full-duplex double buffer (8-bit length) asynchronous transfer or clock-synchronous serial (extended i/o serial) transfer can be set. ? extended i/o serial interface : 1 channel ? dtp/external interrupt circuit (8 channels) activate the extended intelligent i/o service by external interrupt input interrupt output by external interrupt input ? delay interrupt output module output an interrupt request for task switching ? 8/10-bit a/d converter : 16 channels 8-bit resolution or 10-b it resolution can be set. ? usb : 1 channel usb function (correspond to usb full speed) full speed is supported/endpoint are specifiable up to six. dual port ram (the fifo mode is supported). transfer type : control, interrupt, bulk, or isochronous transfer possible usb mini-host function ? i 2 c* interface : 3 channels supports intel sm bus standard and phillips i 2 c bus standards two-wire data transfer protocol specification master and slave transmission/reception * : i 2 c license : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these com- ponents in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips. mb90330a series 4 product lineup * : it is setting of jumper switch (tool vcc) when emulator (mb2147-01) is used. please refer to the mb2147-01 or mb2147-20 hardware manual (3.3 emulator-dedicated power supply switching) about details. part number mb90v330a MB90F334A mb90333a type for evaluation built-in flash memory built-in mask rom rom capacity no 384 kbytes 256 kbytes ram capacity 28 kbytes 24 kbytes 16 kbytes emulator-specific power supply * yes ? cpu functions number of basic instructions : 351 instructions minimum instruction execution time : 41.6 ns/at oscillation of 6 mhz (when 4 times are used : machine clock of 24 mhz) addressing type : 23 types program patch function : for 2 address pointers maximum memory space : 16 mbytes ports i/o ports (cmos) 94 ports uart equipped with full-duplex double buffer clock synchronous or asynchro nous operation selectable it can also be used for i/o serial built-in special baud-rate generator built-in 4 channels 16-bit reload timer 16-bit reload timer operation built-in 3 channels multi-functional timer 16-bit free run timer 1 channel output compare 4 channels input capture 4 channels 8/16-bit ppg timer (8-bit mode 6 channels, 16-bit mode 3 channels) 16-bit pwc timer 1 channel 8/10-bit a/d converter 16 channels (input multiplex) 8-bit resolution or 10-bit resolution can be set. conversion time : 7.16 s at minimum (24 mhz machine clock at maximum) dtp/external interrupt 8 channels interrupt factor : ?l? ?h? edge/?h? ?l? edge/?l? level/ ?h? level selectable i 2 c 3 channels extended i/o serial interface 1 channel usb 1 channel usb function (correspond to usb full speed) usb mini-host function external bus interface for multi-bus/non-multi-bus withstand voltage of 5 v 16 ports (excluding utest and i/o for i 2 c) low power consumption mode sleep mode/time-base timer mode/stop mode/cpu intermittent mode/ watch mode process cmos operating voltage 3.3 v 0.3 v (at maximum machine clock 24 mhz) mb90330a series 5 packages and product models : yes : no note : for detailed information on each package, refer to ? package dimensions?. package mb90333a MB90F334A mb90v330a fpt-120p-m05 (lqfp-0.40 mm) fpt-120p-m21 (lqfp-0.50 mm) pga-299c-a01 (pga) mb90330a series 6 pin assignment (top view) (fpt-120p-m05 / fpt-120p-m21) p30/a00/tin1 p31/a01/tot1 p32/a02/tin2 p33/a03/tot2 p34/a04 p35/a05 p36/a06 p37/a07 p40/a08/tin0 p41/a09/tot0 p42/a10/sin0 p43/a11/sot0 x0a x1a v cc v ss p44/a12/sck0 p45/a13/sin1 p46/a14/sot1 p47/a15/sck1 p60/int0 p61/int1 p62/int2/sin p63/int3/sot p64/int4/sck p65/int5/pwc p66/int6/scl0 p67/int7/sda0 p90/sin2 p91/sot2 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 p27/a23/ppg3 p26/a22/ppg2 p25/a21/ppg1 p24/a20/ppg0 p23/a19 p22/a18 p21/a17 p20/a16 p17/ad15/d15 p16/ad14/d14 p15/ad13/d13 p14/ad12/d12 x0 x1 v ss v cc p13/ad11/d11 p12/ad10/d10 p11/ad09/d09 p10/ad08/d08 p07/ad07/d07 p06/ad06/d06 p05/ad05/d05 p04/ad04/d04 p03/ad03/d03 p02/ad02/d02 p01/ad01/d01 p00/ad00/d00 p57/clk p56/rdy 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p92/sck2 p93/sin3 p94/sot3 p95/sck3 p96/adtg/frck av cc avrh av ss p70/an0 p71/an1 p72/an2 p73/an3 p74/an4 p75/an5 p76/an6 p77/an7 v ss p80/an8 p81/an9 p82/an10 p83/an11 p84/an12 p85/an13 p86/an14 p87/an15 pa0/in0 pa1/in1 pa2/in2 pa3/in3 pa4/out0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 rst md0 md1 md2 p55/hak p54/hrq p53/wrh p52/wrl p51/rd p50/ale hcon v cc hvp hvm v ss v cc dvp dvm v ss utest pb6/ppg5 pb5/ppg4 pb4 pb3/sda2 pb2/scl2 pb1/sda1 pb0/scl1 pa7/out3 pa6/out2 pa5/out1 mb90330a series 7 pin description (continued) pin no. pin name i/o circuit type* function 108, 107 x0, x1 a terminals to connect the oscillator. when connecting an external clock, leave the x1 pin side unconnected. 13, 14 x0a, x1a a 32 khz oscillation terminals. 90 rst f external reset input pin. 93 to 100 p00 to p07 h general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd00 to rd07 = 1) by the pull-up resistor setting register (rdr0). (when the power output is set, it is invalid.) ad00 to ad07 function as an i/o pin for the low-order external address and data bus in multiplex mode. d00 to d07 function as an output pin for the low-order external data bus in non- multiplex mode. 101 to 104 p10 to p13 h general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd10 to rd13 = 1) by the pull-up resistor setting register (rdr1). (when the power output is set, it is invalid.) ad08 to ad11 function as an i/o pin for the high-order external address and data bus in multiplex mode. d08 to d11 function as an output pin for the high-order external data bus in non- multiplex mode. 109 to 112 p14 to p17 h general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd14 to rd17 = 1) by the pull-up resistor setting register (rdr1). (when the power output is set, it is invalid.) ad12 to d15 function as an i/o pin for the high-order external address and data bus in multiplex mode. d12 to d15 function as an output pin for the high-order external data bus in non- multiplex mode. 113 to 116 p20 to p23 d this is a general purpose i/o port. when the bits of external address output control register (hacr) are set to ?1? in external bus mode, these pins function as general purpose i/o ports. a16 to a19 when the bits of external address output control register (hacr) are set to ?0? in multiplex mode, these pins f unction as address high output pins. a16 to a19 when the bits of external address output control register (hacr) are set to ?0? in non-multiple x mode, these pins function as address high output pins. mb90330a series 8 (continued) pin no. pin name i/o circuit type* function 117 to 120 p24 to p27 d this is a general purpose i/o port. when the bits of external address output control register (hacr) are set to ?1? in external bus mode, these pins function as general purpose i/o ports. a20 to a23 when the bits of external address output control register (hacr) are set to ?0? in multiplex mode, these pins fu nction as address high output pins. a20 to a23 when the bits of external address output control register (hacr) are set to ?0? in non-multiplex mode, these pins function as address high output pins. ppg0 to ppg3 function as ch.0 to ch.3 output pins for the 8-bit ppg timer. 1 p30 d general purpose input/output port. a00 function as the external address pin in non-multi-bus mode. tin1 function as an event input pin for 16-bit reload timer ch.1. 2 p31 d general purpose input/output port. a01 function as the external address pin in non-multi-bus mode. tot1 function as the output pin for 16-bit reload timer ch.1. 3 p32 d general purpose input/output port. a02 function as the external address pin in non-multi-bus mode. tin2 function as an event input pin for 16-bit reload timer ch.2. 4 p33 d general purpose input/output port. a03 function as the external address pin in non-multi-bus mode. tot2 function as the output pin for 16-bit reload timer ch.2. 5 to 8 p34 to p37 d general purpose input/output port. a04 to a07 function as the external address pin in non-multi-bus mode. 9 p40 g general purpose input/output port. a08 function as the external address pin in non-multi-bus mode. tin0 function as an event input pin for 16-bit reload timer ch.0. 10 p41 g general purpose input/output port. a09 function as the external address pin in non-multi-bus mode. tot0 function as the output pin for 16-bit reload timer ch.0. 11 p42 g general purpose input/output port. a10 function as the external address pin in non-multi-bus mode. sin0 function as a data input pin for uart ch.0. 12 p43 g general purpose input/output port. a11 function as the external address pin in non-multi-bus mode. sot0 function as a data output pin for uart ch.0. 17 p44 g general purpose input/output port. a12 function as the external address pin in non-multi-bus mode. sck0 function as a clock i/o pin for uart ch.0. mb90330a series 9 (continued) pin no. pin name i/o circuit type* function 18 p45 g general purpose input/output port. a13 function as the external address pin in non-multi-bus mode. sin1 function as a data input pin for uart ch.1. 19 p46 g general purpose input/output port. a14 function as the external address pin in non-multi-bus mode. sot1 function as a data output pin for uart ch.1. 20 p47 g general purpose input/output port. a15 function as the external address pin in non-multi-bus mode. sck1 function as a clock i/o pin for uart ch.1. 81 p50 l general purpose input/output port. ale function as the address latch enabl e signal pin in external bus mode. 82 p51 l general purpose input/output port. rd function as the read strobe output pin in external bus mode. 83 p52 l general purpose input/output port. wrl function as the data write strobe output pin on the lower side in external bus mode. this pin functions as a general-purpose i/o port when the wre bit in the epcr register is ?0?. 84 p53 l general purpose input/output port. wrh function as the data write strobe output pin on the higher side in bus width 16-bit external bus mode. this pin functions as a general-purpose i/o port when the wre bit in the epcr register is ?0?. 85 p54 l general purpose input/output port. hrq function as the hold request input pin in external bus mode. this pin functions as a general-purpose i/o port when the hde bit in the epcr register is ?0?. 86 p55 l general purpose input/output port. hak function as the hold acknowledge output pin in external bus mode. this pin functions as a general-purpose i/o port when the hde bit in the epcr register is ?0?. 91 p56 l general purpose input/output port. rdy function as the external ready input pin in external bus mode. this pin functions as a general-purpose i/o port when the rye bit in the epcr register is ?0?. 92 p57 l general purpose input/output port. clk function as the machine cycle clock outp ut pin in external bus mode. this pin functions as a general-purpose i/o port when the cke bit in the epcr register is ?0?. 21, 22 p60, p61 c general purpose input/output port. (with stand voltage of 5 v) int0, int1 function as external interrupt ch.0 and ch.1 input pins. mb90330a series 10 (continued) pin no. pin name i/o circuit type* function 23 p62 c general purpose input/output ports. (withstand voltage of 5 v) int2 function as an external interrupt ch.2 input pin. sin extended i/o serial interface data input pin. 24 p63 c general purpose input/output port. (withstand voltage of 5 v) int3 function as an external interrupt ch.3 input pin. sot extended i/o serial interface data output pin. 25 p64 c general purpose input/output port. (withstand voltage of 5 v) int4 function as an external interrupt ch.4 input pin. sck extended i/o serial interface clock input/output pin. 26 p65 c general purpose input/output port. (withstand voltage of 5 v) int5 function as an external interrupt ch.5 input pin. pwc function as the pwc input pin. 27 p66 c general purpose input/output port. (withstand voltage of 5 v) int6 function as an external interrupt ch.6 input pin. scl0 function as the ch.0 clock i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 28 p67 c general purpose input/output port. (withstand voltage of 5 v) int7 function as an external interrupt ch.7 input pin. sda0 function as the ch.0 data i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 39 to 46 p70 to p77 i general purpose input/output port. an0 to an7 function as input pins for analog ch.0 to ch.7. 48 to 55 p80 to p87 i general purpose input/output port. an8 to an15 function as input pins for analog ch.8 to ch.15. 29 p90 d general purpose input/output port. sin2 function as a data input pin for uart ch.2. 30 p91 d general purpose input/output port. sot2 function as a data output pin for uart ch.2. 31 p92 d general purpose input/output port. sck2 function as a clock i/o pin for uart ch.2. 32 p93 d general purpose input/output port. sin3 function as a data input pin for uart ch.3. 33 p94 d general purpose input/output port. sot3 function as a data output pin for uart ch.3. 34 p95 d general purpose input/output port. sck3 function as a clock i/o pin for uart ch.3. 35 p96 c general purpose input/output port. (withstand voltage of 5 v) adtg function as the external trigger input pin when the a/d converter is being used. frck function as the external clock input pin when the free-run timer is being used. mb90330a series 11 (continued) * : for circuit information, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* function 56 to 59 pa0 to pa3 c general purpose input/output port. (withstand voltage of 5 v) in0 to in3 function as the input capture ch.0 to ch.3 trigger inputs. 60 to 63 pa4 to pa7 c general purpose input/output port. (withstand voltage of 5 v) out0 to out3 function as the output compare ch.0 to ch.3 event output pins. 64 pb0 c general purpose input/output port. (withstand voltage of 5 v) scl1 function as the ch.1 clock i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 65 pb1 c general purpose input/output port. (withstand voltage of 5 v) sda1 function as the ch.1 data i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 66 pb2 c general purpose input/output port. (withstand voltage of 5 v) scl2 function as the ch.2 clock i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 67 pb3 c general purpose input/output port. (withstand voltage of 5 v) sda2 function as the ch.2 data i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 68 pb4 c general purpose input/output port. (withstand voltage of 5 v) 69, 70 pb5, pb6 d general purpose input/output port. ppg4, ppg5 function as ch.4 and ch.5 output pins for the 8-bit ppg timer. 71 utest c usb test pin. connect this to a pull-down resistor during normal usage. 73 dvm k usb function d ? pin. 74 dvp k usb function d + pin. 77 hvm k usb mini-host d ? pin. 78 hvp k usb mini-host d + pin. 80 hcon e external pull-up resistor connect pin. 36 avcc ? a/d converter power supply pin. 37 avrh j a/d converter external reference power supply pin. 38 avss ? a/d converter power supply pin. 87 to 89 md2 to md0 b operation mode select input pin. 15 vcc ? power supply pin. 75 vcc ? power supply pin. 79 vcc ? power supply pin. 105 vcc ? power supply pin. 16 vss ? power supply pin (gnd). 47 vss ? power supply pin (gnd). 72 vss ? power supply pin (gnd). 76 vss ? power supply pin (gnd). 106 vss ? power supply pin (gnd). mb90330a series 12 i/o circuit type (continued) type circuit remarks a high-rate oscillation feedback resistor, approx.1 m ? low-rate oscillation feedback resistor, approx.10 m ? with standby control b cmos hysteresis input c cmos hysteresis input n-ch open drain output d cmos output cmos hysteresis input (with input interception function at standby) notes : ? share one output buffer because both output of i/o port and internal resource are used. ? share one input buffer because both input of i/o port and internal resource are used. e cmos output f cmos hysteresis input with pull-up resistor x1 x1a x0 x0a standby control signal clock input cmos hysteresis input nout n-ch cmos hysteresis input standby control signal pout nout p-ch n-ch cmos hysteresis input standby control signal pout nout p-ch n-ch r cmos hysteresis input mb90330a series 13 (continued) type circuit remarks g cmos output cmos hysteresis input (with input interception function at standby) with open drain control signal h cmos output cmos input (with input interception function at standby) with input pull-up register control i cmos output cmos hysteresis input (with input interception function at standby) analog input (the a/d converter analog input is enabled when the corresponding bit in the analog input enable register (ader) is 1.) notes: ? because the output of the i/o port and the output of internal resources are used combinedly, one output buffer is shared. ? because the input of the i/o port and the input of internal resources are used combinedly, one input buffer is shared. j a/d converter (avrh) voltage input pin pout nout p-ch n-ch open drain control signal standby control signal cmos hysteresis input pout nout p-ch r n-ch ctl cmos input standby control signal pout nout p-ch n-ch cmos hysteresis input standby control signal a/d converter analog input p-ch n-ch p-ch n-ch a/d converter analog input enable signal avrh input mb90330a series 14 (continued) type circuit remarks k usb i/o pin l cmos output cmos input with standby control d + d ? d + input d - input differential input full d + output full d - output low d + output low d - output direction speed pout nout p-ch n-ch cmos input standby control signal mb90330a series 15 handling devices 1. preventing latch-up and turning on power supply latch - up may occur on cmos ic under the following conditions: ? if a voltage higher than v cc or lower than v ss is applied to input and output pins. ? a voltage higher than the rated voltage is applied between v cc pin and v ss pin. ? if the av cc power supply is turned on before the v cc voltage. ensure that you apply a voltage to the analog power supply at the same time as v cc or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as v cc and the digital power supply). if latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. use meticulous care not to let any voltage exceed the maximum rating. 2. treatment of unused pins leaving unused input pins unconnected can cause abnormal operation or latch - up, leading to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. if there is unused output pin, make it to open. 3. treatment of power supply pins on models with a/d converters even when the a/d converters are not in use, be sure to make the necessary connections av cc = avrh = v cc , and av ss = v ss . 4. about the attention when the external clock is used even when using an external clock si gnal, an oscillation stab ilization delay is applied af ter a power-on reset or when recovering from sub clock or stop mode. when suing an external clock, 25 mhz should be the upper frequency limit. the following figure shows a sample use of external clock signals. 5. treatment of power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 f between v cc pin and v ss pin near this device. x0 x1 open using external clock mb90330a series 16 6. about crystal oscillator circuit noise near the x0/x1 pins and x0a/x1a pins may cause the device to malfunction. design the printed circuit board so that x0/x1 pins and x0a/x1a pins, the crystal oscillator (or the ceramic oscillator) and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended to design the pc board artwork with the x0/x1 pins and x0a/x1a pins surrounded by ground plane because stable operation can be expected with such a layout. please ask the crystal maker to evaluate the oscillati onal characteristics of the crystal and this device. 7. caution on operations during pll clock mode on this microcontroller, if in case the crystal oscillator breaks off or an external re ference clock input stops while the pll clock mode is selected, a self -oscillator circuit contained in the pl l may continue its operation at its self-running frequency. however, fujitsu microelectronics will not guarantee re sults of operations if such failure occurs. 8. stabilization of supply voltage a sudden change in the supply voltage may cause the device to malfunction even within the v cc supply voltage operating range. for stabilization reference, the supply voltage sh ould be stabilized so that v cc ripple variations (peak-to-peak value) at commercial fr equencies (50 hz/60 hz) fall below 10 % of the standard v cc supply voltage and the transient regulation does not exceed 0.1 v/ms at temporary changes such as power supply switching. 9. when the dual-supply is used as a single-supply device if you are using only a single-system of the mb90330a series that come in the dual-system product, use it with x0a = v ss : x1a = open. 10. writing to flash memory for serial writing to flash memory, always make sure that the operating voltage v cc is between 3.13 v and 3.6 v. for normal writing to flash memory, always make sure that the operating voltage v cc is between 3.0 v and 3.6 v. mb90330a series 17 block diagram f 2 mc-16lx cpu ram 8 /16- b it ppg timer ch.0 to ch.5 * inp u t c a pt u re ch.0 to ch. 3 16- b it free-r u n timer o u tp u t comp a re ch.0 to ch. 3 16- b it pwc s io dmac 8 /10- b it a/d converter extern a l interr u pt i/o port (port 0, 1, 2, 3 , 4, 5, 6, 7, 8 , 9, a, b) 16- b it relo a d timer ch.0 to ch.2 u s b (f u nction) (mini-ho s t) clock control circ u it interr u pt controller rom uart/ s io ch.0 to ch. 3 i 2 c ch.0 to ch.2 p00 p07 p10 p17 p20 p27 p 3 0 p 3 7 p40 p47 p50 p57 p60 p67 x0, x1 x0a,x1a r s t md0 to md2 s in0 to s in 3 s ot0 to s ot 3 s ck0 to s ck 3 s cl0 to s cl2 s da0 to s da2 int0 to int7 av cc avrh av ss an0 to an15 adtg dvp dvm hvp hvm hcon ute s t tot0 to tot2 tin0 to tin2 ppg0 to ppg5 frck in0 to in 3 out0 to out 3 pwc s in s ot s ck p 8 0 p 8 7 p70 p77 p90 p96 pb0 pb6 pa 0 pa 7 * : channel for use in 8-bit mode. 3 channels (ch.1, ch.3, ch.5) are used in 16-bit mode. note : i/o ports share pins with peripheral function (resources) . for details, refer to ? pin assignment? and ? pin description?. note also that pins used for peripheral function (resources) cannot serve as i/o ports. internal data bus mb90330a series 18 memory map memory map of mb90330a series (1/3) ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 007100 h 007900 h 00 8 000 h f 8 0000 h f 8 ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90v 33 0a ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 006100 h 007900 h 00 8 000 h f 8 0000 h f 8 ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90f 33 4a ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 004100 h 007900 h 00 8 000 h f 8 0000 h f 8 ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90 333 a rom (ff ba nk) rom (fe ba nk) rom (fd ba nk) rom (fc ba nk) rom (fb ba nk) rom (fa ba nk) rom (f9 ba nk) rom (f 8 ba nk) rom (ff ba nk) rom (fe ba nk) rom (fd ba nk) rom (fb ba nk) rom (fa ba nk) rom (f9 ba nk) rom (ff ba nk) rom (fe ba nk) rom (fd ba nk) rom (fb ba nk) rom (im a ge of ff ba nk) rom (im a ge of ff ba nk) rom (im a ge of ff ba nk) peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a ram a re a (2 8 k b yte s ) ram a re a (24 k b yte s ) ram a re a (16 k b yte s ) regi s ter regi s ter regi s ter single chip mode (with rom mirror function) mb90330a series 19 memory map of mb90330a series (2/3) ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 007100 h 007900 h 00 8 000 h f 8 0000 h f 8 ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90v 33 0a ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 006100 h 007900 h 00 8 000 h f 8 0000 h f 8 ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90f 33 4a ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 004100 h 007900 h 00 8 000 h f 8 0000 h f 8 ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90 333 a rom (ff ba nk) rom (fe ba nk) rom (fd ba nk) rom (fc ba nk) rom (fb ba nk) rom (fa ba nk) rom (f9 ba nk) rom (f 8 ba nk) rom (ff ba nk) rom (fe ba nk) rom (fd ba nk) rom (fb ba nk) rom (fa ba nk) rom (f9 ba nk) rom (ff ba nk) rom (fe ba nk) rom (fd ba nk) rom (fb ba nk) rom (im a ge of ff ba nk) rom (im a ge of ff ba nk) rom (im a ge of ff ba nk) peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a ram a re a (2 8 k b yte s ) ram a re a (24 k b yte s ) ram a re a (16 k b yte s ) regi s ter regi s ter regi s ter * 1 * 1 * 2 * 2 extern a l a re a extern a l a re a extern a l a re a extern a l a re a extern a l a re a extern a l a re a extern a l a re a extern a l a re a internal rom external bus mode (with rom mirror function) *1 : in the area of f80000 h to f8ffff h and fc0000 h to fcffff h at MB90F334A, a value of ?1? is read at read operating. *2 : in the area of fa0000 h to faffff h and fc0000 h to fcffff h at mb90333a, a value of ?1? is read at read operating. mb90330a series 20 memory map of mb90330a series (3/3) notes : ? when the rom mirror function register has been set, the mirror image data at higher addresses (?ff8000 h to ffffff h ?) of bank ff is visible from the higher addresses (?008000 h to 00ffff h ?) of bank 00. ? the rom mirror function is effectiv e for using the c compiler small model. ? the lower 16-bit addresses of bank ff are equival ent to those of bank 00. since the rom area in bank ff exceeds 48 kbytes, however, the mirror image of all the data in the rom area cannot be reproduced in bank 00. ? when the c compiler small model is used, the data table mirror image can be shown at ?008000 h to 00ffff h ? by storing the data table at ?ff8000 h to ffffff h ?. therefore, data tables in the rom area can be referred without declaring the far addressing with the pointer. ffffff h 007fff h 000000 h 0000fb h 000100 h 007100 h 007900 h 00 8 000 h mb90v 33 0a ffffff h 007fff h 000000 h 0000fb h 000100 h 006100 h 007900 h 00 8 000 h mb90f 33 4a ffffff h 007fff h 000000 h 0000fb h 000100 h 004100 h 007900 h 00 8 000 h mb90 333 a peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a peripher a l a re a ram a re a (2 8 k b yte s ) ram a re a (24 k b yte s ) ram a re a (16 k b yte s ) regi s ter regi s ter regi s ter extern a l a re a extern a l a re a extern a l a re a extern a l a re a extern a l a re a extern a l a re a external rom external bus mode mb90330a series 21 f 2 mc - 16l cpu programming model ? dedicated register ? general purpose register ? processor status ah al dpr pcb dtb usb ssb adb 8-bit 16-bit 32-bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16-bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl3 msb lsb ilm 15 13 ps rp ccr 12 8 70 bit mb90330a series 22 i/o map (continued) address register abbreviation register read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w port 7 xxxxxxxx b 000008 h pdr8 port 8 data register r/w port 8 xxxxxxxx b 000009 h pdr9 port 9 data register r/w port 9 - xxxxxxx b 00000a h pdra port a data register r/w port a xxxxxxxx b 00000b h prohibited 00000c h pdrb port b data register r/w port b - xxxxxxx b 00000d h ddrb port b direction register r/w port b - 0 0 0 0 0 0 0 b 00000e h prohibited 00000f h 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 0 0 0 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h ddr7 port 7 direction register r/w port 7 0 0 0 0 0 0 0 0 b 000018 h ddr8 port 8 direction register r/w port 8 0 0 0 0 0 0 0 0 b 000019 h ddr9 port 9 direction register r/w port 9 - 0 0 0 0 0 0 0 b 00001a h ddra port a direction register r/w port a 0 0 0 0 0 0 0 0 b 00001b h odr4 port 4 output pin register r/w port 4 (open drain control) 0 0 0 0 0 0 0 0 b 00001c h rdr0 port 0 pull-up resistance register r/w port 0 (pull-up) 0 0 0 0 0 0 0 0 b 00001d h rdr1 port 1 pull-up resistance register r/w port 1 (pull-up) 0 0 0 0 0 0 0 0 b 00001e h ader0 analog input enable register 0 r/w port 7, 8, a/d 1 1 1 1 1 1 1 1 b 00001f h ader1 analog input enable register 1 r/w port 7, 8, a/d 1 1 1 1 1 1 1 1 b 000020 h smr0 serial mode register 0 r/w uart0 0 0 1 0 0 0 0 0 b 000021 h scr0 serial control register 0 r/w 0 0 0 0 0 1 0 0 b 000022 h sidr0 serial input data register 0 r xxxxxxxx b sodr0 serial output data register 0 w 000023 h ssr0 serial status register 0 r/w 0 0 0 0 1 0 0 0 b 000024 h utrlr0 uart prescaler reload register 0 r/w communication prescaler (uart0) 0 0 0 0 0 0 0 0 b 000025 h utcr0 uart prescaler control register 0 r/w 0 0 0 0 - 0 0 0 b mb90330a series 23 (continued) address register abbreviation register read/ write resource name initial value 000026 h smr1 serial mode register 1 r/w uart1 0 0 1 0 0 0 0 0 b 000027 h scr1 serial control register 1 r/w 0 0 0 0 0 1 0 0 b 000028 h sidr1 serial input data register 1 r xxxxxxxx b sodr1 serial output data register 1 w 000029 h ssr1 serial status register 1 r/w 0 0 0 0 1 0 0 0 b 00002a h utrlr1 uart prescaler reload register 1 r/w communication prescaler (uart1) 0 0 0 0 0 0 0 0 b 00002b h utcr1 uart prescaler control register 1 r/w 0 0 0 0 - 0 0 0 b 00002c h smr2 serial mode register 2 r/w uart2 0 0 1 0 0 0 0 0 b 00002d h scr2 serial control register 2 r/w 0 0 0 0 0 1 0 0 b 00002e h sidr2 serial input data register 2 r xxxxxxxx b sodr2 serial output data register 2 w 00002f h ssr2 serial status register 2 r/w 0 0 0 0 1 0 0 0 b 000030 h utrlr2 uart prescaler reload register 2 r/w communication prescaler (uart2) 0 0 0 0 0 0 0 0 b 000031 h utcr2 uart prescaler control register 2 r/w 0 0 0 0 - 0 0 0 b 000032 h smr3 serial mode register 3 r/w uart3 0 0 1 0 0 0 0 0 b 000033 h scr3 serial control register 3 r/w 0 0 0 0 0 1 0 0 b 000034 h sidr3 serial input data register 3 r xxxxxxxx b sodr3 serial output data register 3 w 000035 h ssr3 serial status register 3 r/w 0 0 0 0 1 0 0 0 b 000036 h utrlr3 uart prescaler reload register 3 r/w communication prescaler (uart3) 0 0 0 0 0 0 0 0 b 000037 h utcr3 uart prescaler control register 3 r/w 0 0 0 0 - 0 0 0 b 000038 h to 00003b h prohibited 00003c h enir dtp/interrupt enable register r/w dtp/external interrupt 0 0 0 0 0 0 0 0 b 00003d h eirr dtp/interrupt source register r/w 0 0 0 0 0 0 0 0 b 00003e h elvr request level setting register lower r/w 0 0 0 0 0 0 0 0 b 00003f h request level setting register upper r/w 0 0 0 0 0 0 0 0 b 000040 h adcs0 a/d control status register lower r/w 8/10-bit a/d converter 0 0 - - - - - 0 b 000041 h adcs1 a/d control status register upper r/w 0 0 0 0 0 0 0 0 b 000042 h adcr0 a/d data register lower r/w xxxxxxxx b 000043 h adcr1 a/d data register upper r/w 0 0 1 0 1 xxx b 000044 h prohibited 000045 h admr a/d conversion channel selection register r/w 8/10-bit a/d converter 0 0 0 0 0 0 0 0 b 000046 h ppgc0 ppg0 operation mode control register r/w ppg ch.0 0x0 0 0xx1 b 000047 h ppgc1 ppg1 operation mode control register r/w ppg ch.1 0x0 0 0 0 0 1 b 000048 h ppgc2 ppg2 operation mode control register r/w ppg ch.2 0x0 0 0xx1 b mb90330a series 24 (continued) address register abbreviation register read/ write resource name initial value 000049 h ppgc3 ppg3 operation mode control register r/w ppg ch.3 0x0 0 0 0 0 1 b 00004a h ppgc4 ppg4 operation mode control register r/w ppg ch.4 0x0 0 0xx1 b 00004b h ppgc5 ppg5 operation mode control register r/w ppg ch.5 0x0 0 0 0 0 1 b 00004c h ppg01 ppg0 and ppg1 output control register r/w ppg ch.0/ch.1 0 0 0 0 0 0xx b 00004d h prohibited 00004e h ppg23 ppg2 and ppg3 output control register r/w ppg ch.2/ch.3 0 0 0 0 0 0 xx b 00004f h prohibited 000050 h ppg45 ppg4 and ppg5 output control register r/w ppg ch.4/ch.5 0 0 0 0 0 0 xx b 000051 h prohibited 000052 h ics01 input capture control status register 01 r/w input capture ch.0/ch.1 0 0 0 0 0 0 0 0 b 000053 h ics23 input capture control status register 23 r/w input capture ch.2/ch.3 0 0 0 0 0 0 0 0 b 000054 h ocs0 output compare control register ch.0 lower r/w output compare ch.0/ch.1 0 0 0 0 - - 0 0 b 000055 h ocs1 output compare control register ch.1 upper r/w - - - 0 0 0 0 0 b 000056 h ocs2 output compare control register ch.2 lower r/w output compare ch.2/ch.3 0 0 0 0 - - 0 0 b 000057 h ocs3 output compare control register ch.3 upper r/w - - - 0 0 0 0 0 b 000058 h smcs serial mode control status register r/w extended serial i/o xxxx0 0 0 0 b 000059 h 0 0 0 0 0 0 1 0 b 00005a h sdr serial data register r/w xxxxxxxx b 00005b h sdcr communication pr escaler control register r/w communication prescaler 0xxx0 0 0 0 b 00005c h pwcsr pwc control status register r/w 16-bit pwc timer 0 0 0 0 0 0 0 0 b 00005d h 0 0 0 0 0 0 0 x b 00005e h pwcr pwc data buffer register r/w 0 0 0 0 0 0 0 0 b 00005f h 0 0 0 0 0 0 0 0 b 000060 h divr pwc dividing ratio control register r/w - - - - - - 0 0 b 000061 h prohibited 000062 h tmcsr0 timer control status register 0 r/w 16-bit reload timer ch.0 0 0 0 0 0 0 0 0 b 000063 h xxxx 0 0 0 0 b 000064 h tmr0 16-bit timer re gister 0 lower r xxxxxxxx b tmrlr0 16-bit reload register 0 lower w xxxxxxxx b 000065 h tmr0 16-bit timer re gister 0 upper r xxxxxxxx b tmrlr0 16-bit reload register 0 upper w xxxxxxxx b mb90330a series 25 (continued) address register abbreviation register read/ write resource name initial value 000066 h tmcsr1 timer control status register 1 r/w 16-bit reload timer ch.1 0 0 0 0 0 0 0 0 b 000067 h xxxx 0 0 0 0 b 000068 h tmr1 16-bit timer register 1 lower r xxxxxxxx b tmrlr1 16-bit reload register 1 lower w xxxxxxxx b 000069 h tmr1 16-bit timer register 1 upper r xxxxxxxx b tmrlr1 16-bit reload register 1 upper w xxxxxxxx b 00006a h tmcsr2 timer control status register 2 r/w 16-bit reload timer ch.2 0 0 0 0 0 0 0 0 b 00006b h xxxx 0 0 0 0 b 00006c h tmr2 16-bit timer register 2 lower r xxxxxxxx b tmrlr2 16-bit reload register 2 lower w xxxxxxxx b 00006d h tmr2 16-bit timer register 2 upper r xxxxxxxx b tmrlr2 16-bit reload register 2 upper w xxxxxxxx b 00006e h prohibited 00006f h romm rom mirror function selection register w rom mirror function selection module - - - - - - 1 1 b 000070 h ibsr0 i 2 c bus status register 0 r i 2 c bus interface ch.0 0 0 0 0 0 0 0 0 b 000071 h ibcr0 i 2 c bus control register 0 r/w 0 0 0 0 0 0 0 0 b 000072 h iccr0 i 2 c bus clock control register 0 r/w xx 0 xxxxx b 000073 h iadr0 i 2 c bus address register 0 r/w xxxxxxxx b 000074 h idar0 i 2 c bus data register 0 r/w xxxxxxxx b 000075 h prohibited 000076 h ibsr1 i 2 c bus status register 1 r i 2 c bus interface ch.1 0 0 0 0 0 0 0 0 b 000077 h ibcr1 i 2 c bus control register 1 r/w 0 0 0 0 0 0 0 0 b 000078 h iccr1 i 2 c bus clock control register 1 r/w xx 0 xxxxx b 000079 h iadr1 i 2 c bus address register 1 r/w xxxxxxxx b 00007a h idar1 i 2 c bus data register 1 r/w xxxxxxxx b 00007b h prohibited 00007c h ibsr2 i 2 c bus status register 2 r i 2 c bus interface ch.2 0 0 0 0 0 0 0 0 b 00007d h ibcr2 i 2 c bus control register 2 r/w 0 0 0 0 0 0 0 0 b 00007e h iccr2 i 2 c bus clock control register 2 r/w xx 0 xxxxx b 00007f h iadr2 i 2 c bus address register 2 r/w xxxxxxxx b 000080 h idar2 i 2 c bus data register 2 r/w xxxxxxxx b 000081 h to 000085 h prohibited mb90330a series 26 (continued) address register abbreviation register read/ write resource name initial value 000086 h tcdt timer data register lower r/w 16-bit free-run timer 0 0 0 0 0 0 0 0 b 000087 h timer data register upper r/w 0 0 0 0 0 0 0 0 b 000088 h tccs timer control status register lower r/w 0 0 0 0 0 0 0 0 b 000089 h timer control status register upper r/w 0 - - 0 0 0 0 0 b 00008a h cpclr compare clear register lower r/w xxxxxxxx b 00008b h compare clear register upper r/w xxxxxxxx b 00008c h to 00009a h prohibited 00009b h dcsr dma descriptor channel specification register r/w dmac 0 0 0 0 0 0 0 0 b 00009c h dsrl dma status register lower r/w 0 0 0 0 0 0 0 0 b 00009d h dsrh dma status register upper r/w 0 0 0 0 0 0 0 0 b 00009e h pacsr program address detection control status register r/w address match detection 0 0 0 0 0 0 0 0 b 00009f h dirr delay interruption factor generation/ release register r/w delay interrupt - - - - - - - 0 b 0000a0 h lpmcr low power consumption mode control register r/w low power consumption control circuit 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selection register r/w clock 1 1 1 1 1 1 0 0 b 0000a2 h prohibited 0000a3 h 0000a4 h dssr dma stop stat us register r/w dmac 0 0 0 0 0 0 0 0 b 0000a5 h arsr automatic ready function selection register w external pin 0 0 1 1- - 0 0 b 0000a6 h hacr external address output control register w ? ? ? ? ? ? ? ? b 0000a7 h epcr bus control signal selection register w 1 0 0 0 ? 1 0 - b 0000a8 h wdtc watchdog timer cont rol register r/w watch dog timer x - xxx 1 1 1 b 0000a9 h tbtc time-base timer control register r/w time-base timer 1 - - 0 0 1 0 0 b 0000aa h wtc watch timer control register r/w watch timer 1 0 0 0 1 0 0 0 b 0000ab h prohibited 0000ac h derl dma enable register lower r/w dmac 0 0 0 0 0 0 0 0 b 0000ad h derh dma enable register upper r/w 0 0 0 0 0 0 0 0 b 0000ae h fmcs flash memory control status register r/w flash memory i/f 0 0 0 x 0 0 0 0 b 0000af h prohibited mb90330a series 27 (continued) address register abbreviation register read/ write resource name initial value 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h hcnt0 host control register 0 r/w usb mini-host 0 0 0 0 0 0 0 0 b 0000c1 h hcnt1 host control register 1 r/w 0 0 0 0 0 0 0 1 b 0000c2 h hirq host interruption register r/w 0 0 0 0 0 0 0 0 b 0000c3 h herr host error status register r/w 0 0 0 0 0 0 1 1 b 0000c4 h hstate host state status register r/w xx 0 1 0 0 1 0 b 0000c5 h hfcomp sof interrupt frame compare reg- ister r/w 0 0 0 0 0 0 0 0 b 0000c6 h hrtimer retry timer setting register r/w 0 0 0 0 0 0 0 0 b 0000c7 h r/w 0 0 0 0 0 0 0 0 b 0000c8 h r/w xxxxxx 0 0 b 0000c9 h hadr host address register r/w x 0 0 0 0 0 0 0 b 0000ca h heof eof setting register r/w 0 0 0 0 0 0 0 0 b 0000cb h r/w xx 0 0 0 0 0 0 b 0000cc h hframe frame setting register r/w 0 0 0 0 0 0 0 0 b 0000cd h r/w xxxxx 0 0 0 b 0000ce h htoken host token end point register r/w 0 0 0 0 0 0 0 0 b 0000cf h prohibited 0000d0 h udcc udc control register r/w usb function 1 0 1 0 0 0 0 0 b 0000d1 h r/w 0 0 0 0 0 0 0 0 b mb90330a series 28 (continued) address register abbreviation register read/ write resource name initial value 0000d2 h ep0c ep0 control register r/w usb function 0 1 0 0 0 0 0 0 b 0000d3 h r/w xxxx 0 0 0 0 b 0000d4 h ep1c ep1 control register r/w 0 0 0 0 0 0 0 0 b 0000d5 h r/w 0 1 1 0 0 0 0 1 b 0000d6 h ep2c ep2 control register r/w 0 1 0 0 0 0 0 0 b 0000d7 h r/w 0 1 1 0 0 0 0 0 b 0000d8 h ep3c ep3 control register r/w 0 1 0 0 0 0 0 0 b 0000d9 h r/w 0 1 1 0 0 0 0 0 b 0000da h ep4c ep4 control register r/w 0 1 0 0 0 0 0 0 b 0000db h r/w 0 1 1 0 0 0 0 0 b 0000dc h ep5c ep5 control register r/w 0 1 0 0 0 0 0 0 b 0000dd h r/w 0 1 1 0 0 0 0 0 b 0000de h tmsp time stamp register r 0 0 0 0 0 0 0 0 b 0000df h r xxxxx0 0 0 b 0000e0 h udcs udc status register r/w xx0 0 0 0 0 0 b 0000e1 h udcie udc interrupt enable register r/w, r 0 0 0 0 0 0 0 0 b 0000e2 h ep0is ep0i status register r/w xxxxxxxx b 0000e3 h r/w 1 0 xxx 1 xx b 0000e4 h ep0os ep0o status register r/w, r 0 xxxxxxx b 0000e5 h r/w 1 0 0 xx 0 0 0 b 0000e6 h ep1s ep1 status register r xxxxxxxx b 0000e7 h r/w, r 1 0 0 0 0 0 0 x b 0000e8 h ep2s ep2 status register r xxxxxxxx b 0000e9 h r/w, r 1 0 0 0 0 0 0 0 b 0000ea h ep3s ep3 status register r xxxxxxxx b 0000eb h r/w, r 1 0 0 0 0 0 0 0 b 0000ec h ep4s ep4 status register r xxxxxxxx b 0000ed h r/w, r 1 0 0 0 0 0 0 0 b 0000ee h ep5s ep5 status register r xxxxxxxx b 0000ef h r/w, r 1 0 0 0 0 0 0 0 b 0000f0 h ep0dt ep0 data register r/w xxxxxxxx b 0000f1 h r/w xxxxxxxx b 0000f2 h ep1dt ep1 data register r/w xxxxxxxx b 0000f3 h r/w xxxxxxxx b 0000f4 h ep2dt ep2 data register r/w xxxxxxxx b 0000f5 h r/w xxxxxxxx b 0000f6 h ep3dt ep3 data register r/w xxxxxxxx b 0000f7 h r/w xxxxxxxx b mb90330a series 29 (continued) address register abbreviation register read/ write resource name initial value 0000f8 h ep4dt ep4 data register r/w usb function xxxxxxxx b 0000f9 h r/w xxxxxxxx b 0000fa h ep5dt ep5 data register r/w xxxxxxxx b 0000fb h r/w xxxxxxxx b 0000fc h to 0000ff h prohibited 000100 h to # h ram area 001ff0 h padr0 program address detection register ch.0 lower r/w address match detection xxxxxxxx b 001ff1 h program address detection register ch.0 middle r/w xxxxxxxx b 001ff2 h program address detection register ch.0 upper r/w xxxxxxxx b 001ff3 h padr1 program address detection register ch.1 lower r/w xxxxxxxx b 001ff4 h program address detection register ch.1 middle r/w xxxxxxxx b 001ff5 h program address detection register ch.1 upper r/w xxxxxxxx b # h to 0078ff h unused area 007900 h prll0 ppg reload regi ster lower ch.0 r/w ppg ch.0 xxxxxxxx b 007901 h prlh0 ppg reload register upper ch.0 r/w xxxxxxxx b 007902 h prll1 ppg reload regi ster lower ch.1 r/w ppg ch.1 xxxxxxxx b 007903 h prlh1 ppg reload register upper ch.1 r/w xxxxxxxx b 007904 h prll2 ppg reload regi ster lower ch.2 r/w ppg ch.2 xxxxxxxx b 007905 h prlh2 ppg reload register upper ch.2 r/w xxxxxxxx b 007906 h prll3 ppg reload regi ster lower ch.3 r/w ppg ch.3 xxxxxxxx b 007907 h prlh3 ppg reload register upper ch.3 r/w xxxxxxxx b 007908 h prll4 ppg reload regi ster lower ch.4 r/w ppg ch.4 xxxxxxxx b 007909 h prlh4 ppg reload register upper ch.4 r/w xxxxxxxx b 00790a h prll5 ppg reload regi ster lower ch.5 r/w ppg ch.5 xxxxxxxx b 00790b h prlh5 ppg reload register upper ch.5 r/w xxxxxxxx b 00790c h to 00790f h prohibited mb90330a series 30 (continued) explanation on read/write explanation on initial values note : no i/o instruction can be used for registers located between 007900 h and 007fff h . address register abbreviation register read/ write resource name initial value 007910 h ipcp0 input capture data register lower ch.0 r input capture ch.0/ch.1 xxxxxxxx b 007911 h input capture data register upper ch.0 r xxxxxxxx b 007912 h ipcp1 input capture data regi ster lower ch.1 r xxxxxxxx b 007913 h input capture data register upper ch.1 r xxxxxxxx b 007914 h ipcp2 input capture data register lower ch.2 r input capture ch.2/ch.3 xxxxxxxx b 007915 h input capture data register upper ch.2 r xxxxxxxx b 007916 h ipcp3 input capture data regi ster lower ch.3 r xxxxxxxx b 007917 h input capture data register upper ch.3 r xxxxxxxx b 007918 h occp0 output compare register lower ch.0 r/w output compare ch.0/ch.1 xxxxxxxx b 007919 h output compare register upper ch.0 r/w xxxxxxxx b 00791a h occp1 output compare register lower ch.1 r/w xxxxxxxx b 00791b h output compare register upper ch.1 r/w xxxxxxxx b 00791c h occp2 output compare register lower ch.2 r/w output compare ch.2/ch.3 xxxxxxxx b 00791d h output compare register upper ch.2 r/w xxxxxxxx b 00791e h occp3 output compare register lower ch.3 r/w xxxxxxxx b 00791f h output compare register upper ch.3 r/w xxxxxxxx b 007920 h dbapl dma buffer address pointer lower 8-bit r/w dmac xxxxxxxx b 007921 h dbapm dma buffer address po inter middle 8-bit r/w xxxxxxxx b 007922 h dbaph dma buffer address po inter upper 8-bit r/w xxxxxxxx b 007923 h dmacs dma control register r/w xxxxxxxx b 007924 h dioal dma i/o register address pointer lower 8-bit r/w xxxxxxxx b 007925 h dioah dma i/o register address pointer upper 8-bit r/w xxxxxxxx b 007926 h ddctl dma data counter lower 8-bit r/w xxxxxxxx b 007927 h ddcth dma data counter upper 8-bit r/w xxxxxxxx b 007928 h to 007fff h prohibited r/w : readable / writable r : read only w : write only 0 : initial value is ?0?. 1 : initial value is ?1?. x : initial value is undefined. - : initial value is undefined (none) . ? : initial value of this bit is ?1? or ?0?. mb90330a series 31 interrupt sources, interrupt vectors, and interrupt control registers (continued) interrupt source ei 2 os support dmac interrupt vector interrupt control register priority number* 1 address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exceptional treatment #10 0a h ffffd4 h ?? usb function1 0, 1 #11 0b h ffffd0 h icr00 0000b0 h usb function2 2 to 6* 2 #12 0c h ffffcc h usb function3 #13 0d h ffffc8 h icr01 0000b1 h usb function4 #14 0e h ffffc4 h usb mini-host1 #15 0f h ffffc0 h icr02 0000b2 h usb mini-host2 #16 10 h ffffbc h i 2 c ch.0 #17 11 h ffffb8 h icr03 0000b3 h dtp/external interrupt ch.0/ch.1 #18 12 h ffffb4 h i 2 c ch.1 #19 13 h ffffb0 h icr04 0000b4 h dtp/external interrupt ch.2/ch.3 #20 14 h ffffac h i 2 c ch.2 #21 15 h ffffa8 h icr05 0000b5 h dtp/external interrupt ch.4/ch.5 #22 16 h ffffa4 h pwc/reload timer ch.0 14 #23 17 h ffffa0 h icr06 0000b6 h dtp/external interrupt ch.6/ch.7 #24 18 h ffff9c h input capture ch.0/ch.1 7 #25 19 h ffff98 h icr07 0000b7 h reload timer ch.1 #26 1a h ffff94 h input capture ch.2/ch.3 8 #27 1b h ffff90 h icr08 0000b8 h reload timer ch.2 #28 1c h ffff8c h output compare ch.0/ch.1 #29 1d h ffff88 h icr09 0000b9 h ppg ch.0/ch.1 #30 1e h ffff84 h output compare ch.2/ch.3 #31 1f h ffff80 h icr10 0000ba h ppg ch.2/ch.3 #32 20 h ffff7c h uart (send completed) ch.2/ch.3 11 #33 21 h ffff78 h icr11 0000bb h ppg ch.4/ch.5 #34 22 h ffff74 h uart (reception completed) ch.2/ch.3 10 #35 23 h ffff70 h icr12 0000bc h a/d converter/free-run timer 15 #36 24 h ffff6c h uart (send completed) ch.0/ch.1 13 #37 25 h ffff68 h icr13 0000bd h extended serial i/o 9#3826 h ffff64 h uart (reception completed) ch.0/ch.1 12 #39 27 h ffff60 h icr14 0000be h time-base timer/watch timer #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delay interrupt output module #42 2a h ffff54 h low mb90330a series 32 (continued) : available, ei 2 os stop function provided (the interrupt request flag is cleared by the interrupt clear signal. with a stop request). : available (the interrupt request flag is cleared by the interrupt clear signal.) : available when any interrupt source sharing icr is not used. : unavailable *1 : if the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority. *2 : ch.2 and 3 can also be used during mini-host operation. notes : ? if the same interrupt control register (icr) has two interrupt factors and the use of the ei 2 os is permitted, the ei 2 os is activated when either of the factors is det ected. as any interrupt other than the activation factor is masked while the ei 2 os is running, it is recommended that you should mask either of the interrupt requests when using the ei 2 os. ? the interrupt flag is cleared by the ei 2 os interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (icr). ? if a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the dmac interrupt clear signal. therefore, when you use either of two interrupt factors for the dmac function, another interrupt function is disabled. set the interrupt request permission bit to ?0? in the appropriate resource, and take measures by software polling. ? content of usb interruption factor * : endpoints 1 and 2 can also be used during mini-host operation. usb interrupt factor details usb function 1 end point0-in end point0-out usb function 2 end point1-5 * usb function 3 susp sof brst wkup conf usb function 4 spk usb mini-host1 dirq cnnirq urirq rwkirq usb mini-host2 sofirq cmpirq mb90330a series 33 peripheral resources 1. i/o port the i/o ports are used as general-purpose input/output ports (parallel i/o ports). mb90330a series model is provided with 12 ports (94 inputs) . the ports function as input/output pins for peripheral functions also. the port data register (pdr) can be used to send output data to the i/o pin and to receive the signal input to the i/o port. the port direction register (ddr) can be used to set the i/o direction of the i/o pin in bit units. the following table lists the i/o ports and the peripheral functions with which they share pins. note : these pins also serve as the analog input pins for ports 7 and 8. to use them as general-purpose ports, be sure to set the corresponding bits in the analog input enable register (ader) to 0 b . the ader is initialized to ff h at a reset. port pin name pin name (peripheral) peripheral function that shares pin port 0 p00 to p07 ? (external bus) port 1 p10 to p17 ? (external bus) port 2 p20 to p23 ? (external bus) p24 to p27 ppg0 to ppg3 8/16-bit ppg timer 0, 1 (external bus) port 3 p30 to p33 tin1, tot1, tin2, tot2 16-bit reload timer 1, 2 (external bus) p34 to p37 ? (external bus) port 4 p40, p41 tin0, tot0 16-bit reload timer 0 (external bus) p42 to p47 sin0, sot0, sck0, sin1, sot1, sck1 uart0, uart1 (external bus) port 5 p50 to p57 ? (external bus) port 6 p60, p61 int0, int1 external interrupt p62 to p64 int2 to int4, sin, sot, sck external interrupt, serial i/o p65 int5, pwc externa l interrupt, pwc p66, p67 int6, int7, scl0, sda0 external interrupt, i 2 c 0 port 7 p70 to p77 an0 to an7 8/10-bit a/d converter port 8 p80 to p87 an8 to an15 8/10-bit a/d converter port 9 p90 to p95 sin2, sot2, sck2, sin3, sot3, sck3 uart2, 3 p96 adtg, frck 8/10-bit a/d converter, free-run timer port a pa0 to pa3 in0 to in3 input capture 0, 1, 2, 3 pa4 to pa7 out0 to out3 output compare 0, 1, 2, 3 port b pb0 to pb3 scl1, sda1, scl2, sda2 i 2 c 1, 2 pb4 ?? pb5, pb6 ppg4, ppg5 ppg timer 2 mb90330a series 34 ? register list (port data register) * : r/w access to i/o ports is a bit different in behavior from r/w access to memory as follows : ? input mode read : the level at the relevant pin is read. write : data is written to the output latch. ? output mode read : the data register latch value is read. write : data is output to the relevant pin. pdr0 bit initial value access address : 000000 h xxxxxxxx b r/w* pdr1 bit address : 000001 h xxxxxxxx b r/w* pdr2 bit address : 000002 h xxxxxxxx b r/w* pdr3 bit address : 000003 h xxxxxxxx b r/w* pdr4 bit address : 000004 h xxxxxxxx b r/w* pdr5 bit address : 000005 h xxxxxxxx b r/w* pdr6 bit address : 000006 h xxxxxxxx b r/w* pdr7 bit address : 000007 h xxxxxxxx b r/w* pdr8 bit address : 000008 h xxxxxxxx b r/w* pdr9 bit address : 000009 h - xxxxxxx b r/w* pdra bit address : 00000a h xxxxxxxx b r/w* pdrb bit address : 00000c h - xxxxxxx b r/w* 76543210 p06 p07 p05 p04 p03 p02 p01 p00 15 14 13 12 11 10 9 8 p16 p17 p15 p14 p13 p12 p11 p10 76543210 p26 p27 p25 p24 p23 p22 p21 p20 15 14 13 12 11 10 9 8 p36 p37 p35 p34 p33 p32 p31 p30 76543210 p46 p47 p45 p44 p43 p42 p41 p40 15 14 13 12 11 10 9 8 p56 p57 p55 p54 p53 p52 p51 p50 76543210 p66 p65 p64 p63 p62 p61 p60 p67 15 14 13 12 11 10 9 8 p76 p75 p74 p73 p72 p71 p70 p77 76543210 p84 p83 p82 p81 p80 p87 p86 p85 15 14 13 12 11 10 9 8 p91 p90 ? p96 p95 p94 p93 p92 76543210 pa1 pa0 pa7 pa6 pa5 pa4 pa3 pa2 76543210 pb1 pb0 ? pb6 pb5 pb4 pb3 pb2 mb90330a series 35 ? register list (port direction register) when each pin is serving as a port, the co rresponding pin is controlled as follows : 0 : input mode 1 : output mode this bit becomes 0 after a reset. note : if these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set for input are rewritten to current input values of the pins. when switching a pin from input port to output port, therefore, write a desired value in the pdr first, then set the ddr to switch the pin for output. ddr0 bit initial value access address : 000010 h 00000000 b r/w ddr1 bit address : 000011 h 00000000 b r/w ddr2 bit address : 000012 h 00000000 b r/w ddr3 bit address : 000013 h 00000000 b r/w ddr4 bit address : 000014 h 00000000 b r/w ddr5 bit address : 000015 h 00000000 b r/w ddr6 bit address : 000016 h 00000000 b r/w ddr7 bit address : 000017 h 00000000 b r/w ddr8 bit address : 000018 h 00000000 b r/w ddr9 bit address : 000019 h -0000000 b r/w ddra bit address : 00001a h 00000000 b r/w ddrb bit address : 00000d h -0000000 b r/w 7654 321 0 d06 d07 d05 d04 d03 d02 d01 d00 15 14 13 12 11 10 9 8 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 d26 d27 d25 d24 d23 d22 d21 d20 15 14 13 12 11 10 9 8 d36 d37 d35 d34 d33 d32 d31 d30 7654 321 0 d46 d47 d45 d44 d43 d42 d41 d40 15 14 13 12 11 10 9 8 d56 d57 d55 d54 d53 d52 d51 d50 7654 321 0 d66 d67 d65 d64 d63 d62 d61 d60 15 14 13 12 11 10 9 8 d75 d74 d73 d72 d71 d70 d76 d77 7654 321 0 d84 d83 d82 d81 d80 d87 d86 d85 15 14 13 12 11 10 9 8 d91 d90 ? d96 d95 d94 d93 d92 7654 321 0 da1 da0 da7 da6 da5 da4 da3 da2 15 14 13 12 11 10 9 8 db1 db0 ? db6 db5 db4 db3 db2 mb90330a series 36 ? register list (analog input enable register) this register controls the port 7, 8 pins as follows. 0 : port input/output mode. 1 : analog input mode. this bit becomes 1 after a reset. ? register list (port pull-up resistance register) controls the pull-up re sistor in input mode. 0 : without pull-up resistor in input mode. 1 : with pull-up resistor in input mode. meaningless in output mode. (without pull-up resistor)/the input/output mode is decided by the setting of the port direction register (ddr). without pull-up resistor is used in stop mode (spl = 1). (high-z) this function is disabled when the external bus is used. do not attempt to write to this register. ? register list (output pin register) controls open-drain in output mode. 0 : serves as a standard output port in output mode. 1 : serves as an open-drain output port in output mode. meaningless in input mode (output high-z)./the input/output mode is decided by the setting of the port direction register (ddr). this function is disabled when the external bus is used. do not attempt to write to this register. ader0 bit initial value access address : 00001e h 11111111 b r/w ader1 bit address : 00001f h 11111111 b r/w 7654 321 0 ade3 ade2 ade1 ade0 ade7 ade6 ade5 ade4 15 14 13 12 11 10 9 8 ade11 ade10 ade9 ade8 ade15 ade14 ade13 ade12 rdr0 bit initial value access address : 00001c h 00000000 b r/w rdr1 bit address : 00001d h 00000000 b r/w 7654 321 0 rd06 rd07 rd05 rd04 rd03 rd02 rd01 rd00 15 14 13 12 11 10 9 8 rd16 rd17 rd15 rd14 rd13 rd12 rd11 rd10 odr4 bit initial value access address : 00001b h 00000000 b r/w 7654 321 0 od46 od47 od45 od44 od43 od42 od41 od40 mb90330a series 37 ? block diagram of port 0 pin and port 1 pin ? block diagram of port 2 pin, port 3 pin, port 4 pin, port 5 pin, port 6 pin, port 9 pin, port a pin and port b pin pull-up resistor setting register (rdrx) port data register (pdrx) port direction register (ddrx) i/o decision circuit input buffer output buffer internal data bus pdrx read pdrx write port pin internal pull-up resistor standby control (lpmcr : spl = ?1?) port data register (pdrx) port direction register (ddrx) i/o decision circuit input buffer output buffer internal data bus pdrx read pdrx write port pin standby control (lpmcr : spl = ?1?) resource output control sig nal resource output resource input mb90330a series 38 ? block diagram of port 7 pin and port 8 pin notes : ? when using as an input port, set ?0? in the corresponding bit of the port-7 and port-8 direction register (ddr7 and ddr8) and ?0? in the related bit of the analog input enable register (ader). ? when using as an analog input pin, set ?0? in the corresponding bit of the port-7 and port-8 direction register (ddr7 and ddr8) and ?1? in the related bit of the analog input enable register (ader). analog input enable register (ader) port data register (pdrx) port direction register (ddrx) i/o decision circuit input buffer output buffer internal data bus pdrx read pdrx write port pin a/d converter analog input signal standby control (lpmcr : s pl = ?1?) mb90330a series 39 2. time-base timer the time-base timer is an 18-bit free-run counter (time-base timer counter) that counts in synchronization with the main clock (2 cycles of the oscillation clock hclk). four different time interval s can be selected, for each of which an interrupt request can be generated. operating cl ock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and watchdog timer. ? interval time of time-base timer notes : ? hclk : oscillation clock frequency ? the parenthesized va lues assume an oscillator clock frequency of 6 mhz. ? clock cycles supplied from time-base timer notes : ? hclk : oscillation clock frequency ? the parenthesized va lues assume an oscillator clock frequency of 6 mhz. ? register list internal count clock cycle interval time 2/hclk (0.33 s) 2 12 /hclk (approx. 0.68 ms) 2 14 /hclk (approx. 2.7 ms) 2 16 /hclk (approx. 10.9 ms) 2 19 /hclk (approx. 87.4 ms) where to supply clock clock cycle main clock oscillation stabilization wait 2 13 /hclk (approx. 1.36 ms) 2 15 /hclk (approx. 5.46 ms) 2 17 /hclk (approx. 21.84 ms) watch dog timer 2 12 /hclk (approx. 0.68 ms) 2 14 /hclk (approx. 2.7 ms) 2 16 /hclk (approx. 10.9 ms) 2 19 /hclk (approx. 87.4 ms) time-base timer control register (tbtc) bit initial value address : 0000a9 h 1 - - 00100 b ( ? )( ? ) ( r/w ) ( r/w ) ( w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( r/w ) resv ? tbie tbof tbr tbc1 tbc0 mb90330a series 40 ? block diagram actual interrupt request number of time-base timer is as follows : interrupt request number : #40 (28 h ) tbie tbof tbr resv ?? tbc1 tbc0 of of of of 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 to ppg timer time-base timer counter dividing hclk by 2 to watchdog timer ckscr : mcs = 1 0* 1 ckscr : scs = 0 1* 2 counter clear control circuit interval timer selector tbof clear time-base timer control register (tbtc) time-base timer interrupt signal to clock controller oscillation stabilizing wait time selector tbof set ? : unused of : overflow hclk : oscillation clock *1 : switching the machine clock from main clock or sub clock to pll clock *2 : switching the machine clock from sub clock to main clock power-on reset stop mode start hold state start mb90330a series 41 3. watchdog timer the watchdog timer is timer counter provided for measure of program runaway. it is a 2-bit counter operating with an output of the timebase timer or watch timer as the count clock and resets the cpu when the counter is not cleared for a preset period of time after start. ? interval time of watchdog timer notes : ? the maximum and minimum time intervals for the watchdog timer depend on the counter clear timing. ? the watchdog timer contains a 2-bit counter that counts the carry-up signal from the time-base timer or watch timer. ? interval time of watchdog timer is longer than the set time during the following conditions. - when clearing the timeba se timer during operati on on oscillation (hclk) - when clearing the watch timer during operation on sub clock (sclk) ? events that stop the watchdog timer stop due to a power-on reset watchdog reset ? clear factor of watchdog timer external reset input by rst pin writing ?0? to the software reset bit writing ?0? to the watchdog timer control bit (second and subsequent times) transition to sleep mode (clearing the watchdog timer to suspend counting) transition to time-base timer mode (clearing the watchdog timer to suspend counting) transition to stop mode (clearing the watchdog timer to suspend counting) hclk : oscillation clock(6 mhz) sclk : sub clock(8 khz) min max clock cycle approx. 2.39 ms approx. 3.07 ms (2 14 2 11 ) / hclk approx. 9.56 ms approx. 12.29 ms (2 16 2 13 ) / hclk approx. 38.23 ms approx. 49.15 ms (2 18 2 15 ) / hclk approx. 305.83 ms approx. 393.22 ms (2 21 2 18 ) / hclk approx. 0.448 s approx. 0.576 s (2 12 2 9 ) / sclk approx. 3.584 s approx. 4.608 s (2 15 2 12 ) / sclk approx. 7.168 s approx. 9.216 s (2 16 2 13 ) / sclk approx. 14.336 s approx. 18.432 s (2 17 2 14 ) / sclk mb90330a series 42 ? register list ? block diagram watchdog timer control register (wdtc) bit initial value address : 0000a8 h x-xxx111 b ( ? ) ( r ) ( r ) ( r ) ( w ) ( w ) ( w ) 765432 10 ( r ) ponr wrst erst srst wte wt1 wt0 ? ponr ? wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 1 sclk clr clr 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 4 watchdog timer control register (wdtc) watchdog timer watch mode start time-base timer mode start sleep mode start hold state start counter clear control circuit count clock selector 2-bit counter watchdog timer reset generation circuit to internal reset generation circuit clr and start (time-base timer counter) main clock (dividing hclk by 2) hclk: oscillation clock sclk: sub clock clear stop mode start wdcs bit of wtc scm bit of ckscr mb90330a series 43 4. watch timer the watch timer is a 15-bit timer using the sub clock. it can generate interval interrupts. it can also be used as a clock source for the watchdog timer. ? register list ? block diagram watch timer control register (wtc) bit initial value address : 0000aa h 10001000 b ( r ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 sce ( r/w ) wdcs wtie wtof wtr wtc2 wtc1 wtc0 wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 10 2 13 2 14 2 15 sub clock watch counter interval selector interrupt generation circuit watch timer interrupt to watchdog timer watch timer control register (wtc) clear mb90330a series 44 5. 16-bit reload timer the 16-bit reload timer has the internal clock mode to decrement in synchronization with 3 different internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the external pin. either can be selected. this timer defines when the count value changes from 0000 h to ffff h as an underflow. the timer therefore causes an underflow when the count reaches [reload register setting + 1]. either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. the interrupt can be generated at the counter underflow occurrence so as to correspond to the dtc. ? register list ? tmcsr (timer control status register 0 to 2) timer control status register (upper) (tmcsr0 to tmcsr2) timer control status register (lower) (tmcsr0 to tmcsr2) ? 16-bit timer register/16-bit reload register tmr0 to tmr2/tmrlr0 to tmrlr2 (upper) tmr0 to tmr2/tmrlr0 to tmrlr2 (lower) address : bit 000063 h 000067 h 00006b h initial value xxxx0000 b address : bit 000062 h 000066 h 00006a h initial value 00000000 b address : bit 000065 h 000069 h 00006d h initial value xxxxxxxx b address : bit 000064 h 000068 h 00006c h initial value xxxxxxxx b ( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ??? csl1 csl0 mod2 mod1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 oute ( r/w ) mod0 outl reld inte uf cnte trg ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 d14 ( r/w ) d15 d13 d12 d11 d10 d09 d08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d06 ( r/w ) d07 d05 d04 d03 d02 d01 d00 mb90330a series 45 ? block diagram tmrlr0 ? 1 tmrlr1 ? 2 tmrlr2 ? 3 tmr0 ? 1 tmr1 ? 2 tmr2 ? 3 clk tin0 ? 1 tin1 ? 2 tin2 ? 3 uf en tot0 ? 1 tot1 ? 2 tot2 ? 3 clk 3 3 2 ???? csl1 csl0 mod2 mod1 mod0 oute outl reld uf inte cnte trg ? 5 internal data bus 16-bit reload register 16-bit timer register reload signal reload control circuit wait signal output control circuit output signal generation circuit pin valid clock decision circuit clock selector operating control circuit select signal external clock internal clock input control circuit pin prescaler count clock generation circuit gate input timer control status register (tmcsr0 to tmcsr2) interrupt request output #23 (17 h ) * 1, * 4 #26 (1a h ) * 2, * 4 #28 (1c h ) * 3, * 4 select function clear trigger machine clock *1 : ch.0 *2 : ch.1 *3 : ch.2 *4 : interrupt number *5 : underflow mb90330a series 46 6. multi function timer the multi-function timer enables the following based on the 16-bit free-run timer. ? output of independent waveform ? measurement of input pulse width ? measurement of external clock cycle ? configuration of a multi-functional timer ? 16-bit free-run timer : 1 channel the 16-bit free-run timer consists of a 16-bit up counter (timer data register (tcdt)), compare clear register (cpclr), timer control status register (tccs), and prescaler. the counter output value of the 16-bit free-run timer is used as the base timer for the output compare and input capture units. the count clock can be set, selected from among the following eight types. 1/ , 2/ , 4/ , 8/ , 16/ , 32/ , 64/ , 128/ : machine clock frequency during the following conditions, the interrupt should be output. - the counter value of 16-bit free run timer will be overflowed. - the counter value of 16-bit free run timer will be clea red after the counter value of 16-bit fr ee run timer = the compare clear register value (cpclr) (tccs : icre = ?1?, mode = ?1?) the counter value of 16-bit free run timer should be cleared to ?0000 h ? during the following conditions. ? reset ? when setting the clear bit (sclr) of timer control status register (tccs) to ?1? ? when the counter value of the 16-bit free run timer = the compare clear register value (cpclr) (tccs : mode = ?1?) ? when setting ?0000 h ? to the timer data register (tcdt) ? output compare : 4 channels the output compare unit consists of compare registers (occp0 to occp3), compare control registers (ocs0 to ocs3), and a compare output latch. the output compare unit can invert the output level and output an interrupt when a compare register (occp0 to occp3) value matches the counter value of the 16-bit free-run timer. output compare registers can operate as 4 independent channels. the output compare registers (occp0 to occp3) of each channel have interrupt request flags of their respective output pins. pin output can be inverted by using 2 channels of output compare registers (occp0 to occp3). if the counter value of 16-bit free run timer = the output compare register (occp0 to occp3) (ocs0, ocs2 : icp0 = ?1?, icp1 = ?1?), the interrupt request should be generated. (ocs0, ocs2 : ice0 = ?1?, ice1 = ?1?) the initial value for pin output of each channel can be set. ? input capture : 4 channels the input capture unit consists of the input capture data registers (ipcp0 to ipcp3) corresponding to external input pins (in0 to in3) and input capture control registers (ics01, ics23). the input capture unit can capture the counter value of the 16-bit free-run timer into the input capture data register (ipcp0 to ipcp3) to generated an interrupt request upon detection of the effective edge of the signal input through the external input. 16-bit free-run timer 16-bit output compare 16-bit input capture 8/16-bit ppg timer 16-bit pwc timer 1 channel 4 channels 4 channels 8-bit 6 channels (16-bit 3 channels) 1 channel mb90330a series 47 the input capture unit in each channel can operate independently. the effective edge of the external signal can be selected (rising edge, falling edge, both edges). an interrupt request can be generated upon detection of the selected effective edge of the external sig- nal.(ics01, ics2 : ice0 = ?1?, ice1 = ?1?, ice2 = ?1?, ice3 = ?1?). ? register list (16-bit free-run timer) compare clear register (cpclr) timer data register (tcdt) timer control/status register (tccs) bit initial value address : 00008b h xxxxxxxx b bit initial value address : 00008a h xxxxxxxx b bit initial value address : 000087 h 00000000 b bit initial value address : 000086 h 00000000 b bit initial value address : 000089 h 0--00000 b bit initial value address : 000088 h 00000000 b 15 14 13 12 11 10 9 8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) cl14 cl15 cl13 cl12 cl11 cl10 cl09 cl08 76543210 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) cl06 cl07 cl05 cl04 cl03 cl02 cl01 cl00 15 14 13 12 11 10 9 8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) t14 t15 t13 t12 t11 t10 t09 t08 76543210 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) t06 t07 t05 t04 t03 t02 t01 t00 15 14 13 12 11 10 9 8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ? ecke ? msi2 msi1 msi0 iclr icre 76543210 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ivfe ivf stop mode sclr clk2 clk1 clk0 mb90330a series 48 ? register list (output compare) compare register (occp0 to occp3) control register (ocs1/ocs3) control register (ocs0/ocs2) address : bit 007919 h 00791b h 00791d h 00791f h initial value xxxxxxxx b address : bit 007918 h 00791a h 00791c h 00791e h initial value xxxxxxxx b bit initial value address : 000055 h 000057 h ---00000 b bit initial value address : 000054 h 000056 h 0000--00 b 15 14 13 12 11 10 9 8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) c14 c15 c13 c12 c11 c10 c09 c08 76 5 4 3 21 0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) c06 c07 c05 c04 c03 c02 c01 c00 15 14 13 12 11 10 9 8 ( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ? ?? cmod ote1 ote0 otd1 otd0 76543210 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ( r/w ) icp0 icp1 ice1 ice0 ?? cst1 cst0 mb90330a series 49 ? register list (input capture) input capture data register (ipcp0 to ipcp3) input capture control status register (ics23) input capture control status register (ics01) address : bit 007911 h 007913 h 007915 h 007917 h initial value xxxxxxxx b address : bit 007910 h 007912 h 007914 h 007916 h initial value xxxxxxxx b bit initial value address : 000053 h 00000000 b bit initial value address : 000052 h 00000000 b 15 14 13 12 11 10 9 8 ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) cp14 cp15 cp13 cp12 cp11 cp10 cp09 cp08 76543210 ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) cp06 cp07 cp05 cp04 cp03 cp02 cp01 cp00 15 14 13 12 11 10 9 8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) icp2 icp3 ice3 ice2 eg31 eg30 eg21 eg20 76543210 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) icp0 icp1 ice1 ice0 eg11 eg10 eg01 eg00 mb90330a series 50 ? block diagram of the 16-bit free-run timer, input capture units, and output compare units ivf 8 ivfe stop mode sclr clk2 clk1 clk0 iclr icp1 icp0 ioe1 ioe0 icp1 icp3 icp0 icp2 ice1 ice3 ice0 ice2 eg11 eg31 eg10 eg30 eg01 eg21 eg00 eg20 in0/in2 in1/in3 cmod tq tq icre msi2 to msi0 3 16 16 16 4 4 4 out0/out2 out1/out3 ote0 ote1 to interrupt #36 (24 h )* 16-bit free-run timer divider clock compare circuit 16-bit compare clear register compare register 0/2 compare circuit compare register 1/3 compare circuit to interrupt #36 (24 h )* to interrupt #29 (1d h )* #31 (1f h )* edge detection edge detection to interrupt #25 (19 h )* #27 (1b h )* capture data register 0/2 capture data register 1/3 internal data bus * : interrupt number : machine clock frequency mb90330a series 51 ? 8/16-bit ppg timer (8-bit : 6 channels, 16-bit : 3 channels) 8/16-bit ppg timer consists of an 8-bit down counter (pcnt), ppg operation mode control register (ppgc0 to ppgc5), ppg output control register (ppg01, ppg23, ppg45) and ppg reload register (prll0 to prll5, prlh0 to prlh5). when used as an 8-/16-bit reload timer, the ppg timer serves as an event timer. it can also output pulses of an arbitrary duty ratio at an arbitrary frequency. 8-bit ppg mode each channel operates as an independent 8-bit ppg. 8-bit prescaler + 8-bit ppg mode operates as an arbitrary-cycle 8-bit ppg with ppg0 (ppg2, ppg4) operating as an 8-bit prescaler and ppg1 (ppg3, ppg5) counted by the borrow output of ppg0 (ppg2, ppg4). 16-bit ppg mode operates as a 16-bit ppg with ppg0 (ppg2, ppg4) and ppg1 (ppg3, ppg5) connected. ppg operation the ppg timer outputs pulses of an arbitrary duty ratio (the ratio between the high and low level periods of pulse waveform) at an arbitrary frequency. this can also be used as a d/a converter by an external circuit. mb90330a series 52 ? register list ppg operation mode control register (ppgc1/ppgc3/ppgc5) (ppgc0/ppgc2/ppgc4) ppg output control register (ppg01/ppg23/ppg45) ppg reload register (prlh0 to prlh5) (prll0 to prll5) address : bit 000047 h 000049 h 00004b h initial value 0x000001 b address : bit 000046 h 000048 h 00004a h initial value 0x000xx1 b address : bit 00004c h 00004e h 000050 h initial value 000000xx b address : bit 007901 h 007903 h 007905 h 007907 h 007909 h 00790b h initial value xxxxxxxx b address : bit 007900 h 007902 h 007904 h 007906 h 007908 h 00790a h initial value xxxxxxxx b 15 14 13 12 11 10 9 8 ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ? pen1 pe10 pie1 puf1 md1 md0 reserved 7654321 0 ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ? pen0 pe00 pie0 puf0 ?? reserved 7654321 0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) pcs1 pcs2 pcs0 pcm2 pcm1 pcm0 reserved reserved 15 14 13 12 11 10 9 8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) d14 d15 d13 d12 d11 d10 d09 d08 76543210 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) d06 d07 d05 d04 d03 d02 d01 d00 mb90330a series 53 ? 8/16-bit ppg ch.0/ch.2/ch.4 block diagram ppg 0/ ppg 2/ ppg 4 pie0 pen0 puf0 irq s rq prll prlbh prll peripheral clock dividing by 16 peripheral clock dividing by 8 peripheral clock dividing by 4 peripheral clock dividing by 2 peripheral clock ppg0/ppg2/ppg4 output enable ppg0/ppg2/ppg4 output latch pcnt (down counter) ?l?/?h? selector ppgc0 (operating mode control) ?l? data bus ?h? data bus ?l?/?h? select count clock select dividing by 512 of timebase counter output main clock a/d converter ch.1/ch.3/ch.5 borrow * : interrupt number to interrupt #30 (1e h )* #32 (20 h )* #34 (22 h )* mb90330a series 54 ? 8-bit ppg ch.1/ch.3/ch.5 block diagram ppg1/ppg 3 /ppg5 pie1 pen1 puf1 irq s rq prll prlbh prll peripher a l clock dividing b y 16 peripher a l clock dividing b y 8 peripher a l clock dividing b y 4 peripher a l clock dividing b y 2 peripher a l clock ppg1/ppg 3 /ppg5 o u tp u t en ab le ppg1/ppg 3 /ppg5 o u tp u t l a tch pcnt (down co u nter) ?l ? / ? h ? s elector ppgc1 (oper a ting mode control) ? l ? d a t a bus ? h ? d a t a bus ? l ? / ? h ? s elect co u nt clock s elect dividing b y 512 time bas e co u nter o u tp u t m a in clock * : interrupt number to interrupt #30 (1e h )* #32 (20 h )* #34 (22 h )* mb90330a series 55 ? pwc timer the pwc timer is a 16-bit multi-function up-count ti mer capable of measuring the input signal pulse width. ? register list pwc control status register (pwcsr) pwc data buffer register (pwcr) pwc ratio of dividing frequency control register (divr) bit address : 00005d h initial value 0000000x b bit address : 00005c h initial value 00000000 b bit address : 00005f h initial value 00000000 b bit address : 00005e h initial value 00000000 b bit address : 000060 h initial value ------00 b ( r/w ) ( r ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r/w ) 15 14 13 12 11 10 9 8 stop ( r/w ) strt edir edie ovir ovie err reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543 210 cks0 ( r/w ) cks1 pis1 pis0 s/c mod2 mod1 mod0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 d14 ( r/w ) d15 d13 d12 d11 d10 d9 d8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( ? )( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ????? div1 div0 mb90330a series 56 ? block diagram err pwcr 16 16 cks1/cks0 15 err cks0/cks1 pis0/pis1 pwcsr divr 2 2 2 2 3 pwc pwcr read error detection reload data transfer overflow 16-bit up count timer clock internal clock (machine clock/4) clock divider control circuit timer clear count enable divider clear flag set etc... control bit output start edge selection measurement termination edge end edge selection edge detection divider on/off measurement starting edge overflow interrupt request divide ratio select 8-bit divider f 2 mc-16 bus measurement termination interrupt request input waveform comparator mb90330a series 57 7. uart uart is a general purpose serial communication interf ace for synchronous or asynchronous (start-stop syn- chronization) communications with external devices. it supports bi-directional communication (normal mode) and master/slave communication (multi-processor mode: supported on master side only). an interrupt can be generated upon completion of reception, detection of a reception error, or completion of transmission. ei 2 os is supported. ? uart functions uart, or a generic serial data communication interface that sends and receives serial data to and from other cpu and peripherals, has the functions listed in following. note : in clock synchronous transfer mode, the uart transfers only data with no start or stop bit added. ? uart operation modes ? : setting disabled *1 : + 1 is an address/data setting bit (a/d) which is used for communication control. *2 : only one bit can be detected as a stop bit at reception. operation mode data length synchronization stop bit length without parity with parity 0 normal mode 7-bit or 8-bit asynchronous 1-bit or 2-bit * 2 1 multi processor mode 8-bit + 1* 1 ? asynchronous 2 normal mode 1 to 8-bit ? synchronous no function data buffer full-duplex double-buffered transmission mode clock synchronous (without start/stop bit) clock asynchronous (start-stop synchronous) baud rate special-purpose baud-rate generator it is optional from 8 kinds. baud rate by external clock (sck0/sck1/sck2/sck3 terminal input) data length 8-bit or 7-bit (in the asynchronous normal mode only) 1-bit to 8-bit (synchronous mode only) signal system non return to zero (nrz) system reception error detection framing error overrun error parity error (not supported in operation mode 1) interrupt request receive interrupt (reception completed, reception error detected) transmission interrupt (transmission completed) both the transmission and reception support ei 2 os. master/slave type communication function (multi processor mode) capable of 1 (master) to many (slaves) communication (available just as master) mb90330a series 58 ? register list serial mode register (smr0 to smr3) serial control register (scr0 to scr3) serial input/output data register (sidr0 to sidr3 / sodr0 to sodr3) serial status register (ssr0 to ssr3) uart prescaler reload regi ster (utrlr0 to utrlr3) uart prescaler control regi ster (utcr0 to utcr3) bit initial value address : 000020 h 000026 h 00002c h 000032 h 00100000 b bit initial value address : 000021 h 000027 h 00002d h 000033 h 00000100 b bit initial value address : 000022 h 000028 h 00002e h 000034 h xxxxxxxx b bit initial value address : 000023 h 000029 h 00002f h 000035 h 00001000 b bit initial value address : 000024 h 00002a h 000030 h 000036 h 00000000 b bit initial value address : 000025 h 00002b h 000031 h 000037 h 0000-000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 md0 ( r/w ) md1 sckl m2l2 m2l1 scke soe m2l0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 p ( r/w ) pen sbl cl a/d rec rxe txe ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( r ) ( r ) ( r ) ( r ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ore ( r ) pe fre rdrf tdre bds rie tie ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( r/w ) ( r/w ) ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 srst ( r/w ) md cks ? d10 d9 d8 reserved mb90330a series 59 ? block diagram md1 md0 sckl m2l2 m2l1 m2l0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre bds rie tie sidr0 to sidr3 sck0 to sck3 sot0 to sot3 sin0 to sin3 sodr0 to sodr3 control bus special-purpose baud-rate generator (uart prescaler control register utcr0 to utcr3) (uart prescaler reload utrlr0 to utrlr3) clock selector receive status decision circuit reception error occurrence signal for ei 2 os ? dmac (to cpu) reception clock reception control circuit start bit detection circuit reception bit counter reception parity counter shift register for reception reception complete internal data bus transmission clock reception interrupt signal #39 (27 h )* #35 (23 h )* transmission control circuit transmission start circuit transmission bit counter transmission parity counter shift register for transmission start transmission smr0 to smr3 * : interrupt number scr0 to scr3 ssr0 to ssr3 send interrupt signal #37 (25 h )* #33 (21 h )* pin pin pin mb90330a series 60 8. extended i/o serial interface the extended i/o serial interface is a serial i/o interface in an 8-bit, single-channel, capable of clock synchronous data transfer. lsb-first or msb-first transfer mode can be selected for data transfer. there are 2 serial i/o operation modes available: internal shift clock mode: transfer data in synchronization with the internal clock. external shift clock mode: transfer data in synchronizati on with the clock supplied via the external pin (sck). by manipulating the general-purpose port sharing the external pin (sck) in this mode, data can also be transferred by a cpu instruction. ? register list serial mode control status register (smcs) serial data register (sdr) communication prescaler c ontrol register (sdcr) bit initial value address : 000059 h 00000010 b bit initial value address : 000058 h xxxx0000 b bit initial value address : 00005a h xxxxxxxx b bit initial value address : 00005b h 0xxx0000 b 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt ( r/w ) ( r ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3210 ? ??? mode bds soe scoe ( ? ) ( ? ) ( ? ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76 5 4 3 21 0 d6 d7 d5 d4 d3 d2 d1 d0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( r/w ) md ?? div3 div2 div1 div0 mb90330a series 61 ? block diagram sin sot sck smd2 smd1 smd0 sie sir busy stop strt mode bds 21 0 soe scoe (msb fast) d0 to d7 d7 to d0 (lsb fast) sdr (serial data register) internal clock internal data bus transfer direction selection read write control circuit shift clock counter interrupt request internal data bus initial value mb90330a series 62 9. i 2 c interface the i 2 c interface is a serial i/o port supporting the inter ic bus. it serves as a master/slave device on the i 2 c bus and has the following features. master/slave sending and receiving arbitration function clock synchronization function slave address and general call address detection function detecting transmitting direction function start condition repeated generation and detection function bus error detection function ? register list i 2 c bus status register (ibsr0 to ibsr2) i 2 c bus control register (ibcr0 to ibcr2) i 2 c bus clock control register (iccr0 to iccr2) i 2 c bus address register (iadr0 to iadr2) i 2 c bus data register (idar0 to idar2) bit initial value address : 000070 h 000076 h 00007c h 00000000 b bit initial value address : 000071 h 000077 h 00007d h 00000000 b bit initial value address : 000072 h 000078 h 00007e h xx0xxxxx b bit initial value address : 000073 h 000079 h 00007f h xxxxxxxx b bit initial value address : 000074 h 00007a h 000080 h xxxxxxxx b ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 rsc ( r ) bb al lrb trx aas gca fbt ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 beie ( r/w ) ber scc mss ack gcaa inte int ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ? en cs4 cs3 cs2 cs1 cs0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 a6 ( ? ) ? a5 a4 a3 a2 a1 a0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 mb90330a series 63 ? block diagram iccrx en iccrx ibsrx bb rsc lrb last bit trx fbt al ibcrx ber beie inte int ibcrx scc mss ack gcaa ibsrx idar iadr aas gca cs4 cs3 cs2 cs1 cs0 2 4 8 16 128 256 32 64 56 78 sync first byte irq sclx sdax i 2 c enable clock divide 2 clock selector 2 bus busy repeat start send/receive start stop condition generation arbitration lo st detection interrupt request start master ack enable gc-ack enable slave global call slave address compare end error shift clock edge change timing start stop condition detection generating shift clock f 2 mc-16 bus clock divide 1 clock selector 1 peripheral clock mb90330a series 64 10. usb function the usb function is an interface supporting the u sb (universal serial bus) communications protocol. ? feature of usb function correspond to usb full speed full speed (12 mbps) is supported. the device status is auto-answer. bit stripping, bit stuffi ng, and automatic generation and check of crc5 and crc16 toggle check by data synchronization bit automatic response to all standard commands except get/setdescriptor and synchframe commands (these 3 commands can be processed the same way as the class vendor commands). the class vendor commands can be received as data and responded via firmware. supports up to 6 endpoints (endpoint0 is fixed to control transfer) 2 transfer data buffers integrated for each end point (one in buffer and one out buffer for endpoint 0) supports automatic transfer mode for transfer data via dma (except buffers for endpoint 0) ? register list (continued) udc control register (udcc) ep0 control register (ep0c) ep1 control register (ep1c) bit initial value address : 0000d0 h 10100000 b bit initial value address : 0000d1 h 00000000 b bit initial value address : 0000d2 h 01000000 b bit initial value address : 0000d3 h xxxx0000 b bit initial value address : 0000d4 h 00000000 b bit initial value address : 0000d5 h 01100001 b ( r/w ) ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ( r/w ) 76 5 4 3 21 0 re s um ( r/w ) r s t hcon u s tp rfbk pwc reserved reserved ( ? )( ? )( ? )( ? )( ? )( ? )( ? ) 15 14 13 12 11 10 9 8 ( ? ) reserved reserved reserved reserved reserved reserved reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 pks0 ( ? ) pks0 pks0 pks0 pks0 pks0 pks0 reserved ( ? )( ? )( ? )( ? )( ? ) ( r/w ) ( ? ) 15 14 13 12 11 10 9 8 ? ( ? ) ??? stal reserved reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 pks1 ( r/w ) pks1 pks1 pks1 pks1 pks1 pks1 pks1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 type ( r/w ) epen type dir dmae nule stal pks1 mb90330a series 65 (continued) ep2/3/4/5 control register (ep2c to ep5c) time stamp register (tmsp) udc status register (udcs) udc interrupt enable register (udcie) ep0i status register (ep0is) address : bit 0000d6 h 0000d8 h 0000da h 0000dc h initial value 01000000 b address : bit 0000d7 h 0000d9 h 0000db h 0000dd h initial value 01100000 b bit initial value address : 0000de h 00000000 b bit initial value address : 0000df h xxxxx000 b bit initial value address : 0000e0 h xx000000 b bit initial value address : 0000e1 h 00000000 b bit initial value address : 0000e2 h xxxxxxxx b bit initial value address : 0000e3 h 10xxx1xx b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543 2 1 0 pks2 to 5 ( r/w ) pks2 to 5 pks2 to 5 pks2 to 5 pks2 to 5 pks2 to 5 pks2 to 5 reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 type ( r/w ) epen type dir dmae nule stal reserved ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 tmsp ( r ) tmsp tmsp tmsp tmsp tmsp tmsp tmsp ( ? )( ? )( ? )( ? ) ( r ) ( r ) ( r ) 15 14 13 12 11 10 9 8 ? ( ? ) ???? tmsp tmsp tmsp ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ? susp sof brst wkup setp conf ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r/w ) 15 14 13 12 11 10 9 8 ( ? ) suspie sofie brstie wkupie confn confie reserved reserved ( ? )( ? )( ? )( ? )( ? )( ? )( ? ) 76543210 ? ( ? ) ?????? ? ( r/w ) ( ? )( ? )( ? ) ( r/w ) ( ? )( ? ) 15 14 13 12 11 10 9 8 drqiie ( r/w ) bfini ??? drqi ?? mb90330a series 66 (continued) ep0o status register (ep0os) ep1 status register (ep1s) ep2/3/4/5 status regi ster (ep2s to ep5s) ep0/1/2/3/4/5 data register (ep0dt to ep5dt) bit initial value address : 0000e4 h 0xxxxxxx b bit initial value address : 0000e5 h 100xx000 b bit initial value address : 0000e6 h xxxxxxxx b bit initial value address : 0000e7 h 1000000x b address : bit 0000e8 h 0000ea h 0000ec h 0000ee h initial value xxxxxxxx b ; address : bit 0000e9 h 0000eb h 0000ed h 0000ef h initial value 10000000 b address : bit 0000f0 h 0000f2 h 0000f4 h 0000f6 h 0000f8 h 0000fa h initial value xxxxxxxx b address : bit 0000f1 h 0000f3 h 0000f5 h 0000f7 h 0000f9 h 0000fb h initial value xxxxxxxx b ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 size ( ? ) size size size size size size reserved ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ( r/w ) ( ? ) 15 14 13 12 11 10 9 8 drqoie ( r/w ) bfini spkie ?? drqo spk reserved ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 size ( r ) size size size size size size size ( r/w ) ( r/w ) ( ? ) ( r ) ( r/w ) ( r/w ) ( r ) 15 14 13 12 11 10 9 8 drqie ( r/w ) bfini spkie busy drq spk size reserved ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 size ( ? ) size size size size size size reserved ( r/w ) ( r/w ) ( ? ) ( r ) ( r/w ) ( r/w ) ( ? ) 15 14 13 12 11 10 9 8 drqie ( r/w ) bfini spkie busy drq spk reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 bfdt ( r/w ) bfdt bfdt bfdt bfdt bfdt bfdt bfdt ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 bfdt ( r/w ) bfdt bfdt bfdt bfdt bfdt bfdt bfdt mb90330a series 67 11. usb mini-host usb mini-host provides minimal host operations required and is a function that enables data to be transferred to and from device without pc intervention. ? feature of usb mini-host automatic detection of low speed/full speed transfer low speed/full speed transfer support automatic detection of connection and cutting device reset sending function support to usb-bus support of in/out/setup/sof token in-token handshake packet automatic transmission (excluding stall) out-token handshake packet automatic detection supports a maximum packet length of 256 bytes. error (crc erro r/toggle error/time-o ut) various supports wake-up function support ? differences between the usb host and usb mini-host : supported : not supported host mini-host hub support transfer bulk transfer control transfer interrupt transfer iso transfer transfer speed low speed full speed pre packet support sof packet support error crc error toggle error time-out maximum packet < receive data detection of connection and cutting of device transfer speed detection mb90330a series 68 ? register list (continued) host control register 0 (hcnt0) host control register 1 (hcnt1) host interruption register (hirq) host error status register (herr) host state status register (hstate) sof interruption frame comparison register (hfcomp) bit initial value address : 0000c0 h 00000000 b bit initial value address : 0000c1 h 00000001 b bit initial value address : 0000c2 h 00000000 b bit initial value address : 0000c3 h 00000011 b bit initial value address : 0000c4 h xx010010 b bit initial value address : 0000c5 h 00000000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 urire ( r/w ) rwkire cmpire cnnire dire sofire urst host ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ( r/w ) sofstep cancel retry reserved reserved reserved reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ( r/w ) tcan rwkirq urirq cmpirq cnnirq dirq sofirq reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rerr ( r/w ) lstsof tout crc tgerr stuff hs hs ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r ) 76543210 ? ( ? ) ? alive clksel sofbusy susp tmode cstat ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ( r/w ) frame comp frame comp frame comp frame comp frame comp frame comp frame comp frame comp mb90330a series 69 (continued) retry timer setting register (hrtimer) host address register (hadr) eof setting register (heof) frame setting register (hframe) host token end point register (htoken) bit initial value address : 0000c6 h 00000000 b bit initial value address : 0000c7 h 00000000 b bit initial value address : 0000c8 h xxxxxx00 b bit initial value address : 0000c9 h x0000000 b bit initial value address : 0000ca h 00000000 b bit initial value address : 0000cb h xx000000 b bit initial value address : 0000cc h 00000000 b bit initial value address : 0000cd h xxxxx000 b bit initial value address : 0000ce h 00000000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 rtimer0 ( r/w ) rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rtimer1 ( r/w ) rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 ( ? )( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ????? rtimer2 rtimer2 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 address ( ? ) ? addressaddressaddressaddressaddressaddress ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 eof0 ( r/w ) eof0 eof0 eof0 eof0 eof0 eof0 eof0 ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ? eof1 eof1 eof1 eof1 eof1 eof1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 frame0 ( r/w ) frame0 frame0 frame0 frame0 frame0 frame0 frame0 ( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ???? frame1 frame1 frame1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 tknen ( r/w ) tggl tknen tknen endpt endpt endpt endpt mb90330a series 70 12. 8/10-bit a/d converter the a/d converter converts analog input voltages into digital values and has the following features. rc sequential compare conversion method with sample and hold circuit selectable 8-bit resolution or 10-bit resolution analog input program-selectable from among 16 channels single conversion mode : convert 1 selected channel scan conversion mode : continuous plural channels (max imum 16 channels can be programmed) are converted. continuous conversion mode : repeatedly convert the specified channels. stop conversion mode: convert 1 channel then suspend conversion to remain on standby until the next activation (simultaneous conversion start available). an interrupt request to the cpu can be generated upon completion of a/d conversion. suitable for continuous processing as this interrupt activates dma to transfer the data resulting from a/d conversion to memory. the activation source can be selected from among software, external trig ger (falling edge), and timer (rising edge). ? register list a/d control status register lower/upper (adcs0/adcs1) a/d data register lowe r/upper (adcr0/adcr1) a/d conversion channel selection register (admr) bit initial value address : 000040 h 00 - - - - - 0 b bit initial value address : 000041 h 00000000 b bit initial value address : 000042 h xxxxxxxx b bit initial value address : 000043 h 00101xxx b bit initial value address : 000045 h 00000000 b ( r/w ) ( ? )( ? )( ? )( ? )( ? ) ( r/w ) 76543210 md0 ( r/w ) md1 ????? reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( w ) ( r/w ) 15 14 13 12 11 10 9 8 int ( r/w ) busy inte paus sts1 sts0 strt reserved ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 765432 10 d6 ( r ) d7 d5 d4 d3 d2 d1 d0 ( w ) ( w ) ( w ) ( w ) ( ? ) ( r ) ( r ) 15 14 13 12 11 10 9 8 st1 ( r/w ) s10 st0 ct1 ct0 ? d9 d8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ans2 ( r/w ) ans3 ans1 ans0 ane3 ane2 ane1 ane0 mb90330a series 71 ? block diagram mp adtg an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 adcr0, adcr1 adcs0, adcs1 av cc avrh av ss admr input circuit d/a converter sequential comparison register data register a/d control status register upper a/d control status register lower prescaler operating clock trigger start timer start decoder comparator sample & hold circuit timer (ppg1 output) data bus conversion channel selection mb90330a series 72 13. dtp/external interrupt circuit dtp (data transfer peripheral)/external interrupt circui t detects the interrupt request input from the external interrupt input terminal (int7 to int0) , and outputs the interrupt request. ? dtp/external interrupt circuit function the dtp/external interrupt function outputs an interrupt request upon detection of the edge or level signal input to the external interrupt input pins (int7 to int0). if cpu accepts the interrupt request, and if the extended intellig ent i/o service (ei 2 os) is enabled, branches to the interrupt handling routine after completing the automatic data transfer (dtp function) performed by ei 2 os. and if ei 2 os is disabled, it branches to the interrupt handling routine without activating the automatic data transfer (dtp function) performed by ei 2 os. ? overview of dtp/external interrupt circuit external interrupt dtp function input pin 8 channels (p60/int0, p61/int1, p62/int2/sin, p63/int3/sot, p64/int4/sck, p65/int5/pwc, p66/int6/scl0, p67/int7/sda0) interrupt source the detection level or the type of the edge for each terminal can be set in the request level setting register (elvr). input of h level/l level/rising edge/falling edge. interrupt number #18 (12 h ), #20 (14 h ), #22 (16 h ), #24 (18 h ) interrupt control enabling/disabling the interrupt request output using the dtp/interrupt enable register (enir) interrupt flag holding the interrupt causes using the dtp/interrupt cause register (eirr) process setting disable ei 2 os (icr: ise=?0?) enable ei 2 os (icr: ise=?1?) process branched to the interrupt handling routine after an automatic data transfer by ei 2 os, branched to the interrupt handling routine mb90330a series 73 ? register list dtp/interrupt enable register (enir) dtp/interrupt source register (eirr) request level setting register (elvr) bit initial value address : 00003c h 00000000 b bit initial value address : 00003d h 00000000 b bit initial value address : 00003e h 00000000 b bit initial value address : 00003f h 00000000 b 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) en6 en7 en5 en4 en3 en2 en1 en0 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) er6 er7 er5 er4 er3 er2 er1 er0 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) la3 lb3 lb2 la2 lb1 la1 lb0 la0 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) la7 lb7 lb6 la6 lb5 la5 lb4 la4 mb90330a series 74 ? block diagram lb7 er7 er6 er5 er4 er3 er2 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 p60/int0 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 p61/int1 p62/int2/ sin p63/int3/ sot #18(12 h ) * #20(14 h ) * #22(16 h ) * #24(18 h ) * 22222222 p64/int4/ sck p65/int5/ pwc p66/int6/ scl0 p67/int7/ sda0 request level setting register (elvr) pin pin pin pin selector selector selector selector selector selector selector selector pin pin pin pin interrupt request signal internal data bus dtp/interrupt source register (eirr) dtp/interrupt enable register (enir) * : interrupt number dtp/external interrupt input detection circuit mb90330a series 75 14. interrupt controller the interrupt control register is located inside the interrupt controller; it exists for every i/o having an interrupt function. this register has the following functions. setting of the interrupt levels of relevant resources ? register list note : do not access interrupt control registers using any read modify write instruction because it causes a malfunction. ? block diagram interrupt control register (icr01, icr03, icr05, icr07, icr09, icr11, icr13, icr15) interrupt control register (icr00, icr02, icr04, icr06, icr08, icr10, icr12, icr14) bit initial value 00000111 b address : icr01 : 0000b1 h icr03 : 0000b3 h icr05 : 0000b5 h icr07 : 0000b7 h icr09 : 0000b9 h icr11 : 0000bb h icr13 : 0000bd h icr15 : 0000bf h bit initial value 00000111 b address : icr00 : 0000b0 h icr02 : 0000b2 h icr04 : 0000b4 h icr06 : 0000b6 h icr08 : 0000b8 h icr10 : 0000ba h icr12 : 0000bc h icr14 : 0000be h ( w ) ( w ) ( w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ics2 ( w ) ics3 ics1 ics0 il2 il1 il0 ise ( w ) ( w ) ( w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ics2 ( w ) ics3 ics1 ics0 il2 il1 il0 ise il2 il1 il0 32 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 determine priority of interrupt interrupt request (peripheral resource) (cpu) interrupt level f 2 mc-16lx bus mb90330a series 76 15. dmac dmac is simple dma with the function equal with ei 2 os. it has 16 channels dma transfer channels with the following features. performs automatic data transfer between the peripheral resource (i/o) and memory the program execution of cpu stops in the dma start-up capable of selecting whether to increment the transfer source and destination addresses dma transfer is controlled by the dma enable register, dma stop status register, dma status register, and descriptor. a stop request is available for stopping dma transfer from the resource. upon completion of dma transfer, the flag bit corresponding to the transfer completed channel in the dma status register is set and a termination interrupt is output to the transfer controller. ? register list (continued) dma enable register upper (derh) dma enable register lower (derl) dma stop status register (dssr) dma status register upper (dsrh) dma status register lower (dsrl) dma descriptor channel specification register (dcsr) * : the dssr is lower when the stp bit of dcsr in the dssr is ?0?. the dssr is upper when the stp bit of dcsr in the dssr is ?1?. bit initial value address : 0000ad h 00000000 b bit initial value address : 0000ac h 00000000 b bit initial value address : 0000a4 h 00000000 b * bit initial value address : 00009d h 00000000 b bit initial value address : 00009c h 00000000 b bit initial value address : 00009b h 00000000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 en14 ( r/w ) en15 en13 en12 en11 en10 en9 en8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 en6 ( r/w ) en7 en5 en4 en3 en2 en1 en0 76543210 stp6 stp14 stp7 stp15 stp5 stp13 stp4 stp12 stp3 stp11 stp2 stp10 stp1 stp9 stp0 stp8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 dte14 dte15 dte13 dte12 dte11 dte10 dte9 dte8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3210 dte6 ( r/w ) dte7 dte5 dte4 dte3 dte2 dte1 dte0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ( r/w ) stp dcsr3 dcsr2 dcsr1 dcsr0 reserved reserved reserved mb90330a series 77 (continued) dma buffer address pointer lower 8-bit (dbapl) dma buffer address point er middle 8-bit (dbapm) dma buffer address point er upper 8-bit (dbaph) dma control register (dmacs) dma i/o register address pointer lower 8-bit (dioal) dma i/o register address pointer upper 8-bit (dioah) dma data counter lower 8-bit (ddctl) dma data counter up per 8-bit (ddcth) note : the above register is switched for each channel depending on the dcsr. bit initial value address : 007920 h xxxxxxxx b bit initial value address : 007921 h xxxxxxxx b bit initial value address : 007922 h xxxxxxxx b bit initial value address : 007923 h xxxxxxxx b bit initial value address : 007924 h xxxxxxxx b bit initial value address : 007925 h xxxxxxxx b bit initial value address : 007926 h xxxxxxxx b bit initial value address : 007927 h xxxxxxxx b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 dbapl ( r/w ) dbapl dbapl dbapl dbapl dbapl dbapl dbapl 15 14 13 12 11 10 9 8 dbapm dbapm dbapm dbapm dbapm dbapm dbapm dbapm ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 dbaph dbaph dbaph dbaph dbaph dbaph dbaph dbaph ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rdy1 rdy2 bytel if bw bf dir se ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 a06 ( r/w ) a07 a05 a04 a03 a02 a01 a00 15 14 13 12 11 10 9 8 a14 a15 a13 a12 a11 a10 a09 a08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 b06 b07 b05 b04 b03 b02 b01 b00 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 b14 b15 b13 b12 b11 b10 b09 8 b08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) mb90330a series 78 16. external bus pin control circuit the external bus pin control circuit controls external bus pins to extend the cpu address and data buses to externals. ? register list ? block diagram ? automatic ready function selection register (arsr) ? external address output control register (hacr) ? bus control signal sele ction register (epcr) bit initial value address : 0000a5 h 0011- - 00 b bit initial value address : 0000a6 h * * * * * * * * b bit initial value address : 0000a7 h 1000*10 - b w ? * :write only :unused :?1? or ?0? (w) (w) (w) ( ? )( ? ) (w) (w) 15 14 13 12 11 10 9 8 icr0 (w) icr1 hmr1 hmr0 ?? lmr1 lmr0 (w) (w) (w) (w) (w) (w) (w) 76543210 e22 (w) e23 e21 e20 e19 e18 e17 e16 (w) (w) (w) (w) (w) (w) ( ? ) 15 14 13 12 11 10 98 rye (w) cke hde reserved hmbs (w)re lmbs ? p3 p2 p1 p0 p0 p5 rb p4 p5 access control access control address control data control p0 direction p0 data mb90330a series 79 17. address matching detection function when the address is equal to the value set in the address detection register, the instruction code to be read into the cpu is forcibly replaced wit h the int9 instruction code (01 h ). as a result, the cpu executes the int9 instruction when executing the set instruction. by performing processing by the int#9 interrupt routine, the program patch function is enabled. 2 address detection registers are provided, for each of which there is an interrupt enable bit. when the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the cpu is forcibly replaced with the int9 instruction code. ? register list ? program address detect register 0 to 2 (padr0) ? program address detect register 3 to 5 (padr1) ? program address detection control status register (pacsr) padr0 (lower) bit initial value xxxxxxxx b address : 001ff0 h padr0 (middle) bit initial value xxxxxxxx b address : 001ff1 h padr0 (upper) bit initial value xxxxxxxx b address : 001ff2 h padr1 (lower) bit initial value xxxxxxxx b address : 001ff3 h padr1 (middle) bit initial value xxxxxxxx b address : 001ff4 h padr1 (upper) bit initial value xxxxxxxx b address : 001ff5 h pacsr bit initial value 00000000 b address : 00009e h (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) adie adde reserved reserved reserved reserved reserved reserved r/w : readable and writable x : undefined mb90330a series 80 18. delay interrupt generator module the delay interrupt generation module is a module that generates interrupts for switching tasks. a hardware interrupt can be generated by software. ? delay interrupt generator module function ? block diagram function and control interrupt source ? setting the r0 bit in the delayed interrupt request generation/release register to 1 (dirr: r0 = 1) generates a delayed interrupt request. ? setting the r0 bit in the delayed interrupt request generation/release register to 0 (dirr: r0 = 0) cancels the delayed interrupt request. interrupt control no setting of permission register is provided. interrupt flag set in bit r0 of the delayed interrupt request generation /clear register (dirr : r0) ei 2 os support not ready for exte nded intelligent i/o service (ei 2 os). ??????? r0 internal data bus delay interrupt factor generation/release register(dirr) s interrupt request r latch ? : undefined interrupt request signal mb90330a series 81 19. rom mirror function selection module the rom mirror function select module can make a setting so that rom data located in bank ff can be read by accessing bank 00. ? rom mirroring function selection module function ? block diagram description mirror setting address ffffff h to ff8000 h in the ff bank can be read through 00ffff h to 008000 h in the 00 bank. interrupt source none. ei 2 os support not ready for extended intelligent i/o service (ei 2 os) . ?????? mi rom internal data bus rom mirror function selection register (romm) 00 bank ff bank address data address area re- served mb90330a series 82 20. low power consumption (standby) mode the f 2 mc-16lx can be set to save power consumption by selecting and setting the low power consumption mode. ? cpu operation mode and functional description ? register list cpu operating clock operation mode description pll clock normal run the cpu and peripheral resources operate at the clock frequency obtained by pll multiplication of oscillator clock (hclk) frequency. sleep only peripheral resources operate at the clock frequency obtained by pll multiplica- tion of the oscillator clock (hclk) . time-base timer only the time-base timer operates at the clock frequency obtained by pll multiplica- tion of the oscillator clock (hclk) frequency. stop the cpu and peripheral re sources are suspe nded with the osc illator clock stopped. main clock normal run the cpu and peripheral resources operate at the clock frequency obtained by divid- ing the oscillator clock (hclk) frequency by two. sleep only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (hclk) frequency by two. time-base timer only the time-base timer operates at the clock frequency obtained by dividing the oscillator clock (hclk) frequency by two. stop the cpu and peripheral re sources are suspe nded with the osc illator clock stopped. sub clock normal run the cpu and peripheral resources operate at the clock frequency obtained by dividing the sub clock (scl k) frequency by four. sleep only peripheral resources operate at the clock frequency obtained by dividing the sub clock (sclk) frequency by four. watch mode only the watch timer operates at the clock frequency obtained by dividing the sub clock (sclk) frequency by four. stop the cpu and peripheral resources are suspended with the sub clock stopped. cpu intermittent operation mode normal run the halved or pll-multiplied oscillator clock (hclk) fr equency or th e sub clock (sclk) frequency is used for operation while being decimated in a certain period. low power consumption mode control register (lpmcr) bit initial value address : 0000a0 h 00011000 b ( w ) ( r/w ) ( w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 slp ( w ) stp spl rst tmd cg1 cg0 reserved mb90330a series 83 21. clock the clock generator controls the internal clock as the operating clock for the cpu and peripheral resources. the internal clock is referred to as machine clock whose on e cycle is defined as machine cycle. the clock based on source oscillation is referred to as oscillator clock while the clock based on internal pll oscillation is referred to as pll clock. ? register list clock selection register (ckscr) bit initial value address : 0000a1 h 11111100 b ( r ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 mcm ( r ) scm ws1 ws0 scs mcs cs1 cs0 mb90330a series 84 22. 3 mbits flash memory the description that follows applies to the flash memory bu ilt in the MB90F334A; it is not applicable to evaluation rom or mask rom. the flash memory is located in bank ff in the cpu memory map. ? function to flash memory description memory capacity 3072 kbits (384 kbytes) memory configuration 384 kwords 8 bits/192 kwords 16 bits sector configuration 64 kbytes 5 + 32 kbytes + 8 kbytes 2 + 16 kbytes sector protect function possi bility that set up with a reco mmendation parallel writer program algorithm automatic program algorithm (e mbedded algorithm : similar to mbm29lv400tc) operation command ? compatibility with the je dec standard -type command ? built-in deletion pause/deletion resume function ? detection of programming/ erasure completion using data polling and the toggle bit ? capable of erasing data sector by sector (in arbitrary combination of sectors) program/erase cycle at least 10000 times guaranteed how to program and erase memory ? parallel programmer available for programming and erasure (flash support group, inc. : af9708, af9709, af9709b) ? can be written and erased using a dedicated serial writer (yokogawa digital computer corporation : af220/af210/af120/af110) ? write/delete operation by program execution interrupt source programming/erasure completion sources ei 2 os supports not ready for expanded intelligent i/o service (ei 2 os). mb90330a series 85 ? sector configuration of flash memory ? register list s a0 (64 k b yte s ) prohi b ited prohi b ited s a1 (64 k b yte s ) f 8 0000 h f 8 ffff h f90000 h f9ffff h fa0000 h faffff h fb0000 h fbffff h 00000 h 0ffff h 10000 h 1ffff h 20000 h 2ffff h 3 0000 h 3 ffff h s a2 (64 k b yte s ) fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h ff7fff h 40000 h 4ffff h 50000 h 5ffff h 60000 h 6ffff h 70000 h 77fff h s a 3 (64 k b yte s ) s a4 (64 k b yte s ) s a5 ( 3 2 k b yte s ) s a6 ( 8 k b yte s ) s a7 ( 8 k b yte s ) s a 8 (16 k b yte s ) ff 8 000 h ff9fff h ffa000 h ffbfff h ffc000 h ffffff h 7 8 000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h flash memory cpu address writer address * * : the writer address is relative to the cpu address when data is programmed into flash memory by a parallel programmer. programming and erasing by the general-purpose parallel programmer are executed based on writer addresses. flash memory control status register (fmcs) bit initial value address : 0000ae h 000x0000 b ( r/w ) ( r/w ) ( r ) ( w ) ( r/w ) ( w ) ( r/w ) 7654 3 210 rdyint ( r/w ) inte we rdy lpm1 lpm0 reserved reserved mb90330a series 86 ? standard configuration for fujitsu microelectronics standard serial on-board writing the flash microcontroller programmer (af220/af210/af120/af110) made by yokogawa digital computer cor- poration is used for fujitsu microelectronics standard serial on-board writing. note : inquire of yokogawa digital computer corporation for details about the functions and operations of the af220, af210, af120 and af110 flash microcontroller programmer, general-purpose common cable for connection (az210) and connectors. ? pins used for fujitsu microelectronics standard serial on-board programming pin function description md2, md1, md0 mode input pins the device enters the serial program mode by setting md2=1, md1=1 and md0 =0. x0, x1 oscillation pins because the internal cpu operation clo ck is set to be the 1 multiplication pll clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. p60, p61 programming program start pins input a low level to p60 and a high level to p61. rst reset input pin ? sin0 serial data input pins. uart0 is used as clk synchronous mode. in program mode, the pins used for the uart0 clk synchronous mode are sin0, sot0 and sck0. sot0 serial data output pin sck0 serial clock input pin v cc power source input pin when supplying the write voltage (MB90F334A : 3.3 v 0.3 v) from the user system, connection with the flash microcontroller programmer is not necessary. when connecting, do not short-circuit with the user power supply. v ss gnd pin share gnd with the flash microcontroller programmer. host interface cable (az201) general-purpose common cable (az210) clk synchronous serial MB90F334A user system rs232c can operate stand alone flash microcontroller programmer + memory card mb90330a series 87 the control circuit shown in the figure is required for using the p60, p61, sin0, sot0 and sck0 pins on the user system. isolate the user circuit during serial on-b oard writing, with the /tics signal of the flash microcon- troller programmer. the MB90F334A serial clock frequency that can be input is determined by the following expression: use the flash microcontroller programmer to change the serial clock input frequency setting depending on the oscillator clock freq uency to be used. inputable serial clock frequency = 0.125 oscillation clock frequency. ? maximum serial clock frequency ? system configuration of the flash microcontroller prog rammer (af220/af210/af120/af110) (made by yokogawa digital computer corporation) contact to : yokogawa digital computer corporation tel : 81-423-33-6224 note : the af200 flash microcontroller programmer is a retired product, but it can be supported using control module ff201. oscillation clock frequency maximum serial clock frequency acceptable to the flash microcontroller maximum serial clock frequency that can be set with the af220, af210, af120 or af110 maximum serial clock frequency that can be set with the af200 at 6 mhz 750 khz 500 khz 500 khz part number function unit af220/ac4p model with internal ethernet interface /100 v to 220 v power adapter af210/ac4p standard model /100 v to 220 v power adapter af120/ac4p single key internal ethernet interface mode /100 v to 220 v power adapter af110/ac4p single key model /100 v to 220 v power adapter az221 pc/at rs232c cable for writer az210 standard target probe (a) length : 1 m ff201 control module for fujit su microelectronics f 2 mc-16lx flash microcontroller control module az290 remote controller /p4 4 mbytes pc card (option) flash memory capacity to 512 kbytes correspondence 10 k ? af220, af210, af120, af110 program control pin af220, af210, af120, af110, /tics pin MB90F334A program control pin user ? control circuit mb90330a series 88 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss = av ss = 0.0 v. *2 : be careful not to let av cc exceed v cc , for example, when the power is turned on. *3 : be careful not to let avrh exceed avcc. *4 : v i and v o must not exceed vcc + 0.3 v. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *5 : applicable to pins : p60 to p67, p96, pa0 to pa7, pb0 to pb4, utest (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 4.0 v av cc v ss ? 0.3 v ss + 4.0 v v cc av cc * 2 avrh v ss ? 0.3 v ss + 4.0 v av cc avr 0 v* 3 input voltage* 1 v i v ss ? 0.3 v ss + 4.0 v *4 v ss ? 0.3 v ss + 6.0 v n-ch open-drain (withstand voltage of 5 v i/o)* 5 ? 0.5 v ss + 4.5 v usb i/o output voltage* 1 v o v ss ? 0.3 v ss + 4.0 v *4 ? 0.5 v ss + 4.5 v usb i/o maximum clamp current i clamp ? 2.0 + 2.0 ma *6 total maximum clamp current ? i clamp ?? 20 ma *6 ?l? level maximum output current i ol1 ? 10 ma other than usb i/o* 7 i ol2 ? 43 ma usb i/o* 7 ?l? level average output current i olav1 ? 4ma*8 i olav2 ? 15/4.5 ma usb-io (full speed/ low speed) * 8 ?l? level maximum to tal output current i ol ? 100 ma ?l? level average total output current i olav ? 50 ma *9 ?h? level maximum output current i oh1 ?? 10 ma other than usb i/o* 7 i oh2 ?? 43 ma usb i/o* 7 ?h? level average output current i ohav1 ?? 4ma*8 i ohav2 ?? 15/ ? 4.5 ma usb-io (full speed/ low speed) * 8 ?h? level maximum total output current i oh ?? 100 ma ?h? level average total output current i ohav ?? 50 ma *9 power consumption pd ? 340 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c ? 55 + 125 c usb i/o mb90330a series 89 (continued) *6 : ? applicable to pins: p00 to p07, p10 to p17, p20 to p 27, p30 to p37, p40 to p47, p50 to p57, p70 to p77, p80 to p87, p90 to p95, pb5, pb6 ? use within recommended operating conditions. ? use at dc voltage (current) ? the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pi ns other than p60 to p67, p96, pa0 to pa7, pb0 to pb4, dvp, dvm, hvp, hvm, utest, hcon ? sample recommended circuits: *7 : a peak value of an applicable one pin is specified as a maximum output current. *8 : the average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *9 : the average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode mb90330a series 90 2. recommended operating conditions (v ss = av ss = 0.0 v) * : applicable to pins : p60 to p67, p96, pa0 to pa7, pb0 to pb4, utest warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3.0 3.6 v at normal operation (when using usb) 2.7 3.6 v at normal operation (when not using usb) 1.8 3.6 v hold state of stop operation input ?h? voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs1 0.8 v cc v cc + 0.3 v cmos hysteresis input pin v ihs2 0.8 v cc v ss + 5.3 v n-ch open-drain (withstand voltage of 5 v i/o)* v ihm v cc ? 0.3 v cc + 0.3 v md pin input v ihusb 2.0 v cc + 0.3 v usb pin input input ?l? voltage v il v ss ? 0.3 0.3 v cc v cmos input pin v ils v ss ? 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss ? 0.3 v ss + 0.3 v md pin input v ilusb v ss 0.8 v usb pin input differential input sensitivity v di 0.2 ? v usb pin input differential common mode input voltage range v cm 0.8 2.5 v usb pin input operating temperature t a ? 40 + 85 c when not using usb 0 + 70 c when using usb mb90330a series 91 3. dc characteristics (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max output ?h? voltage v oh output pins other than p60 to p67, p96, pa0 to pa7, pb0 to pb4, hvp, hvm, dvp, dvm i oh = ? 4.0 ma v cc ? 0.5 ? vcc v hvp, hvm, dvp, dvm r l = 15 k ? 5 % 2.8 ? 3.6 v output ?l? voltage v ol output pins other than hvp, hvm, dvp, dvm i ol = 4.0 ma vss ? vss + 0.4 v hvp, hvm, dvp, dvm r l = 1.5 k ? 5 % 0 ? 0.3 v input leak current i il output pins other than p60 to p67, p96, pa0 to pa7, pb0 to pb4, hvp, hvm, dvp, dvm v cc = 3.3 v, vss < v i < v cc ? 10 ?+ 10 a hvp, hvm, dvp, dvm ?? 5 ?+ 5 a pull-up resistance r pull p00 to p07, p10 to p17 v cc = 3.3 v, t a = + 25 c 25 50 100 k ? open drain output current i liod p60 to p67, p96, pa0 to pa7, pb0 to pb4 ?? 0.1 10 a power supply current i cc v cc v cc = 3.3 v, internal frequency 24 mhz, at normal operating at usb operating (ustp = 0) ? 75 85 ma MB90F334A ? 65 75 ma mb90333a v cc = 3.3 v, internal frequency 24 mhz, at normal operating at non-operating usb (ustp = 1) ? 70 80 ma MB90F334A ? 60 70 ma mb90333a i ccs v cc = 3.3 v, internal frequency 24 mhz, at sleep mode ? 27 40 ma i cts v cc = 3.3 v, internal frequency 24 mhz, at timer mode ? 3.5 10 ma v cc = 3.3 v, internal frequency 3 mhz, at timer mode ? 12ma i ccl v cc = 3.3 v, internal frequency 8 khz, at sub clock operation, (t a = + 25 c) ? 25 150 a mb90330a series 92 (continued) (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : p60 to p67, p96, pa0 to pa7, and pb0 to pb4 are n-ch open-drain pins usually used as cmos. parameter sym- bol pin name conditions value unit remarks min typ max power supply current i ccl s v cc v cc = 3.3 v, internal frequency 8 khz, at sub clock, at sleep operating, (t a = + 25 c) ? 10 50 a i cct v cc = 3.3 v, internal frequency 8 khz, watch mode, (t a = + 25 c) ? 1.5 40 a i cch t a = + 25 c, at stop ? 140 a input capacitance c in other than avcc, avss, vcc, vss ?? 515pf pull-up resistor r up rst ? 25 50 100 k ? usb i/o output impedance z usb dvp, dvm hvp, hvm ? 3 ? 14 ? mb90330a series 93 4. ac characteristics (1)clock input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name value unit remarks min typ max clock frequency f ch x0, x1 ? 6 ? mhz when oscillator is used 6 ? 24 mhz external clock input f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 ? 166.7 ? ns when oscillator is used 166.7 ? 41.7 ns external clock input t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh p wl x0 10 ?? ns a reference duty ratio is 30 % to 70 % . p whl p wll x0a ? 15.2 ? s input clock rise time and fall time tcr tcf x0 ?? 5 ns at external clock internal operating clock frequency f cp ? 3 ? 24 mhz when main clock is used f cpl ?? 8.192 ? khz when sub clock is used internal operating clock cycle time t cp ? 42 ? 333 ns when main clock is used t cpl ?? 122.1 ? s when sub clock is used 0.8 v cc 0.2 v cc t cf t cr t hcyl p wh p wl x0 ? clock timing 0.8 v cc 0.2 v cc t cf t cr t lcyl p whl p wll x0a mb90330a series 94 3.6 3.0 2.7 3 6 12 24 ? pll operation guarantee range pll operation guarantee range normal operation assurance range note : when the usb is used, operation is guaranteed at voltages between 3.0 v and 3.6 v. relation between power supply voltage and internal operation clock frequency internal clock f cp (mhz) power voltage v cc (v) 24 12 6 3 6 24 relation between internal operation clock frequency and external clock frequency multiplied by 4 multiplied by 2 multiplied by 1 external clock fc (mhz) external clock internal clock f cp (mhz) mb90330a series 95 the ac standards assume the following measurement reference voltages. 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform hysteresis input pin hysteresis input/other than md input pin ? output signal waveform output pin mb90330a series 96 (2)clock output timing (v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit remarks min max cycle time t cyc clk ? t cp ? ns clk clk t chcl clk v cc = 3.0 v to 3.6 v t cp / 2 ? 15 t cp / 2 + 15 ns at f cp = 24 mhz t cp / 2 ? 20 t cp / 2 + 20 ns at f cp = 12 mhz t cp / 2 ? 64 t cp / 2 + 64 ns at f cp = 6 mhz clk t cyc 2.4 v 2.4 v 0.8 v t chcl mb90330a series 97 (3) reset (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : oscillation time of oscillator is th e time that the amplitude reaches 90%. it takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a ceramic oscillator, and 0 millis econds on an external clock. parameter symbol pin name conditions value unit remarks min max reset input time t rstl rst ? 500 ? ns at normal operating, at time base timer mode, at main sleep mode, at pll sleep mode oscillation time of oscillator* + 500 ns ? s at stop mode, at sub clock mode, at sub sleep mode, at watch mode rst rst x0 500 ns t rstl 0.2 v cc 0.2 v cc t rstl 0.2 v cc 0.2 v cc ? during stop mode, sub clock mode, sub-sleep mode and watch mode internal operation clock internal reset oscillation time of oscillator oscillation stabili zation wait time execute instruction 90 % of amplitude ? during normal operation, time-base timer mode, main sleep mode and pll sleep mode mb90330a series 98 (4) power-on reset (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? v cc must be lower than 0.2 v before the power supply is turned on. ? the above standard is a value for performing a power-on reset. ? in the device, there are internal registers which is initialized only by a power-on reset. when the initialization of these items is expected, turn on the power supply according to the standards. ? sudden change of power supply voltage may activate the power-on reset function. when changing the power supply volta ge during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. when raising the power, do not use pll clock. however, if voltage drop is 1 v/s or less, use of pll clock is allowed during operation. parameter symbol pin name conditions value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms power supply shutdown time t off v cc 1 ? ms waiting time until power-on v cc t r 0.2 v 0.2 v 2.7 v t off 0.2 v v cc 3 .0 v v ss ram data hold the rising edge should be 50 mv/ms or less. mb90330a series 99 (5) uart0, uart1, uart2, uart3 i/o extended serial timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? above rating is the case of clk synchronous mode. ? c l is a load capacitance value on pins for testing. ? t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sckx internal shift clock mode output pin is : c l = 80 pf + 1ttl 8 t cp ? ns sck sot delay time t slov sckx, sotx ? 80 + 80 ns valid sin sck t ivsh sckx, sinx 100 ? ns sck valid sin hold time t shix sckx, sinx 60 ? ns serial clock h pulse width t shsl sckx, sinx external shift clock mode output pin is : c l = 80 pf + 1ttl 4 t cp ? ns serial clock l pulse width t slsh sckx, sinx 4 t cp ? ns sck sot delay time t slov sckx, sotx ? 150 ns valid sin sck t ivsh sckx, sinx 60 ? ns sck valid sin hold time t shix sckx, sinx 60 ? ns mb90330a series 100 ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc mb90330a series 101 (6) i 2 c timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : f cp is internal operating clock frequency. refer to ? (1) clock input timing?. *2 : r and c are pull-up resistance of scl and sda lines and load capacitance. *3 : the maximum t hddat only has to be met if the device does not stretch the ?l? width (t low ) of the scl signal. *4 : refer to ? ? note of sda, scl set-up time?. parameter symbol conditions value unit min max scl clock frequency f scl power-supply voltage of external pull-up resistor at 5.0 v. r = 1.2 k ? , c = 50 pf* 2 power-supply voltage of external pull-up resistor at 3.6 v. r = 1.0 k ? , c = 50 pf* 2 0 100 khz (repeat) [start] condition hold time sda scl t hdsta 4.0 ? s scl clock ?l? width t low 4.7 ? s scl clock ?h? width t high 4.0 ? s repeat [start] condition setup time scl sda t susta 4.7 ? s data hold time scl sda t hddat 03.45* 3 s data setup time sda scl t sudat power-supply voltage of external pull-up resistor at 5.0 v. f cp * 1 20 mhz, r = 1.2 k ? , c = 50 pf* 2 power-supply voltage of external pull-up resistor at 3.6 v. f cp * 1 20 mhz, r = 1.0 k ? , c = 50 pf* 2 250* 4 ? ns power-supply voltage of external pull-up resistor at 5.0 v. f cp * 1 > 20 mhz, r = 1.2 k ? , c = 50 pf* 2 power-supply voltage of external pull-up resistor at 3.6 v. f cp * 1 > 20 mhz, r = 1.0 k ? , c = 50 pf* 2 200* 4 ? [stop] condition setup time scl sda t susto power-supply voltage of external pull-up resistor at 5.0 v. r = 1.2 k ? , c = 50 pf* 2 power-supply voltage of external pull-up resistor at 3.6 v. r = 1.0 k ? , c = 50 pf* 2 4.0 ? s bus free time between [stop] condition and [s tart] condition t bus 4.7 ? s mb90330a series 102 note : the rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. be sure to adjust the pull-up resistor of sda and scl if the rating of the input data set-up time cannot be satisfied. sda scl 6 tcp ? note of sda, scl set-up time input data set-up time sda scl t low t hdsta t hddat t sudat t susta t susto t hdsta t high t bus ? timing definition mb90330a series 103 (7) timer input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp : refer to ? (1) clock input timing?. (8) timer output timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (9) trigger input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit min max input pulse width t tiwh t tiwl frck, inx, tinx, pwc ? 4 t cp ? ns parameter symbol pin name conditions value unit min max clk t out change time ppg0 to ppg5 change time out0 to out3 change time t to totx, ppgx, outx ? 30 ? ns parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl intx, adtg ? 5 t cp ? ns at normal operating 1 ? s in stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl pwc tinx inx frck clk ppgx outx 2.4 v t to 2.4 v 0.8 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl intx adtgx mb90330a series 104 (10) bus read timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) note : t cp : refer to ? (1) clock input timing?. parameter sym- bol pin name conditions value unit remarks min max ale pulse width t lhll ale ? t cp / 2 ? 15 ? ns at f cp = 24 mhz t cp / 2 ? 20 ? ns at f cp = 12 mhz t cp / 2 ? 35 ? ns at f cp = 6 mhz valid address ale time t avll address, ale ? t cp / 2 ? 17 ? ns t cp / 2 ? 40 ? ns at f cp = 6 mhz ale address valid time t llax ale, address ? t cp / 2 ? 15 ? ns valid address rd time t avrl rd , address ? t cp ? 25 ? ns valid address valid data input t avdv address/ data ? ? 5 t cp / 2 ? 55 ns ? 5 t cp / 2 ? 80 ns at f cp = 6 mhz rd pulse width t rlrh rd ? 3 t cp / 2 ? 25 ? ns at f cp = 24 mhz 3 t cp / 2 ? 20 ? ns at f cp = 12 mhz rd valid data input t rldv rd , data ? ? 3 t cp / 2 ? 55 ns ? 3 t cp / 2 ? 80 ns at f cp = 6 mhz rd data hold time t rhdx rd , data ? 0 ? ns rd ale time t rhlh rd , ale ? t cp / 2 ? 15 ? ns rd address valid time t rhax address, rd ? t cp / 2 ? 10 ? ns valid address clk time t avch address, clk ? t cp / 2 ? 17 ? ns rd clk time t rlch rd , clk ? t cp / 2 ? 17 ? ns ale rd time t llrl rd , ale ? t cp / 2 ? 15 ? ns mb90330a series 105 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc clk ale rd a23 to a16 ad15 to ad00 2.4 v t avch t lhll t rhlh t avll t avrl t rldv t rlrh t rhax t rhdx t llax t llrl t rlch t avdv 0.8 v 2.4 v 0.8 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc a23 to a00 d15 to d00 t rldv t rhax t rhdx t avdv 0.8 v 2.4 v address read data read data in multiplex mode in non-mult iplex mode mb90330a series 106 (11) bus write timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) note : t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit remarks min max valid address wr time t avwl address, wr ? t cp ? 15 ? ns wr pulse width t wlwh wrl , wrh ? 3 t cp / 2 ? 25 ? ns at f cp = 24 mhz ? 3 t cp / 2 ? 20 ? ns at f cp = 12 mhz valid data output wr time t dvwh data, wr ? 3 t cp / 2 ? 15 ? ns wr data hold time t whdx wr , data ? 10 ? ns at f cp = 24 mhz ? 20 ? ns at f cp = 12 mhz ? 30 ? ns at f cp = 6 mhz wr address valid time t whax wr , address ? t cp / 2 ? 10 ? ns wr ale time t whlh wr , ale ? t cp / 2 ? 15 ? ns wr clk time t wlch wr , clk ? t cp / 2 ? 17 ? ns wr (wrl, wrh) 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v clk ale a23 to a16 ad15 to ad00 t whlh t avwl t dvwh t dvwh t wlwh t whax t whdx t wlch 0.8 v 2.4 v 0.8 v 2.4 v a23 to a00 d15 to d00 t whax t whdx 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v address write data write data in multiplex mode in non-multiplex mode mb90330a series 107 (12) ready input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name conditions value unit remarks min max rdy set-up time t ryhs rdy ? 35 ? ns ? 70 ? ns f cp = 6 mhz rdy hold time t ryhh ? 0 ? ns t ryhh 2.4 v 2.4 v 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc clk ale rd/wr t ryhs t ryhs rdy wait applies (1cycle) rdy wait not applied mb90330a series 108 (13) hold timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) notes : ? it takes one cycle or more for hak to change after the hrq pin is captured. ? t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit min max pin floating hak time t xhal hak ? 30 t cp ns hak pin valid time t hahv hak t cp 2 t cp ns hak t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v each pin high-z mb90330a series 109 5. electrical characteristics for the a/d converter (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : t cp : refer to ? 4. ac characteristics (1) clock input timing?. *2 : the current when the cpu is in stop mode and the a/d converter is not operating (for v cc = av cc = avrh = 3.3 v). parameter sym- bol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinear error ?? ? ? 2.5 lsb differential linear error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an15 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv 1 lsb = avrh/1024 full-scale transition voltage v fst an0 to an15 avrh ? 3.5 lsb avrh ? 1.5 lsb avrh + 0.5 lsb mv conversion time ?? ? 176 t cp *1 ? ns sampling time ?? ? 64 t cp *1 ? ns analog port input current i ain an0 to an15 ?? 10 a analog input voltage v ain an0 to an15 0 ? avrh v reference voltage ? avrh 2.7 ? av cc v power supply current i a av cc ? 1.4 3.5 ma i ah av cc ?? 5 a*2 reference voltage supplying current i r avrh ? 95 170 a i rh avrh ?? 5 a*2 interchannel disparity ? an0 to an15 ?? 4lsb mb90330a series 110 notes : ? about the external impedance of the analog input and its sampling time ? a/d converter with sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. ? to satisfy the a/d conversion precision standard, cons ider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. ? if the sampling time cannot be sufficient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as | avrh | becomes smaller, values of relative errors grow larger. r c analog input comparator ? analog input circuit model during sampling : on note : the values are reference values. mb90333a MB90F334A mb90v330a r 1.9 k ? (max) 1.9 k ? (max) 1.9 k ? (max) c 32.3 pf (max) 25.0 pf (max) 32.3 pf (max) 100 90 8 0 70 60 50 40 3 0 20 10 0 0 5 10 15 20 25 3 0 3 5 mb90 333 a/ mb90v 33 0a mb90f 33 4a 20 1 8 16 14 12 10 8 6 4 2 0 012 3 456 8 7 mb90 333 a/ mb90v 33 0a mb90f 33 4a (external impedance = 0 k ? to 100 k ? ) external impedance [k ? ] minimum sampling time [ s] (external impedance = 0 k ? to 20 k ? ) external impedance [k ? ] minimum sampling time [ s] ? the relationship between the external impedance and minimum sampling time mb90330a series 111 a/d converter glossary (continued) resolution : analog changes that are identifiable with the a/d converter. linearity error : the deviation of the straight line connecting the zero transition point (?00 0000 0000? ? ?00 0000 0001?) with the full-scale transition point (?11 1111 1110? ? ?11 1111 1111?) from actual conversion characteristics. differential linearity error : the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value. total error : the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. 3 ff h 3 fe h 3 fd h 004 h 00 3 h 002 h 001 h avrl avrh v nt 0.5 l s b 0.5 l s b {1 l s b (n ? 1) + 0.5 l s b} act ua l conver s ion v a l u e (me asu red v a l u e) act ua l conver s ion v a l u e theoretic a l ch a r a cteri s tic s digit a l o u tp u t an a log inp u t total error total error for digital output n = v nt ? { 1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb (theoretical value) = avr ? avss 1024 [v] v ot (theoretical value) = avss + 0.5 lsb [v] v fst (theoretical value) = avr ? 1.5 lsb [v] v nt : voltage at a transition of digital output from (n - 1) h to n h mb90330a series 112 (continued) 3 ff h 3 fe h 3 fd h 004 h 00 3 h 002 h 001 h avrl avrh v ot (me asu red v a l u e) {1 l s b (n ? 1) + v ot } act ua l conver s ion v a l u e v f s t (me asu red v a l u e) v nt (me asu red v a l u e) act ua l conver s ion v a l u e theoretic a l ch a r a cteri s tic s digit a l o u tp u t digit a l o u tp u t an a log inp u t avrl avrh (n + 1) h n h (n ? 1) h (n ? 2) h act ua l conver s ion v a l u e act ua l conver s ion v a l u e theoretic a l ch a r a cteri s tic s an a log inp u t v nt (me asu red v a l u e) v (n + 1) t (me asu red v a l u e) linearity error differe ntial linearity error linearity error of digital output n v nt ? { 1 lsb (n ? 1) + v ot } 1 lsb [lsb] = differential linearity error of digital output n v ( n + 1 ) t ? v nt 1 lsb ? 1 [lsb] = v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at transition of digital output from ?000 h ? to ?001 h ? v fst : voltage at transition of digital output from ?3fe h ? to ?3ff h ? mb90330a series 113 6. usb characteristics (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) * : arrange the series resistance r s values in order to set the impedance value within the output impedance zsrv. ? data signal timing (full speed) ? data signal timing (low speed) parameter sym- bol value unit remarks min max input characteristics input high level voltage v ih 2.0 ? v input low level voltage v il ? 0.8 v differential input sensitivity v di 0.2 ? v differential common mode range v cm 0.8 2.5 v output characteristics output high level voltage v oh 2.8 3.6 v i oh = ? 200 a output low level voltage v ol 0.0 0.3 v i ol = 2 ma cross over voltage v crs 1.3 2.0 v rise time t fr 4 20 ns full speed t lr 75 300 ns low speed fall time t ff 4 20 ns full speed t lf 75 300 ns low speed rising/falling time matching t rfm 90 111.11 % (t fr /t ff ) t rlm 80 125 % (t lr /t lf ) output impedance z drv 28 44 ? including rs = 27 ? series resistance r s 25 30 ? recommended value = 27 ? at using usb* dvp/hvp dvm/hvm 90 % t fr 10 % 90 % 10 % t ff vcr s rise time fall time hvp hvm 90 % t lr 10 % 90 % 10 % tlf vcr s rise time fall time mb90330a series 114 ? load condition (full speed) ? load condition (low speed) dvp/hvp r s = 27 ? c l = 50 pf dvm/hvm r s = 27 ? z usb z usb c l = 50 pf testing point testing point hvp r s = 27 ? c l = 50 pf to 150 pf hvm r s = 27 ? c l = 50 pf to 150 pf z u s b z u s b testing point testing point mb90330a series 115 7. flash memory write/erase characteristics * : this value comes from the technology qualification. (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) parameter condition value unit remarks min typ max sector erase time t a = + 25 c v cc = 3.0 v ? 115s excludes 00 h programming prior to erasure. chip erase time ? 9 ? s excludes 00 h programming prior to erasure. word (16-bit width) programming time ? 16 3600 s except for over head time of system level programming/erase cycle ? 10000 ?? cycle flash memory data retaining period average t a = + 85 c 20 ?? year * mb90330a series 116 ordering information part number package remarks MB90F334Apff mb90333apff 120-pin plastic lqfp (fpt-120p-m05) MB90F334Apmc mb90333apmc 120-pin plastic lqfp (fpt-120p-m21) mb90v330a 299-pin ceramic pga (pga-299c-a01) for evaluation mb90330a series 117 package dimensions please confirm the la test package dimens ion by following url. http://edevice.fujitsu.com/package/en-search/ (continued) 120-pin pl as tic lqfp le a d pitch 0.40 mm p a ck a ge width p a ck a ge length 14.0 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0.62 g code (reference) p-lfqfp120-14 14-0.40 120-pin pl as tic lqfp (fpt-120p-m05) (fpt-120p-m05) c 200 3 fujit s u limited f120006 s -c-4-5 0.07(.00 3 ) m index 16.000.20(.6 3 0.00 8 ) s q 14.000.10(.551.004) s q 1 3 0 3 1 60 91 120 61 90 lead no. ( s t a nd off) 0.100.10 (.004.004) 0.25(.010) (.024.006) 0.600.15 (.020.00 8 ) 0.500.20 (mo u nting height) 0~ 8 ? det a il s of "a" p a rt 1.50 +0.20 ?0.10 +.00 8 ?.004 .059 "a" 0.40(.016) 0.160.0 3 (.006.001) 0.1450.055 (.006.002) 0.0 8 (.00 3 ) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. mb90330a series 118 (continued) please confirm the la test package dimens ion by following url. http://edevice.fujitsu.com/package/en-search/ 120-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 16.0 16.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 88 g code (reference) p-lfqfp120-16 16-0.50 120-pin pl as tic lqfp (fpt-120p-m21) (fpt-120p-m21) c 2002 fujit s u limited f1200 33s -c-4-4 1 3 0 60 3 1 90 61 120 91 s q 1 8 .000.20(.709.00 8 ) s q 0.50(.020) 0.220.05 (.009.002) m 0.0 8 (.00 3 ) index .006 ?.001 +.002 ?0.0 3 +0.05 0.145 "a" 0.0 8 (.00 3 ) lead no. .059 ?.004 +.00 8 ?0.10 +0.20 1.50 det a il s of "a" p a rt (mo u nting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 ( s t a nd off) 0~ 8 ? * .6 3 0 ?.004 +.016 ?0.10 +0.40 16.00 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. re s in protr us ion i s +0.25(.010) max(e a ch s ide). note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder. mb90330a series 119 main changes in this edition the vertical lines marked in the left side of the page show the changes page section change results 3 internal peripheral function (resource) changed as follows conform to usb2.0 full speed correspond to usb full speed 4 product lineup 64 peripheral resources 10. usb function ? feature of usb function fujitsu microelectronics limited shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. 151 lorong chuan, #05-08 new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ fujitsu microelectronics shanghai co., ltd. rm.3102, bund center, no.222 yan an road(e), shanghai 200002, china tel: +86-21-6335-1560 fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road tsimshatsui, kowloon hong kong tel: +852-2377-0226 fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porat- ing the device based on such in formation, you must assume any responsibility arising out of such use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringeme nt of any third-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use acco mpanying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuc lear reaction control in nuclear facility, airc raft flight control, air traffic c ontrol, mass transport control, me dical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high re liability (i.e ., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety desi gn measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited strategic business development dept. |
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