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hb56uw873e-a series 64mb buffered edo dram dimm 8-mword 72-bit, 4k refresh, 1 bank module (9 pcs of 8m 8 components) ade-203-821b (z) rev. 2.0 nov. 20, 1997 description the hb56uw873e-a belongs to 8 byte dimm (dual in-line memory module) family, and has been developed as an optimized main memory solution for 4 and 8 byte processor applications. the hb56uw873e-a is a 8m 72 dynamic ram module, mounted 9 pieces of 64-mbit dram (hm5165805a) sealed in tsop package and 2 pieces of 16-bit bicmos line driver sealed in tssop package. the hb56uw873e-a offers extended data out (edo) page mode as a high speed access mode. an outline of the hb56uw873e-a is 168-pin socket type package (dual lead out). therefore, the hb56uw873e-a makes high density mounting possible without surface mount technology. the hb56uw873e-a provides common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the its module board. features 168-pin socket type package (dual lead out) ? lead pitch: 1.27 mm single 3.3 v supply: 3.3 v +0.3 v/C0.15 v (hb56uw873e-5ar) 3.3 v 0.3 v (hb56uw873e-6a/7a) high speed ? access time: t rac = 50 ns /60 ns /70 ns (max) ? access time: t cac = 18 ns /20 ns /23 ns (max) low power dissipation ? active mode: 6.32 mw/5.38 w/4.73 w (max) ? standby mode (ttl): 100 mw (max) buffered input except ras and dq 4 byte interleave enabled, dual address input (a0/b0) edo page mode capability 4,096 refresh cycle: 64 ms 2 variations of refresh ? ras -only refresh ? cas -before- ras refresh
hb56uw873e-a series 2 ordering information type no. access time package contact pad hb56uw873e-5ar hb56uw873e-6a HB56UW873E-7A 50 ns 60 ns 70 ns 168-pin dual lead out socket type gold pin arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin pin arrangement (cont) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 oe2 86 dq36 128 nc 3 dq1 45 re2 87 dq37 129 nc 4 dq2 46 ce4 88 dq38 130 nc 5 dq3 47 nc 89 dq39 131 nc 6v cc 48 we2 90 v cc 132 pde 7 dq4 49 v cc 91 dq40 133 v cc 8 dq5 50 nc 92 dq41 134 nc 9 dq6 51 nc 93 dq42 135 nc 10 dq7 52 dq18 94 dq43 136 dq54 11 dq8 53 dq19 95 dq44 137 dq55 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq20 97 dq45 139 dq56
hb56uw873e-a series 3 pin arrangement (cont) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 14 dq10 56 dq21 98 dq46 140 dq57 15 dq11 57 dq22 99 dq47 141 dq58 16 dq12 58 dq23 100 dq48 142 dq59 17 dq13 59 v cc 101 dq49 143 v cc 18 v cc 60 dq24 102 v cc 144 dq60 19 dq14 61 nc 103 dq50 145 nc 20 dq15 62 nc 104 dq51 146 nc 21 dq16 63 nc 105 dq52 147 nc 22 dq17 64 nc 106 dq53 148 nc 23 v ss 65 dq25 107 v ss 149 dq61 24 nc 66 dq26 108 nc 150 dq62 25 nc 67 dq27 109 nc 151 dq63 26 v cc 68 v ss 110 v cc 152 v ss 27 we0 69 dq28 111 nc 153 dq64 28 ce0 70 dq29 112 nc 154 dq65 29 nc 71 dq30 113 nc 155 dq66 30 re0 72 dq31 114 nc 156 dq67 31 oe0 73 v cc 115 nc 157 v cc 32 v ss 74 dq32 116 v ss 158 dq68 33 a0 75 dq33 117 a1 159 dq69 34 a2 76 dq34 118 a3 160 dq70 35 a4 77 dq35 119 a5 161 dq71 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 pd1 121 a9 163 pd2 38 a10 80 pd3 122 a11 164 pd4 39 nc 81 pd5 123 nc 165 pd6 40 v cc 82 pd7 124 v cc 166 pd8 41 nc 83 id0 (v ss ) 125 nc 167 id1 (v ss ) 42 nc 84 v cc 126 b0 168 v cc
hb56uw873e-a series 4 pin description pin name function a0 to a11, b0 address input (d0 to d8) : a0 to a11, b0 row address (d0 to d8) : a0 to a11, b0 column address (d0 to d8) : a0 to a10, b0 refresh address (d0 to d8) : a0 to a11, b0 dq0 to dq71 data-in/data-out re0 , re2 row address strobe ( ras ) ce0 , ce4 column address strobe ( cas ) we0 , we2 read/write enable oe0 , oe2 output enable v cc power supply v ss ground pd1 to pd8 presence detect id0, id1 id bit pde presence detect enable nc non connection presence detect pin assignment pde = low pde = high pin name pin no. 50 ns 60 ns 70ns all pd1 79 1 1 1 high-z pd2 163 0 0 0 high-z pd3 80 1 1 1 high-z pd4 164 1 1 1 high-z pd5 81 1 1 1 high-z pd6 165 0 1 0 high-z pd7 82 0 1 1 high-z pd8 166 0 0 0 high-z 1 : high level (driver output) 0 : low level (driver output)
hb56uw873e-a series 5 block diagram re0 ce0 we0 oe0 dq36 dq37 dq38 dq39 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq32 dq33 dq34 dq35 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o cas ras we oe cas ras we oe cas ras we oe cas ras we oe cas ras we oe d0 d1 d2 d3 d4 re2 ce4 we2 oe2 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq64 dq65 dq66 dq67 dq68 dq69 dq70 dq71 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o cas ras we oe cas ras we oe cas ras we oe cas ras we oe d5 d6 d7 d8 a0 b0 a1 to a11 v cc v ss d0 to d4 d5 to d8 d0 to d8 d0 to d8, 16-bit line driver d0 to d8,16-bit line driver 0.22 m f 11 pcs pd1 to pd8 v cc v ss v cc v cc v cc v cc v ss v cc v ss v ss pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 * d0 to d8 : hm5165805 : 16-bit line driver
hb56uw873e-a series 6 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C0.5 to +4.6 v supply voltage relative to v ss v cc C0.5 to +4.6 v short circuit output current iout 50 ma power dissipation pt 10 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to 70 c) parameter symbol min typ max unit notes supply voltage v cc (hb56uw873e-5ar) 3.15 3.3 3.6 v 1, 2 v cc (hb56uw873e-6a/7a) 3.0 3.3 3.6 v 1, 2 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il C0.3 0.8 v 1 note: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hb56uw873e-a series 7 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v +0.3 v/C0.15 v, v ss = 0 v) (hb56uw873e-5ar) (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hb56uw873e-6a/7a) hb56uw873e-a 50 ns 60 ns 70 ns parameter symbol min max min max min max unit test conditions operating current* 1 , * 2 i cc1 1765 1495 1315 ma t rc = min standby current i cc2 28 28 28 ma ttl interface ras , cas = v ih dout = high-z 19 19 19 ma cmos interface ras , cas 3 v cc C 0.2 v dout = high-z ras -only refresh current* 2 i cc3 1765 1495 1315 ma t rc = min standby current* 1 i cc5 555555ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 1540 1270 1090 ma t rc = min edo page mode current* 1, * 3 i cc7 1360 1135 1000 ma t hpc = min input leakage current i li C10 10 C10 10 C10 10 m a 0 v vin v cc + 0.3 v output leakage current i lo C10 10 C10 10 C10 10 m a 0 v vout v cc dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = C2 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected, i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less within one page mode cycle t hpc . capacitance (ta = 25?c, v cc = 3.3 v +0.3 v/C0.15 v, v ss = 0 v) (hb56uw873e-5ar) (ta = 25?c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hb56uw873e-6a/7a) parameter symbol typ max unit notes input capacitance (address) c i1 20pf1 input capacitance ( cas , we , oe )c i2 20pf1 input capacitance ( ras )c i3 55pf1 i/o capacitance (dq) c i/o 20 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout.
hb56uw873e-a series 8 ac characteristics* 1 , * 2 , * 17 (ta = 0 to +70 c, v cc = 3.3 v +0.3 v/C0.15 v, v ss = 0 v) (hb56uw873e-5ar) (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hb56uw873e-6a/7a) test conditions input rise and fall times: 2 ns input levels: v il = 0 v, v ih = 3.0 v input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load:1 ttl gate + c l (50 pf) (including scope and jig) (hb56uw873e-5ar) 1 ttl gate + c l (100 pf) (including scope and jig) (hb56uw873e-6a/7a) read, write, read-modify-write and refresh cycles (common parameters) 50 ns 60 ns 70 ns parameter symbol min max min max min max unit notes random read or write cycle time t rc 84 104 124 ns ras precharge time t rp 30 40 50 ns cas precharge time t cp 8 10 13 ns ras pulse width t ras 50 10000 60 10000 70 10000 ns cas pulse width t cas 8 10000 10 10000 13 10000 ns row address setup time t asr 5 5 5 ns row address hold time t rah 8 10 10 ns column address setup time t asc 0 0 0 ns column address hold time t cah 8 10 13 ns ras to cas delay time t rcd 12 32 20 40 20 47 ns 3 ras to column address delay time t rad 10 20 14 25 14 30 ns 4 ras hold time t rsh 18 20 23 ns cas hold time t csh 40 48 58 ns 21 cas to ras precharge time t crp 10 10 10 ns oe to din delay time t oed 18 20 23 ns 5 oe delay time from din t dzo 0 0 0 ns6 cas delay time from din t dzc 0 0 0 ns6 transition time (rise and fall) t t 250 2 50 250 ns7
hb56uw873e-a series 9 read cycle 50 ns 60 ns 70 ns parameter symbol min max min max min max unit notes access time from ras t rac 50 60 70 ns 8, 9 access time from cas t cac 18 20 23 ns 9, 10, 16 access time from address t aa 30 35 40 ns 9, 11, 16 access time from oe t oea 182023ns9 read command setup time t rcs 0 00ns read command hold time to cas t rch 0 00ns12 read command hold time from ras t rchr 50 60 70 ns read command hold time to ras t rrh 5 00ns12 column address to ras lead time t ral 30 35 40 ns column address to cas lead time t cal 15 18 23 ns cas to output in low-z t clz 2 22ns output data hold time t oh 3 33ns20 output data hold time from oe t oho 3 33ns output buffer turn-off time t off 20 20 20 ns 13, 20 output buffer turn-off to oe t oez 182020ns13 cas to din delay time t cdd 18 20 23 ns 5 output data hold time from ras t ohr 3 33ns20 output buffer turn-off to ras t ofr 13 15 15 ns 13, 20 output buffer turn-off to we t wez 182020ns13 we to din delay time t wed 18 20 23 ns ras to din delay time t rdd 13 15 18 ns write cycle 50 ns 60 ns 70 ns parameter symbol min max min max min max unit notes write command setup time t wcs 000ns14 write command hold time t wch 8 10 13 ns write command pulse width t wp 8 10 10 ns write command to ras lead time t rwl 18 20 23 ns write command to cas lead time t cwl 10 10 13 ns data-in setup time t ds 000ns data-in hold time t dh 13 15 18 ns
hb56uw873e-a series 10 read-modify-write cycle 50 ns 60 ns 70 ns parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 111 154 180 ns ras to we delay time t rwd 72 83 96 ns 14 cas to we delay time t cwd 30 33 39 ns 14 column address to we delay time t awd 42 48 56 ns 14 oe hold time from we t oeh 13 15 18 ns refresh cycle 50 ns 60 ns 70 ns parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 10 ns cas hold time (cbr refresh cycle) t chr 8 10 10 ns we setup time (cbr refresh cycle) t wrp 555ns we hold time (cbr refresh cycle) t wrh 10 10 10 ns ras precharge to cas hold time t rpc 500ns edo page mode cycle 50 ns 60 ns 70 ns parameter symbol min max min max min max unit notes edo page mode cycle time t hpc 20 25 30 ns 19 edo page mode ras pulse width t rasp 100000 100000 100000 ns 15 access time from cas precharge t cpa 33 40 45 ns 9, 16 ras hold time from cas precharge t cprh 33 40 45 ns output data hold time from cas low t doh 3 3 3 ns9 cas hold time referred oe t col 8 10 13 ns cas to oe setup time t cop 8 10 10 ns read command hold time from cas precharge t rchc 28 35 40 ns write pulse width during cas precharge t wpe 8 10 10 ns oe precharge time t oep 8 10 10 ns
hb56uw873e-a series 11 edo page mode read-modify-write cycle 50 ns 60 ns 70 ns parameter symbol min max min max min max unit notes edo page mode read- modify-write cycle time t hprwc 57 68 79 ns we delay time from cas precharge t cpw 45 54 62 ns 14 refresh parameter symbol max unit notes refresh period t ref 64 ms 4096 cycles notes: 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 50 pf (hb56uw873e-5ar) and 1 ttl loads and 100 pf (hb56uw873/eje-6a/7a). 10. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 11. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max), t oez (max), t wez (max) and t ofr (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t rasp defines ras pulse width in edo page mode cycles. 16. access time is determined by the longest among t aa , t cac and t cpa . 17. all the v cc and v ss pins shall be supplied with the same voltages. 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device.
hb56uw873e-a series 12 19. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle (t cas + t cp + 2 t t ) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). 20. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh and between t ofr and t off . 21. t csh (min) can be achieved when t rcd t csh (min) C t cas (min). 22. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hb56uw873e-a series 13 timing waveform * 22 read cycle ras address we dout oe din t rc row column t rcs t rch t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez cas t rdd t wed t ofr t ohr t wez t ras t cas t rp t csh t rcd t rsh t crp t t t rad t ral t cal t asr t asc t cah t rchr t rrh t rah
hb56uw873e-a series 14 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t cas
hb56uw873e-a series 15 delayed write cycle * 18 address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t oep t clz t oez high-z invalid dout din high-z
hb56uw873e-a series 16 read-modify-write cycle * 18 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z cas t oep
hb56uw873e-a series 17 ras -only refresh cycle ras cas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off t ofr
hb56uw873e-a series 18 cas -before- ras refresh cycle ras cas we dout address t rc t rp t ras t rpc t csr t chr t rpc t crp t cp t wrh t wrp t cp t t t off t ofr high-z t rp
hb56uw873e-a series 19 edo page mode read cycle din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t cac t cpa t t oez t oea t oez t aa t cac t t rasp cop t rp t cas t cas t cas t cal t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 2 dout 4 dout 1 t cas t rcs t t rcs dout 3 t oho t t cprh t hpc t oea t wez dzo t oed oho doh rch t wpe t rchr t cal t cal t cal t rsh t rchc cpa asc t oep t oep
hb56uw873e-a series 20 edo page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n cas
hb56uw873e-a series 21 edo page mode delayed write cycle * 18 we din oe dout address ras t rasp t rp t crp t rsh t cas t hpc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z cas t oep t oep t oep
hb56uw873e-a series 22 edo page mode read-modify-write cycle * 18 we din oe dout address ras t rasp t crp t cp t hprwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oep t oep t oep t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh cas
hb56uw873e-a series 23 edo page mode mix cycle (1) * 19 oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t cpa t oez t aa t oea t t rasp t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal row dout 2 dout 4 cpa t cas t wcs dout 3 t t t wp t wch t wed t wez t ds t dh t ds t dh din 3 din 1 t oea t oed t oep t cac t asc t cpw t awd oho t cal t rcs t rcs t csh t rcd t rsh doh asc t din
hb56uw873e-a series 24 edo page mode mix cycle (2) * 19 din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t oez t t oea t t rasp t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t rcs row dout 1 dout 4 cpa t cas dout 3 t oho t wed t wez t ds t dh t ds t din 3 din 2 t oea t t cac t cpw t rch t rcs t wch t rac t oed t col t oea t oho t oez t dh oed t rcs t cal t cal t cal t cal t rcd t rchr t wcs t rsh t wp t asc aa t oep t oep cop
hb56uw873e-a series 25 physical outline hb56uw873e-a series 6.35 0.250 3.175 0.125 detail b and c detail a 0.25 max 2.54 min 0.010 max 0.100 min 3.125 0.125 0.123 0.005 1.27 0.050 3.00 133.35 0.118 5.250 127.35 5.014 3.00 0.118 8.89 11.43 36.83 54.61 0.350 0.450 2.150 1.450 a b c 1 84 front side back side 1.27 0.10 4.00 min 0.157 min 0.050 0.004 4.00 max 0.157 max 85 4.00 0.157 17.78 0.700 25.40 1.000 168 2 ? f 3.00 2 ? f 0.118 1.00 0.05 0.039 0.002 2.00 0.10 0.079 0.004 component area (front) component area (back) unit: mm inch
hb56uw873e-a series 26 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hb56uw873e-a series 27 revision record rev. date contents of modification drawn by approved by 1.0 sep. 12, 1997 initial issue (referred to hm5164805a/5165805a series rev. 1.0) y. saitou k. tsuneda 2.0 nov. 20, 1997 (referred to hm5164805a/5165805a series rev. 2.0) addition of hb56uw873e-5ar series deletion of driver name 74lvt16244 from description recommended dc operating conditions addition of note 2 block diagram 74lvt16244 to 16-bit line driver ac characteristics t rad min: 14/15 ns to 10/14/14 ns timing waveforms correct errors: edo page mode mix cycle (1)

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