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db08-000181-00 march 2002 1 of 16 copyright 2002 by lsi logic corporation. all rights reserved. ETHERNET phy-110 core preliminary datasheet the lsi logic phy-110 core is a complete physical layer solution for 10 and 100 mbits/s ETHERNET connections. figure 1 shows a typical application of the phy-110. when combined with a 10/100 mbits/s media access controller (mac), the phy-100 and mac become a complete network interface chip, reducing the component system and assembly costs of a network connection. the phy-110 has also been designed for cost-effective, multiple-channel applications by breaking out the common channel circuits, such as the clock generator, in a separate hardmac that need not be repeated for each channel. figure 1 a typical phy-110 application phy-110 overview as shown in figure 2 , the phy-110 core is actually three phys in one, 10base-t, 100base-tx, and 100base-fx. the phy operates in the 100base-tx or 100base-fx mode at 100 mbits/s, or in the 10base-t mode at 10 mbits/s. the 100 mbits/s mode and the 10 mbits/s mode differ in data rate, signaling protocol, and cabling as follows: ? 100base-tx mode uses two pairs of category 5 or better utp or stp twisted-pair cable with 4b5b encoded, scrambled, mlt3 coded, 125 mhz data to achieve a throughput of 100 mbits/s. phy-110 media interface circuits access controller mii/smii mi 10 mbits/s tx 100 mbits/s tx/fx core core network interface chip network interface card to/from host to/from network
2 of 16 ETHERNET phy-110 core db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. ? 10base-t mode uses two pairs of category 3 or better utp or stp twisted-pair cable with manchester encoded, 10 mhz data to achieve a 10 mbits/s throughput. ? 100base-fx mode uses two ?ers with 4b5b encoded, nrzi, 125 mhz data through an ecl driver to achieve a throughput of 100 mbits/s. figure 2 top level block diagram there is a transmit data path and a receive data path associated with each phy mode. the transmit data path is from the mii/smii module input to the twisted-pair or ?er output of the crossover (automdix) module. the receive data path is from the twisted-pair or ?er input of the crossover module to the mii/smii module output. the mii management interface provides host access to control and status registers in the core. phy core and the osi model figure 3 shows how the phy core ?s into the iso open systems interconnection (osi) reference model. the osi model de?es a data communications protocol consisting of seven distinct layers. see the csma/cd access method and physical layer speci?ations, 1998 edition ansi/ieee standard 802.3 for detailed descriptions of the functions of a phy. mii/smii module autonegotiation, registers, and pmd control 10base-t transmit and receive 100base-tx/fx transmit and receive crossover module smii mii 10base-t data 100base-tx/fx data control & tx flps data data data data register info mii management i/f
ETHERNET phy-110 core 3 of 16 db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. figure 3 phy core relationship to the osi model features the main features of the phy core are: ? single-channel phy con?urable for 10base-t, 100base-tx, or 100base-fx operation ? meets all applicable ieee 802.3, 10base-t, 100base-tx, and 100base-fx speci?ations ? automdix or manual crossover for transmit and receive twisted-pair input/outputs ? 1.8 vdc required ? low power (< 280 mw) for high port-count integration ? half-duplex or full-duplex operation ? mii or serial mii (smii) interface to ETHERNET mac application (7) osi reference model layers lan csma/cd layers mdi = medium-dependent interface pcs = physical coding sublayer phy = physical layer device pmd = physical medium dependent pma = physical medium attachment pmd medium phy-110 mdi pcs pma 10/100 mbit/s link segment mii mac?edia access control llc?ogical link control mii = media-independent interface higher layers autonegotiation automdix automdix = auto crossover at mdi presentation (6) session (5) transport (4) network (3) data link (2) physical (1)
4 of 16 ETHERNET phy-110 core db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. ? management interface (mi) for access to con?uration and status registers ? autonegotiation for 10/100 mbits/s, full/half duplex operation ? in-core wave shaping (no external ?ters required) ? adaptive equalizer for 100base-tx operation ? baseline wander correction ? strap options for con?uring core (without using the management interface) ? far-end fault (fef) handling ? supports up to four parallel led outputs or a serial led output programmable to re?ct any one of 16 events ? scan support in the digital logic ? pattern generators and checkers for ate tests, characterization and diagnostics deliverables the primary deliverables are four hardmacros: ? channel core ? channel i/o core ? common reference (cref) core ? cref i/o core ? encrypted rtl simulation models and/or behavioral models ? gate netlist and wrappers ? a system veri?ation environment (sve) ? synthesis and timing models ? complete documentation ? lsi logic flexstream software support
ETHERNET phy-110 core 5 of 16 db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. core layouts figure 4 shows ?orplans of asics with a single-channel phy and a multiple-channel phy. in all designs, the phy cores must be arranged similar to that shown. that is, the reference core must be adjacent to a channel core, and the i/o cores must be between the channel and reference cores and the edge of the asic. one common reference core can support up to eight channel cores. figure 4 phy-110 layout con?urations external tx connections figure 5 shows the external components and wiring for the common reference and channel cores for connection to twisted-pair cable. the differential, twisted-pair outputs of the channel core are outp0 and outn0 and the inputs are outp1 and outn1. the transformers have a 1: turns ratio and are available from pulse, bel fuse inc., and halo electronics inc. the terminating resistors shown are for 50 ? , utp cable. channel i/o core cref i/o core asic single-channel application multiple-channel application channel core channel i/o core asic channel core #1 channel core #2 channel core #3 channel core #8 common reference core common reference core 2
6 of 16 ETHERNET phy-110 core db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. figure 5 front-end schematic test features the phy-110 has several built-in features that can be used for ate testing and diagnostics. it contains pattern generators that can be used for various twisted-pair measurements such as, the transmit output voltage (tov), total harmonic distortion (thd), template match, rise/fall time, overshoot, duty cycle distortion, and waveform symmetry. a pattern generator on the transmit side, a loopback feature at the twisted-pair output, and a crc checker on the receive side allows most of the phy-110 circuits to be easily tested. outp0 v dd 0.01 f 25 ? 25 ? 4 5 rj45 75 ? 7 8 3 6 1 2 1: 2 75 ? 75 ? 75 ? 0.01 f 25 ? 25 ? v dd 0.01 f 1: 2 = signal ground = chassis ground outn0 outn1 outp1 common reference core channel core fxdis 25 mhz asic 10 k ? rextp rextn
ETHERNET phy-110 core 7 of 16 db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. i/o signals figure 6 shows the i/o signals of the phy-110 organized by interface. the sections following list the signals in the order of the ?ure and describe them. unless otherwise noted in the descriptions, the signals are active high. figure 6 i/o signals media interface signals outp0 twisted-pair transmit output (positive), or fx receive input (negative) o/i the sdtxb input controls the con?uration of the outp0/outn0 signals. the outp0/outn0 signals function as twisted-pair outputs or ?er optic inputs, based on the outp0 1 outn0 1 outp1 1 outn1 1 sdtxb rextp 1 media interface s_smii_pin rx_sync_in mtxen mcrs mrxd[3:0] mrxer controller interface management interface mdc mdi mdintn phyad[3:0] led_3/sled_clko 3 led_2/sled_latchen 3 led_1/sled_out 3 led_0 3 logic scan interface scanmode test_se scanck test_si test_so macif_sel_pin miscellaneous g12 ETHERNET phy core (mii and smii) mtxd[3:0] mdo mdoen phyad_offs[4:0] rxtb mtxer mtxc mcol mrxdv mrxc cross_pin con?[2:0] rextn 1 ckin 2 pd leds vddrx/vddtx/vssrx/ vsstxcore/vsstxio 1 vddl/vssl 1 pin must be external to asic. 2 can be provided externally or from an asic internal clock. 3 optional external pins.
8 of 16 ETHERNET phy-110 core db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. signal level of the corresponding sdtxb input. for more details, see the sdtxb signal description in this section. outn0 twisted-pair transmit output (negative), or fx receive input (positive) o/i the sdtxb input controls the con?uration of the outp0/outn0 signals. the outp0/outn0 signals function as twisted-pair outputs or ?er optic inputs, based on the signal level of the corresponding sdtxb input. for more details, see the sdtxb signal description in this section. outp1 twisted-pair receive input (positive), or fx transmit output (positive) i/o the sdtxb input controls the con?uration of the outp1/outn1 signals. the outp1/outn1 signals function as twisted-pair outputs or ?er optic inputs, based on the signal level of the corresponding sdtxb input. for more details, see the sdtxb signal description in this section. outn1 twisted-pair receive input (negative), or fx transmit output (negative) i/o the sdtxb input controls the con?uration of the outp1/outn1 signals. the outp1/outn1 signals function as twisted-pair outputs or ?er optic inputs, based on the signal level of the corresponding sdtxb input. for more details, see the sdtxb signal description in this section. sdtxb fx signal detect input/fx interface disable i when this line is not tied to gnd, the fx interface is enabled and this line becomes an ecl signal detect input. when this line is tied to gnd, the fx interface is disabled and the tp interface is enabled. rextp, rextn transmit current set i an external resistor connected between the rextp and rextn inputs sets the peak output current for the tp and fx transmit outputs according to the following formula: where: r ext is the value of the external resistor i out is the peak output current i ref = 40.0 x 2 ma (100 mbits/s, utp) 32.6 x 2 ma (100 mbits/s, stp) 100.0 x 2 ma (10 mbits/s, utp) 81.6 x 2 ma (10 mbits/s, stp) r ext 10 k i out ------------- i ref =
ETHERNET phy-110 core 9 of 16 db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. controller interface signals (mii and smii) ckin global clock in i this clock input generates all the devices internal clocks. controller interface data for all channels is latched in and out of the device on the rising edges of ckin. in mii mode, ckin must run at 25 mhz; in smii mode, it must run at 125 mhz. macif_sel_pin controller interface select pullup i this input is tied high to select mii mode and tied low to select smii mode. s_smii_pin smii source synchronous mode select i this pin is tied high for smii source synchronous mode and tied low for source non-synchronous mode. mtxd[3:0] transmit data input i transmit, 4-bit parallel data in for processing and transmission over the tp or fx outputs. the data is clocked in on the rising edge of ckin in mii and smii modes. mtxen transmit enable input i in mii mode, the mtxen input from the controller interface is asserted to indicate valid data on mtxd and mtxer. these inputs are clocked in on the rising edges of ckin. in smii mode, this signal is not used. mtxer transmit error i when asserted, this signal indicates that an error was detected in the connecting mac. when mtxer is asserted for one or more clock periods while mtxen is asserted, the phy-110 transmits one or more symbols in the current frame which are not part of the valid data or delimiter set. the phy-110 ignores mtxer when mtxen is deasserted. mtxc transmit clock o timing signal for all transmit nibble operations. it is 25 mhz in 100 mbits/s operation and 2.5 mhz in 10 mbits/s operation.
10 of 16 ETHERNET phy-110 core db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. mcrs carrier sense o in mii mode, this output is asserted when valid data is detected on the receive tp or fx inputs. the output toggles at 12.5 mhz when no more valid data is detected but data is still being output on the mrxd[3:0] pins. mcrs is deasserted on the rising edge of ckin when data output on mrxd[3:0] has been completed. mcrs is not used in smii mode. mcol collision o this signal is asserted when the phy-110 detects simultaneous transmit and receive activity in half-duplex mode. rx_sync_in global smii synchronization i in smii mode, the rx_sync_in input is asserted once every ten mtxd/mrxd bits to indicate the beginning of each 10-bit data segment on mtxd/mrxd. rx_sync_in is clocked into the core on the rising edge of ckin. in mii mode, rx_sync_in is not used. mrxd[3:0] receive data out o these signals connect to the controller interface. they contain data from the receive tp or fx inputs and are clocked out on the rising edge of ckin in mii and smii modes. mrxdv receive data valid o the phy-110 asserts this signal when it is presenting valid data on the mrxd[3:0] lines. the mrxdv signal remains asserted for the entire duration of the frame and is deasserted prior to the ?st rising edge following the end of the frame. mrxer receive error o this controller interface output is asserted when coding or other speci?d errors are detected on the tp or fx inputs. it is clocked out on the rising edge of mtxc in mii mode. in smii mode, mrxer is not used. mrxc receive clock o timing signal for all receive nibble operations. it is 25 mhz in 100 mbits/s operation and 2.5 mhz in 10 mbits/s operation.
ETHERNET phy-110 core 11 of 16 db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. management interface (mi) signals mdc mi clock i the mdc clock shifts serial data for the internal registers into and out of the mdio line on its rising edge. mdi mi input data i this line carries serial data to the internal registers. the data is clocked in the core on the rising edge of mdc. mdo mi output data o this line carries serial data from the internal registers. the data is clocked out of the core on the rising edge of mdc. mdoen management data output enable o this signal is asserted when valid data is placed on mdo and can be used as a data strobe by the connecting device. mdintn mi interrupt o.d. pullup o the mdintn signal is an active low interrupt output. it is asserted when there is a change in certain internal register bits and deasserted after all changed bits have been read. phyad[3:0] mi physical address i this is the 4-bit address provided to the phy-110. it is a unique address and distinguishes this phy-110 from any other phy present in the system. the phy-110 only responds to transactions if the address in the management frame matches the address on these pins. phyad_offs[4:0] physical address offset i these signals are only relevant when this phy-110 is used for multi-port designs. in multi-port designs the 5-bit offset helps determine the unique 5-bit address of a port, since the device will only have a 5-bit address input. for example, in a two-port design, the offset of the ?st port is zero and the offset of the second port is one. when the offset is added to phyad[4:0], the port gets its unique address. the address offset is a 5-bit input since the absolute maximum number of phys that can be controlled by an sta is 32.
12 of 16 ETHERNET phy-110 core db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. led signals led0? parallel led outputs 0? o these outputs can each be programmed though the mi serial port to indicate any one of 16 events when they are asserted. the following table lists the events and indicates the default for each output. these outputs can drive an led from either v dd or gnd. sled_out (led_1 pin) serial led out o led data output line in serial led mode. sled_latchen (led_2 pin) serial led latch enable o the latch signal is a one-clock wide pulse indicating the end of a frame. sled_clko (led_3 pin) serial led clock o this signal clocks the data out on sled_out at 1 mhz. events defaults fef (far end failure) blink hi z off on 10/100 led0 hdx/fdx led1 col act led2 xmtact rcvact link + aneg link + act link100 link10 link detect led3
ETHERNET phy-110 core 13 of 16 db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. logic scan interface signals scanmode scan mode select i this input is asserted to select the logic scan mode and deasserted (default) for normal operation. test_se scan chain enable i this input is asserted to enable the scan and put all the logic in the scan chain into scan mode. scanck scan clock i the scan clock is connected to all ?ps during scan mode. test_si scan data in i this is the input of the core scan chain during scan mode. scan patterns will be loaded to this input pin. test_so scan data out o this is the output of the scan chain to carry the scan patterns out of the core during scan mode. miscellaneous signals cross_pin crossover enable i asserting the cross input causes a manual crossover of the tp outputs and inputs whether or not autocrossover is enabled (see con?[2:0] following). con?[2:0] core con?urations i the con?[2:0] inputs are read at reset and their coding is used to set the default condition of the register con?uration bits as shown in ta b l e 1 . for example, a con? setting of 0b010 turns off autonegotiation, sets operation to 10 mbits/s half duplex, and turns off autocrossover.
14 of 16 ETHERNET phy-110 core db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. rxtb hardware reset pullup i this input is asserted and then deasserted to reset the core. the core completes reset 100 ms after this signal is deasserted. pd power down i when asserted, pd powers down all of the common reference circuits except those that generate the frck25m clock signal. power supplies vddrx, vddtx, vssrx, vsstxcore, vsstxio i 1.8 v analog supplies and grounds. vddl, vssl i 1.8 v digital supply and ground for digital core circuits. table 1 phy-110 con?urations con?[2:0] internal register bits auto spdsel dplx autoxen 0b000 0b1 = on x x 0b1 = on 0b001 0b1 = on x x 0b0 = off 0b010 0b0 = off 0b0 = 10 mbits/s 0b0 = half 0b0 = off 0b011 0b0 = off 0b0 = 10 mbits/s 0b1 = full 0b0 = off 0b100 0b0 = off 0b1 = 100 mbits/s 0b0 = half 0b0 = off 0b101 0b0 = off 0b1 = 100 mbits/s 0b1 = full 0b0 = off 0b110 0b0 = off 0b0 = 10 mbits/s 0b0 = half 0b1 = on 0b111 0b0 = off 0b1 = 100 mbits/s 0b0 = half 0b0 = off
ETHERNET phy-110 core 15 of 16 db08-000181-00 march 2002 copyright 2002 by lsi logic corporation. all rights reserved. notes
bd printed in usa doc. no. db08-000181-00 to receive product literature, visit us at http://www.lsilogic.com. for a current list of our distributors, sales offices, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/na_salesoffices.html. lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or lia- bility arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. this document is preliminary. as such, it contains data derived from functional simulations and performance estimates. lsi logic has not veri?d the functional descriptions or electrical and mechanical speci?ations using production parts. the lsi logic logo design, flexstream, and g12 are trade- marks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. headquarters lsi logic corporation north american headquarters milpitas ca tel: 408.433.8000 fax: 408.433.8989 lsi logic europe ltd european headquarters bracknell england tel: 44.1344.426544 fax: 44.1344.481039 lsi logic k.k. headquarters tokyo japan tel: 81.3.5463.7821 fax: 81.3.5463.7820 printed on recycled paper iso 9000 certified notes

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