application note AN120-1 AN120 figure 1. digitally-controlled potentiometer xdcp is a trademark of xicor, inc. for the most part, the universe of feedback system design separates neatly into two fundamental design paradigms: analog-based designs and digital-based designs. both design strategies are characterized by advantages and liabilities that generally make one or the other a clearly superior choice for any given application. pure analog designs, for example, tend to display design simplicity and low development costs that play well in the context of smaller system applications. digital-based designs, by contrast, have essentially unlimited ?xibility in computation of the feedback function and therefore dominate in more complex feedback applications in which higher development costs (generally including software implementation) can be justi?d. sometimes, a feature of particular utility in digital designs is the availability of digital memory with its ability to store feedback parameters for arbitrary lengths of time without drift. this makes possible a variety of system solutions including multiple system operating modes in which feedback values can be acquired in some modes and then applied in others. but what about feedback systems that lie in between these clear opposites? what about, for example, relatively simple cost-sensitive applications that yet would bene? from functions that are dif?ult to implement in analog circuits and which therefore require digital techniques? a basis for a useful middle ground between the extremes of pure analog or pure digital feedback designs is offered by an inexpensive component: the xicor 3-wire digitally controlled potentiometer. figure 1 illustrates the architecture of the 3-wire xdcp. the 3-wire xdcp is seen to comprise a digital input and an analog output interface. the 3-wire xdcp digital input interface consists of a bidirectional counter controlled by direction (u/d ), clock (inc ) inputs, and chip select/eeprom-store (cs ) logic signals. the xdcp analog output interface consists of the digitally controlled variable resistance/ potentiometer element. a generalized basic conceptual topology representative of feedback control systems based on the 3-wire xdcp is illustrated in figure 2. it comprises six design elements: a. the xdcp error integrator. during the feedback process, the xdcp closes the feedback loop by accumulating in its up/down control counter successive samples of the system state. b. clocking oscillator. the oscillator controls the rate of feedback sampling. selection of the oscillator period must therefore be based on consideration of both the minimum response time of the xdcp (< 500? for typical xicor parts) and of the rest of the feedback system as determined by such factors as the gain-bandwidth products of the op amp and comparator. appropriate oscillator periods will typically lie in the range of 1 to 100 milliseconds. application of xicor digitally controlled potentiometers (xdcp ) as hybrid analog/digital feedback system control elements w. s. woodward, january 1999 control and memory up/down (u/d) increment (inc) device select (cs) v cc (supply voltage) v ss (ground) v h /r h v w /r w v l /r l
xicor application note AN120-2 AN120 mode control switching feedback networks e d f op amp signal source + output comparator mode control gated clock oscillator digitally controlled pot as feedback error integrator c a b v w v h v l u/d cs inc c. analog/digital feedback (voltage comparator). conversion between the analog state of the output node and the digital u/d xdcp input is the traditional role of the analog comparator. however, the ?xibility of the cmos logic inputs of xicor xdcps often makes it possible to substitute a simple passive voltage-translation network, as will be illustrated in the design applications to follow. d. digital/analog feedback (resistance element circuitry). closure of the feedback loop is achieved by incorporation of the variable resistance element of the xdcp into the active circuitry of the rest of the feedback system. e. intermittent feedback control circuitry (selectable operating modes). some uniquely versatile xdcp-based feedback control applications derive their utility from the ability to implement multiple operation modes in which circuit setpoints (e.g. precision op amp offset null) derived from one operating mode (e.g. autonull mode) are retained in xdcp memory and used in a subsequently selected system mode (e.g. dc ampli?ation). control and selection of such system operating modes is easily achieved through the use of inexpensive, logic-compatible, cmos analog switch elements such as the 74hc4053. f. operational ampli?r. essentially all precision analog systems of the sort that can bene? from xdcp-based feedback designs will incorporate at least one monolithic op amp. selection of a suitable (e.g. adequate gain, bandwidth, dc accuracy) op amp is therefore an important step in the feedback system design process. figure 2 s conceptual topology has been utilized to advantage in a variety of real-life applications. examples include: auto-nulling delta-t thermometer some precision temperature measurement applications, such as acquiring the temperature rise of a heatsink in response to a thermal load, are inherently concerned with temperature change relative to an initial value, rather than absolute temperature. in such applications, important figure 2. basic xdcp-based feedback control loop
xicor application note AN120-3 AN120 100hz .022 r 5 24k -5v 10k r 2 v w v h +5v platinum rtd (100 @ 0 c) +0.385%/ c r t r 1 +5v 4870 249k 3 6 7 5110 3 4 -5 5 a 1 ad822 3 2 + a 2 + 9 s 3 +5v 5 100pf .001 +5v u/d p 1 cs 4 7 12 x9c102 p 2 s 2 r 9 r 8 p 2 calibration/adj data 6 ? t out 1k s 1 c 1 10k r 4 274k 5 .1 7 4 ad822 acquire t 0 10 6 0 74hc4053 oscillator ~10mv/ c inc 1 p 1 200k +9.625 @ 25 c 0 c to 50 c v l 1 sec 1 r 3 2 16 8 +5 200k 8 13 1k "0" = output (t-t 0 ) "1" = acquires t 0 improvement in measurement resolution can be gained from the scale expansion made possible by acquisition of the initial baseline temperature and subtracting it from subsequent measurements before analog to digital conversion. figure 3 presents an auto-nulling thermometric circuit that performs this function automatically using digitally controlled potentiometers as the baseline temperature memory. the basis for temperature sensing in this circuit is rt, a standard 100ohm @ 25? pt rtd. such devices have a highly stable and accurate tempco of +0.385ohm/?. therefore the -lma of excitation current provided by r1 leads to a temperature-dependent signal of ~385uv/1?. r2, p1, and r3 complete a ratiometric bridge with a1 as the bridge ampli?r. the feature of the circuit that utilizes the ability of digitally-controlled-pot s to act as feedback elements is the process that automatically captures and holds the initial reference temperature that is subtracted from subsequent readings. acquisition of a reference temperature is initiated by bringing the 5v logic signal acquire low. this causes s3 to open the feedback loop around a1 and simultaneously enables the s1-s2 multivibrator. the result is to cause p1 to sample a1 s output at a 100hz rate and drive a1 toward null. figure 3. autonulling d t?thermometer?etailed
xicor application note AN120-4 AN120 the 100hz sampling rate is determined by the r8, r9, c1 timing components in the s1-s2 multivibrator with the oscillator period approximately equal to c1(r8 + r9). the relatively long (~10ms) period is dictated by the operation of a1 as an open-loop comparator while in null mode. op amps such as a1 make relatively good comparators in terms of ultimate dc accuracy, but they have much slower response times (multiple millisecond slew times) than true comparators, especially when the differential input voltage is near null. because the ad822 op amp has a gain- bandwidth product of ~3mhz, the time required for a 5v output slew is approximately 5v/(3mhz* vin)=1.7ms/mv. therefore, allowing ~10ms settling time between output- state samples implies a null-point resolution of +/-170? =+/-0.50?. if acquire is held low long enough (1 second will always suf?e), the result will be for p1 to be driven to the setting that causes a1 to dither around zero output, indicating that p1 s setting is alternating between the two values that bracket optimum t0 null. when acquire is returned to logic ?? p1 will therefore retain the bridge-ratio needed to cancel the temperature present at rt during the nulling process and cause the thermometric signal presented to scaling op amp a2 to thus be referenced to this initial t0. because p1 setpoint memory is digital, it will hold this ratio forever unless acquire is deliberately put through another 0/1 cycle to acquire a new t0, or power is removed from the thermometer. a2 applies the necessary gain, digitally ?e-adjusted by p2, of 01/.000385=25.97 to achieve an output scale factor of 10mv/?. op amp offset nulling op amp applications that need the highest possible dc accuracy are generally best served by cmos chopper- stabilized ampli?rs, such as the ltc1050. but high-speed, low-noise applications may require high-performance rockets, such as the 700-mhz lt1226. so what to do for applications that need it all ? sometimes, a composite topology in which a bipolar ampli?r provides gain- bandwidth and a cmos chopper acts as an offset-nulling servo can do the job. such arrangements can successfully null out offset-voltage errors. but these circuits can get messy if you also need bias-current-related error correction. the circuit in figure 4 offers an error- cancellation method that handles both error sources. figure 4. have your cake (high speed) and eat it (low dc errors) too, with this autonulling circuit, using a digitally controlled potentiometer.
xicor application note AN120-5 AN120 the circuit consists of op amp ic1 (for example, linear technology s lt1226), cmos multiplexer s c (one-third of an hc4053), and digital potentiometer p1 (xicor s x9c103). the topology supports two modes of operation, as selected by the ttl/cmos-compatible nadj signal. nadj=0 connects ic1 as a standard noninverting gain block. the circuit values shown, combined with the impressive specs of the frequency-compensated lt1226, provide a gain of 1001 with bandwidth extending from dc to beyond 500 khz and input-related noise of approximately 2 nv/ ? hz . null-adjustment mode occurs when nadj=1 disconnects the input source and effectively causes ic1 s output to run open-loop. ic1 s output and then slews to one rail or the other, as determined by the sign of its net offset error. if r3=rs?1||r2, where rs is the dc source resistance, then ic1 s output re?cts the sum of both voltage and current bias errors. the circuit level-shifts and ?ters ic1 s output and applies it to the up/down control input of p1. this action sets up p 1 s internal up/down-counter logic to increment of decrement one step, depending on the state of ic1 s output and thus on the sign of ic1 s offset. the counter step occurs on the subsequent nadj=0 transition. the connection of the vl, vw, and vh terminals of p1 to the nulling terminals of ic1 closes a feedback loop that tends to push ic1 one step toward null for every 10 cycles of nadj. because the x9c103 has 100 resolved settings, the technique requires a maximum of 99 nadj pulses to complete the nulling process. after nulling, p1 retains the ?al null setting in digital memory as long as the 5v supply remains connected or until the nulling process repeats. observed performance reveals that using an op37 consistently achieves residual-offset errors of less than 5 ?. if it is inconvenient to provide an external nadj clock source in a given application, you can add the sa/sb multivibrator at node 1. this 1-khz clock circuit receives its gating from the cmos-compatible anull signal, such that anull=1 enables continuous null adjustment, and anull=0 enables normal ampli?r operation. the maximum anull duration required to achieve initial null is 100msec. if desired, you can also include d1, r8, and c3 at node 2 to provide an automatic null on each power-up cycle. although figure 4 shows an lt1226, the circuit works without modi?ation with an op37 and lt1028. the circuit is also pin-compatible with the popular lt1128, op07, op77, op177, and ?25 op amps. with these op amps, however, the circuit may require a slower nadj clock rate and a longer nulling interval (increase c2 and c3), because of the lower gain-bandwidth product of these compensated types. the circuit can accommodate many other op-amp types with a simple change of pin connections. the circuit can handle 15v positive-rail operations by substituting an x9312 for the x9c103 with no other changes. power amplifier biasing the day may be near when every ampli?r application can be served simply by ?ding the right off-the-shelf stand- alone chip. maybe. but for now, many jobs require that even the best monolithic devices be supplemented with a sprinkling of active discrete devices. one such category of application is the high-output-current, high-frequency buffer ampli?r in figure 5. of course it s simplicity in itself to add an arbitrary amount of muscle to a ?ilquetoast op amp by following it with a class ab complementary bipolar emitter-follower or fet source follower pair like q1 and q2 in the figure 5. many successful driver designs are based on just this elementary topology. but all such designs must confront the problem of stable dc biasing of the follower while avoiding unconscionable amounts of quiescent power draw and unbearable levels of harmonic distortion. this is a problem fraught with the classic twin-design-bogeymen of thermal runaway and cross-over distortion. the new solution to this old puzzle described here comprises an automatic bias adjustment loop consisting of a xicor digital potentiometer p1, international recti?r photovoltaic optoisolator o1, cmos switches s1-s3, and linear technology op amps a2-3. the resulting adjustment loop includes two modes of operation selected by the cmos/ttl-compatible adj input. when adj=0, s3 closes a normal feedback loop around a1 and the q1/q2 pair thus forcing the circuit to become a fairly normal, gain of -5 ampli?r with a bandpass of dc to 10 mhz, full power bandwidth (limited by a1 slew) of 5 mhz, and output limits of ?0v and ?0a. harmonic distortion over the full operating range is minimized by the impressive gbw of capacitive-load-compatible a1 combined with stable quiescent biasing of the q1/q2 pair to a thrifty no signal value of 50 ma. the trick behind these performance numbers is the way an appropriate bias level for the follower is achieved, one that s independent of temperature and component tolerance variations. to understand how this is done, consider how the circuit rearranges itself when adj=1 causes s3 to disconnect a1 s input from the signal source and substitute a ground reference. simultaneously, the s1/s2, 20-hz multivibrator is enabled and begins clocking p1. in response, p1 begins to vary the input to a3, which then servos the control current into o1 and thus the net gate bias voltage at the follower mosfets.
xicor application note AN120-6 AN120 this action combines with a2 to establish a feedback loop, which tends to drive the follower pair to the desired zero- signal bias. this action occurs because, if the follower bias current iq is less than 50 ma, then the drop across r3 will be less than the drop across r4. as a result, a2 drives the up/down input of p1 high (up). therefore, on the next negative transition of the clock, the vw terminal of p1 will make one step toward the vh terminal. this increases the drive to c1, which ups the follower bias. if iq is more than 50 ma, then a2 s output state will reverse, causing p1 to step vw toward vl and decrease the follower quiescent bias. consequently, after a maximum of 5 seconds and 99 multivibrator cycles, the follower bias will have been forced to converge to the bias level set by the r4/r3 ratio. adj then may be reset to zero for normal ampli?r operation; the ?al bias setting will be retained by p1 until either power is removed or a new adj cycle initiated. thermal coupling between d1/q1 and d2/q2 improves overall bias stability between adjustment cycles. although illustrated with ?5-v supplies, the unique ?ver- the-top input topology of a2 is compatible with v+ voltages as high as 36 v (but be careful to observe a1 limitations). also, there is no requirement that the v+ and v- voltages be symmetrical. many variations are possible when selecting a1 and the follower mosfets to achieve different combination of output capabilities. proportional-integral thermostat a classic scheme for precision temperature control is the proportional-integral or ?/i algorithm. in this method, the heater control equation consists of two terms. one term (?? is proportional to the instantaneous error differential between sensor and setpoint temperatures. the other (?? is proportional to the time integral of the error. p/i controllers characteristically have reasonably good dynamic response due to the proportional feedback term, nominally zero steady-state error thanks to the error integration term, and relatively simple loop optimization figure 5. this high-output-current, high-frequency buffer amplifier uses an automatic bias adjustment loop, utilizing a xicor digital potentiometer p1, to minimize harmonic distortion while drawing a thrifty no-signal supply current of only 50 ma.
xicor application note AN120-7 AN120 because only three adjustments (setpoint, proportional gain, and integrator time-constant) are involved in the setup process. the simplicity of the p/i feedback algorithm argues for a similarly simple analog-based controller design. but some temperature-control applications involve long time- constants (running to minutes and hours) and often must live in hostile (hot and contaminated) industrial environments. these gremlins combine to make analog long-time-constant circuits problematic, with their high impedances and nano-ampere signal currents. this is so because nasty ambients exaggerate the leakage and bias currents of op amps, integrator capacitors, and even circuit boards. the controller shown in the figure 6 achieves adequate time-constants without the delicate high-impedance analog circuits. it uses xicor s x9c103 digitally controlled potentiometers as feedback elements together with the linear technology ltc1040 sampled comparator. controller operation is based upon a positive-temperature- coef?ient (3850 ppm/?) platinum rtd sensor arranged in a standard ratiometric bridge with reference resistors r1, r3, and r5, and setpoint pot r4. aiding controller stability and precision is high level ( ? 5 ma) bridge excitation. it produces a relatively large 1.7 mv/? rtd output signal that competes well against noise pickup and thermal-emf error sources. typically, such a high rtd drive level would threaten to produce large and unacceptable sensor self-heating errors. but in this case, sensor excitation is pulsed (80?) under control of the ltc1040. this keeps average sensor dissipation duty factor low ( ? 1%) and self-heating error inconsequential. figure 6. this controller acheives extended time constants without the delicate high-impedance analog circuits by using xicor? x9c103 digitally-controlled potentiometers as feedback elements, combined with linear technology? ltc1040 sampled comparator.
xicor application note AN120-8 AN120 on each measurement cycle, a1 s lower input pair samples the bridge output. depending on the result of the comparison, they tend to drive the pin 4 output bit to 0 or 1, as the bridge reports an rtd-setpoint differential that s negative or positive. thus, the solid-state relay (ssr) and heater will most likely turn on when the temperature is low and off when it s high. to make the resulting on/off heater drive have an average duty-factor that s nicely proportional to the magnitude of the temperature error signal and not just a simple ?ang- bang relationship, the bridge output voltage is summed with a triangular dither signal produced by p2. the combination of p2 and u2 causes p2 to output one full triangular dither waveform every 128 measurement cycles. thermal inertia of the hearer and the thermal load averages over the heater cycle rate (1 hz in this example). consequently, suitable selection of the r6-c1 oscillator rc will avoid signi?ant temperature ripple. r2 adjusts the amplitude of the p2 dither signal and thereby sets the effective controller p-term gain that relates heater duty factor to temperature error to get adequate control loop ?tiffness without oscillation. meanwhile, error integrator a2 + p1 also samples the temperature difference signal. the integration sampling frequency, and therefore the integrator time constant, is set by the choice of which u2 output bit is connected to p1 s clock. this arrangement causes the integrator to take one step in the direction of zero setpoint error every 1, 2, 4, 8, 16, 32, 64, or 128 heater dither cycles. as a result, it
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