? at a glance ? product brief S19233 10 gbe/fibre channel/sonet/sdh/fec dual cdr empowering intelligent optical networks 1 pb1592_v1.01_02/11/05 description the S19233 10 gbe/fc/sonet/sdh/ fec dual clock data recovery (cdr) is one of the latest additions to the amcc product family. S19233 device contains dual cdrs that provide fully integrated clock recovery signal conditioning capabilities for low power 10 gbps applications. the device performs all necessary clock and data recovery/clock clean-up functions in conformance with sonet/sdh, 10gbe, 10 gbps fc and g.709 transmission standards. the S19233 is primarily designed to be used in the xfp msa module. the standard operating range is from 9.95 gbps to 11.3 gbps. figure 1, system block diagram , shows a typical network application. overview the S19233 can be used to implement the front end of sonet/sdh/fec/ 10gbe/10gfc equipment which consists primarily of the serial transmit interface and the serial receive interface. the system circuitry consists of a high- speed phase detector, clock dividers, and equalization circuitry. the device utilizes on-chip cloc k recovery/clock clean-up pll components that allow the use of a slower external clock reference, 155.52 mhz (or equivalent fec/10gbe/ 10 gbps fc rates), in support of existing system clocking schemes. an equalizer is integrated in the receive front end of the tx side and it reshapes the data after transmission over a standard fr-4 material. this enables low bit error rate and transmission over longer distances. the device would allow users to meet the maximum dispersion penalty per itu lr 2a, b, & c specifications with margin. integrated in the S19233 on the receive optical side is an adjustable filter (dispersionxx tm ), offset cancellation circuitry to improve sensitivity, limiting amp with threshold adjust, and a cdr with phase adjust. the low-jitter, 1-bit, cml interfaces guarantee compliance with the bit-error rate requirements of the telcordia and itu-t standards. the high speed serial input and output can be connected to the amcc serdes (s19235 or s19237) or others across 24 inches of standard fr- 4 with one connector. the S19233 is packaged in a 6 mm x 6 mm package, offering designers a small package outline. s 1 9 2 3 3 general features ? complies with itu-t specifica- tions, 2.7 mui rms max. jitter gen- eration (50 khz - 80 mhz) ? complies with xfp msa specifi- cations ? 9.95 to 11.3 gbps operation ? optimized for up to 100 km smf ? dual cdr - typical power 0.6 w ? optical and electrical loopbacks ? threshold & phase adjust ? cml serial input sensitivity at 10 mv pk-pk differential ? offset cancellation circuit ? rssi - receive signal strength indicator ? los - loss of signal detect ? termination and biasing for ac coupling ? power down cdr mode ? reference clocks range 155 - 176 mhz ? equalization on the electrical receive side ? lock detect indication ? -40 to 85 c operation ? 1.8/3.3 volt power supply ?i 2 c serial interface continued on next page... figure 1. system block diagram 16 orx otx 16-bit framer amcc S19233 xfp module tosa rosa tx rx 1 1 amcc s19235 or s19237 16 otx orx 16-bit framer 1 1 amcc s19235 or s19237 tosa rosa amcc S19233 xfp module tx rx 16 16
6290 sequence drive ? san diego, ca 92121 ? tel: 858 450-9333 ? fax: 858 450-9885 ? http://www.amcc.com amcc reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is current. amcc is a registered trademark of applied micro circuits corporation. copyright ? 200 5 applied micro circuits corporation. all rights reserved. distribute only on a need-to-know basis, and subj ect to applicable nda. not to be disclosed to or used by any other person with out prior authorization. product brief S19233 10 gbe/fibre channel/sonet/sdh/fec dual cdr pb1592_v1.01_02/11/05 2 empowering intelligent optical networks confidential and proprietary the sequence of operations is as follows: transmitter operations 1. 1-bit serial data input 2. equalization to compensate for 24+ inches of fr-4 3. clock recovery 4. data retime 5. serial data output receiver operations 1. serial input to post amp 2. equalization adjust 3. 10 mv input sensitivity (differential) 4. threshold adjustment 5. lock detect 6. clock and data recovery 7. serial data output internal clocking and control functions are transparent to the user. amcc suggested interface devices s19235 sonet/sdh sts-192/10 gig ethernet cmos transceiver with isi compensation s19237 sonet/sdh sts-192/10 gig ethernet cmos transceiver with isi compensation s3390 oc-192 transimpedance amplifier s3095 oc-192 transimpedance with automatic gain control ? serial interface polarity swap (per input) ? 6 mm x 6 mm, 49 pin pbga package with 0.8 mm pitch applications ? xfp msa modules ? 10 gbe and 10g fc designs ? sonet/sdh based transmission equipment ? sonet/sdh test equipment ? sonet/sdh/fec dwdm equipment figure 2. S19233 ordering information prefix package device s ? integrated circuit 19233 fp s 19233 fp prefix device package
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