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data sheet ?2010 greenliant systems, ltd. s71060-10-000 05/10 www.greenliant.com 512 kbit (64k x8) page-write eeprom gls29ee512 features: ? single voltage read and write operations ? 4.5-5.5v for gls29ee512 ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption ? active current: 20 ma (typical) ? standby current: 10 a (typical) ? fast page-write operation ? 128 bytes per page, 512 pages ? page-write cycle: 5 ms (typical) ? complete memory rewrite: 2.5 sec (typical) ? effective byte-write cycle time: 39 s (typical) ? fast read access time ? 4.5-5.5v operation: 70 ns ? latched address and data ? automatic write timing ? internal v pp generation ? end of write detection ? toggle bit ? data# polling ? hardware and software data protection ? product identification can be accessed via software operation ? ttl i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 32-lead plcc ? 32-lead tsop (8mm x 20mm) ? 32-pin pdip ? all non-pb (lead-free) devices are rohs compliant product description the gls29ee512 is a 64k x8 cmos, page-write eeprom manufactured with high-performance super- flash technology. the split-gate cell design and thick- oxide tunneling injector attain better reliability and manu- facturability compared with alternate approaches. the gls29ee512 writes with a single power supply. internal erase/program is transparent to the user. the gls29ee512 conforms to jedec standard pin assign- ments for byte-wide memories. featuring high performance page-write, the gls29ee512 provides a typical byte-write time of 39 sec. the entire memory, i.e ., 64 kbyte, can be written page-by-page in as little as 2.5 seconds, when using interface features such as toggle bit or data# polling to indicate the completion of a write cycle. to protect against inadvertent write, the gls29ee512 have on-chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, the gls29ee512 is offered with a guar- anteed page-write endurance of 10,000 cycles. data retention is rated at greater than 100 years. the gls29ee512 is suited for applications that require convenient and economical updating of program, config- uration, or data memory. for all system applications, the gls29ee512 significantly improves performance and reliability, while lowering power consumption. the gls29ee512 improves flexibility while lowering the cost for program, data, and configuration storage applica- tions. to meet high density, surface mount requirements, the gls29ee512 is offered in 32-lead plcc and 32-lead tsop packages. a 600-mil, 32-pin pdip package is also available. see figures 1, 2, and 3 for pin assignments. device operation the greenliant page-write eeprom offers in-circuit elec- trical write capability. t he gls29ee512 does not require separate erase and program operations. the internally timed write cycle executes both erase and program trans- parently to the user. the gls29ee512 has industry stan- dard optional software data protection, which greenliant recommends always to be enabled. the gls29ee512 is compatible with industry standard eeprom pinouts and functionality. gls29ee512512kb (x8) page-write, small-sector flash memories
2 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 read the read operations of the gls29ee512 is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is t he output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram fo r further details (figure 4). write the page-write to the gls2 9ee512 should always use the jedec standard software data protection (sdp) three-byte command sequence. the gls29ee512 con- tains the optional jedec approved software data protec- tion scheme. greenliant reco mmends that sdp always be enabled, thus, the description of the write operations will be given using the sdp enabled format. the three-byte sdp enable and sdp write commands are identical; therefore, any time a sdp write command is issued, software data protection is automatically assured. the first time the three-byte sdp command is given, the device becomes sdp enabled. subsequ ent issuance of the same command bypasses the data protection for the page being written. at the end of the desired page-write, the entire device remains protected. for additional descriptions, please see the application notes the proper use of jedec standard software data protection and protecting against unintentional writes when using single power supply flash memories . the write operation consists of three steps. step 1 is the three-byte load sequence for software data protection. step 2 is the byte-load cycle to a page buffer of the gls29ee512. steps 1 and 2 use the same timing for both operations. step 3 is an interna lly controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. during both the sdp three- byte load sequence and the by te-load cycle, the addresses are latched by the falling e dge of either ce# or we#, whichever occurs last. the data is latched by the rising edge of either ce# or we#, whichever occurs first. the internal write cycle is initiated by the t blco timer after the rising edge of we# or ce#, wh ichever occurs first. the write cycle, once initiated, wil l continue to completion, typi- cally within 5 ms. see figures 5 and 6 for we# and ce# controlled page-write cycle timing diagrams and figures 15 and 17 for flowcharts. the write operation has three functional cycles: the soft- ware data protection load sequence, the page-load cycle, and the internal write cycle. the software data protection consists of a specific three- byte load sequence that allows writing to the selected page and will leave the gls29ee512 protected at the end of the page-write. the page-load cycle consists of loading 1 to 128 bytes of data into the page buffer. the inter nal write cycle consists of the t blco time-out and the write ti mer operation. during the write operation, the only valid reads are data# polling and toggle bit. the page-write operation allows the loading of up to 128 bytes of data into the page buffer of the gls29ee512 before the initiation of the internal write cycle. during the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. hence, the page- write feature of gls29ee512 allows the entire memory to be written in as little as 2.5 seconds. during the internal write cycle, the host is fr ee to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. in each page-write oper- ation, all the bytes that are loaded into the page buffer must have the same page address, i.e. a 7 through a 16 . any byte not loaded with user data will be written to ffh. see figures 5 and 6 for the page-write cycle timing dia- grams. if after the completion of the three-byte sdp load sequence or the initial byte-l oad cycle, the host loads a second byte into the page buffer within a byte-load cycle time (t blc ) of 100 s, the gls29 ee512 will stay in the page-load cycle. additional by tes are then loaded consecu- tively. the page-load cycle will be terminated if no addi- tional byte is loaded into the page buffer within 200 s (t blco ) from the last byte-load cycle, i.e., no subsequent we# or ce# high-to-low transiti on after the last rising edge of we# or ce#. data in the page buffer can be changed by a subsequent byte-load cycl e. the page-load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 s. the page to be loaded is determined by the page address of the last byte loaded. software chip-erase the gls29ee512 provides a chip-erase operation, which allows the user to simultaneously clear the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the software chip-erase operation is initiated by using a specific six-byte load sequen ce. after the load sequence, the device enters into an internally timed cycle similar to the
data sheet 512 kbit page-write eeprom gls29ee512 3 ?2010 greenliant systems, ltd. s71060-10-000 05/10 write cycle. during the erase operation, the only valid read is toggle bit. see table 4 for the load sequence, figure 10 for timing diagram, and fi gure 19 for the flowchart. write operation status detection the gls29ee512 provides two software means to detect the completion of a write cycle, in order to optimize the sys- tem write cycle time. the soft ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end of write detection mode is enabled after the rising we# or ce# whichever occurs firs t, which initiates the internal write cycle. the actual completion of the n onvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the writ e cycle, otherwise the rejec- tion is valid. data# polling (dq 7 ) when the gls29ee512 is in t he internal write cycle, any attempt to read dq 7 of the last byte loaded during the byte- load cycle will receive the complement of the true data. once the write cycle is completed, dq 7 will show true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. see fig- ure 7 for data# polling timing diagram and figure 16 for a flowchart. toggle bit (dq 6 ) during the internal write cycl e, any consecutive attempts to read dq 6 will produce alternating ?0?s and ?1?s, i.e., toggling between 0 and 1. when the write cycle is completed, the toggling will stop. the device is then ready for the next operation. see figure 8 for toggle bit timing diagram and figure 16 for a flowchart. the initial read of the toggle bit will typically be a ?1?. data protection the gls29ee512 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 2.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write oper ation. this pr events inadver- tent writes during power-up or power-down. software data protection (sdp) the gls29ee512 provides the jedec approved optional software data protection scheme for all data alteration operations, i.e., write and ch ip-erase. with this scheme, any write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. the three-byte l oad sequence is used to initiate the write cycle, prov iding optimal protection from inadver- tent write operations, e.g. , during the system power-up or power-down. the gls29ee512 is shipped with the soft- ware data protection disabled. the software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (figures 5 and 6). the device will then be automatically set into the data protect mode. any subsequent write operation wi ll require the preceding three-byte sequence. see tabl e 4 for the specific soft- ware command codes and figures 5 and 6 for the tim- ing diagrams. to set the device into the unprotected mode, a six-byte sequence is required. see table 4 for the specific codes and figure 9 for the timing diagram. if a write is attempted wh ile sdp is enabled the device will be in a non-accessible state for ~ 300 s. greenliant recommends software data protection always be enabled. see figure 17 for flowcharts. the gls29ee512 software data protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). therefore using sdp for a sing le page-write will enable sdp for the entire array. single pages by themselves cannot be sdp enabled or disabled, although the page addressed during the sdp write will be written.
4 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 single power supply reprogrammable nonvolatile memo- ries may be unintentionally alte red. greenliant strongly rec- ommends that software data protection (sdp) always be enabled. the gls29ee512 s hould be programmed using the sdp command sequence. gr eenliant recommends the sdp disable command sequence not be issued to the device prior to writing. please refer to the following application notes for more information on using sdp: ? protecting against unin tentional writes when using single power supply flash memories ? the proper use of jedec standard software data protection product identification the product identification mode i dentifies the device as the gls29ee512 and manufacturer as greenliant. this mode is accessed via software. for details, see table 4, figure 11 for the software id entry, and read timing diagram and figure 18 for the id entry command sequence flowchart. product identification mode exit in order to return to the standard read mode, the software product identification mode must be exited. exiting is accomplished by issuing the soft ware id exit (reset) opera- tion, which returns the device to the read operation. the reset operation may also be used to reset the device to the read mode after an inadvert ent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. see table 4 for software command codes, figure 12 for timing waveform, and figure 18 for a flowchart. table 1: p roduct i dentification address data manufacturer?s id 0000h bfh device id gls29ee512 0001h 5dh t1.3 1060 y-decoder and page latches i/o buffers and data latches 1060 b1.1 address buffer & latches x-decoder dq 7 - dq 0 a 15 - a 0 we# oe# ce# superflash memory control logic f unctional b lock d iagram
data sheet 512 kbit page-write eeprom gls29ee512 5 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 1: p in a ssignments for 32- lead plcc figure 2: p in a ssignments for 32- lead tsop 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 nc nc v dd we# nc 32-lead plcc top view 1060 32-plcc nh p1.0 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6 1060 32-tsop eh p2 .0 a11 a9 a8 a13 a14 nc w e# v dd nc nc a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 standard pinout top view die up
6 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 3: p in a ssignments for 32- pin pdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin pdip top view 1060 32-pdip ph p3.0 nc nc a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd we# nc a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3
data sheet 512 kbit page-write eeprom gls29ee512 7 ?2010 greenliant systems, ltd. s71060-10-000 05/10 table 2: p in d escription symbol pin name functions a 15 -a 7 row address inputs to provide me mory addresses. row addresses define a page for a write cycle. a 6 -a 0 column address inputs column addresses are toggled to load page data dq 7 -dq 0 data input/output to out put data during read cycles and rece ive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide: 5.0v supply (4.5-5.5v) for gls29ee512 v ss ground nc no connection unconnected pins. t2.3 1060 table 3: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in page-write v il v ih v il d in a in standby v ih x 1 1. x can be v il or v ih , but no other value. x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x software chip-erase v il v ih v il d in a in, see table 4 product identification software mode v il v ih v il manufacturer?s id (bfh) device id 2 2. device id = 5dh for gls29ee512 see table 4 sdp enable mode v il v ih v il see table 4 sdp disable mode v il v ih v il see table 4 t3.4 1060
8 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 note: this product supports both the jedec standard three-byte comma nd code sequence and greenliant?s original six-byte command code sequence. for new designs, greenliant recommends that the three-byte command code sequence be used. table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data software data protect enable & page-write 5555h aah 2aaah 55h 5555h a0h addr 2 data software chip- erase 3 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 4,5 5555h aah 2aaah 55h 5555h 90h software id exit 5555h aah 2aaah 55h 5555h f0h alternate software id entry 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 60h t4.4 1060 1. address format a 14 -a 0 (hex), address a 15 can be v il or v ih , but no other value.? 2. page-write consists of loading up to 128 bytes (a 6 -a 0 ) 3. the software chip-erase function is not supported by the industrial temperature part. please contact greenliant if you require this function for an industrial temperature part. 4. the device does not remain in software product id mode if powered down. 5. with a 14 -a 1 = 0; greenliant manufacturer?s id = bfh, is read with a 0 = 0, gls29ee512 device id = 5dh, is read with a 0 = 1 6. alternate six-byte software product id command code
data sheet 512 kbit page-write eeprom gls29ee512 9 ?2010 greenliant systems, ltd. s71060-10-000 05/10 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater th an those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress ra ting conditions may affe ct device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 14.0v package power dissipa tion capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hole lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 m a 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc pack age types are capable of 240 c for 10 seconds; please consult the factory for the latest information. 2. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange for gls29ee512 range ambient temp v dd commercial 0c to +70c 4.5-5.5v industrial -40c to +85c 4.5-5.5v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . . . . . 1 ttl gate and c l = 100 pf see figures 13 and 14 table 5: dc o perating c haracteristics v dd = 4.5-5.5v for gls29ee512 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht , at f=1/t rc min, v dd =v dd max read 30 ma ce#=oe#=v il , we#=v ih , all i/os open program and erase 50 ma ce#=we#=v il , oe#=v ih , v dd =v dd max i sb1 standby v dd current (ttl input) 3 ma ce#=oe#=we#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 50 a ce#=oe#=we#=v dd -0.3v, v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v v dd =v dd max v ol output low voltage 0.4 v i ol =2.1 ma, v dd =v dd min v oh output high voltage 2.4 v i oh =-400 a, v dd =v dd min t5.2 1060
10 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 ac characteristics table 6: r eliability c haracteristics symbol parameter minimum sp ecification units test method n end 1 1. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 ma jedec standard 78 t6.5 1060 table 7: r ead c ycle t iming p arameters for gls29ee512 symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 30 ns t clz 1 1. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t7.3 1060 table 8: p age -w rite c ycle t iming p arameters symbol parameter min max units t wc write cycle (erase and program) 10 ms t as address setup time 0 ns t ah address hold time 50 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 0 ns t cp ce# pulse width 70 ns t wp we# pulse width 70 ns t ds data setup time 35 ns t dh 1 1. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this paramet er. data hold time 0 ns t blc 1 byte load cycle time 0.05 100 s t blco 1 byte load cycle time 200 s t ida 1 software id access and exit time 10 s t sce software chip-erase 20 ms t8.6 1060
data sheet 512 kbit page-write eeprom gls29ee512 11 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 4: r ead c ycle t iming d iagram figure 5: we# c ontrolled p age -w rite c ycle t iming d iagram 1060 f04 .0 ce# a ddress a 15-0 oe# we# dq 7-0 v ih t clz t oh data valid data valid t olz t oe high-z t ce t chz t ohz t rc t aa 1060 f05.0 ce# oe# we# address a 15-0 dq 7-0 sw0 aa 55 a0 data valid sw1 sw2 byte 0 byte 1 byte 127 t ds t dh t blc t blco t wc t wp t oeh t oes t ch t cs t ah t as 5555 three-byte sequence for enabling sdp 2aaa 5555
12 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 6: ce# c ontrolled p age -w rite c ycle t iming d iagram figure 7: d ata # p olling t iming d iagram 1060 f06.0 ce# oe# we# address a 15-0 dq 7-0 sw0 aa 55 a0 data valid sw1 sw2 byte 0 byte 1 byte 127 t ds t dh t blc t blco t wc t cp t oeh t oes t ch t cs t ah t as 5555 three-byte sequence for enabling sdp 2aaa 5555 1060 f07 .0 ce# oe# we# t wc + t blco d# t oe t oeh t ce t oes d# d a ddress a 15-0 dq 7 d
data sheet 512 kbit page-write eeprom gls29ee512 13 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 8: t oggle b it t iming d iagram figure 9: s oftware d ata p rotect d isable t iming d iagram 1060 f08.0 ce# oe# we# t wc + t blco two read cycles with same outputs t oeh t oe t oes t ce a ddress a 15-0 dq 6 1060 f09.0 ce# oe# we# address a 14-0 dq 7-0 sw0 sw1 sw2 sw3 sw4 sw5 t blco t blc t wc t wp 5555 5555 55 aa 55 20 aa 80 six-byte sequence for disabling software data protection 2aaa 2aaa 5555 5555
14 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 10: s oftware c hip -e rase t iming d iagram figure 11: s oftware id e ntry and r ead 1060 f10.0 ce# oe# we# address a 14-0 dq 7-0 sw0 sw1 sw2 sw3 sw4 sw5 t blco t blc t sce t wp 5555 5555 55 aa 55 10 aa 80 six-byte code for software chip-erase 2aaa 2aaa 5555 5555 1060 f11.0 ce# oe# we# address a 14-0 dq 7-0 sw0 sw1 sw2 t ida t aa t blc t wp 5555 55 aa bf 5d 90 three-byte sequence for software id entry 0000 2aaa 0001 5555
data sheet 512 kbit page-write eeprom gls29ee512 15 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 12: s oftware id e xit and r eset 1060 f12.0 ce# oe# we# a ddress a 14-0 dq 7-0 sw0 sw1 sw2 t ida t blc t wp 5555 55 aa f0 three-byte sequence for software id exit and reset 2aaa 5555
16 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 13: ac i nput /o utput r eference w aveforms figure 14: a t est l oad e xample 1060 f13.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (2.4v) for a logic ?1? and v ilt (0.4 v) for a logic ?0?. measurement reference points for inputs and outputs are v ht (2.0 v) and v lt (0.8 v). input rise and fall times (10% ? 90%) are <10 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test 1060 f14.0 to tester to dut c l r l low r l high v dd
data sheet 512 kbit page-write eeprom gls29ee512 17 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 15: w rite a lgorithm 1060 f15.0 no load byte data ye s byte address = 128? write completed increment byte address by 1 wait t blco wait for end of write (t wc , data# polling bit or toggle bit operation) set byte address = 0 set page address software data protect write command start see figure 17
18 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 16: w ait o ptions 1060 f16.0 no no read a byte from page ye s ye s does dq 6 match? write completed read same byte page-write initiated toggle bit wait t wc write completed page-write initiated internal timer read dq 7 (data for last byte loaded) is dq 7 = true data? write completed page-write initiated data# polling
data sheet 512 kbit page-write eeprom gls29ee512 19 ?2010 greenliant systems, ltd. s71060-10-000 05/10 1060 f17.0 write data: aah address: 5555h software data protect enable command sequence write data: 55h address: 2aaah write data: a0h address: 5555h wait t wc wait t blco sdp enabled load 0 to 128 bytes of page data optional page load operation write data: aah address: 5555h software data protect disable command sequence write data: 55h address: 2aaah write data: 80h address: 5555h write data: aah address: 5555h wait t wc wait t blco sdp disabled write data: 55h address: 2aaah write data: 20h address: 5555h
20 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 17: s oftware d ata p rotection f lowcharts figure 18: s oftware p roduct c ommand f lowcharts 1060 f18.0 write data: aah address: 5555h software product id entry command sequence write data: 55h address: 2aaah pause 10 ? write data: 90h address: 5555h read software id write data: aah address: 5555h software product id exit & reset command sequence write data: 55h address: 2aaah pause 10 ? write data: f0h address: 5555h return to normal operation
data sheet 512 kbit page-write eeprom gls29ee512 21 ?2010 greenliant systems, ltd. s71060-10-000 05/10 figure 19: s oftware c hip -e rase c ommand c odes 1060 f19 .0 write data: aah address: 5555h s oftware chip-erase c ommand sequence write data: 55h address: 2aaah write data: aah address: 5555h write data: 55h address: 2aaah write data: 10h address: 5555h wait t sce chip-erase to ffh write data: 80h address: 5555h
22 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 product ordering information valid combinations for gls29ee512 gls29ee512-70-4c-nh gls29ee512-70-4c-eh gls29ee512-70-4c-ph gls29ee512-70-4c-nhe GLS29EE512-70-4C-EHE gls29ee512-70-4i-nh gls29ee512-70-4i-eh gls29ee512-70-4i-nhe gls29ee512-70-4i-ehe note: valid combinations are those products in mass production or will be in mass production. consult your greenliant sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. note: the software chip-erase function is not s upported by the industrial temperature part. please contact greenliant if this function is required in an industrial temperature part. environmental attribute e 1 = non-pb package modifier h = 32 leads or pins package type e = tsop (type 1, die up, 8mm x 20mm) n = plcc p = pdip temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns device density 512 = 512 kbit function e = page-write voltage e = 4.5-5.5v product series 29 = page-write flash 1. environmental suffix ?e? denotes non-pb solder. greenliant non-pb solder devices are ?rohs com- pliant?. gls 29 ee 512 - 70 - 4c - nh e xx x x xxxx -xxx -xx - xxx x
data sheet 512 kbit page-write eeprom gls29ee512 23 ?2010 greenliant systems, ltd. s71060-10-000 05/10 packaging diagrams 32- lead p lastic l ead c hip c arrier (plcc) g reenliant p ackage c ode : nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30?
24 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 32- lead t hin s mall o utline p ackage (tsop) 8 mm x 20 mm g reenliant p ackage c ode : eh 0.15 0.05 20.20 19.80 18.50 18.30 0.70 0.50 8.10 7.90 0.27 0.17 1.05 0.95 32-tsop-eh-7 note: 1.complies with jedec publication 95 mo-142 bd dimensions, although some dimensions may be more stringent. 2.all linear dimensions are in millimeters (max/min). 3.coplanarity: 0.1 mm 4.maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads. pin # 1 identifier 0. 50 bsc 1mm 1.20 max. detail 0.70 0.50 0?- 5?
data sheet 512 kbit page-write eeprom gls29ee512 25 ?2010 greenliant systems, ltd. s71060-10-000 05/10 32- pin p lastic d ual i n - line p ins (pdip) g reenliant p ackage c ode : ph 32-pdip-ph-3 pin #1 identifier c l 32 1 base plane seating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .200 .170 7? 4 plcs. .600 bsc .100 bsc .150 .120 .022 .016 .065 .045 .080 .070 .050 .015 .075 .065 1.655 1.645 .012 .008 0? 15? .625 .600 .550 .530
26 data sheet 512 kbit page-write eeprom gls29ee512 ?2010 greenliant systems, ltd. s71060-10-000 05/10 table 9: r evision h istory number description date 06 ? 2002 data book may 2002 07 ? wh package is no longer offered ? removed the sst29ee512 90 ns read access time ? removed the sst29le512 200 ns read access time ? removed the sst29ve512 250 ns read access time ? clarified i dd write to be program and erase in table 6 on page 11 mar 2003 08 ? 2004 data book ? added non-pb mpns and removed footnote (see page 22) nov 2003 09 ? removed 2.7v and 3v devices and associated mpns refer to eol product data sheet s71060(01). ? added rohs compliance information on page 1 and in the ?product ordering information? on page 22 ? clarified the solder temperature profile un der ?absolute maximum stress ratings? on page 9 sep 2005 10 ? transferred from sst to greenliant may 2010 ? 2010 greenliant systems, ltd. all rights reserved. greenliant, the greenliant logo and nandrive ar e trademarks of greenliant systems, ltd. all trademarks and registered trademarks are t he property of their respective owners. these specifications are s ubject to change without notice. ssf is a trademark and superflash is a regi stered trademark of silicon storage technology, inc., a wholly owned subsidiary of microchip technology inc.

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