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" for more information + ! " understanding page mode flash memory devices application note publication number 23711 revision a amendment 0 issue date may 25, 2000
publication# 23711 rev: a amendment/ 0 issue date: may 25, 2000 understanding page mode flash memory devices application note current amd flash memory products operate with ran- dom access times ranging anywhere from 45 ns to 150 ns. though most applications use an amd flash device with a random access time of about 70 ns to 90 ns. the faster access times of 45 ns to 55 ns are only available today in lower density devices from 1 to 4 mbits. how- ever, many new applications need high-speed access, high density, and are migrating to lower voltages to save power. but, higher density and lower voltage tend to reduce performance in a standard random access memory architecture. therefore, amd is using different architectural approaches to increasing performance in several new flash memories. one approach is called page mode . to help describe how a page mode device works, the am29pl160c will be used as an example. device migration just as the flash memory overall performance in- creases, the internal architecture also becomes more complex. by comparing the three current amd flash ar- chitectures, standard, page mode, and burst mode, you can see how the complexity increases in order to achieve faster access times. the following graph shows a relative performance vs. complexity relation- ship. a page mode device is pin compatible with a standard flash device. this ensures an easy migration for a bet- ter performance part, with little added complexity to the overall system. if more performance is still desired, burst mode devices can offer that performance. but, the system complexity becomes much greater. what is a ?page?? a page is a small group of memory words that are ac- cessed, internal to the memory, in parallel rather than one at a time. the time to reach the first word in the group is called the initial access time and is analogous to standard architecture flash memory access times. however, since all the words in the group are stored in an internal buffer following the initial access time, other words in the group can be delivered with a much re- duced access time. all pages in a memory device are the same size, but the size of the pages varies depending on the device. the page size of the am29pl160c device is 8 words, or 16 bytes, with the appropriate page being selected by the higher address bits a3?a19. the lsb bits a0? a2 (in word mode) and a?1 to a2 (in byte mode) select the specific word/byte within a page. the pages are therefore always aligned on an 8-word address bound- ary. table 1 shows the words for a given page, and table 2 shows the bytes for a given page. table 1. word mode complexity performance standard page mode burst mode word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1
understanding page mode flash memory devices 2 table 2. byte mode how does a page mode read work? the first read from the page mode device is identical to a read from a standard flash device: ce# and oe# must go to v il , and a valid address must be placed on a19:a0. this first read has an access time t ce or t acc which is typical of a standard flash device. however, a subsequent page read access to a location anywhere within the same page is much faster. this access time is denoted as t pacc . fast page mode accesses are ob- tained by keeping a3?a19 constant and changing a0? a2 to select the specific word, or changing a?1 to a2 to select the specific byte, within that page. what are the benefits of operating in page mode? the major benefit of operating in page mode is the speed. some other benefits are potential reductions in cost and power consumption. it would be possible to build a fast memory subsystem through the use of mul- tiple memory devices in a technique called bank inter- leaving. however, bank interleaving requires multiple memories and external logic, which significantly add to cost compared to a single page mode memory device. page mode devices can also reduce power in two ways. first, by reducing the time power must be at the higher active read consumption level. second, in some page mode devices, by reducing the active read cur- rent requirement following the initial access time, such that the average power for a series of page reads is lower. to demonstrate the speed advantage of a page mode device, we will compare the timing of the am29pl160c to a standard flash device. figure 1. timing diagram for am29pl160c page mode read (byte mode) the am29pl160c is available with t acc varying from 60 ns to 120 ns, but we will look at one in which t acc = 90 ns, and t pacc = 30 ns. figure 1 clearly depicts that the initial access time of 90 ns is required to do the first read from a given page, but each subsequent read from the page is only 30 ns. each read from within the page is triggered by changing a?1 to a2. byte a2 a1 a0 a-1 byte 0 0000 byte 1 0001 byte 2 0010 byte 3 0011 byte 4 0100 byte 5 0101 byte 6 0110 byte 7 0111 byte 8 1000 byte 9 1001 byte 101010 byte 111011 byte 121100 byte 131101 byte 141110 byte 151111 a3 - a19 ce# oe# a - 1 - a2 data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
3 understanding page mode flash memory devices example: comparing a page mode device to a standard device by comparing a page mode device and a standard de- vice, the true advantage in speed can clearly be seen. let?s say that system a uses a page mode flash mem- ory device, and system b uses a comparable standard flash memory device. both systems are using the same processor, and both flash devices have the same ran- dom access time. table 3 shows how much time is re- quired by both systems to read eight consecutive bytes from memory. table 3. chart comparing read times between page and standard devices both systems require a t acc of 90 ns to do the first ran- dom access read. however, system a can now do sub- sequent reads in 30 ns, whereas system b still requires 90 ns to complete each and every read com- mand. by adding all the access times together, you can see that system a, using a page mode memory de- vice, can read almost 2.5 times as fast as system b. is the speed improvement always constant? although the previous example shows that a page mode memory device can be dramatically faster than a standard flash, the improvement is not always con- stant. the more the system reads from the same page, the faster the average access time. the less the sys- tem reads from the same page, the slower the average access time. in order to obtain optimum performance from a page mode device, the system?s program should be structured such that as many consecutive reads as possible are from within the same page. this could involve aligning frequently accessed data struc- tures or loop and jump labels to start on page bound- aries. what about program and erase operations? program commands work on one word/byte, and erase commands work on one sector at a time, just as they do in standard flash memories. what are the requirements on a system using a page mode flash? the system must provide memory interface logic that is aware of the page address boundaries and the differ- ence in access time between an initial access and a subsequent access within the same page so that the access time (number of wait states) can be adjusted dynamically. fortunately, many microprocessors already have such interface logic already integrated into their memory in- terface. table 4 describes some of these processors. table 4. processor families and examples from each family software implications in order to take full advantage of the performance en- hancement of the page mode feature, initial accesses need to be minimized and page mode accesses need to be maximized, making the average access time as system a: am29pl160c system b: comparable standard device byte 0 90 ns (t acc ) 90 ns (t acc ) byte 1 30 ns (t pacc ) 90 ns byte 2 30 ns 90 ns byte 3 30 ns 90 ns byte 4 30 ns 90 ns byte 5 30 ns 90 ns byte 6 30 ns 90 ns byte 7 30 ns 90 ns total time 300 ns 720 ns processor family examples motorola powerpc mpc850 motorola coldfire mcf5307, mcf5206e, mcf5206 sharp arm lh77790 hitachi superh risc sh7709 (sh-3)
understanding page mode flash memory devices 4 low as possible. ideally, in code, all branch target loca- tions would be aligned at the beginning of pages, branch instructions would be located at the end of pages, with all the locations in between used by se- quentially executed instructions. ideally, all data struc- tures would be aligned on page boundaries. however, few if any code compilers have been opti- mized to the point to align all branch targets on pro- grammer defined boundaries. some optimizing compilers support specific techniques like instruction reordering and loop unrolling which will produce longer sequences of sequential instructions which in turn re- duce code branching, but at the cost of lower code den- sity. code linkers can also start code modules at specific addresses or boundaries to force alignment. extensive optimization of branch target locations would require either manual code optimization or some kind of code post-processor algorithm that would reorder in- structions or insert no-ops and recalculate the relative branch addresses in order to force branch target align- ment. data structure alignment is easier to control since sev- eral compilers do support that function. one example is the microsoft compiler that comes with visual studio 6.0. one of the compile options is /zp[n], or ?struct member alignment,? where n is in bytes and can be 1, 2, 4, 8, or 16. depending on what n is set to, the com- piler will align data structures to the given page bound- ary. for example, /zp16 would put structures on 16- byte, or 8-word boundaries. however, this may lead to an increase in the memory space required as unused space may have to be inserted between each data record in order to align the start of each record. summary page mode memory devices have been developed to increase system performance in spite of the market de- mands for higher density and lower voltage, that would otherwise tend to reduce memory performance. by changing the internal architecture, the page mode memory allows for faster read access times within each page. using a page mode memory device can improve performance while holding or reducing cost and power consumption. but, the system must use the page mode feature properly in order to fully take advantage of the available performance advantage. trademarks copyright ? 2000 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc.

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