mosel vitelic 1 V43648S04VTG-10PC 3.3 volt 8m x 64 high performance pc100 unbuffered sdram module preliminary V43648S04VTG-10PC rev. 1.0 february 1999 features n 168 pin unbuffered 8,388,608 x 64 bit oganization sdram modules n utilizes high performance 8m x 8 sdram in tsopii-54 packages n fully pc board layout compatible to intels rev 1.0 module specification n single +3.3v ( 0.3v) power supply n programmable cas latency, burst length, and wrap sequence (sequential & interleave) n auto refresh (cbr) and self refresh n all inputs, outputs are lvttl compatible n 4096 refresh cycles every 64 ms n serial present detect (spd) n sdram performance n supported latencies at 100 mhz operation description the V43648S04VTG-10PC memory module is organized 8,388,608 x 64 bits in a 168 pin memory module. the 8m x 64 memory module uses 8 mosel-vitelic 8m x 8 sdram. the x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. component used -8pc units t ck clock frequency (max.) 125 mhz t ac clock access time cas latency = 2 & 3 6ns cl t rcd t rp t rc 3228clk 2227clk V43648S04VTG-10PC-01
2 V43648S04VTG-10PC rev. 1.0 february 1999 mosel vitelic V43648S04VTG-10PC pin configurations (front side/back side) notes: * these pins are not used in this module. pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vss i/o1 i/o2 i/o3 i/o4 vcc i/o5 i/o6 i/o7 i/o8 i/o9 vss i/o10 i/o11 i/o12 i/o13 i/o14 vcc i/o15 i/o16 cbo* cb1* vss nc nc vcc we dqm0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 dqm1 cs0 du vss a0 a2 a4 a6 a8 a10(ap) ba1 vcc vcc clk0 vss du cs2 dqm2 dqm3 du vcc nc nc cb2* cb3* vss i/o17 i/o18 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 i/o19 i/o20 vcc i/o21 nc du cke1 vss i/o22 i/o23 i/o24 vss i/o25 i/o26 i/o27 i/o28 vcc i/o29 i/o30 i/o31 i/o32 vss clk2 nc wp sda scl vcc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 vss i/o33 i/o34 i/o35 i/o36 vcc i/o37 i/o38 i/o39 i/o40 i/o41 vss i/o42 i/o43 i/o44 i/o45 i/o46 vcc i/o47 i/o48 cb4* cb5* vss nc nc vcc cas dqm4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 dqm5 cs1 ras vss a1 a3 a5 a7 a9 ba0 a11 vcc clk1 nc vss cke0 cs3 dqm6 dqm7 du vcc nc nc cb6* cb7* vss i/o49 i/o50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 i/o51 i/o52 vcc i/o53 nc du nc vss i/o54 i/o55 i/o56 vss i/o57 i/o58 i/o59 i/o60 vcc i/o61 i/o62 i/o63 i/o64 vss clk3 nc sa0 sa1 sa2 vcc pin names a0Ca11 address inputs i/o1Ci/o64 data inputs/outputs ras row address strobe cas column address strobe we read/write input ba0, ba1 bank selects cke0 , cke1 clock enable cs 0 Ccs 3 chip select clk0Cclk3 clock input dqm0Cdqm7 data mask vcc power (+3.3 volts) vss ground scl clock for presence detect sda serial data out for presence detect sa0Ca2 serial data in for presence detect cb0Ccb1 check bits (x72 organization) nc no connection du dont use
mosel vitelic V43648S04VTG-10PC 3 V43648S04VTG-10PC rev. 1.0 february part number information block diagram sdram 3.3v V43648S04VTG-10PC-02 4 mosel-vitelic manufactured v 168 pin unbuffered dimm x 8 component s refresh rate 4k 0 3 depth 8 4 banks 4 tsdp width 64 lvttl v gold g - 100 mhz pc compliant 10pc t dqm0 i/o1?/o8 cs0 10 10 10 10 we we dqm4 i/o40?/o33 dqm1 i/o9?/o16 dqm5 i/o48?/o41 dqm2 i/o17?/o24 cs2 10 10 10 10 dqm6 i/o49?/o56 dqm3 i/o25?/o32 dqm7 i/o57?/o64 V43648S04VTG-10PC-03 we: sdram d0-d7 cke: sdram d0-d7 ras: sdram d0-d7 a(11:0): sdram d0-d7 ba0, ba1: sdram d0-d7 cke0 ras cas we a(11:0) ba0, ba1 cas: sdram d0-d7 c0-c15 d0-d7 d0-d7 v cc v ss scl0 sa2 sa1 sa0 sda wp e 2 prom spd (256 word x 8 bits) 47k clock wiring clock input load clk0 4 sdrams +3.3pf cap clk1 termination clk2 4 sdrams +3.3pf cap clk3 termination d4 dqm i/o1?/o8 cs d5 dqm i/o1?/o8 cs d6 dqm i/o1?/o8 cs d7 dqm i/o1?/o8 cs dqm i/o1?/o8 cs d0 dqm i/o1?/o8 cs d1 dqm i/o1?/o8 cs d2 dqm i/o1?/o8 cs d3 we we we we we we we
4 V43648S04VTG-10PC rev. 1.0 february 1999 mosel vitelic V43648S04VTG-10PC serial presence detect information a serial presence detect storage device - e 2 prom - is assembled onto the module. informa- tion about the module configuration, speed, etc. is written into the e 2 prom device during module pro- duction using a serial presence detect protocol (i 2 c synchronous 2-wire bus) pd-table for -8 modules: byte number function described sdp entry value hex value 8mx64 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addresses (for x8 sdram) 9 09 5 number of dimm banks 1 01 6 module data width 64 40 7 module data width (continued) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 10.0 ns a0 10 sdram access time from clock at cl=3 6.0 ns 60 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 m s80 13 sdram width, primary x8 08 14 error checking sdram data width n/a / x8 00 15 minimum clock delay from back to back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4, 8 & full page 8f 17 number of sdram banks 4 04 18 supported cas latencies cl = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies wl = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes: general vcc tol 10% 06 23 minimum clock cycle time at cas latency = 2 10.0 ns a0 24 maximum data access time from clock for cl = 2 6.0 ns 60 25 minimum clock cycle time at cl = 1 not supported ff 26 maximum data access time from clock at cl = 1 not supported ff 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay t rrd 16 ns 10 29 minimum ras to cas delay t rcd 20 ns 14 30 minimum ras pulse width t ras 45 ns 2d
mosel vitelic V43648S04VTG-10PC 5 V43648S04VTG-10PC rev. 1.0 february dc characteristics t a = 0 c to 70 c; v ss = 0 v; v dd , v ddq = 3.3v 0.3v 31 module bank density (per bank) 64 mbyte 10 32 sdram input setup time 2 ns 20 33 sdram input hold time 1 ns 10 34 sdram data input setup time 2 ns 20 35 sdram data input hold time 1 ns 10 62-61 superset information (may be used in future) ff 62 spd revision revision 1 12 63 checksum for bytes 0 - 62 63 64-125 manufacturerss information (optional) (ffh if not used) xx 126 max. frequency specification 100 mhz 64 127 100 mhz support details af 128+ unused storage location ff symbol parameter limit values unit min. max. v ih input high voltage 2.0 v cc +0.3 v v il input low voltage C0.5 0.8 v v oh output high voltage (i out = C2.0 ma) 2.4 v v ol output low voltage (i out = 2.0 ma) 0.4 v i i(l) input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0v) C10 10 m a i o(l) output leakage current (dq is disabled, 0v < v out < v cc ) C10 10 m a pd-table for -8 modules: (continued) byte number function described sdp entry value hex value 8mx64
6 V43648S04VTG-10PC rev. 1.0 february 1999 mosel vitelic V43648S04VTG-10PC capacitance t a = 0 c to 70 c; v dd = 3.3v 0.3v, f = 1 mhz standby and refresh currents 1 t a = 0 c to 70 c, v cc = 3.3v 0.3v symbol parameter limit values unit max. 8m x 64 c i1 input capacitance (a0 to a11, ras , cas , we )45pf c i2 input capacitance (cs0 -cs3 )20pf c icl input capacitance (clk0-clk3) 22 pf c i3 input capacitance (cke0, cke1) 22 pf c i4 input capacitance (dqm0-dqm7) 13 pf c io input/output capacitance (i/o1-i/064) 13 pf c sc input capacitance (scl, sa0-2) 8 pf c sd input/output capacitance (sa0-sa2) 10 pf symbol parameter test conditions max. x64 unit note i cc 1 operating current burst length = 4, cl = 3 t rc > = t rc (min), t ck > = t ck (min), io = 0 ma 2 bank interleave operation 800 ma 1,2 i cc 2p precharged standby current in power down mode cke< = v il (max), t ck > = t ck (min) 24 ma i cc 2ps cke< = v il (max), t ck = infinite 16 ma i cc 2n precharged standby current in non-power down mode cke> = v ih (min), t ck > = t ck (min), input changed once in 3 cycles 160 ma cs = high i cc 2ns cke> = v ih (min), t ck = infinite, no input change 80 ma i cc 3p active standby current in power down mode cke< = v il (max), t ck > = t ck (min) 24 ma i cc 3ps cke< = v il (max), t ck = infinite 16 ma i cc 3n active standby current in non-power down mode cke> = v ih (min), t ck > = t ck (min), input changed one time 200 ma cs = high i cc 3ns cke> = v ih (min), t ck = infinite, no input change 120 ma i cc 4 burst operating current burst length = full page, t rc = infinite, cl = 3, t ck > = t ck (min), io = 0 ma 2 banks activated 760 ma 1, 2 i cc 5 auto refresh current t rc >= t rc (min) 720 ma 1,2 i cc 6 self refresh current cke = <0,2 v 8 ma 1,2
mosel vitelic V43648S04VTG-10PC 7 V43648S04VTG-10PC rev. 1.0 february ac characteristics 3,4 t a = 0 to 70 c; v ss = 0v; v cc = 3.3v 0.3v, t t = 1 ns # symbol parameter limit values unit note -10pc min. max. clock and clock enable 1t ck clock cycle time cas latency = 3 cas latency = 2 10 10 ns ns 2f ck system frequency cas latency = 3 cas latency = 2 C C 100 100 mhz mhz 3t ac clock access time cas latency = 3 cas latency = 2 C C 6 6 ns ns 4,5 4t ch clock high pulse width 3 C ns 6 5t cl clock low pulse width 3 C ns 6 6t cs input setup time 2 C ns 7 7t ch input hold time 1 C ns 7 8t cksp cke setup time (power down mode) 2.5 C ns 8 9t cksr cke setup time (self refresh exit) 8 C ns 9 10 t t transition time (rise and fall) 1 C ns common parameters 11 t rcd ras to cas delay 20 C ns 2 clk 12 t rc cycle time 70 120k ns 7 clk 13 t ras active command period 45 C ns 5 clk 14 t rp precharge time 20 C ns 2 clk 15 t rrd bank to bank delay time 16 C ns 2 clk 16 t ccd cas to cas delay time (same bank) 1 C clk refresh cycle 17 t srex self refresh exit time 10 Cns9 18 t ref refresh period (4096 cycles) 64 C ms 8 read cycle 19 t oh data out hold time 3 C ns 4 20 t lz data out to low impedance time 0 C ns 21 t hz data out to high impedance time 3 9 ns 10 22 t dqz dqm data out disable latency 2 C clk write cycle 23 t dpl data input to precharge (write recovery) 2 C clk 24 t dal data in to active/refresh 5 C clk 11 25 t dqw dqm write mask latency 0 C clk
8 V43648S04VTG-10PC rev. 1.0 february 1999 mosel vitelic V43648S04VTG-10PC notes: 1. the specified values are valid when addresses are changed no more than once during t ck (min.) and when no operation commands are registered on every rising clock edge during t rc (min). values are shown per module bank. 2. the specified values are valid when data inputs (dqs) are stable during t rc (min.). 3. all ac characteristics are shown for device level. an initial pause of 100 m s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 4. ac timing tests have v il = 0.4v and v ih = 2.4v with the timing referenced to the 1.4v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. specific tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0v. 5. if clock rising time is longer than 1 ns, a time (t t /2 -0.5) ns has to be added to this parameter. 6. rated at 1.5v 7. if t t is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 8. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake-up the device. 9. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied once the self refresh exit command is registered. 10. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. t dal is equivalent to t dpl + t rp . 1.4v 1.4v tsetup thold tac tac tlz toh thz clock input output 50 pf i/o z=50 ohm + 1.4 v 50 ohm 2.4v 0.4v t t tcl tch i/o measurement conditions for tac and toh 50 pf
mosel vitelic V43648S04VTG-10PC 9 V43648S04VTG-10PC rev. 1.0 february package diagram l-dim-168-30 sdram dimm module package V43648S04VTG-10PC-04 127.35 133.35 42.18 d 66.68 3.0 31.75 17.78 11011 4041 84 85 94 95 124 125 168 b a 6.35 2.26 radius 1.27 + 0.10 detail a 3.125 8.25 4.45 2.0 c 6.35 detail b 3.125 2.0 1.0 + 0.5 1.27 detail c 2.4 min. 0.2 0.15
mosel vitelic worldwide offices V43648S04VTG-10PC ? copyright 1997, mosel vitelic inc. 2/99 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2665-4883 fax: 852-2664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-578-3344 fax: 886-3-579-2838 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel ) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341
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