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peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 1 of 13 product description figure 1. block diagram product specification PE3239 2.2 ghz integer-n pll for low phase noise applications features ? 2.2 ghz operation ? 10/11 prescaler ? internal phase detector with charge pump ? serial programmable ? low power ? 20 ma at 3 v ? ultra-low phase noise ? available in 20-lead tssop peregrine?s PE3239 is a high performance integer-n pll capable of frequency synthesis up to 2.2 ghz. the superior phase noise performance of the PE3239 is ideal for applications such as wireless local loop basestations, lmds systems and other demanding terrestrial systems. the PE3239 features a 10/11 dual modulus prescaler, counters, phase detector and a charge pump as shown in figure 1. counter values are programmable through a three wire serial interface. fabricated in peregrine?s patented utsi? (ultra thin silicon) cmos technology, the PE3239 offers excellent rf performance with the economy and integration of conventional cmos. f in f in prescaler 10/11 20 main counter 20 secon- dary 20-bit latch 20 primary 20-bit latch r counter f r phase detector 6 6 pd_u pd_d 13 sdata charge pump cp
PE3239 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0047~01a | utsi ? cmos rfic solutions page 2 of 13 figure 2. pin configuration table 1. pin descriptions pin no. pin name type description 1 v dd (note 1) power supply input. input may range from 2.85 v to 3.15 v. bypassing required. 2 enh input enhancement mode. when asserted low (?0?), enhancement register bits are functional. internal 70 k ? pull-up resistor. 3 s_wr input serial load enable input. while s_wr is ?low?, sdata can be serially clocked. primary register data are transferred to the secondary register on s_wr rising edge. 4 sdata input binary serial data input. input data entered msb first. 5 sclk input serial clock input. sdata is clocked serially into the 20-bit primary register (e_wr ?low?) or the 8-bit enhancement register (e_wr ?high?) on the rising edge of sclk. 6 gnd ground. 7 fsels input selects contents of primary register (fsels=1) or se condary register (fsels=0) for programming of internal counters. internal 70 k ? pull-down resistor. 8 e_wr input enhancement register write enable. while e_wr is ?high?, sdata can be serially clocked into the enhancement register on the rising edge of sclk. internal 70 k ? pull-down resistor. 9 v dd (note 1) same as pin 1. 10 f in input prescaler input from the vco. max frequency input is 2.2 ghz. 11 f in input prescaler complementary input. a bypass capacitor shoul d be placed as close as possible to this pin and be connected in series with a 50 ? resistor to the ground plane. 12 gnd ground. 13 cext output logical ?nand? of pd_ u and pd_ d terminated through an on chip, 2 k ? series resistor. connecting cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving ld. 14 ld output lock detect is an open drain logical inversion of cext. when the loop is in lock, ld is high impedance, otherwise ld is a logic low (?0?). 15 dout output data out function, dout, enabled in enhancement mode. 16 v dd (note 1) same as pin 1. v dd 1 enh 2 s_wr 3 sdata 4 sclk 5 gnd 6 fsels 7 e_wr 8 v dd 9 f in 10 f in 11 gnd 12 cext 13 ld 14 dout 15 v dd 16 cp 17 n/c 18 gnd 19 f r 20
PE3239 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 3 of 13 pin no. pin name type description 17 cp output charge pump current is sourced when f c leads f p and sinked when f c lags f p . 18 nc output no connection. 19 gnd ground. 20 f r input reference frequency input. note 1: v dd pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level. table 2. absolute maximum ratings symbol parameter/conditions min max units v dd supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v i i dc into any input -10 +10 ma i o dc into any output -10 +10 ma t stg storage temperature range -65 150 c table 3. operating ratings symbol parameter/conditions min max units v dd supply voltage 2.85 3.15 v t a operating ambient temperature range -40 85 c table 4. esd ratings symbol parameter/conditions level units v esd esd voltage human body model (note 1) 1000 v note 1: periodically sampled, not 100% tested. tested per mil- std-883, m3015 c2 electrostatic discharge (esd) precautions when handling this utsi device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 4. latch-up avoidance unlike conventional cmos devices, utsi cmos devices are immune to latch-up.
PE3239 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0047~01a | utsi ? cmos rfic solutions page 4 of 13 table 5. dc characteristics v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified symbol parameter conditions min typ max units i dd operational supply current; prescaler enabled v dd = 2.85 to 3.15 v 20 26 ma digital inputs: s_wr, sdata, sclk v ih high level input voltage v dd = 2.85 to 3.15 v 0.7 x v dd v v il low level input voltage v dd = 2.85 to 3.15 v 0.3 x v dd v i ih high level input current v ih = v dd = 3.15 v +1 a i il low level input current v il = 0, v dd = 3.15 v -1 a digital inputs: enh (contains a 70 k ? pull-up resistor) v ih high level input voltage v dd = 2.85 to 3.15 v 0.7 x v dd v v il low level input voltage v dd = 2.85 to 3.15 v 0.3 x v dd v i ih high level input current v ih = v dd = 3.15 v +1 a i il low level input current v il = 0, v dd = 3.15 v -100 a digital inputs: fsels, e_wr (contains a 70 k ? pull-down resistor) v ih high level input voltage v dd = 2.85 to 3.15 v 0.7 x v dd v v il low level input voltage v dd = 2.85 to 3.15 v 0.3 x v dd v i ih high level input current v ih = v dd = 3.15 v +100 a i il low level input current v il = 0, v dd = 3.15 v -1 a reference divider input: f r i ihr high level input current v ih = v dd = 3.15 v +100 a i ilr low level input current v il = 0, v dd = 3.15 v -100 a counter output: dout v old output voltage low i out = 6 ma 0.4 v v ohd output voltage high i out = -3 ma v dd - 0.4 v lock detect outputs: (cext, ld) v olc output voltage low, cext i out = 0.1 ma 0.4 v v ohc output voltage high, cext i out = -0.1 ma v dd - 0.4 v v olld output voltage low, ld i out = 1 ma 0.4 v charge pump output: cp i cp ? source drive current v cp = v dd / 2 -2.6 -2 -1.4 ma i cp ? sink drive current v cp = v dd / 2 1.4 2 2.6 ma i cpl leakage current 1.0 v < v cp < v dd ? 1.0 v -1 1 a i cp ? source vs. 1 cp sink sink vs. source mismatch v cp = v dd / 2, t a = 25 c 15 % i cp vs. v cp output current magnitude variation vs. voltage 1.0 v < v cp < v dd ? 1.0 v t a = 25 c 15 %
PE3239 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 5 of 13 table 6. ac characteristics v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified symbol parameter conditions min max units control interface and latches (see figures 5, 6, 7) f clk serial data clock frequency (note 1) 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t dsu sdata set-up time to sclk rising edge 10 ns t dhld sdata hold time after sclk rising edge 10 ns t pw s_wr pulse width 30 ns t cwr sclk rising edge to s_wr rising edge 30 ns t ce sclk falling edge to e_wr transition 30 ns t wrc s_wr falling edge to sclk rising edge 30 ns t ec e_wr transition to sclk rising edge 30 ns main divider (including prescaler) f in operating frequency 200 2200 mhz p fin input level range external ac coupling -5 5 dbm main divider (prescaler bypassed) f in operating frequency 20 220 mhz p fin input level range external ac coupling -5 5 dbm reference divider f r operating frequency (note 3) 100 mhz p fr reference input power (note 2) single ended input -2 dbm phase detector f c comparison frequency (note 3) 20 mhz note 1: fclk is verified during the functional pattern test. serial progr amming sections of the functional pattern are clocked at 10 m hz to verify fclk specification. note 2: cmos logic levels can be used to drive reference input if dc coupled. voltage input needs to be a minimum of 0.5 vp-p. for optimum phase noise performance, the refer ence input falling edge rate s hould be faster than 80mv/ns. note 3: parameter is guaranteed through characterization only and is not tested.
PE3239 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0047~01a | utsi ? cmos rfic solutions page 6 of 13 -30 -25 -20 -15 -10 -5 0 0 500 1000 1500 2000 2500 3000 frequency (mhz) (dbm) -130 -120 -110 -100 -90 -80 -70 -60 100 1000 10000 100000 1000000 frequency offset (hz) (dbc/hz) typical performance data (v dd = 3.00v, t a = 25c) figure 3. typical rf input sensitivity figure 4. typical phase noise performance frequency = 1300 mhz reference = 10 mhz loop band width = 30 khz comparison frequency = 1.25mhz
PE3239 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 7 of 13 functional description the PE3239 consists of a prescaler, counters, a phase detector, charge pump and control logic. the dual modulus prescaler divides the vco frequency by either 10 or 11, depending on the value of the modulus select. counters ?r? and ?m? divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. an additional counter (?a?) is used in the modulus select logic. the phase-frequency detector generates up and down frequency control signals which direct the charge pump operation. the control logic includes a selectable chip interface. data is written into the internal registers via the three wire serial bus. there are also various operational and test modes and a lock detect output. figure 5. functional block diagram control logic modulus select 10/11 prescaler m counter (9-bit) r counter (6-bit) phase detector pd_u pd_d ld cext r(5:0) m(8:0) a(3:0) sdata control pins f r f in charge pump cp f in f c f p
PE3239 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0047~01a | utsi ? cmos rfic solutions page 8 of 13 main counter chain the main counter chain divides the rf input frequency, f in , by an integer derived from the user defined values in the ?m? and ?a? counters. it is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9 bit m counter. setting pre_en ?low? enables the 10/11 prescaler. setting pre_en ?high? allows f in to bypass the prescaler and powers down the prescaler. the output from the main counter chain, f p , is related to the vco frequency, f in , by the following equation: f p = f in / [10 x (m + 1) + a] (1) where a m + 1, m 0 when the loop is locked, f in is related to the reference frequency, f r , by the following equation: f in = [10 x (m + 1) + a] x (f r / (r+1)) (2) where a m + 1, m 0 a consequence of the upper limit on a is that f in must be greater than or equal to 90 x (f r / (r+1)) to obtain contiguous channels. programming the m counter with the minimum value of ?1? will result in a minimum m counter divide ratio of ?2?. reference counter the reference counter chain divides the reference frequency, f r , down to the phase detector comparison frequency, f c . the output frequency of the 6 bit r counter is related to the reference frequency by the following equation: f c = f r / (r + 1) (3) where r > 0 note that programming r equal to ?0? will pass the reference frequency, f r , directly to the phase detector. register programming serial interface mode while the e_wr input is ?low? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 19 , are clocked serially into the primary register on the rising edge of sclk, msb (b 0 ) first. the contents from the primary register are transferred into the secondary register on the rising edge of either s_wr according to the timing diagrams shown in figure 6. data are transferred to the counters as shown in table 7 on page 9. the double buffering provided by the primary and secondary registers allows for ?ping-pong? counter control using the fsels input. when fsels is ?high?, the primary register contents set the counter inputs. when fsels is ?low?, the secondary register contents are utilized. while the e_wr input is ?high? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 7 , are clocked serially into the enhancement register on the rising edge of sclk, msb (b 0 ) first. the enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of e_wr according to the timing diagram shown in figure 6. after the falling edge of e_wr, the data provide control bits as shown in table 8 on page 9 will have their bit functionality enabled by asserting the enh input ?low?.
PE3239 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 9 of 13 table 7. primary register programming interface mode enh r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 serial* 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 *serial data clocked serially on sclk rising edge while e_wr ?low? and captured in secondary register on s_wr rising edge. msb (first in) (last in) lsb table 8. enhancement register programming interface mode enh reserved reserved f p output power down counter load msel output f c output reserved serial* 0 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 *serial data clocked serially on sclk rising edge while e_wr ?high? and captured in the double buffer on e_wr falling edge. msb (first in) (last in) lsb figure 6. serial interface mode timing diagram t dhld t dsu t clkh t clkl t cwr t pw t wrc t ec t ce e_wr sdata sclk s_wr
PE3239 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0047~01a | utsi ? cmos rfic solutions page 10 of 13 r c1 c2 charge pump to vco tune enhancement register the functions of the enhancement register bits ar e shown below with all bits active ?high?. table 9. enhancement register bit functionality bit function description bit 0 reserved** bit 1 reserved** bit 2 f p output drives the m counter output onto the dout output. bit 3 power down power down of all f unctions except programming interface. bit 4 counter load immediate and continuous load of counter programming. bit 5 msel output drives the internal dual modulus prescaler modulus select (msel) onto the dout output. bit 6 f c output drives the reference c ounter output onto the dout output bit 7 reserved** ** program to 0 phase detector the phase detector is triggered by rising edges from the main counter (f p ) and the reference counter (f c ). it has two outputs, namely pd_ u , and pd_ d . if the divided vco leads the divided reference in phase or frequency (f p leads f c ), pd_ d pulses ?low?. if the divided reference leads the divided vco in phase or frequency (f c leads f p ), pd_ u pulses ?low?. the width of either pulse is directly proportional to phase offset between the two input signals, f p and f c . the signals from the phase detector couple directly to a charge pump. pd_ u controls a current source at pin cp with constant amplitude and pulse duration approximately the same as pd_ u . pd_ d similarly drives a current sink at pin cp. the current pulses from pin cp are low pass filtered externally and then connected to the vco tune voltage. pd_ u pulses result in a current source, which increases the vco frequency and pd_ d results in a current sink, which decreases vco frequency when using a positive kv vco. a lock detect output, ld is also provided, via the pin cext. cext is the logical ?nand? of pd_ u and pd_ d waveforms, which is driven through a series 2 kohm resistor. connecting cext to an external shunt capacitor provides low pass filtering of this signal. cext also drives the input of an internal inverting comparator with an open drain output. thus ld is an ?and? function of pd_ u and pd_ d . figure 7. typical PE3239 loop filter application example
PE3239 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 11 of 13 1.10 max front view 0.30 max 0.10 c b a 0.10 c 0.100.0 5 - c - 0.65bsc 1 2 0 4.400.1 0 .20 c b a - a - 27 1 0 - b - 1 1 1 9 1 4 top view 6.4 0 1.0 0 1.0 0 0.32 5 3.2 0 0.900.0 5 side view 3 1 8 4 1 7 5 1 6 89 6 1 5 1 3 1 2 6.400.1 0 ?1.000.1 0 2 x figure 8. package drawing 20-lead tssop (jedec mo-153-ac)
PE3239 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0047~01a | utsi ? cmos rfic solutions page 12 of 13 table 10. ordering information order code part marking description package shipping method 3239-11 PE3239 PE3239-20tssop-74a 20-lead tssop 74 units / tube 3239-12 PE3239 PE3239-20tssop-2000c 20-lead tssop 2000 units / t&r 3239-00 PE3239ek PE3239-20tssop-eval kit evaluation board 1 / box
PE3239 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 13 of 13 sales offices united states peregrine semiconductor corp. 6175 nancy ridge drive san diego, ca 92121 tel 1-858-455-0660 fax 1-858-455-0770 japan peregrine semiconductor k.k. the imperial tower, 15th floor 1-1-1 uchisaiawaicho, chiyoda-ku tokyo 100-0011 japan tel: 03-3507-5755 fax: 03-3507-5601 europe peregrine semiconductor europe aix-en-provence office parc club du golf, bat 9 13856 aix-en-provence cedex 3 france tel 33-0-4-4239-3360 fax 33-0-4-4239-7227 australia peregrine semiconductor australia 8 herb elliot ave. homebush, nsw 2140 australia tel: 011-61-2-9763-4111 fax: 011-61-2-9746-1501 for a list of representatives in your area, please refer to our web site at: http://www.peregrine-semi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target s pecifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. pe regrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a pcn (product change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. peregrine products are protected under one or more of the following u.s. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. other patents may be pending or applied for. utsi, the peregrine logotype, sel safe, and peregrine se miconductor corp. are registered trademarks of peregrine semiconductor corp. all pe product names and prefixes are trademarks of peregrine semiconductor corp. copyright ? 2001 peregrine semic onductor corp. all rights reserved.

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