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cxk77920tm/ym- 11/12/15 262144-word x 9-bit high speed synchronous static ram description the cxk77920tm/ym is a high speed cmos synchronous static ram with common l/o pins, orga- nized as 262144-word-by-9-bit. this synchronous sram integrates input registers, high speed sram and output registers onto a single monolithic ic. all input signals are latched at the positive edge of an external clock (clk). the ram data from the previous cycle is presented at the positive edge of the subsequent clock cycle. write operation is initiated by the positive edge of clk and is internally self-timed. this feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. 90mhz operation is obtained from a single 5v power supply. function there are three possible user transactions with the stram: read operation, write operation and deselect operation. the read operation requires we = ?igh?and oe = ce = ?ow?on the positive edge of clk. the memory location pointed to by the contents of the address registers is read internally and the contents of the location are captured in the data-out registers on the next positive edge of clk. the state of data-out will re?ct the contents of the data-out regis- ters. the write operation requires ce = we = ?ow?on the positive edge of clk. the memory location pointed to by the contents of the address registers is written with the contents of the data-in registers. the write opera- tion is entirely self-timed, eliminating critical timing edges. the deselect cycle requires ce = ?igh?or oe = we = ?igh?on the positive edge of clk. write operation and internal read operation are disabled during the clock cycle. the data outputs are forced to a high impedance state during the next clock cycle. during the deselect cycle by ce = ?igh? stram turns to power down mode. ? e93z08-st sony reserves the right to change products and speci?ations without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. structure silicon gate cmos ic features fast cycle time: (cycle) (frequency) cxk77920tm/ym-11 11.0ns 90mhz cxk77920tm/ym-12 12.5ns 80mhz cxk77920tm/ym-15 15.0ns 66.7mhz fast clock to data valid cxk77920tm/ym-11 6.0ns cxk77920tm/ym-12 6.5ns cxk77920tm/ym-15 7.0ns high speed, low power consumption single +5v power supply: 5v?% separate output power supply: 3.15 to 5.25v inputs and outputs are ttl compatible (3.3v l/o compatible) common data input and output all inputs and outputs are registered on a single clock edge self-timed write cycle package line-up: 400mil, 44 pin tsop ii with 0.8mm pitch cxk77920tm 44pin tsop (ii) (plastic) cxk77920ym 44pin tsop (ii) (plastic)
cxk77920tm/ym ? a17 a16 a15 a14 a13 ce v ssq i/o8 i/o7 v ccq v cc v ss v ssq i/o6 i/o5 v ccq we a12 a11 a10 a9 nc cxk77920tm a0 a1 a2 a3 oe v ccq i/o0 i/o1 i/o2 v ssq v ss v cc v ccq i/o3 i/o4 v ssq clk a4 a5 a6 a7 a8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a17 a16 a15 a14 a13 ce v ssq i/o8 i/o7 v ccq v cc v ss v ssq i/o6 i/o5 v ccq we a12 a11 a10 a9 nc cxk77920ym a0 a1 a2 a3 oe v ccq i/o0 i/o1 i/o2 v ssq v ss v cc v ccq i/o3 i/o4 v ssq clk a4 a5 a6 a7 a8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 pin con?uration (top view) pin description (1) block diagram symbol description a0 to a17 address input i/o0 to l/o8 data input/output clk clock ce chip enable input we write enable input oe output enable input v ccq output power supply v cc +5v power supply v ss /v ssq ground a0 clk clk clk clk ce we oe clk register register register register decoder self-timed write logic sense amp register 256kx9 ram a17 i/o0 i/o8
cxk77920tm/ym ? pin description (2) clk (clock, positive edge triggered) all timing is controlled by the rising or positive edge of clk. all synchronous input and output signals are regis- tered on the positive edge of clk with set-up and hold times referenced to that edge. since only one edge of clk is referenced, the duty cycle of clk is not critical. a0 to a17 (address) the address inputs are decoded on-chip to select one of 262,144 words. the state of the address inputs is reg- istered into the address register on the positive edge of clk. the address inputs must be valid during every pos- itive edge with all set-up and hold times referenced to that edge. i/o0 to l/o8 (data input/output) i/o terminals are three-state and data input/output common. the state is de?ed by the control block (refer to the truth table on page 4). the data inputs for write operation must be valid during every positive edge of clk with all set-up and hold times referenced to that edge. the data outputs are triggered by the positive edge of clk and the contents of the output-registers are presented. we (synchronous write enable, active low) we is used to indicate whether a read or write opera- tion is to be performed. we is ?ow?to perform a write operation. we is registered on every positive edge of clk with set-up and hold times referenced to that edge. the internal timing required to store data into the memory array is self-timed. ce (synchronous chip enable, active low) ce is used to select the synchronous sram when low (or deselect when high). when selected, the synchronous sram will perform a read or write operation (refer to the truth table on page 4). the state of ce is reg- istered on every positive edge of clk with set-up and hold times referenced to that edge. oe (synchronous output enable, active low) oe is used to indicate that a read operation is to be performed. if the synchronous sram is selected, the oe is low to perform a read operation (refer to the truth table on page 4). the state of oe is registered on every posi- tive edge of clk with set-up and hold times referenced to that edge.
cxk77920tm/ym ? item symbol rating unit supply voltage v cc ?.5 to +7.0 v input voltage v in ?.5 to v cc +0.5 v output voltage v o ?.5 to v cc +0.5 v allowable power dissipaiton p d 1.0 w operating temperature t opr 0 to +70 ? storage temperature t stg ?5 to +150 ? soldering temperature ?time t solder 235 ?10 ? l sec absolute maximum ratings (ta = +25?, gnd = 0v) truth table clk ce (tn) we (tn) oe (tn) mode i/o0 to l/o8 v cc current h x x deselect hi-z i sb l h h read hi-z i cc l h l read data out (1) i cc l l x write data in i cc notes: 1. data comes out on the next positive edge of clk. x: ??or ? dc recommended operating conditions (ta = +25?, gnd = 0v) item symbol min. typ. max. unit supply voltage v cc 4.75 5.0 5.25 v output supply voltage v ccq 3.15 5.25 v input high voltage v ih 2.2 v cc +0.3 v input low voltage v il ?.3 (1) 0.8 v note: 1. v il = ?.5v min. for pulse width less than 1ns.
dc characteristics (v cc = 5v ?%, gnd = 0v, ta = 0 to = +70?) item symbol test conditions min. max. unit input leakage current i li v in = gnd to v cc ? 1 a output leakage current i lo v o = gnd to v cc ? 1 a oe = v ih average operating i cc duty = 100% cycle = 90mhz 180 current i out = 0ma cycle = 80mhz 170 ma cycle = 66.7mhz 160 standby current i sb ce 3 v ih 130 ma cycle min, duty = 100% output high voltage v oh i oh = ?.0ma 2.4 v output low voltage v ol i ol = 4.0ma 0.4 v cxk77920tm/ym ? item symbol test conditions min. max. unit input capacitance c in v in = 0v 5 pf i/o capacitance c i/o v l/o = 0v 7 pf item conditions input pulse high level v ih = 3.0v input pulse low level v il = 0v input rise time tr = 3ns input fall time tf = 3ns input reference level 1.5v output reference level 1.5v output load conditions figure 1 i/o capacitance (ta = +25?, f = 1mhz) note: this parameter is sampled and is not 100% tested. ac characteristics ac test conditions (v cc = 5v?%, ta = 0 to +70?) *1. including scope and jig capacitance. *2. t ckhqz , t ckhqx output load (1) output load (2) *2 5pf *1 i/o 5v 480 255 50pf *1 i/o figure 1 electrical characteristics w w
cxk77920tm/ym ? -11 -12 -15 item symbol min. max. min. max. min. max. unit read cycle time t ckhckh 11 12.5 15 ns clock high pulse width t ckhckl 3.5 4.0 5.0 ns clock low pulse width t cklckh 3.5 4.0 5.0 ns clock to data valid t ckhqv 6.0 6.5 7.0 ns address setup to clock high t avckh 2.5 2.5 3.0 ns address hold from clock high t ckhax 0.5 0.5 0.5 ns chip enable setup to clock high t cevckh 2.5 2.5 3.0 ns chip enable hold from clock high t ckhcex 0.5 0.5 0.5 ns output enable setup to clock high t oevckh 2.5 2.5 3.0 ns output enable hold from clock high t ckhoex 0.5 0.5 0.5 ns clock high to output low-z t ckhqx (1) 1.5 1.5 1.5 ns clock high to output high-z t ckhqz (1) 4.5 5.0 6.0 ns read cycle note: 1. transition is measured +200mv from steady voltage with speci?d loading in figure 1-(2). this parameter is sampled and is not 100% tested. -11 -12 -15 item symbol min. max. min. max. min. max. unit read cycle time t ckhckh 11 12.5 15 ns clock high pulse width t ckhckl 3.5 4.0 5.0 ns clock low pulse width t cklckh 3.5 4.0 5.0 ns address setup to clock high t avckh 2.5 2.5 3.0 ns address hold from clock high t ckhax 0.5 0.5 0.5 ns chip enable setup to clock high t cevckh 2.5 2.5 3.0 ns chip enable hold from clock high t ckhcex 0.5 0.5 0.5 ns write enable setup to clock high t wevckh 2.5 2.5 3.0 ns write enable hold from clock high t ckhwex 0.5 0.5 0.5 ns input data setup to clock high t dvckh 2.5 2.5 3.0 ns input data hold from clock high t ckhdx 0.5 0.5 0.5 ns write cycle
cxk77920tm/ym ? timing waveform read cycle t ckhckh t avckh t ckhax t wevckh t ckhwex t cevckh t ckhcex t oevckh note: 1. valid data from clk high is the data from the previous cycle. t ckhoex t ckhqv t ckhckl clk n qn? qn? qn n+1 n+2 address we ce oe data out t cklckh (1) (1) (1)
cxk77920tm/ym ? write cycle: oe = v ih or v il t ckhckh t avckh t ckhax t dvckh t ckhdx t oeckh t ckhoex t wevckh t ckhwex t cevckh t ckhcex t ckhckl clk n dn dn+1 dn+2 n+1 n+2 address ce we oe data in t cklckh
cxk77920tm/ym ? read/write cycle t avckh t ckhax t wevckh t ckhwex t dvckh t ckhqz t ckhdx t ckhqx t ckhqv t oevckh t ckhoex t ceckh t ckhcex n+1 qn-2 dn qn+1 n n+2 clk address ce we oe i/o t ckhckh t ckhckl t cklckh
cxk77920tm/ym ?0 1.4 1.2 1.0 0.8 0.6 1.4 1.2 1.0 0.8 0.6 4.5 4.75 5.0 supply current vs. supply voltage supply current vs. ambient temperature v cc ?upply voltage (v) v cc ?upply voltage (v) i cc ?upply current (normalized) i cc ?upply current (normalized) 5.25 5.5 1.2 0.8 1.0 0.6 0.4 20 40 supply current vs. frequency frequency (1/t ckhckh ) (mhz) i cc ?upply current (normalized) 60 80 100 1.4 1.0 1.2 0.8 0.6 1.4 1.0 1.2 0.8 0.6 4.5 4.75 5.0 5.25 5.5 0 20 40 60 80 1.2 1.4 1.0 0.8 0.6 02550 access time vs. load capacitance cycle time (minimum) / access time vs. supply voltage cycle time (minimum) / access time vs. ambient temperature c l ?oad capacitance (pf) t ckhqv ?access time (normalized) t ckhckh ?cycle time, t ckhqv ?access time (normalized) t ckhckh ?cycle time, t ckhqv ?access time (normalized) 75 100 02040 ta?mbient temperature ( c) ta?mbient temperature ( c) 60 80 i cc i cc t ckhqv t ckhckh t ckhckh t ckhckh t ckhqv t ckhqv ta = +25 c ta = +25 c read, write v cc = 5.0v v cc = 5.0v v cc = 5.0v ta = +25 c v cc = 5.0v ta = +25 c example of representative characteristics
cxk77920tm/ym ?1 1.4 1.2 1.0 0.8 0.6 4.5 4.75 5.0 standby current vs. supply voltage v cc ?upply voltage (v) i sb ?tandby current (normalized) 5.25 5.5 i sb ta = +25 c 1.8 1.4 1.0 0.2 0.6 02040 standby current vs. ambient temperature ta?mbient temperature ( c) i sb ?tandby current (normalized) 60 80 v cc = 5.0v 1.4 1.2 1.0 0.8 0.6 4.5 4.75 5.0 input voltage level vs. supply voltage v cc ?upply voltage (v) v il , v ih ?nput voltage (normalized) 5.25 5.5 v ih , v il v ih ta = +25 c 1.4 1.2 0.8 1.0 0.6 02040 input voltage level vs. ambient temperature ta?mbient temperature ( c) v il , v ih ?nput voltage (normalized) 60 80 v cc = 5.0v 1.8 1.4 1.0 0.6 0.2 0 0.2 0.4 output low current vs. output low voltage v ol ?utput low voltage (v) i ol , output low current (normalized) 0.6 0.8 4 3 1 0 2 01 2 output high current vs. output high voltage v oh ?utput high voltage (v) i oh , output high current (normalized) 34 v il v cc = 5.0v ta = +25 c v cc = 5.0v ta = +25 c
cxk77920tm/ym ?2 0 -10 detail a detail b 11.76 0.2 *10.16 0.1 0.5 0.1 (0.125) 0.145 0.55 0.8 23 44 22 1 package structure sony code note>dimension ??does not include mold protrusion. eiaj code tsop(ii)-44p-l01 tsop(ii)044-p-0400-a package material lead treatment lead material package weight epoxy resin solder plating 42 alloy 0.5g jedec code 0.3 0.1 0.32 0.08 (0.3) 0.125 a b +0.05 -0.02 0.1 +0.1 -0.05 1.2max *18.41 0.1 0.1 44 pin tsop (ii) (plastic) 400mil 0.13 m 0 -10 detail a detail b 11.76 0.2 *10.16 0.1 0.5 0.1 (0.125) 0.145 0.55 0.8 23 44 22 1 package structure sony code note>dimension ??does not include mold protrusion. eiaj code tsop(ii)-44p-l01r tsop(ii)044-p-0400-b package material lead treatment lead material package weight epoxy resin solder plating 42 alloy 0.5g jedec code 0.3 0.1 0.32 0.08 (0.3) 0.125 a b +0.05 -0.02 0.1 +0.1 -0.05 1.2max *18.41 0.1 0.1 44 pin tsop (ii) (plastic) 400mil 0.13 m package dimensions unit: mm cxk77920tm cxk77920ym

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