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? amd-k6 processor bios design publication # 21329 rev: l amendment/ 0 issue date: december 1999 application note ?
trademarks amd, the amd logo, k6, 3dnow!, and combinations thereof, k86, and amd-k5 are trademarks, and amd-k6 is a registered trademark of advanced micro devices, inc. mmx is a trademark and pentium is a registered trademark of intel corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 1999 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
contents iii 21329l/0 december 1999 amd-k6 ? processor bios design contents contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 processor models and steppings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 bios consideration checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 amd-k6 ? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpuid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . 3 cache testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 smm issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 amd-k6 ? -2 processor model 8/[f:8] . . . . . . . . . . . . . . . . . . . . . 4 cpuid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 cpu speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . 4 cache testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 smm issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 amd-k6 ? -iii processor model 9. . . . . . . . . . . . . . . . . . . . . . . . . 5 cpuid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 cpu speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . 6 cache testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 smm issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 register states after reset and init . . . . . . . . . . . . . . . . . . . . . . . . 7 state of the processor after init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 cpuid identification algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
iv contents amd-k6 ? processor bios design 21329l/0december 1999 system management mode (smm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 state-save map differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i/o trap dword differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 standard msrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 machine-check address register (mcar) and machine-check type register (mctr). . . . . . . . . . . . . . . . . . 15 test register 12 (tr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 amd-k6 ? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 extended feature enable register (efer) . . . . . . . . . . . . . . 16 write handling control register (whcr). . . . . . . . . . . . . . . 17 syscall/sysret target address register (star) . . . . . . 19 amd-k6 ? -2 processor model 8/[f:8] . . . . . . . . . . . . . . . . . . . . 20 extended feature enable register (efer) . . . . . . . . . . . . . . 20 write handling control register (whcr). . . . . . . . . . . . . . . 23 syscall/sysret target address register (star) . . . . . . 26 uc/wc cacheability control register (uwccr) . . . . . . . . . 26 processor state observability register (psor). . . . . . . . . . . 30 page flush/invalidate register (pfir) . . . . . . . . . . . . . . . . . . 31 amd-k6 ? -iii processor model 9. . . . . . . . . . . . . . . . . . . . . . . . 33 extended feature enable register (efer) . . . . . . . . . . . . . . 33 write handling control register (whcr). . . . . . . . . . . . . . . 34 syscall/sysret target address register (star) . . . . . . 35 uc/wc cacheability control register (uwccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 processor state observability register (psor). . . . . . . . . . . 35 page flush/invalidate register (pfir) . . . . . . . . . . . . . . . . . . 36 level-2 cache array access register (l2aar) . . . . . . . . . . . 36 new amd-k6 ? processor instructions . . . . . . . . . . . . . . . . . . . . . . . . 41 additional considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 software timing dependencies relative to memory controller setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 pipelining support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 read-only memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
list of figures v 21329l/0 december 1999 amd-k6 ? processor bios design list of figures figure 1. cpuid instruction flow chart . . . . . . . . . . . . . . . . . . . . . 12 figure 2. extended feature enable register (efer) msr c000_0080h (models 6, 7, and 8/[7:0]) . . . . . . . . 16 figure 3. write handling control register (whcr) msr c000_0082h (models 6, 7, and 8/[7:0]) . . . . . . . . 18 figure 4. syscall/sysret target address register (star) msr c000_0081h (models 8 and 9) . . . . . . . . . . . . . . . 19 figure 5. extended feature enable register (efer) msr c000_0080h (model 8/[f:8]) . . . . . . . . . . . . . . . . . 21 figure 6. write handling control register (whcr) msr c000_0082h (model 8/[f:8]). . . . . . . . . . . . . . . . . 24 figure 7. uc/wc cacheability control register (uwccr )msr c000_0085h (model 8/[f:8]) . . . . . . . . . . . . . . . . 27 figure 8. processor state observability register (psor) msr c000_0087h (model 8/[f:8]) . . . . . . . . . . . . . . . . . 30 figure 9. page flush/invalidate register (pfir) msr c000_0088h (model 8/[f:8]) . . . . . . . . . . . . . . . . . 31 figure 10. extended feature enable register (efer) msr c000_0080h (model 9) . . . . . . . . . . . . . . . . . . . . . 34 figure 11. processor state observability register (psor) msr c000_0087h (model 9) . . . . . . . . . . . . . . . . . . . . . 35 figure 12. l2 cache organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. l2 cache sector and line organization . . . . . . . . . . . . . 37 figure 14. l2 tag or data location - edx . . . . . . . . . . . . . . . . . . . . . 38 figure 15. l2 data - eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. l2 tag information - eax . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. lru byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
vi list of figures amd-k6 ? processor bios design 21329l/0december 1999
list of tables vii 21329l/0 december 1999 amd-k6 ? processor bios design list of tables table 1. state of the amd-k6 ? processor models 6, 7, and 8/[7:0] after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. state of the amd-k6 ? -2 processor model 8/[f:8] after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. state of the amd-k6 ? -iii processor model 9 after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. summary of amd-k6 ? processor models and bios boot string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. amd-k6 ? processor i/o trap dword configuration at offset ffa4h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. summary of msr differences within the amd-k6 ? family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. extended feature enable register (efer) definition (models 6, 7, and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. syscall/sysret target address register (star) definition (models 8 and 9). . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. extended feature enable register (efer) definition (model 8/[f:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. ewbec settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. wc/uc memory type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. valid masks and range sizes . . . . . . . . . . . . . . . . . . . . . . 28 table 13. processor-to-bus clock ratios . . . . . . . . . . . . . . . . . . . . . . 31 table 14. extended feature enable register (efer) definition (model 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. tag versus data selector . . . . . . . . . . . . . . . . . . . . . . . . . . 38
viii list of tables amd-k6 ? processor bios design 21329l/0december 1999
revision history ix 21329l/0 december 1999 amd-k6 ? processor bios design revision history date rev description dec 1997 g added boot string information to the cpuid description on page 4. dec 1997 g added processor speeds, bus speeds, and boot string information to table 4 on page 10. dec 1997 g added 3dnow!? to new amd-k6? processor instructions on page 41. may 1998 h deleted amd-k5? processor information. added url to bios information for the amd-k5 processor on page 1. nov 1998 h1 added processor models and steppings on page 2. nov 1998 h1 added amd-k6?-2 processor model 8/[f:8] on page 4 to the bios consideration checklist. nov 1998 h1 added table 2, state of the amd-k6?-2 processor model 8/[f:8] after reset, on page 7. nov 1998 h1 added table 6, summary of msr differences within the amd-k6? family, on page 14. nov 1998 h1 moved paragraphs describing four msrs into standard msrs on page 15. nov 1998 h1 added amd-k6? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] on page 16 and amd-k6?-2 processor model 8/[f:8] on page 20 to the model-specific register (msrs) section. nov 1998 h1 added pipelining support and read-only memory on page 42. july 1998 i released under a nondisclosure agreement. feb 1999 j added amd-k6- iii processor information to processor models and steppings on page 2 and to bios consideration checklist on page 5. feb 1999 j added table 3, state of the amd-k6?-iii processor model 9 after reset, on page 8. feb 1999 j added to cpuid identification algorithms on page 9 a recommendation to change l2 to external within the summary/configuration screen. feb 1999 j added new boot strings to table 4, summary of amd-k6? processor models and bios boot string, on page 10. feb 1999 j added extended function 8000_0006h to figure 1, cpuid instruction flow chart, on page 12. feb 1999 j added l2 unified cache to built-in self-test (bist) on page 13. feb 1999 j added amd-k6- iii processor information to table 6, summary of msr differences within the amd-k6? family, on page 14. feb 1999 j added amd-k6?-iii processor model 9 on page 33. sept 1999 k added note 2 to table 1, state of the amd-k6? processor models 6, 7, and 8/[7:0] after reset, on page 7. sept 1999 k revised figure 1, cpuid instruction flow chart, on page 12. dec 1999 l added amd-k6-2/533 to table 4, summary of amd-k6? processor models and bios boot string, on page 10.
x revision history amd-k6 ? processor bios design 21329l/0december 1999
21329l/0 december 1999 amd-k6 ? processor bios design audience 1 application note amd-k6 processor bios design this document highlights the bios modifications required to fully support the amd-k6 ? processors. this document is a supplement to the amd k86? family bios and software tools developers guide , order# 21062. unless otherwise noted, the information in this application note pertains to all processors in the amd-k6 family, which includes the amd-k6 processor models 6 and 7, the amd-k6-2 processor model 8, and the amd-k6-iii processor model 9. there can be more than one way to implement the functionality detailed in this document, and the information provided is for demonstration purposes. all referenced amd-k6 processor documents can be found on the amd website at http://www.amd.com/k6/k6docs. for bios in formation on the amd-k5? processor, refer to the amd k86? family bios design application note that can be found at http://www.amd.com/products/cpg/techdocs/archive.html. audience it is assumed that the reader possesses the proper knowledge of the k86 processors, the x86 architecture, and programming requirements to understand the information presented in this document. ?
2 processor models and steppings amd-k6 ? processor bios design 21329l/0december 1999 processor models and steppings there are four models within the amd-k6 family of processorsmodels 6, 7, 8, and 9: n model 6 (amd-k6 processor model 6) this processor is manufactured in the 0.35-micron process. the model 6 supports six model-specific registers (msrs). n model 7 (amd-k6 processor model 7) this is the first processor manufactured in the 0.25-micron process. the model 7 implements the same six msrs as the model 6, and the bits and fields within these six msrs are defined identically. n model 8 (amd-k6-2 processor model 8) this processor is also manufactured in the 0.25-micron process. some important features supported by the model 8 include the 3dnow!? instruction set and support for a 100-mhz processor bus. this document covers the following two specific stepping ranges of the model 8: ? model 8/[7:0] is any of eight possible model/steppings models 8/0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, or 8/7. model 8/[7:0] implements the same six msrs as the models 6 and 7, and the bits and fields within these six msrs are defined identically. model 8/[7:0] also implements the syscall/sysret target address register (star) msr for a total of seven msrs. ? model 8/[f:8] is any of eight possible model/steppings models 8/8, 8/9, 8/a, 8/b, 8/c, 8/d, 8/e, or 8/f. model 8/[f:8] implements the same six msrs as the models 6, 7, and 8/[7:0], but the bits and fields within two of these msrs are not defined identically. also, model 8/[f:8] supports the star msr and three additional msrs, for a total of ten msrs. n model 9 ( amd-k6-iii processor model 9 )this processor is also manufactured in the 0.25-micron process. in addition to supporting the 3dnow! instruction set and a 100-mhz processor bus, the model 9 contains a 256-kbyte backside l2 cache. the model 9 implements the same six msrs as the models 6, 7, and 8/[7:0], but the bits and fields within two of these msrs are not defined identically. also, the model 9 supports the star msr and four additional msrs, for a total of eleven msrs. table 6 on page 14 summarizes the msr differences between the models and steppings of the amd-k6 family of processors.
bios consideration checklist 3 21329l/0 december 1999 amd-k6 ? processor bios design bios consideration checklist amd-k6 ? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] the term processor in this section is defined as the amd-k6 processor models 6 and 7, and the amd-k6-2 processor model 8/[7:0]. cpuid n use the cpuid instruction to properly identify the processor. for information on the cpuid instruction, refer to the amd processor recognition application note , order# 20734. n determine the processor model, stepping, and features using functions 0000_0001h and 8000_0001h of the cpuid instruction. n display bios boot strings: amd-k6(tm)/xxx for models 6 and 7, and amd-k6(tm)-2/xxx for all steppings of the model 8. for more information, see cpuid identification algorithms on page 9. cpu speed detection n use speed detection algorithms that do not rely on repetitive instruction sequences. n use the time stamp counter (tsc) to clock a timed operation and compare the result to the real time clock (rtc) to determine the operating frequency. see the cpu speed determination program available on the amd website at http://www.amd.com/k6/k6docs/. n display the recommended bios boot string as shown in table 4, summary of amd-k6 ? processor models and bios boot string , on page 10. model-specific registers (msrs) n only access msrs implemented in the processor. n enable write allocation by programming the write handling control register (whcr). see write handling control register (whcr) on page 17 and the implementation of write allocate in the k86? processors application note , order# 21326 for more information. cache testing n the processor does not contain msrs to allow for testing of the l1 cache.
4 bios consideration checklist amd-k6 ? processor bios design 21329l/0december 1999 smm issues n the system management mode (smm) functionality of the processor is the same as the pentium ? processor. n implement the processor smm state-save area in a similar manner as pentium processors except for the idt base and possibly pentium processor-reserved areas. see system management mode (smm) on page 13 for more information. amd-k6 ? -2 processor model 8/[f:8] the term processor in this section is defined as the amd-k6-2 processor model 8/[f:8]. cpuid n use the cpuid instruction to properly identify the processor. for information on the cpuid instruction, refer to the amd processor recognition application note , order# 20734. n determine the processor model, stepping and features using functions 0000_0001h and 8000_0001h of the cpuid instruction. n display bios boot string: amd-k6(tm)-2/xxx for all steppings of the model 8. for more information, see cpuid identification algorithms on page 9. cpu speed detection n use speed detection algorithms that do not rely on repetitive instruction sequences. n use the time stamp counter (tsc) to clock a timed operation and compare the result to the real time clock (rtc) to determine the operating frequency. see the cpu speed determination program available on the amd website at http://www.amd.com/k6/k6docs/. n display the recommended bios boot string as shown in table 4, summary of amd-k6 ? processor models and bios boot string , on page 10. model-specific registers (msrs) n only access msrs implemented in the processor. n enable write allocation by programming the write handling control register (whcr). see write handling control register (whcr) on page 23 and the implementation of write allocate in the k86? processors application note , order# 21326 for more information. note: the whcr register as defined in the model 6, model 7, and model 8/[7:0] has changed in the model 8/[f:8].
bios consideration checklist 5 21329l/0 december 1999 amd-k6 ? processor bios design n utilize the information provided in the processor state observability register (psor) to display the correct processor bus frequency. cache testing n the processor does not contain msrs to allow for testing of the l1 cache. smm issues n the system management mode (smm) functionality of the processor is the same as the pentium processor. n implement the processor smm state-save area in a similar manner as pentium processors except for the idt base and possibly pentium processor-reserved areas. see system management mode (smm) on page 13 for more information. amd-k6 ? -iii processor model 9 the term processor in this section is defined as the amd-k6-iii processor model 9. cpuid n use the cpuid instruction to properly identify the processor. for information on the cpuid instruction, refer to the amd processor recognition application note , order# 20734. n determine the processor model, stepping and features using functions 0000_0001h and 8000_0001h of the cpuid instruction. n display bios boot string: amd-k6(tm)-iii/xxx for all steppings of the model 9. for more information, see cpuid identification algorithms on page 9. cpu speed detection n use speed detection algorithms that do not rely on repetitive instruction sequences. n use the time stamp counter (tsc) to clock a timed operation and compare the result to the real time clock (rtc) to determine the operating frequency. see the cpu speed determination program available on the amd website at http://www.amd.com/k6/k6docs/. n display the recommended bios boot string as shown in table 4, summary of amd-k6 ? processor models and bios boot string , on page 10.
6 bios consideration checklist amd-k6 ? processor bios design 21329l/0december 1999 model-specific registers (msrs) n only access msrs implemented in the processor. n enable write allocation by programming the write handling control register (whcr). see write handling control register (whcr) on page 34 and the implementation of write allocate in the k86? processors application note , order# 21326 for more information. note: the whcr register as defined in the model 6, model 7, and model 8/[7:0] has changed in the model 9. n utilize the information provided in the processor state observability register (psor) to display the correct processor bus frequency. cache testing n the amd-k6-iii processor does not contain msrs to allow for testing of the l1 cache. however, the amd-k6-iii processor does contain a msr that allows for testing of its l2 cache. this msr is called l2aar and it is described in level-2 cache array access register (l2aar) on page 36. smm issues n the system management mode (smm) functionality of the processor is the same as the pentium processor. n implement the processor smm state-save area in a similar manner as pentium processors except for the idt base and possibly pentium processor-reserved areas. see system management mode (smm) on page 13 for more information.
register states after reset and init 7 21329l/0 december 1999 amd-k6 ? processor bios design register states after reset and init after the processor has completed its initialization following the recognition of an asserted reset or init signal, the states of all architecture registers and msrs are compatible with those of pentium processors. differences are listed in table 1 through table 3. table 1. state of the amd-k6 ? processor models 6, 7, and 8/[7:0] after reset register reset state notes edx 0000_05msh 1 efer 0000_0000_0000_0000h star 0000_0000_0000_0000h 2 whcr 0000_0000_0000_0000h notes: 1. m represents the model and s represents the stepping. 2. amd-k6 processor models 6 and 7 do not support star. table 2. state of the amd-k6 ? -2 processor model 8/[f:8] after reset register reset state notes edx 0000_058sh 1 efer 0000_0000_0000_0002h pfir 0000_0000_0000_0000h psor 0000_0000_0000_01sbh 1, 2 star 0000_0000_0000_0000h uwccr 0000_0000_0000_0000h whcr 0000_0000_0000_0000h notes: 1. s represents the stepping. 2. b represents psor[3:0], where psor[3] equals 0, and psor[2:0] is equal to the value of the bf[2:0] signals sampled during the falling transition of reset.
8 state of the processor after init amd-k6 ? processor bios design 21329l/0december 1999 state of the processor after init the assertion of init causes the processor to empty its pipelines, initialize most of its internal state, and branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the smm base, msrs, and the cd and nw bits of the cr0 register. the edge-sensitive interrupts flush# and smi# are sampled and preserved during the init process and are handled accordingly after the initialization is complete. however, the processor resets any pending nmi interrupt upon sampling init asserted. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. table 3. state of the amd-k6 ? -iii processor model 9 after reset register reset state notes edx 0000_059sh 1 efer 0000_0000_0000_0002h 2 l2aar 0000_0000_0000_0000h pfir 0000_0000_0000_0000h psor 0000_0000_0000_00sbh 1, 3 star 0000_0000_0000_0000h uwccr 0000_0000_0000_0000h whcr 0000_0000_0000_0000h notes: 1. s represents the stepping. 2. because efer[4] equals 0 after r eset, the l2 cache is enabled by default after reset. 3. b represents psor[3:0], where psor[3] equals 0, and psor[2:0] is equal to the value of the bf[2:0] signals sampled during the falling transition of reset.
cpuid identification algorithms 9 21329l/0 december 1999 amd-k6 ? processor bios design cpuid identification algorithms the cpuid instruction provides information about the processor (vendor, type, name, etc.) and its capabilities (features). after detecting the processor and its capabilities, software can be accurately tuned to the system for maximum performance and benefit to users. for example, game software can test the performance level available from a particular processor by detecting the type of processor. if the performance level is high enough, the software can enable additional capabilities or more advanced algorithms. another example involves testing if the processor supports 3dnow! instructions. if the software finds this functionality present when it checks the feature bits, it can utilize these more powerful extensions for better performance on new multimedia software. for more detailed information, refer to the amd processor recognition application note , order# 20734. table 4 on page 10 shows the recommended bios boot strings for the amd-k6 processor. the recommended boot strings are: n amd-k6(tm)/xxx for models 6 and 7 n amd-k6(tm)-2/xxx for model 8 (all steppings) n amd-k6(tm)-iii/xxx for model 9 the value for xxx is determined by calculating the core frequency of the processor. use the time stamp counter (tsc) to clock a timed operation and compare the result to the real time clock (rtc) to determine the operating frequency. in addition to displaying the recommended boot string, bios code that normally indicates the presence of a l2 cache within the summary/configuration screen should change all occurrences of l2 to external. note: table 4 contains information intended to prepare the infrastructure for potential future products. these products at these speed grades may or may not be announced, but bios software should be prepared to support these options.
10 cpuid identification algorithms amd-k6 ? processor bios design 21329l/0december 1999 table 4. summary of amd-k6 ? processor models and bios boot string instruction family model cpu speed (mhz) cpu bus speed (mhz) recommended bios boot-string display 5 (amd-k6 ? processor) 6 166 66 amd-k6(tm)/166 200 66 amd-k6(tm)/200 233 66 amd-k6(tm)/233 7 200 66 amd-k6(tm)/200 233 66 amd-k6(tm)/233 266 66 amd-k6(tm)/266 300 66 amd-k6(tm)/300 8 233 66 amd-k6(tm)-2/233 266 66 amd-k6(tm)-2/266 300 66 amd-k6(tm)-2/300 333 66 amd-k6(tm)-2/333 366 66 amd-k6(tm)-2/366 400 66 amd-k6(tm)-2/400 333 95 amd-k6(tm)-2/333 380 95 amd-k6(tm)-2/380 300 100 amd-k6(tm)-2/300 350 100 amd-k6(tm)-2/350 400 100 amd-k6(tm)-2/400 450 100 amd-k6(tm)-2/450 475 95 amd-k6(tm)-2/475 500 100 amd-k6(tm)-2/500 533 97 amd-k6(tm)-2/533 550 100 amd-k6(tm)-2/550 600 100 amd-k6(tm)-2/600 9 350 100 amd-k6(tm)- iii /350 400 100 amd-k6(tm)- iii /400 450 100 amd-k6(tm)- iii /450 475 95 amd-k6(tm)- iii/ 475 500 100 amd-k6(tm)- iii /500 550 100 amd-k6(tm)- iii /550 600 100 amd-k6(tm)- iii /600
cpuid identification algorithms 11 21329l/0 december 1999 amd-k6 ? processor bios design figure 1 shows a flow chart for the cpuid instruction. use this chart to implement a cpuid algorithm.
12 cpuid identification algorithms amd-k6 ? processor bios design 21329l/0december 1999 figure 1. cpuid instruction flow chart check for cpuid instruction support cpuid instruction supported no cpuid instruction use other means to detect cpu type no execute cpuid standard function eax=0 store vendor string eax > 1 ? execute cpuid standard function eax=1 store returned standard function feature bits and processor signature; determine mmx and, optionally, sse* support no amd processor not presentcheck for other cpu brands execute cpuid extended function eax=8000_0001h utilize vendor string and extended function feature bits to determine 3dnow!, 3dnow! extensions and mmx extensions support execute cpuid extended functions eax=8000_0002h, 8000_0003h, and 8000_0004h to display processor name string execute cpuid extended functions eax=8000_0005h and eax=8000_0006h (model 9) to gather processor cache and tlb information tune software to optimize for features present yes yes execute cpuid extended function eax=8000_0000h to determine number of extended functions supported eax > 8000_0001h ? no yes utilize processor signature to determine msr support done extended functions not supported * streaming simd extensions
built-in self-test (bist) 13 21329l/0 december 1999 amd-k6 ? processor bios design built-in self-test (bist) for all models of the amd-k6 processor, bist is run unconditionally following the falling transition of reset. the results of the test are contained in the general purpose register eax. if eax contains 0000_0000h, then bist was successful. if the contents of eax are non-zero, the bist failed. the internal resources tested during bist include the following: n l1 instruction and data caches n l2 unified cache (model 9 only) n instruction and data translation lookaside buffers (tlbs) system management mode (smm) this section documents the smm differences between specified models of the amd-k6 processor and the pentium processor. for more information on smm implementation in the k86 processors, see the amd k86? family bios and software tools developers guide , order# 21062. state-save map differences the smm implemented in the amd-k6 processor differs from the smm implemented in the pentium processor in one way. the idt base location in the amd-k6 processor is located at offset ff90h. pentium has the idt base located at offset ff94h. i/o trap dword differences the i/o trap dword is located at offset ffa4h. this state-save area, which is reserved in pentium, contains information regarding an i/o instruction that may have been trapped by an smi# assertion. table 5. amd-k6 ? processor i/o trap dword configuration at offset ffa4h bits 31C16 bits 15C4 bit 3 bit 2 bit 1 bit 0 i/o port address reserved rep string operation i/o string operation valid i/o instruction input or output
14 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 model-specific registers (msrs) all models and steppings of the amd-k6 processor family support the following four standard msrs, and the bits and fields within each of these msrs are defined identically: n machine-check address register (mcar)ecx = 00h n machine-check type register (mctr)ecx = 01h n test register 12 (tr12)ecx = 0eh n time stamp counter (tsc)ecx = 10h all models and steppings of the amd-k6 processor family also support the following two msrs, but the fields within each of these msrs are defined differently as shown in table 6 (an x indicates support for a register or field): n extended feature enable register (efer)ecx = c000_0080h n write handling control register (whcr)ecx = c000_0082h table 6. summary of msr differences within the amd-k6 ? family model stepping standard 1 msrs efer 2 whcr 3 uwccr psor pfir l2aar l2d ewbec dpe sce 508 mb 4092 mb 6all x xx 7all x xx 87:0 x xx 8f:8 x xxx x x xx 9 all x xxxx x x x x x notes: 1. there are four m srs that every model and stepping of the amd-k6 family of processors support identicallymcar, mctr, tr12, and tsc. 2. l2d, ewbec, and dpe are bits/fields supported in efer for the indicated models/steppings. all models/steppings support the system call extension (sce) bit in efer, even if the corresponding syscall and sysret instructions and the star register are not supported. 3. indicates whether the waelim field supports 508 mbytes or 4092 mbytes of memory. the location of the wae15m bit and the waelim field within the whcr register differs between the models/steppings that support 508 mbytes of memory and those that support 4092 mbytes of memory.
model-specific registers (msrs) 15 21329l/0 december 1999 amd-k6 ? processor bios design standard msrs this section describes the four standard msrs that every model and stepping of the amd-k6 family of processors support identically. machine-check address register (mcar) and machine-check type register (mctr) the processor does not support the generation of a machine check exception, but does provide a 64-bit machine check address register (mcar) and a 64-bit machine check type register (mctr) for software compatibility. because the processor does not support machine check exceptions, the contents of the mcar and mctr are only affected by the wrmsr instruction and by reset being sampled asserted (where all bits in each register are reset to 0). the processor also provides the machine check exception (mce) bit in control register 4 (cr4, bit 6) as a read-write bit. however, the state of this bit has no effect on the operation of the processor. test register 12 (tr12) the processor provides the 64-bit test register 12 (tr12), but only the cache inhibit (ci) bit (bit 3 of tr12) is supported. all other bits in tr12 have no effect on the processors operation. the i/o trap restart function (bit 9 of tr12) is always enabled on the amd-k6. time stamp counter (tsc) with each processor clock cycle, the processor increments a 64-bit time stamp counter (tsc) msr. the counter can be written or read using the wrmsr or rdmsr instructions when the ecx register contains the value 10h and cpl = 0. the counter can also be read using the rdtsc instruction, but the required privilege level for this instruction is determined by the time stamp disable (tsd) bit in cr4. with either of these instructions, the edx and eax registers hold the upper and lower dwords of the 64-bit value to be written to or read from the tsc, as follows: n edx upper 32 bits of tsc n eax lower 32 bits of tsc the tsc can be loaded with any arbitrary value. this feature is compatible with the pentium processor.
16 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 amd-k6 ? processor models 6, 7 and amd-k6-2 processor model 8/[7:0] the amd-k6 processor models 6 and 7 and the amd-k6-2 processor model 8/[7:0] provide the following msrs. the first four m srs are described in standard msrs on page 15. the contents of ecx selects the msr to be addressed by the rdmsr and wrmsr instruction. n machine-check address register (mcar)ecx = 00h n machine-check type register (mctr)ecx = 01h n test register 12 (tr12)ecx = 0eh n time stamp counter (tsc)ecx = 10h n extended feature enable register (efer)ecx = c000_0080h n write handling control register (whcr)ecx = c000_0082h all steppings (f:0) of the amd-k6-2 processor model 8 support the following msr, and the bits and fields within this msr are defined identically: n syscall/sysret target address register (star)ecx = c000_0081h extended feature enable register (efer) the extended feature enable register (efer) contains the control bits that enable the extended features of the amd-k6 processor. figure 2 shows the format of the efer register, and table 7 defines the function of each bit of the efer register. the efer register is msr c000_0080h. figure 2. extended feature enable register (efer)msr c000_0080h (models 6, 7, and 8/[7:0]) 10 63 s c e reserved symbol description bit sce system call extension 0
model-specific registers (msrs) 17 21329l/0 december 1999 amd-k6 ? processor bios design note: the amd-k6 processor models 6 and 7 provide the sce bit in the efer register, but this bit does not affect processor operation because the syscall and sysret instructions and the star register are not supported in these models. write handling control register (whcr) the processor contains a split level-1 (l1) 64-kbyte writeback cache organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes and lines are read from memory using an efficient pipelined burst read cycle. further performance gains are achieved by the implementation of a write allocation scheme. a write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the l1 cache. for more information on write allocate, see the implementation of write allocate in the k86? processors application note , order# 21326, and the cache organization section of the amd-k6 ? processor data sheet , order# 20695 or the amd-k6 ? -2 processor data sheet , order# 21850. this section describes two programmable mechanisms used by the processor to determine when to perform write allocate. when either of these mechanisms indicates that a pending write is to a cacheable area of memory, a write allocate is performed. before enabling write allocate or changing memory cacheability/writeability, the bios must writeback and invalidate the internal cache by using the wbinvd instruction. in addition, write allocate should be enabled only after performing any memory sizing or typing algorithms. the write handling control register (whcr) is a msr that contains three fieldsthe wcde bit, the write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 3). table 7. extended feature enable register (efer) definition (models 6, 7, and 8/[7:0]) bit description r/w function 63C1 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 0 system call extension (sce) r/w sce must be set to 1 to enable the usage of the syscall and sysret instructions.
18 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 figure 3. write handling control register (whcr)msr c000_0082h (models 6, 7, and 8/[7:0]) wcde. for proper functionality, always program bit 8 of whcr to 0. see pipelining support on page 42 for more information on wcde. write allocate enable limit. the waelim field is 7 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that misses the l1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector (for more information, see the cache organization chapter in the amd-k6 ? processor data sheet , order# 20695 or the amd-k6 ? -2 processor data sheet , order# 21850). the maximum value of this limit is ((2 7 C1) 4 mbytes) = 508 mbytes. when all the bits in this field are set to 0, all memory is above this limit and the write allocate mechanism is disabled (even if all bits in the waelim field are set to 0, write allocates can still occur due to the write to a cacheable page and write to a sector mechanisms). once the bios determines the amount of ram installed in the system, this number should also be used to program the waelim field. for example, a system with 32 mbytes of ram would program the waelim field with the value 0001000b. this value (8), when multiplied by 4 mbytes, yields 32 mbytes as the write allocate limit. 710 63 reserved waelim 8 0 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits wcde always program to 0 8 waelim write allocate enable limit 7C1 wae15m write allocate enable 15-to-16-mbyte 0 9
model-specific registers (msrs) 19 21329l/0 december 1999 amd-k6 ? processor bios design write allocate enable 15-to-16-mbyte. the wae15m bit is used to enable write allocations for the memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocates in this memory area. this sub-mechanism of the waelim provides a memory hole to prevent write allocates. this memory hole is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0 (even if the wae15m bit is set to 0, write allocates can still occur between 15 mbytes and 16 mbytes due to the write to a cacheable page and write to a sector mechanisms). the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition, write allocations are not performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by means of write to a cacheable page or write to a sector. it is not safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a noncacheable region of memory. syscall/sysret target address register (star) all steppings (f:0) of the amd-k6-2 processor model 8 and the amd-k6-iii processor model 9 implement the star register. this register contains the target eip address used by the syscall instruction and the 16-bit code and stack segment selector bases used by the syscall and sysret instructions. figure 4 shows the format of the star register, and table 8 defines the function of each field of the star register. the star register is msr c000_0081h. for more information about syscall/sysret, see the amd-k6 ? processor syscall and sysret instruction specification application note , order# 21086. figure 4. syscall/sysret target address register (star)msr c000_0081h (models 8 and 9) 31 0 63 target eip address 32 47 48 syscall cs selector and ss selector base sysret cs selector and ss selector base
20 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 amd-k6 ? -2 processor model 8/[f:8] the amd-k6-2 processor model 8/[f:8] provides the following ten msrs. the first four m srs are described in standard msrs on page 15. the contents of ecx selects the msr to be addressed by the rdmsr and wrmsr instruction. n machine-check address register (mcar)ecx = 00h n machine-check type register (mctr)ecx = 01h n test register 12 (tr12)ecx = 0eh n time stamp counter (tsc)ecx = 10h n extended feature enable register (efer)ecx = c000_0080h n write handling control register (whcr)ecx = c000_0082h n syscall/sysret target address register (star)ecx = c000_0081h n uc/wc cacheability control register (uwccr)ecx = c000_0085h n processor state observability register (psor)ecx = c000_0087h n page flush/invalidate register (pfir)ecx = c000_0088h extended feature enable register (efer) the extended feature enable register (efer) contains the control bits that enable the extended features of the processor. figure 5 shows the format of the efer register, and table 9 on page 21 defines the function of each bit of the efer register. the efer register is msr c000_0080h. table 8. syscall/sysret target address register (star) definition (models 8 and 9) bit description r/w function 63C48 sysret cs and ss selector base r/w during the sysret instruction, this field is copied into the cs register and the contents of this field, plus 1000b, are copied into the ss register. 47C32 syscall cs and ss selector base r/w during the syscall instruction, this field is copied into the cs register and the contents of this field, plus 1000b, are copied into the ss register. 31C0 target eip address r/w during the syscall instruction, this address is copied into the eip and points to the new starting address.
model-specific registers (msrs) 21 21329l/0 december 1999 amd-k6 ? processor bios design figure 5. extended feature enable register (efer)msr c000_0080h (model 8/[f:8]) ewbe control. the amd-k6-2 processor model 8/[f:8] contains an 8-byte write merge buffer that allows the processor to conditionally combine data from multiple noncacheable write cycles into this merge buffer. the merge buffer operates in conjunction with the memory type range registers (mtrrs). refer to uc/wc cacheability control register (uwccr) on page 26 for a description of the mtrrs. merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. the presence of the merge buffer creates the potential to perform out-of-order write cycles relative to the processors table 9. extended feature enable register (efer) definition (model 8/[f:8]) bit description r/w function 63C4 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 3-2 ewbe control (ewbec) r/w this 2-bit field controls the behavior of the processor with respect to the ordering of write cycles and the ewbe# signal. efer[3] and efer[2] are global ewbe disable (gewbed) and speculative ewbe disable (sewbed), respectively. 1 data prefetch enable (dpe) r/w dpe must be set to 1 to enable data prefetching (this is the default setting following reset). if enabled, cache misses initiated by a memory read within a 32-byte cache line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. 0 system call extension (sce) r/w sce must be set to 1 to enable the usage of the syscall and sysret instructions. 10 63 s c e reserved 2 3 4 d p e ewbec symbol description bi t ewbec ewbe control 3-2 dpe data prefetch enable 1 sce system call extension 0
22 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 cache. in general, the ordering of write cycles that are driven externally on the system bus and those that hit the processors cache can be controlled by the ewbe# signal. if ewbe# is sampled negated, the processor delays the commitment of write cycles to cache lines in the modified state or exclusive state in the processors cache. therefore, the system logic can enforce strong ordering by negating ewbe# until the external write cycle is complete, thereby ensuring that a subsequent write cycle that hits the cache does not complete ahead of the external write cycle. however, the addition of the write merge buffer introduces the potential for out-of-order write cycles to occur between writes to the merge buffer and writes to the processors cache. because these writes occur entirely within the processor and are not sent out to the processor bus, the system logic is not able to enforce strong ordering with the ewbe# signal. the ewbe control (ewbec) bits provide a mechanism for enforcing three different levels of write ordering in the presence of the write merge buffer: n efer[3] is defined as the global ewbe disable (gewbed). when gewbed equals 1, the processor does not attempt to enforce any write ordering internally or externally (the ewbe# signal is ignored). this is the maximum performance setting. n efer[2] is defined as the speculative ewbe disable (sewbed). sewbed only affects the processor when gewbed equals 0. if gewbed equals 0 and sewbed equals 1, the processor enforces strong ordering for all internal write cycles with the exception of write cycles addressed to a range of memory defined as uncacheable (uc) or write-combining (wc) by the mtrrs. in addition, the processor samples the ewbe# signal. if ewbe# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until ewbe# is sampled asserted. this setting provides performance comparable to, but slightly less than, the performance obtained when gewbed equals 1 because some degree of write ordering is maintained.
model-specific registers (msrs) 23 21329l/0 december 1999 amd-k6 ? processor bios design n if gewbed equals 0 and sewbed equals 0, the processor enforces strong ordering for all internal and external write cycles. in this setting, the processor assumes, or speculates , that strong order must be maintained between writes to the merge buffer and writes that hit the processors cache. once the merge buffer is written out to the processors bus, the ewbe# signal is sampled. if ewbe# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until ewbe# is sampled asserted. this setting is the default after reset and provides the lowest performance of the three settings because full write ordering is maintained. table 10 summarizes the three settings of the ewbec field for the efer register, along with the effect of write ordering and performance. enforcing complete write ordering in a uniprocessor system is usually not necessary. in order to achieve the highest level of performance while still maintaining support for the ewbe# signal, amd recommends that the bios set efer[3:2] to 01b (close-to-best performance). many uniprocessor systems do not support the ewbe# signal, in which case amd recommends that the bios set efer[3:2] to 10b or 11b (best performance). write handling control register (whcr) the amd-k6-2 processor model 8/[f:8] contains a split level-1 (l1) 64-kbyte writeback cache organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes, and lines are read from memory using an efficient pipelined burst read cycle. further performance gains are achieved by the implementation of a write allocation scheme. table 10. ewbec settings efer[3] (gewbed) efer[2] (sewbed) write ordering performance 1 0 or 1 none best 0 1 all except uc/wc close-to-best 0 0 all slowest
24 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 a write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the l1 cache. for more information on write allocate, see the implementation of write allocate in the k86? processors application note , order# 21326 and the cache organization section of the amd-k6 ? -2 processor data sheet , order# 21850 or the amd-k6 ? -iii processor data sheet , order# 21918. this section describes two programmable mechanisms used by the amd-k6-2 processor model 8/[f:8] to determine when to perform write allocate. when either of these mechanisms indicates that a pending write is to a cacheable area of memory, a write allocate is performed. before enabling write allocate or changing memory cacheability, the bios must write back and invalidate the internal cache by using the wbinvd instruction. in addition, write allocate should be enabled only after performing any memory sizing or typing algorithms. the write handling control register (whcr) is a msr that contains two f ieldsthe write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 6). note: the whcr register as defined in the model 6, model 7, and model 8/[7:0] has changed in the model 8/[f:8]. figure 6. write handling control register (whcr)msr c000_0082h (model 8/[f:8]) 15 22 0 63 reserved waelim 16 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits waelim write allocate enable limit 31-22 wae15m write allocate enable 15-to-16-mbyte 16 17 21 31 32
model-specific registers (msrs) 25 21329l/0 december 1999 amd-k6 ? processor bios design write allocate enable limit. the waelim field is 10 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that misses the l1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector (for more information, see the cache organization chapter in the amd-k6 ? -2 processor data sheet , order# 21850 or the amd-k6 ? -iii processor data sheet , order# 21918). the maximum value of this limit is ((2 10 C1) 4 mbytes) = 4092 mbytes. when all the bits in this field are set to 0, all memory is above this limit and the write allocate mechanism is disabled (even if all bits in the waelim field are set to 0, write allocates can still occur due to the write to a cacheable page and write to a sector mechanisms). once the bios determines the amount of ram installed in the system, this number should also be used to program the waelim field. for example, a system with 32 mbytes of ram would program the waelim field with the value 00_0000_1000b. this value (8), when multiplied by 4 mbytes, yields 32 mbytes as the write allocate limit. write allocate enable 15-to-16-mbyte. the wae15m bit is used to enable write allocations for the memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocates in this memory area. this sub-mechanism of the waelim provides a memory hole to prevent write allocates. this memory hole is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0 (even if the wae15m bit is set to 0, write allocates can still occur between 15 mbytes and 16 mbytes due to the write to a cacheable page and write to a sector mechanisms). the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition, write allocations are not performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by
26 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 means of write to a cacheable page or write to a sector. it is not safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a noncacheable region of memory. additionally, if a memory region is defined as write-combinable or uncacheable by a mtrr, write allocates are not performed in that region. syscall/sysret target address register (star) the star register in the amd-k6-2 processor model 8/[f:8] is identical to the implementation of this register in the model 8/[7:0]. see syscall/sysret target address register (star) on page 19. uc/wc cacheability control register (uwccr) the amd-k6-2 processor model 8/[f:8] provides two variable- range memory type range registers (mtrrs)mtrr0 and mtrr1that each specify a range of memory. each range can be defined as one of the following memory types: n uncacheable (uc) memorymemory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. memory write cycles are targeted at the specified memory address and a write allocation does not occur. n write-combining (wc) memorymemory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. the processor conditionally combines data from multiple noncacheable write cycles that are addressed within this range into a merge buffer. merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. this memory type is applicable for linear video frame buffers. note: the mtrrs defined in this document are not software compatible to the mtrrs defined by the pentium pro and pentium ii processors. the programmer accesses the mtrrs by addressing the 64-bit msr known as the uc/wc cacheability control register (uwccr). the msr address of the uwccr is c000_0085h. following reset, all bits in the uwccr register are set to 0. mtrr0 (lower 32 bits of the uwccr register) defines the size and memory type of range 0 and mtrr1 (upper 32 bits) defines the size and memory type of range 1 (see figure 7).
model-specific registers (msrs) 27 21329l/0 december 1999 amd-k6 ? processor bios design prior to programming write-combining or uncacheable areas of memory in the uwccr, the software must disable the processors cache, then flush the cache. this can be achieved by setting the cd bit in cr0 to 1 and executing the wbinvd instruction. following the programming of the uwccr, the processors cache must be enabled by setting the cd bit in cr0 to 0. figure 7. uc/wc cacheability control register (uwccr) msr c000_0085h (model 8/[f:8]) physical base address n (n=0, 1). this address is the 15 most- significant bits of the physical base address of the memory range. the least-significant 17 bits of the base address are not needed because the base address is by definition always aligned on a 128-kbyte boundary. physical address mask n (n=0, 1). this value is the 15 most- significant bits of a physical address mask that is used to define the size of the memory range. this mask is logically anded with both the physical base address field of the uwccr register and the physical address generated by the processor. if the results of the two and operations are equal, then the generated physical address is considered within the range. that is, if: mask & physical base address = mask & physical address generated then the physical address generated by the processor is in the range. wcn (n=0, 1). when set to 1, this memory range is defined as write-combinable (refer to table 11). write-combinable memory is uncacheable. 16 0 63 physical address mask 0 17 31 physical base address 0 1 2 physical address mask 1 physical base address 1 32 33 34 48 49 u c 0 w c 0 u c 1 w c 1 mtrr1 mtrr0 symbol description bits uc0 uncacheable memory type 0 wc0 write-combining memory type 1 symbol description bits uc1 uncacheable memory type 32 wc1 write-combining memory type 33
28 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 ucn (n=0, 1). when set to 1, this memory range is defined as uncacheable (refer to table 11). memory-range restrictions. the following rules regarding the address alignment and size of each range must be adhered to when programming the physical base address and physical address mask fields of the uwccr register: n the minimum size of each range is 128 kbytes. n the physical base address must be aligned on a 128-kbyte boundary. n the physical base address must be range-size aligned . for example, if the size of the range is 1 mbyte, then the physical base address must be aligned on a 1-mbyte boundary. n all bits set to 1 in the physical address mask must be contiguous. likewise, all bits set to 0 in the physical address mask must be contiguous. for example: 111_1111_1100_0000b is a valid physical address mask 111_1111_1101_0000b is invalid table 12 lists the valid physical address masks and the resulting range sizes that can be programmed in the uwccr register. table 11. wc/uc memory type wcn ucn memory type 0 0 no effect on cacheability or write-combining 1 0 write-combining memory range (uncacheable) 0 or 1 1 uncacheable memory range table 12. valid masks and range sizes masks size 111_1111_1111_1111b 128 kbytes 111_1111_1111_1110b 256 kbytes 111_1111_1111_1100b 512 kbytes 111_1111_1111_1000b 1 mbyte 111_1111_1111_0000b 2 mbytes
model-specific registers (msrs) 29 21329l/0 december 1999 amd-k6 ? processor bios design example. suppose that the range of memory from 16 mbytes to 32 mbytes is uncacheable, and the 8-mbyte range of memory on top of 1 gbyte is write-combinable. range 0 is defined as the uncacheable range, and range 1 is defined as the write- combining range. extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 16 mbytes (0100_0000h) yields a physical base address 0 field of 000_0000_1000_0000b. because the uncacheable range size is 16 mbytes, the physical mask value 0 field is 111_1111_1000_0000b, according to table 12. bit 1 of the uwccr register (wc0) is set to 0 and bit 0 of the uwccr register is set to 1 (uc0). extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 1 gbyte (4000_0000h) yields a physical base address 1 field of 010_0000_0000_0000b. because the write-combining range size is 8 mbytes, the physical mask value 1 field is 111_1111_1100_0000b, according to table 12. bit 33 of the uwccr register (wc1) is set to 1 and bit 32 of the uwccr register is set to 0 (uc1). 111_1111_1110_0000b 4 mbytes 111_1111_1100_0000b 8 mbytes 111_1111_1000_0000b 16 mbytes 111_1111_0000_0000b 32 mbytes 111_1110_0000_0000b 64 mbytes 111_1100_0000_0000b 128 mbytes 111_1000_0000_0000b 256 mbytes 111_0000_0000_0000b 512 mbytes 110_0000_0000_0000b 1 gbyte 100_0000_0000_0000b 2 gbytes 000_0000_0000_0000b 4 gbytes table 12. valid masks and range sizes (continued) masks size
30 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 processor state observability register (psor) the amd-k6-2 processor model 8/[f:8] provides the processor state observability register (psor) (see figure 8). . figure 8. processor state observability register (psor )msr c000_0087h (model 8/[f:8]) nol2. this read-only bit indicates whether the processor contains a l2 cache. this bit is always set to 1 for model 8/[f:8]. step. this read-only field contains the stepping id. this is identical to the value returned by cpuid standard function 1 in eax[3:0]. bf. this read-only field contains the value of the bf signals sampled by the processor during the falling transition of reset, which allows the bios to determine the frequency of the host bus. the core frequency must first be determined using the time stamp counter method (see time stamp counter (tsc) on page 15). the core frequency is then divided by the processor-clock to bus-clock ratio as determined by the bf field of the psor register (see table 13). the result is the frequency of the processor bus. 20 63 bf reserved symbol description bit nol2 no l2 functionality 8 step processor stepping 7-4 bf bus frequency divisor 2-0 3 4 step 7 8 9 n o l 2
model-specific registers (msrs) 31 21329l/0 december 1999 amd-k6 ? processor bios design table 13. processor-to-bus clock ratios page flush/invalidate register (pfir) the amd-k6-2 processor model 8/[f:8] contains the page flush/invalidate register (pfir) (see figure 9 on page 31) that allows cache invalidation and optional flushing of a specific 4-kbyte page from the linear address space. the total amount of l1 cache in the model 8/[f:8] is 64 kbytes. using this register can result in a much lower cycle count for flushing particular pages versus flushing the entire cache. when the pfir is written to (using the wrmsr instruction), the invalidation and, optionally, the flushing begins. figure 9. page flush/invalidate register (pfir)msr c000_0088h (model 8/[f:8]) state of bf[2:0] processor-clock to bus-clock ratio 100b 2.5x 101b 3.0x 110b 6.0x* 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x note: * the 2.0x ratio that was supported on models 6, 7, and 8/[7:0] is no longer supported on model 8/[f:8] or model 9. instead, if bf[2:0] equals 110b, a ratio of 6.0x is selected. linpage 10 63 f / i reserved symbol description bi t linpage 20-bit linear page address 31-12 pf page fault occurred 8 f/i flush/invalidate command 0 11 31 12 32 p f 987
32 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 linpage. this 20-bit field must be written with bits 31:12 of the linear address of the 4-kbyte page that is to be invalidated and optionally flushed from the l1 cache. pf. if an attempt to invalidate or flush a page results in a page fault, the processor sets the pf bit to 1, and the invalidate or flush operation is not performed (even though invalidate operations do not normally generate page faults). in this case, an actual page fault exception is not generated. if the pf bit equals 0 after an invalidate or flush operation, then the operation executed successfully. the pf bit must be read after every write to the pfir register to determine if the invalidate or flush operation executed successfully. f/i. this bit is used to control the type of action that occurs to the specified linear page. if a 0 is written to this bit, the operation is a flush, in which case all cache lines in the modified state within the specified page are written back to memory, after which the entire page is invalidated. if a 1 is written to this bit, the operation is an invalidation, in which case the entire page is invalidated without the occurrence of any writebacks.
model-specific registers (msrs) 33 21329l/0 december 1999 amd-k6 ? processor bios design amd-k6 ? -iii processor model 9 the amd-k6-iii processor model 9 provides the following eleven msrs. the first four m srs are described in standard msrs on page 15. the contents of ecx selects the msr to be addressed by the rdmsr and wrmsr instruction. n machine-check address register (mcar)ecx = 00h n machine-check type register (mctr)ecx = 01h n test register 12 (tr12)ecx = 0eh n time stamp counter (tsc)ecx = 10h n extended feature enable register (efer)ecx = c000_0080h n write handling control register (whcr)ecx = c000_0082h n syscall/sysret target address register (star)ecx = c000_0081h n uc/wc cacheability control register (uwccr)ecx = c000_0085h n processor state observability register (psor)ecx = c000_0087h n page flush/invalidate register (pfir)ecx = c000_0088h n level-2 cache array access register (l2aar)ecx = c000_0089h extended feature enable register (efer) bits 3:0 of the efer register in the amd-k6-iii processor model 9 are identical to the implementation of these bits in the model 8/[f:8]. see extended feature enable register (efer) on page 20. the l2 disable bit (l2d)efer[4]is an addition to the efer register in the model 9. figure 10 shows the format of the efer register, and table 14 defines the function of each bit of the efer register. the efer register is msr c000_0080h.
34 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 figure 10. extended feature enable register (efer)msr c000_0080h (model 9) note: setting l2d to 1 does not guarantee cache coherency. to ensure coherency, the processors caches must be disabled (by setting the cd bit of the cr0 register to 1), then flushed prior to setting l2d to 1. write handling control register (whcr) the amd-k6-iii processor contains a split level-1 (l1) 64-kbyte writeback cache organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes, and lines are read from memory table 14. extended feature enable register (efer) definition (model 9) bit description r/w function 63C5 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 4 l2 disable (l2d) r/w if l2d is set to 1, the l2 cache is completely disabled. this bit is provided for debug and testing purposes. for normal operation and maximum performance, this bit must be set to 0 (this is the default setting following reset). 3-2 ewbe control (ewbec) r/w this 2-bit field controls the behavior of the processor with respect to the ordering of write cycles and the ewbe# signal. efer[3] and efer[2] are global ewbe disable (gewbed) and speculative ewbe disable (sewbed), respectively. 1 data prefetch enable (dpe) r/w dpe must be set to 1 to enable data prefetching (this is the default setting following reset). if enabled, cache misses initiated by a memory read within a 32-byte cache line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. 0 system call extension (sce) r/w sce must be set to 1 to enable the usage of the syscall and sysret instructions. 10 63 s c e reserved 2 3 4 d p e ewbec l 2 d symbol description bit l2d l2 disable 4 ewbec ewbe control 3-2 dpe data prefetch enable 1 sce system call extension 0 5
model-specific registers (msrs) 35 21329l/0 december 1999 amd-k6 ? processor bios design using an efficient pipelined burst read cycle. in addition, the amd-k6-iii processor also contains a 256-kbyte, 4-way set associative, unified level-2 (l2) cache. further performance gains are achieved by the implementation of a write allocation scheme. the whcr register in the amd-k6-iii processor model 9 is identical to the implementation of this register in the model 8/[f:8]. see write handling control register (whcr) on page 23. note: the whcr register as defined in the model 6, model 7, and model 8/[7:0] has changed in the model 9. syscall/sysret target address register (star) the star register in the amd-k6-iii processor model 9 is identical to the implementation of this register in the model 8/[7:0]. see syscall/sysret target address register (star) on page 19. uc/wc cacheability control register (uwccr) the uwccr register in the amd-k6-iii processor model 9 is identical to the implementation of this register in the model 8/[f:8]. see uc/wc cacheability control register (uwccr) on page 26. processor state observability register (psor) the amd-k6-iii processor model 9 provides the processor state observability register (psor) (see figure 11). . figure 11. processor state observability register (psor )msr c000_0087h (model 9) nol2. this read-only bit indicates whether the processor contains an l2 cache. this bit is always set to 0 for model 9. 20 63 bf reserved symbol description bit nol2 no l2 functionality 8 step processor stepping 7-4 bf bus frequency divisor 2-0 3 4 step 7 8 9 n o l 2
36 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 step. this read-only field contains the stepping id. this is identical to the value returned by cpuid standard function 1 in eax[3:0]. bf. this read-only field contains the value of the bf signals sampled by the processor during the falling transition of reset, which allows the bios to determine the frequency of the host bus. the core frequency must first be determined using the time stamp counter method (see time stamp counter (tsc) on page 15). the core frequency is then divided by the processor-clock to bus-clock ratio as determined by the bf field of the psor register (see table 13 on page 31). the result is the frequency of the processor bus. page flush/invalidate register (pfir) the pfir register in the amd-k6-iii processor model 9 is identical to the implementation of this register in the model 8/[f:8]. see page flush/invalidate register (pfir) on page 31. the invalidate and flush operations affect the processors l1 and l2 caches on the model 9. level-2 cache array access register (l2aar) the amd-k6-iii processor model 9 provides the l2aar register that allows for direct access to the l2 cache and l2 tag arrays. the 256-kbyte l2 cache in the amd-k6-iii processor is organized as shown in figure 12: n four 64-kbyte ways n each way contains 1024 sets n each set contains four 64-byte sectors (one sector in each way) n each sector contains two 32-byte cache lines n each cache line contains four 8-byte octets n each octet contains an upper and lower dword (4 bytes) each line within a sector contains its own mesi state bits, and associated with each sector is a tag and lru (least recently used) information.
model-specific registers (msrs) 37 21329l/0 december 1999 amd-k6 ? processor bios design figure 12. l2 cache organization figure 13 shows the l2 cache sector and line organization. if bit 5 of the address of a cache line equals 1, then this cache line is stored in line 1 of a sector. similarly, if bit 5 of the address of a cache line equals 0, then this cache line is stored in line 0 of a sector. figure 13. l2 cache sector and line organization the l2aar register is msr c000_0089h. the operation that is performed on the l2 cache is a function of the instruction executedrdmsr or wrmsrand the contents of the edx register. the edx register specifies the location of the access, and whether the access is to the l2 cache data or tags (refer to figure 14). bit 20 of edx (t/d) determines whether the access is to the l2 cache data or tag. table 15 describes the operation that is performed based on the instruction and the t/d bit. 1024 sets set 0 64 bytes way 2 line1/mesi line0/mesi tag/lru 64 bytes way 1 line1/mesi line0/mesi tag/lru 64 bytes way 0 line1/mesi line0/mesi tag/lru 64 bytes way 3 line1/mesi line0/mesi tag/lru set 1023 upper dword lower dword octet 0 line 1 octet 1 octet 2 octet 3 upper dword lower dword line 0 sector
38 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 figure 14. l2 tag or data location - edx when the l2aar is read or written, edx is left unchanged. this facilitates multiple accesses when testing the entire cache/tag array. if the l2 cache data is read (as opposed to reading the tag information), the result (dword) is placed in eax in the format as illustrated in figure 15. similarly, if the l2 cache data is written, the write data is taken from eax. reserved 0 set 21 31 20 19 17 16 5 15 18 way 4321 6 symbol description bit set selects the desired cache set 15-6 line selects line1 (1) or line0 (0) 5 octet selects one of four octets 4-3 dword selects upper (1) or lower (0) dword 2 l i n e octet d w o r d t / d symbol description bit t/d selects tag (1) or data (0) access 20 way selects desired cache way 17-16 table 15. tag versus data selector instruction t/d (edx[20]) operation rdmsr 0 read dword from l2 data array into eax. dword location is specified by edx. rdmsr 1 read tag, line state and lru information from l2 tag array into eax. location of tag is specified by edx. wrmsr 0 write dword to the l2 data array using data in eax. dword location is specified by edx. wrmsr 1 write tag, line state and lru information into l2 tag array from eax. location of tag is specified by edx.
model-specific registers (msrs) 39 21329l/0 december 1999 amd-k6 ? processor bios design figure 15. l2 data - eax if the l2 tag is read (as opposed to reading the cache data), the result is placed in eax in the format as illustrated in figure 16. similarly, if the l2 tag is written, the write data is taken from eax. when writing to the l2 tag, special consideration must be given to the least significant bit of the tag field of the eax register eax[15]. the length of the l2 tag required to support the 256-kbyte l2 cache on the model 9 is 16 bits, which corresponds to bits 31:16 of the eax register. however, the processor provides a total of 17 bits for storing the l2 tagthat is, 16 bits for the tag (eax[31:16]), plus an additional bit for internal purposes (eax[15]). during normal operation, the processor ensures that this additional bit (bit 15) always corresponds to the set in which the tag resides. note that bits 15:6 of the address determine the set, in which case bit 15 equal to 0 addresses sets 0 through 511, and bit 15 equal to 1 addresses sets 512 through 1023. in order to set the full 17-bit l2 tag properly when using the l2aar register, eax[15] must likewise correspond to the set in which the tag is being writtenthat is, eax[15] must be equal to edx[15] (refer to figure 14 and figure 16). it is important to note that this special consideration is only required if the processor will subsequently be expected to properly execute instructions or access data from the l2 cache following the setup of the l2 cache by means of the l2aar register. if the intent of using the l2aar register is solely to test or debug the l2 cache without the subsequent intent of executing instructions or accessing data from the l2 cache, then this consideration is not required. when accessing the l2 tag, the line, octet, and dword fields of the edx register are ignored. 0 31 data
40 model-specific registers (msrs) amd-k6 ? processor bios design 21329l/0december 1999 figure 16. l2 tag information - eax lru (least recently used). for the 4-way set associative l2 cache, each way has a 2-bit lru field for each sector. values for the lru field are 00b, 01b, 10b, and 11b, where 00b indicates that the sector is most recently used, and 11b indicates that the sector is least recently used (see figure 17). eax[7:6] indicate lru information for way 0, eax[5:4] for way 1, eax[3:2] for way 2, and eax[1:0] for way 3. figure 17. lru byte c m d reserved 0 tag 15 31 14 12 10 9 7 8 11 lru line0st line1st symbol description bit tag tag data read or written 31-15 line1st line 1 state (m=11, e=10, s=01, i=00) 11-10 line0st line 0 state (m=11, e=10, s=01, i=00) 9-8 lru two bits of lru for each way 7-0 7654 32 1 0 way 2 lru values 00b most recently used 01b used more recent than 10b, but less recent than 00b 10b used more recent than 11b, but less recent than 01b 11b least recently used way 3 way 0 way 1
new amd-k6 ? processor instructions 41 21329l/0 december 1999 amd-k6 ? processor bios design new amd-k6 ? processor instructions all models of the amd-k6 processor implement the following new instruction set: n mmx? instructions57 new instructions for multimedia software. see the amd-k6 ? processor multimedia technology manual , order# 20726 for more information. amd-k6-2 processor models 8 and above, and the amd-k6-iii processor model 9 implement the following new instructions: n 3dnow!? instructions21 new instructions for multimedia software. see the 3dnow!? technology manual , order# 21928 for more information. n syscall and sysret see the syscall and sysret instruction specification application note , order# 21086 for more information. additional considerations software timing dependencies relative to memory controller setup processors in the k86 family differ from other processors with regards to instruction latencies and the order or priority of processor bus cycles. timing-dependent software that relies on the specific latencies of other processors should be re-tested for proper operation with the k86 processor. in addition, re-testing should be performed on components with variable timing (such as, memory modules, oscillators, and timers). particular attention should be paid to memory-setup subroutines that determine the type of dram in the system. some chipsets may not tolerate a dram mode change (such as, edo to sdram) on the same clock as a dram refresh cycle. for example some chipsets do not tolerate having its memory refresh enabled prior to changing memory mode types. refresh should only be enabled after the memory type has been determined. note: the bios for the k86 family of processors should enable the write allocate mechanisms only after performing any memory sizing or typing algorithms.
42 additional considerations amd-k6 ? processor bios design 21329l/0december 1999 pipelining support all production models and steppings of the amd-k6 processor support the waelim form of write allocate, which is the only form of write allocate that should be enabled. amd does not recommend enabling the obsolete form of write allocate (wcde) because system performance can be degraded by doing so. early implementations of the amd-k6 processor did not support the whcr register and therefore did not support the waelim form of write allocate. wcde was the only form of write allocate supported, which required the chipset to assert ken# for cacheable memory write cycles. because ken# is sampled by the processor on the clock edge on which the first brdy# or na# is sampled asserted, some chipsets that supported the wcde form of write allocate did not assert na# during write cycles in order to prevent the processor from sampling ken# before it was valid (in this case, brdy# was used by the processor to sample ken#). if na# is not asserted during memory write cycles, then the processor does not fully take advantage of the potential performance gains that bus pipelining can achieve. for proper functionality, always program the wcde bit to 0 for models 6, 7, and 8/[7:0]. models 8/[f:8] and 9 do not support the wcde bit. read-only memory the processors caches must be flushed prior to defining any area of memory as cacheable and read only. (the bios is typically shadowed into main memory and defined as cacheable and read only.) if the caches are not flushed, then a line that resides in the processors cache that falls within a read- only area of memory can be written to, which would place the cache line in the modified state. if this modified line is subsequently replaced and written back to memory, then the system may hang (or other unpredictable effects may occur) because the writeback is directed to an area of memory defined as read only by the chipset.

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