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 81A
CYM1481A
2048K x 8 SRAM Module
Features
* High-density 16-megabit SRAM modules * High-speed CMOS SRAMs -- Access time of 70 ns * Low active power -- 605 mW (max.), 2M x 8 * Double-sided SMD technology * TTL-compatible inputs and outputs * Small footprint SIP -- PCB layout area of 0.72 sq. in. * 2V data retention (L version) are constructed from four 512K x 8 SRAMs in plastic surface-mount packages on an epoxy laminate board with pins. On-board decoding selects one of the SRAMs from the high-order address lines, keeping the remaining devices in standby mode for minimum power consumption. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When MS and WE inputs are both LOW, data on the eight data input/output pins is written into the memory location specified on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs MS and OE active LOW while WE remains inactive or HIGH. Under these conditions, the content of the location addressed by the information on the address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Functional Description
The CYM1481A is a high-performance 16-megabit static RAM module organized as 2048K words by 8 bits. These modules
Logic Block Diagram
A0-A 18
19
Pin Configuration SIP
A19 VCC WE I/O2 I/O3 I/O0 A1 A2 A3 A4 GND I/O5 A10 A11 A5 A13 A14 A20 MS A15 A16 A12 A18 A6 I/O1 GND A0 A7 A8 A9 I/O7 I/O4 I/O6 A17 I/O0-I/O 7 VCC OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Top View
512K x 8 SRAM
OE WE A 19-A 20
2 1 of 4 DECODER 512K x 8 SRAM
MS
512K x 8 SRAM
512K x 8 SRAM
8 1481-1
/
Selection Guide
CYM1481A Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Cypress Semiconductor Corporation Document #: 38-05074 Rev. ** * 70 110 64 3901 North First Street * 85 110 64 San Jose * 100 110 64 120 110 64
CA 95134 * 408-943-2600 Revised September 4, 2001
CYM1481A
Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature -55C to +125C Ambient Temperature with Power Applied0C to +70C Supply Voltage to Ground Potential-0.3V to +7.0V DC Voltage Applied to Outputs in High Z State-0.3V to +7.0V Range Commercial DC Input Voltage-0.3V to +7.0V Output Current into Outputs (LOW)20 mA
Operating Range
Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
1481A Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Automatic MS Power-Down Current Automatic MS Power-Down Current GND < VI < VCC GND < VO < VCC, Output Disabled Max. VCC, MS > VIH, Min. Duty Cycle = 100% Max. VCC, MS > VCC - 0.2V, VIN > VCC - 0.2V, or VIN < 0.2V Standard L Version -100, -120 L Version -85 Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.0 mA 2.2 -0.3 -20 -20 Min. 2.4 0.4 VCC + 0.3 0.8 +20 +20 110 64 32 500 1600 Max. Unit V V V V A A mA mA mA A A
VCC Operating Supply Current VCC = Max., MS < VIL, IOUT = 0 mA
Capacitance[1]
Parameter CINA CINB COUT Description Input Capacitance (A0-16, OE, WE) Input Capacitance (A17-20, MS) Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V CYM1481AM ax. 125 25 165 Unit pF pF pF
Note: 1. Tested on a sample basis.
Document #: 38-05074 Rev. **
Page 2 of 9
CYM1481A
AC Test Loads and Waveforms
R1 2530 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 2830 R2 2830 R1 2530 3.0V 90% 5 pF GND < 10 ns 10% 90% 10% < 10 ns ALL INPUT PULSES
INCLUDING JIG AND SCOPE
(a)
Equivalent to: OUTPUT
1481-2
(b)
1481-3
1481-4
THEVENIN EQUIVALENT 1340 2.64V
Switching Characteristics Over the Operating Range[2]
1481A-70 Parameter READ CYCLE tRC tAA tOHA tAMS tDOE tLZOE tHZOE tLZMS tHZMS tWC tSMS tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change MS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z MS LOW to Low Z
[5] [3] [4]
1481A-85 Min. 85 Max.
1481A-100 Min. 100 Max.
1481A-120 Min. 120 Max. Unit ns 120 10 120 60 5 45 10 45 120 100 100 7 5 85 45 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40 5 ns ns
Description
Min. 70
Max.
70 5 70 40 5 30 5 30 70 65 65 5 0 65 30 0 30 5 5 85 75 75 7 5 65 35 5 10 5 10
85 10 85 45 5 30 10 30 100 90 90 7 5 75 40 5 30 5
100 100 50 35 35
MS HIGH to High Z[3, 4] Write Cycle Time MS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[3]
WRITE CYCLE
35
WE HIGH to Low Z
Notes: 2. Test conditions assume signal transition time of 10 s or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of 1 TTL load, and 100-pF load capacitance. 3. tHZOE, tHZMS, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 4. At any given temperature and voltage condition, tHZMS is less than tLZMS for any given device. These parameters are guaranteed and not 100% tested. 5. The internal write time of the memory is defined by the overlap of MS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05074 Rev. **
Page 3 of 9
CYM1481A
Data Retention Characteristics (L Version Only)
1481A-70 Parameter VDR ICCDR tCDR[6] tR Description VCC for Retention Data Data Retention Current VDR = 3.0V, MS > VCC - 0.2V, Chip Deselect to Data VIN > VCC - 0.2V or VIN Retention Time < 0.2V Operation Recovery Time Test Conditions Min. 2 800 0 5 0 5 Max. 1481A-85 Min. 2 800 0 5 Max. 1481A-100 148A1-120 Min. 2 250 Max. Unit V A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR VDR CS VIH VIH
1481-6
VDR > 2V
4.5V tR
Switching Waveforms
Read Cycle No. 1[7, 8]
tRC ADDRESS tAA tOHA DATAOUT PREVIOUS DATA VALID DATA VALID
1481-7
Notes: 6. Guaranteed, not tested. 7. Device is continuously selected. OE, MS = VIL. 8. Address valid prior to or coincident with MS transition LOW.
Document #: 38-05074 Rev. **
Page 4 of 9
CYM1481A
Switching Waveforms (continued)
Read Cycle No. 2 [8, 9]
tRC MS tAMS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZMS DATA VALID
1481-8
tHZOE tHZMS HIGH IMPEDANCE
Write Cycle No. 1
[5, 10]
tWC ADDRESS tSMS MS tAW tSA WE tSD DATA IN DATA VALID tHZWE DATA I/O DATA UNDEFINED
1481-9
tHA tPWE
tHD
tLZWE HIGH IMPEDANCE
Notes: 9. WE is HIGH for read cycle. 10. Data I/O is high impedance if OE = VIH.
Document #: 38-05074 Rev. **
Page 5 of 9
CYM1481A
Switching Waveforms (continued)
Write Cycle No. 2
[5, 10, 11]
tWC ADDRESS tSA MS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED
1481-10
tSMS
tHA
tHD
Note: 11. If MS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05074 Rev. **
Page 6 of 9
CYM1481A
Truth Table
MS H L L L WE X H L H OE X L X H Input/Outputs High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
Ordering Information
Speed (ns) 70 85 100 120 Ordering Code CYM1481APS-70C CYM1481ALPS-70C CYM1481APS-85C CYM1481ALPS-85C CYM1481APS-100C CYM1481ALPS-100C CYM1481APS-120C CYM1481ALPS-120C PS10 36-Pin SIP Module Commercial PS10 36-Pin SIP Module Commercial PS10 36-Pin SIP Module Commercial Package Type PS10 Package Type 36-Pin SIP Module Operating Range Commercial
Document #: 38-05074 Rev. **
Page 7 of 9
CYM1481A
Package Diagram
36-Pin SIP Module PS10
Document #: 38-05074 Rev. **
Page 8 of 9
(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYM1481A
Document Title: CYM1481A 2048K x 8 SRAM Module Document Number: 38-05074 REV. ** ECN NO. 107267 Issue Date 09/15/01 Orig. of Change SZV Description of Change Change from Spec number: 38-M-00041 to 38-05074
Document #: 38-05074 Rev. **
Page 9 of 9


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