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| (R) APPLICATION NOTE DESIGNING A HIGH POWER FACTOR SWITCHING PREREGULATOR WITH THE L6560/A TRANSITION MODE I.C. by G. Comandatore and U. Moriconi Active power factor correction techniques are going to grow in conversion applications. Market interest (legislation to be considered) is also moving towards fairly low (36-150W) conversion power ranges (lighting, monitor). This paper describes an "easy to use" 8 Pin Controller that allows the realization of very low cost offline Power Factor Correction. Switching at a frequency much higher than the line, the preregulator draws a half-sinusoidal input current, in phase with the line voltage. BOOST TOPOLOGY with its inductor at the input is well suited for PFC application. The input di/dt is low because the inductor is located between the bridge and the switch. This minimizes line noise and, in addition, the line spikes can be absorbed by the Boost Inductor. L6560/A PFC controller Integrated Circuit The L6560/A is an integrated circuit in Minidip and SO8 packages designed to perform the control of active power factor correction circuits. The I.C. is optimized for electronic ballast, but it can be easily used in switched mode AC-DC conversion. It can directly drive Mosfet or Igbt (see block diagram fig.1). Introduction Conventional AC to DC converters employ a full wave rectifier bridge with a simple capacitor filter to draw DC power from the mains AC. This filter capacitor must be large enough to supply the total power during most of each half-cycle while instantaneous line voltage is below the DC output voltage. With this bulk capacitor filter, the line current waveform is a narrow pulse. Consequently the power factor is poor (0.5-0.6) due to high harmonic distortion of the current waveform. With a high power factor switching preregulator, interposed between the input rectifier bridge and the bulk filter capacitor, the power factor will be improved (up to 0.99). The current capability increased, the bulk capacitor peak current and the harmonic disturbances are reduced. Figure 1: Block Diagram AN667/1003 1/11 APPLICATION NOTE The on chip features are: * Undervoltage lockout with hysteresis and micropower start-up. * Stable error amplifier. * Output overvoltage protection. * Transition Mode Operating * Zero Current and coil Voltage detection. * Internal start oscillator. Device Blocks Description Supply Block (see fig. 2): A precise bandgap reference is internally built to ensure a good regulation. The undervoltage comparator with hysteresis and the very-low supply current, before the turn-on threshold is reached, allows to minimize the startup and supply circuitry. Figure 2: Supply Block Diagram +Vi lows the feedback for the boosted output DC voltage regulation. The E/A output will be connected to the compensation capacitor (see biasing of I.C.) to filter the twice rectified mains frequency (2f) so that the circuit doesn't attempt to regulate the output ripple. The device is provided with an effective overvoltage protection (OVP), realized using the same input pin used for the DC voltage regulation. Since the compensation capacitor slows the E/A response, an internal fast OVP detector is implemented. In steady state condition, the current through R1 is equal to the current in R2 because the comp. capacitor does not allow DC current (nor of course the inverting input of the E/A). IR= V O - 2.5 V 2.5 V = R2 R1 8 H = VALID SUPPLY L = UNDERVOLTAGE + REF. D93IN034A When the output voltage increase, abruptly the current in R1 will be increased of V OUT R 1 value and since the R2 current is fixed by the internal 2.5V reference, the current must flow through the capacitor. This current is sensed inside the L6560/A I.C and compared with an internal 40 A reference. If this limit is exceeded, the dinamic OVP is detected. As the time constant of this fast detection is over, in case the overvoltage condition persists (i.e. disconnected load), the output of the E/A goes below an internal reference and the OVP condition will be confirmed. The OVP detection disables the driver and the external Mosfet is forced off until the overvoltage condition disappears. Moreover, during the OVP conditions all the internal blocks are disabled (except the ZCD clamp) allowing to reduce the power consumption. The OVP limit VOUT will be selected by the equation: V OUT = R 1 40 A Error Amplifier and Overvoltage Detector Block (see fig. 3): The Error Amplifier input, through the ratio of two external resistors connected to the output bus, alFigure 3: Error Amplifier and Overvoltage Detector Block Ccomp. +Vo R1 1 R2 + 2.5V 3.1V I + E/A Zero Current Detection and Triggering Block (see fig. 4): Figure 4: Zero Current Detection and Triggering Block I 2 X PWM DRIVER +Vi PWM 5 5V + 40A D93IN036A R S Q 7 DRIVER 1.3V - GD D93IN035B 2/11 APPLICATION NOTE The zero current detection block switches on the external mosfet as the voltage acroos the boost inductor crosses zero (after the current through the boost diode is over). This feature allows to reduce the equivalent drain capacitance energy, that is dissipated by the external Mosfet, because of the lower effective drain voltage at turn-on (Virms instead of VO). To allow the start-up of the circuit without external parts, an internal pulser has been provided. The pulser, with repetition rate of 45 to 70 s, forces the drive to deliver a narrow pulse (200 to 300ns) to the gate of the mosfet producing the signal for ZCD. On the other hand, for a correct working of the system, the switching frequency must be higher than 23kHz. As the circuit is running, the signal for ZCD is obtained with an auxiliary winding of the booster inductor. Figure 6: Current Comparator and PWM Latch Q 4 RS X D93IN037A A totem pole buffer, with 400mA, source and sink capability allows the external mosfet to switch at high frequency. Multiplier Block (see fig. 5): The multiplier delivers the programming signal to the current comparator. The error signal programs, cycle by cycle, the peak Mosfet current . Current Comparator and PWM Latch (see fig.6): Figure 5: Multiplier Block Diagram Figure 7: Driver VCC DRIVER Rs P.F.C. Boost Topology Operation Although the easy-to-use I.C. and low external component count allows a simple approach, it can be useful to remind some design criteria. The selection of the external components is mainly related on the application's parameters such as: Input main voltage range (Virms), Output power(PO), D.C. output voltage (VO), Switching frequency (sw), etc. The operation of the P.F.C. transition mode controlled boost converter, can be summarized in the following description: The A.C. mains voltage is rectified by a diodes bridge and the rectified voltage delivered to the boost converter. The boost converter section, using a switching technique, boosts the rectified input voltage to a D.C. controlled output voltage (VO). 3/11 CURR.CMP E/A X The current Comp. senses the voltage across the current sense resistor (RS) and, comparing it with the programming signal delivered by the multiplier, produce the switching modulation. Driver (see fig.7): + - 2 3 4 D93IN039A + CMP R S Q DRIVER 7 Q D93IN038 APPLICATION NOTE The section consists of a boost inductor (L), a controlled power switch (Q), a boost diode (D), an output capacitor (CO) and, obviously, a control circuitry (see fig.8). Since the input is a time-variable supply voltage Figure 8: Boost Converter Circuit L D IQ Q ID IC CONTROLLER CO LOAD IO tion mode to lower power range applications than the continuous one. Design Criterias Here below some design criterias are described. For reference, the following definitions are useful: Virms Vo Po Pi Irms = Effective A.C. mains voltage (spec. range) = Regulated output D.C. voltage (rated) = Output Power (rated) = Input Power = Efficiency (PO/Pi) = Effective A.C. mains current (PL/Virms) ~ IL ~ Cin D94IN119 (sinewave), to make the input current shaped like the line voltage, the converter has to produce a boost inductor average current alike the rectified input voltage. To make it possible the I.C. L6560/A controls the system in transition mode. Transition mode approch consists in a "zero current turn on" system, switching at variable frequency and duty cycle (see fig.9). The signal on ZCD (pin 5) allows the Power MosFigure 9: Current Wave PEAK Power Section Design INPUT BRIDGE The input diodes bridge can be a standard offline, slow_recovery, low cost device. The quantities to consider will be just the input current (Irms) and the thermal data. INPUT CAPACITOR The input high frequency filter capacitor (Cin) has to attenuate the switching noise due to high frequency inductor current ripple (twice the average line value) see fig. 9. The worst conditions will be found at the peak of the minimum rated input voltage. The maximum high frequency voltage ripple (r = V I V I) has to be imposed usually between 3% to 9%. C in = I rms 2 sw r V irms INDUCTOR CURRENT where: sw is the switching frequency AVERAGE In real conditions the input capacitance will be designed taking into account the EMI filter. 0 On MOSFET Q Off D93IN040A fet to be turned on after the boost inductor current is reduced to zero and the Mosfet drain capacitance is discharged to the rectified input voltage value (output of the bridge), instead of the output boosted D.C. voltage. Such a method will save crossover power dissipation at turn on. Moreover, working in transition mode, allows to minimize the inductor size due to lower inductance value. On the other hand, higher current ripple on the inductor involves higher noise on the rectified main bus to be filtered with higher input capacitor values. This limits the use of the transi4/11 OUTPUT CAPACITOR The Output Capacitor Filter (CO) choice depends on the electrical parameters that affect the filter performances and also on the final application. The D.C. output voltage and overvoltage, the output power and voltage ripple are the first parameters to consider in all applications. The 100 / 120 Hz (twice the mains frequency) voltage ripple (VO= 1/2 ripple peak/peak value) is a function of the capacitor impedence and the peak capacitor current (IC(2f)pk=IO). ( 2 2f C O) With a low ESR capacitor this can be simplyed: V O = I O 1 2 + ESR 2 APPLICATION NOTE IO 4 f V O PO Being constant the ratio between the input voltage and current, the ton of Power Mosfet is constant too. The switching frequency varies with the instantaneous (Vin) mains voltage. It has its minimum value at the maximum or the minimum mains voltage (depending on the Virms/Voratio). The inductor value is so defined by: L 2 V2irms (VO - Virms ) 2 fsw (min) PO VO CO = 4 f V O V O Although ESR normally does not affect the output ripple parameter, it has to be considered in power losses account both for the rectified main frequency and switching frequency. The RMS capacitor ripple current I C(2f)rms = IO 2 If the application (e.g. computer supply) has to guarantee a specified Hold-Up time (tHold), the capacitance sizing criteria will change: CO has to deliver the supply energy for a certain time with a specified maximum dropout voltage. CO= 2 P O t Hold V O_min 2 - V op_min 2 Where Virms is the maximum or minimum mains voltage value depending on the one which produces the maximum inductor value. Because of the internal oscillator characteristic (see ZCD and triggering block description), the minimum suggested switching frequency is fixed at about 23kHz. The next step designing the Boost Inductor is the core choice. To get the approximated value of the minimum core size, the formula is: Volume 4 K L Irms2(max) where: K = specific energy constant. L = boost inductor values (in mH). The constant K is a function of the magnetic path and for ferrite gapped core-sets depends on the ratio between the gap lenght (lgap) and the total effective lenght (leff) of the magnetic core-set. It has been found that K=1 is a good value to get the minimum core-set volume, in cm3. As the minimum size of the core-set is estimated, the suitable type will be selected with technical and economic considerations. The next step in boost inductor design has to define the coil parameters. The number of turns and the wire section are important quantities to be defined. The above mentioned formula: PO L sw I Lpk 2 2 where: VO_min is the minimum output voltage value (normally at the maximum load conditions) Vop_min is the minimum output operative voltage before the 'power fail' detection. BOOST INDUCTOR Designing the Boost Inductor involves several parameters to be handled and different approaches can be used to define the quantities. The high voltage, flux density and freqency range, make the standard high frequency ferrite (gapped coreset) the most useful material in P.F.C. applications. The inductance value (L) could be defined as follow (assuming = 1): PO L where: (duty-cycle) = 1 - Vit / VO ILpk is the peak inductor current sw is the switching freq. To be noted that and ILpk are variable with Vin: min = L sw I Lpk 2 2 2PO I Lpk 2 sw referred to the magnetic path, can be rewritten as: PO where: A e l eff H B sw 2 V O - 2 V irms VO PO Virms 2 ILpkmax = 2 Ae is the effective area of the core section. l eff is the effective magnetic path length H is the magnetic field strength B is the deviated magnetic flux density. To avoid the saturation of the core, related to the high permeability materials, it is necessary the use 5/11 APPLICATION NOTE of an air-gap in order to allow an adequate magnetic force range (H+Hgap). The ratio between the ferrite and the air path magnetic permeability, depends on the ferrite materials. Core materials for power application (i.e. B50/B51), have permeability value of about 2500 times the air one. This means that, using enough air-gap percentage lenght, it is possible to neglect the contribution of the magnetic reluctance of the core, using lgap instead of leff to semplify the calculation. E.g. with 1% of air-gap length (that is the minimum suggested value) the introduced error, related to the neglected ferrite core magnetic field contribute, is about 4% . The higher air-gap percentage, the lower the error percent. The last formula can be written as: PO A e l gap H gap B sw 2 POWER MOSFET The choice of the Mosfet mainly depends on the output power for its relation with Rdson. The breakdown voltage is just fixed by the output voltage, plus the overvoltage protection imposed limit and the safety margin. The Mosfet power dissipation depends on two contributions: Conduction losses: P on = I Qrms 2 R DSon where: 2 I Qrms = 2 I rms irms 1 - 4 2 V 6 9 V O and simplified with PO L sw I Lpk 2 2 Switching losses: because of the operation mode (zero current turn_on) the crossover losses occur only at turn off of the mosfet: P cross = V O I rms t Fall sw where: tFall is the crossover time at the turn off. While at the turn on, the quantity to be considered is the capacitive loss: P cap = 1 C d V Irms 2 sw 2 to obtain: A e l gap H gap B L I Lpk 2 because l gap H gap N I Lpk B=oH we obtain: N gap L l Where Cd is the equivalent drain capacitance. BOOSTER DIODE The booster freewheeling diode is a fast recovery. The RMS diode current formula, useful for losses computation, is: I Drms = 2 I rms 2 4 2 V irms 9 V O Aeo where N is the number of turns of the coil. As N is defined, it's recommended to check for the saturation of the core (rated N I max in the ferrites databook). If the check results too close to the rated limit, an increase of the lgap (gap size) and a new calculus will be necessary. The wire selection is oriented to limit the copper losses (Pcu = 4/3 I2rms Rcu); due to the high frequency ripple the effective wire resistance is affected by skin and proximity effect. For this reason Litz wire or multi-wire solution is recommended. Finally, the available winding space will be evaluated, and if it isn't sufficient, a bigger core set will be considered. An auxiliary winding, for the operation mode of the controller is necessary because the ZCD pin has to recognize when the voltage across the coil has gone to zero, it is a low cost thin wire coil and the number of turns is the only parameter to be defined; if the coil is used also for the I.C. supply, the voltage ratio defines the number of turns. 6/11 The breakdown voltage is fixed with the same criterias of the Mosfet. L6560/A Controller Biasing Circuitry (pin by pin) Referring to the schematic circuit of practical example shown below. Pin 1(INV) leads to the inv. input of the error amplifier and to the overvoltage protection (OVP). A resistive divider will be connected between the regulated output voltage and INV pin. The typical voltage feedback input threshold is 2.5V and the precise overvoltage alarm level current is 40A. R7 and R8 will be selected as follow : VO R7 = -1 R8 2.5V V OUT R7 = 40 A APPLICATION NOTE Pin 2(COMP) is the output of the error amplifier (and one of the two inputs to the multiplier). A feedback compensation network, placed between this pin and INV(1), reduces the frequency block gain to avoid the attempt of the system to control the output voltage ripple (100 / 120Hz). Typically this compensation is just a capacitor that makes possible to reduce the gain for the low frequency output ripple (to minimize the third harmonic distortion) sustaining an high DC gain. A simple criterion, to define the capacitor value, is to set the bandwidth (BW) from 20 to 30Hz. 1 2 R7 / / R8 C comp 1 C comp 2 R7 / / R8 BW BW = This pin can be used also to disable the IC. For this function see Appendix A. Pin 3 (MULT) is the second multiplier input. It has to be connected, through a resistive divider, to the rectified mains. The feature of the multiplier is described by the relation: V xcs = k ( V comp - 3.5V ) V mult where: VXCS (Mult.out) is the Input ref. to current-sense; k is the multiplier gain; Vcomp is the Comp. output Vmult is the multiplier input. Figure 10: Multiplier characteristics family VCS(pin4) (V) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -1.0 0.0 1.0 2.0 3.0 VMULT(pin3) (V) 4.0 5.0 3.7 3.9 D94IN042 In the application circuit: V mult = V in R10 R9 + R10 V multpk = V irms 2 R10 R9 + R10 The Mult. gain k can vary point to point. Fig.10 diagram shows the typical multiplier characteristics family in variable inputs condition. The output of the multiplier, controls the peak current flowing in the sense resistor, each cicle of operation. Pin 4 (CS) is the input (inv.in) for the current sense comparator, the instantaneous Mosfet current is converted in a proportional voltage signal by an external sense resistor. Comparing this signal with the threshold set by the multiplier output, as the current exceed the set value, the power mosfet will be turned off by the reset signal until next set by the PWM latch. An internal circuit (Zerocurrent comparator) ensures that the PWM latch can't be set until the signal on pin 4 (CS) disappear. The sense resistor (Rs) value is calculated as: Rs where: V xcspk I Rspk Vxcspk cannot exceed 1.6V max. value 2 I Rspk = 2 P i / V irms VCOMP(pin2) (V) 5.7 5.1 4.7 4.3 4.1 Pin 5 (ZCD) is the input to the zero current detector. The ZCD pin has to be connected, through a limiting resistor, to the auxiliary winding of the booster inductor. To perform the ZCD (zero-coil current and voltage) function the chip processes the inductor signal and turns on the external Mosfet as the voltage at the pin crosses the threshold level 2.3V to 1.1V (negative sensitive edge). Pin 6 (GND), this pin is the common reference of the circuitry. Pin 7 (GD), output of the driver, this pin is able to drive an external Mosfet with 400mA (source and sink). Pin 8 (Vcc). Input for the supply voltage, this pin is externally connected to a filter capacitor. The minimum start up supply voltage has to be reached. (It depends on the version, see electrical characteristics on the datasheet). If the supply decreases below VCCoff the device recognizes the undervoltage condition and stops driving the external Mosfet. 7/11 3.6 APPLICATION NOTE PRACTICAL DESIGN EXAMPLE To fix the main concepts, here below the demonstration board design criteria are described and the evaluation results are reported. Demo 1: Target specifications AC mains RMS voltage: DC output regulated voltage: VIrms = 88V to 132V VO = 240V Booster Inductor (T): Inductor design starts defining the inductance value (L), considering the minimum frequency not less than 23kHz. DEMO 1: From the formula showed in the boost design section, the inductance value of about 0.6mH gives a minimum switching frequency of 28kHz. The magnetic core size estimate (Volume 4 K L Irms2(max)) results of 3.5cm3 and so the ETD29 x 16 x 10 (effective volume of 5.4cm3) has been selected. DEMO 2: The inductance value of about 0.8mH gives the minimum switching frequency of 24kHz. The same magnetic core ETD29 x 16 x 10 has been selected. The other coil data are reported in the schematic diagram (figg.11 and 12). To reduce copper losses a multiwire solution (10 x 0.02mm) has been adopted. Measuring the series resistance (RCU) at 25kHz results: 0.56 on DEMO1 and 0.7 on DEMO 2. The maximum copper losses 3 are: PCU = ILrms2 RCU where ILrms = 2/ Irms. Considering a converter efficiency of 95% at the minimum mains voltage, follow: PCU = 1.9 0.56 = 1.06W on DEMO 1, and PCU = 0.68 0.7 = 0.48W. Output Filter capacitor (CO): In this application the output voltage ripple is the parameter considered to select capacitance value. DEMO 1: The capacitance of 150F and rated voltage 385V gives on output voltage ripple VO = 4V. DEMO 2: The capacitance of 47F and rated voltage 450V gives an output voltage ripple VO = 10V. Sense Resistor (R6): The resistance value has been selected looking at the multiplier characteristic diagram (see fig.10), because both the sense resistance and the divider (R9,R10) define the working point of the system. The metallic film resistor are suited for high peak current flowing in this resistor. The schematic circuit of applications of figg.11 and 12, report the values of all parts used. Rated output power: PO = 100W Full load output voltage ripple: VO 10V Maximum output overvoltage: VOUT = 60V Demo 2: Target specifications AC mains RMS voltage: DC output regulated voltage: Rated output power: VIrms = 176V to 264V VO = 400V PO = 120W Full load output voltage ripple: VO 15V Maximum output overvoltage: VOUT = 40V To match the above specifications the material selection, expecially for the most critical components, is an important step. Power Mosfet (MOS): Two parameters are useful to select the best device. The minimum blocking voltage (V(BR)DSS) and the RDSON because of power dissipation. DEMO 1: The selected device is the STP10NA40, because the V(BR)DSS = 400V is enough for the application and the RDSON(25C) = 0.55 (RDSON(75C) = 0.7) causes a ON-STATE power dissipation of: PON = IQrms2 RDSON(75C) = 1.03 0.7 = 740 mW. DEMO 2: The selected device is the STP5NA50, because the V(BR)DSS = 500V is enough for the application and the RDSON(25C) = 1.6 (RDSON(75C) = 2) causes a ON-STATE power dissipation of: PON = IQrms2 RDSON(75C) = 0.29 2 = 585 mW. Booster Diode (D1): Fast recovery diode suitable for rated breakdown voltage are used on demoboards. The plastic axial package BYT03-400 and BYT13-600 has been selected. 8/11 APPLICATION NOTE Figure 11: Typical Application Circuit (100W, 110VAC) D1 BYT03-400 C6 T R7 1.5M 1% C3 330nF + Vo=240V Po=100W R3 68K 5% BRIDGE + 4 x BY255 FUSE 4A/250V Vac (85V to 135V) R10 16K 1% D3 1N4150 D2 1N5248B R2 100 5% 10nF R1 68K 5% 5 2 1 7 4 R4 330 C7 10nF C4 1nF R6 0.33 1W R8 16K 1% D94IN050C C1 1F 250V R9 1.5M 1% 8 L6560 3 C2 22F 25V 6 R5 10 MOS STP10NA40 C5 150F 315V - TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A7) primary 90T of Litz wire 10 x 0.2mm secondary 11T of #27 AWG (0.15mm) gap 1.9mm for a total primary inductance of 0.6mH ORDERING NUMBER: EVAL6560-1 Figure 12: Typical Application Circuit (120W, 220VAC) D1 BYT13-600 C6 T R7 1M 1% C3 1F + Vo=400V Po=120W R3 220K 5% BRIDGE + 4 x BY255 FUSE 4A/250V Vac (175V to 265V) R10 6.2K 1% D3 1N4150 D2 1N5248B R2 100 5% 4.7nF R1 68K 5% 5 2 1 7 4 R4 330 C7 10nF C4 1nF R6 0.4 1W R8 6.34K 1% D94IN049B C1 1F 400V R9 1.8M 1% 8 L6560 3 C2 22F 25V 6 R5 10 MOS STP5NA50 C5 47F 450V - TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8) primary 90T of Litz wire 10 x 0.2mm secondary 7T of #27 AWG (0.15mm) gap 1.25mm for a total primary inductance of 0.8mH ORDERING NUMBER: EVAL6560-2 Figure 13: P.C. Board and component Layout of the Figg. 11 and 12 (1:1 scale) 9/11 APPLICATION NOTE DEMOBOARD EVALUATION RESULTS To evaluate the PFC demoboard performances, the following parameters have been tested: PF(power factor), A_THD(percentage of current AC POWER SOURCE LARCET /3KW PM1200 AC POWER ANALYSER total harmonic distortion), H3..H9(percentage of current nth harmonic amplitude), VO (output voltage ripple), VO (output voltage), (efficiency). Test configuration, equipment and results are shown below:. EMI FILTER PFC L6560 DEMO LOAD D94IN051 DEMO 1: VI [Vrms ] 88 110 132 PI [W] 110.2 108.7 107.9 0.997 0.999 0.999 PF A_THD [%] 2.47 2.37 2.57 H3 [%] 2.04 2.10 2.33 H5 [%] 0.98 0.58 0.48 H7 [%] 0.44 0.40 0.40 H9 [%] 0.19 0.32 0.32 VO [V] 237.4 237.4 237.4 PO [W] 102.5 102.5 102.5 VO [V] 4 4 4 [%] 93.0 94.0 95.0 DEMO 2: VI [Vrms ] 180 220 260 PI [W] 127.3 126.5 126.0 0.995 0.988 0.976 PF A_THD [%] 3.48 6.27 9.56 H3 [%] 2.68 4.70 7.09 H5 [%] 0.95 1.96 2.64 H7 [%] 0.62 1.39 2.42 H9 [%] 0.44 1.17 2.06 VO [V] 398.1 398.1 398.1 PO [W] 122.0 122.0 122.0 VO [V] 10 10 10 [%] 95.8 96.4 96.8 EMI/RFI filter The harmonic content measurement has been done using an EMI/RFI filter interposed between the AC source and the demoboard under test, while the efficiency has been calculated without the filter contribution. The used filter is shown: where: T1 = 1mH T2 = 27mH C1 = 0.22F, 630V C = 2.2nF, 630V Note The PC board has been designed to accept some additional components, not used in this one. For example, The NTC resistor could be placed on on board to avoid in rush current risk. Since, normally, in evaluation stage this risk doesn't arise, the part has been shorted. T1 LINE C1 T2 PFC C EARTH D94IN052 APPENDIX A Disable The PFC controller L6560 allows an easy mode to be disabled. If for some reason, the system using PFC section needs to disable this function, the best way is to force Pin2 (E/A output) to a voltage below 2.5V (see fig A1). That allows also to reduce the supply consumption of the IC during the disable so the startup circuit is able to restart the system once the disable condition is removed. Figure A1. 1 2 I 1mA DISABLE L6560/A D95IN282A 10/11 APPLICATION NOTE Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 11/11 |
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