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| TDA7718N 3 band car audio processor Features Input multiplexer - QD1: quasi-differential stereo inputs - SE1: stereo single-ended input - SE2: stereo single-ended input - SE3: stereo single-ended input - FD1 / SE4+SE5: 1 full-differential input or 2 stereo single-ended inputs Loudness - 2nd order frequency response - Programmable center frequency (400 Hz / 800 Hz / 2400 Hz) - 15 dB with 1 dB steps - Selectable high frequency boost - Selectable flat-mode (constant attenuation) Volume - +23 dB to -31 dB with 1 dB step resolution - Soft-step control with programmable blend times Bass - 2nd order frequency response - Center frequency programmable in 4 steps (60 Hz / 80 Hz / 100 Hz / 200 Hz) - Q programmable 1.0/1.25/1.5/2.0 - DC gain programmable - -15 dB to 15 dB range with 1 dB resolution Middle - 2nd order frequency response - Center frequency programmable in 4 steps (500 Hz / 1 kHz / 1.5 kHz / 2.5 kHz) - Q programmable 0.75/1.0/1.25 - -15 dB to 15 dB range with 1 dB resolution Treble - 2nd order frequency response (10 kHz / 12.5 kHz / 15 kHz / 17.5 kHz) - Center frequency programmable in 4 steps (10 kHz / 12.5 kHz / 15 kHz / 17.5 kHz) - -15 dB to 15 dB with 1 dB resolution TSSOP28 Speaker - 4 independent soft step speaker controls - +15 dB to -79 dB with 1 dB steps - Direct mute Subwoofer - 2nd order low pass filter with programmable cut off frequency (55 Hz / 85 Hz / 120 Hz / 160 Hz) - 2 independent soft step level control, +15 dB to -79 dB with 1 dB steps Mute functions - Direct mute - Digitally controlled SoftMute with 4 programmable mute-times (0.48 ms/0.96 ms/8 ms/16 ms) Offset detection - Offset voltage detection circuit for on-board power amplifier failure diagnosis Description The TDA7718N is a high performance signal processor specifically designed for car radio applications. The device includes a high performance audioprocessor with fully integrated audio filters and new Soft Step architecture. The digital control allows programming in a wide range of filter characteristics. Table 1. Device summary Package TSSOP28 TSSOP28 Packing Tube Tape and reel Order code TDA7718N TDA7718NTR October 2009 Doc ID 16502 Rev 1 1/40 www.st.com 1 Contents TDA7718N Contents 1 2 Block circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 3.2 3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Description of the audioprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Input stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.1 4.1.2 4.1.3 Quasi-differential stereo input (QD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Single-ended stereo input (SE1, SE2, SE3) . . . . . . . . . . . . . . . . . . . . . 13 Full-differential stereo input or single-ended input (FD1/QD2/SE4+SE5) 13 4.2 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 4.2.2 4.2.3 4.2.4 Loudness attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Peak frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 High frequency boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Flat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 4.4 4.5 SoftMute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SoftStep volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5.1 4.5.2 4.5.3 4.5.4 Bass attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 Middle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.1 4.6.2 4.6.3 Middle attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Middle center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7 Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/40 Doc ID 16502 Rev 1 TDA7718N 4.7.1 4.7.2 Contents Treble attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 4.9 4.10 4.11 Subwoofer filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Softstep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC offset detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Audioprocessor testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 5.2 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C bus electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.1 5.2.2 5.2.3 Receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Doc ID 16502 Rev 1 3/40 List of tables TDA7718N List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C bus electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Main selector (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Soft mute / others (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SoftStep I (5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SoftStep II / DC detector (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loudness (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Volume / output gain (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Treble filter (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Middle filter (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Bass filter (11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Subwoofer / middle / bass (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Speaker attenuation (FL/FR/RL/RR/SWL/SWR) (13-18) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Testing audio processor 1 (19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Testing audio processor 2 (20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Testing audio processor 3 (21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/40 Doc ID 16502 Rev 1 TDA7718N List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FD / QD / SE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Loudness attenuation @ fP = 400 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loudness center frequencies @ attn. = 15 dB.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loudness attenuation, fc = 2.4 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SoftMute timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bass control @ fC = 80 Hz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass center frequencies @ gain = 14 dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass quality factors @ gain = 14 dB, fC = 80 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass normal and DC mode @ gain = 14 dB, fC = 80 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Middle control @ fC = 1 kHz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Middle center frequencies @ gain = 14 dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Middle quality factors @ gain = 14 dB, fC = 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble control @ fC = 17.5 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble center frequencies @ gain = 14 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Subwoofer cut frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC offset detection circuit (simplified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C bus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TSSOP28 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Doc ID 16502 Rev 1 5/40 1 FD1L-/QD2G/SE4R FD1R-/QD2G/SE5L FD1R+/QD2R/SE5R DC-Offset Detector DIGITAL CONTROL I2C BUS MAIN INPUT MULTIPLEXER 6/40 Block circuit diagram Figure 1. MUTE MONO FADER VOLUME TREBLE MIDDLE BASS MONO FADER OUTLF OUTRF LOUDNESS SOFT MUTE SE1L MONO FADER MONO FADER OUTLR OUTRR Block circuit diagram Block circuit diagram SE1R SE2L SE2R SE3L SE3R SUBWOOFER MONO FADER MONO FADER OUTSWL OUTSWR Doc ID 16502 Rev 1 SUPPLY VCC GND CREF SCL SDA WIN_IN QD1L QD1G QD1R FD1L+/QD2L/SE4L WIN_TC DC_ERR TDA7718N TDA7718N Pin connection and pin description 2 2.1 Pin connection and pin description Pin connection Figure 2. Pin connection (top view) SE1L SE1R SE2L SE2R SE3L SE3R QD1L QD1G QD1R FD1L+/QD2L/SE4L FD1L-/QD2G/SE4R FD1R-/QD2G/SE5L FD1R+/QD2R/SE5R CREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Winin DCErr SDA SCL VCC MUTE WINTC OUTLF OUTLR OUTRR OUTRF OUTSWL OUTSWR GND 2.2 Table 2. No. 1 2 3 4 5 6 7 8 9 10 Pin description Pin description Pin name SE1L SE1R SE2L SE2R SE3L SE3R QD1L QD1G QD1R FD1L+/QD2L/SE4L Single-end input left Single-end input right Single-end input left Single-end input right Single-end input left Single-end input right quasi-differential stereo inputs left quasi-differential stereo inputs common quasi-differential stereo inputs right Full differential + input left or quasi-differential left or single-end input left Description I/O I I I I I I I I I I Doc ID 16502 Rev 1 7/40 Pin connection and pin description Table 2. No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TDA7718N Pin description (continued) Pin name Description Full differential - input left or quasi-differential ground or single-end input right Full differential - input right or quasi-differential ground or single-end input left I/O I I I O S O O O O O O O I S I I/O O I FD1L-/QD2G/SE4R FD1R-/QD2G/SE5L FD1R+/QD2R/SE5R Full differential + input right or quasi-differential right or single-end input right CREF GND OUTSWR OUTSWL OUTRF OUTRR OUTLR OUTLF WinTC MUTE VCC SCL SDA DC_ERR WIN_IN Reference capacitor Ground Subwoofer right output Subwoofer left output Front right output Rear right output Rear left output Front left output DC offset detector filter output External mute pin Supply I 2C bus clock bus data I2C DC offset detector output DC offset detector input 8/40 Doc ID 16502 Rev 1 TDA7718N Electrical specifications 3 3.1 Electrical specifications Thermal data Table 3. Symbol Rth-j amb Thermal data Description Thermal resistance junction-to-ambient Value 114 Unit C/W 3.2 Absolute maximum ratings Table 4. Symbol VS Vin_max Tamb Tstg Absolute maximum ratings Parameter Operating supply voltage Maximum voltage for signal input pins Operating ambient temperature Storage temperature range Value 10.5 7 -40 to 85 -55 to 150 Unit V V C C 3.3 Table 5. Symbol Supply Vs Is Electrical characteristics VS = 8.5 V; Tamb= 25 C; RL= 10 k; all gains = 0 dB; f = 1 kHz; unless otherwise specified Electrical characteristics Parameter Test condition Min. Typ. Max. Unit Supply voltage Supply current - 7.5 23 8.5 29 10 35 V mA Input selector Rin VCL SIN Input resistance Clipping level Input separation All single ended inputs Input gain = 0 dB 70 2 100 95 130 k VRMS dB Differential stereo inputs Rin CMRR eNo Input resistance Common mode rejection ratio for main source Output noise @ speaker outputs Differential VCM = 1 VRMS @ 1 kHz VCM = 1 VRMS @ 10 kHz 20 Hz - 20 kHz, A-weighted; all stages 0 dB 70 44 44 100 60 60 12 22 k dB dB V Doc ID 16502 Rev 1 9/40 Electrical specifications Table 5. Symbol Loudness control AMAX ASTEP fPeak Max attenuation Step resolution Peak frequency fP1 fP2 fP3 Volume control GMAX AMAX ASTEP EA ET Max gain Max attenuation Step resolution Attenuation set error Tracking error DC steps Adjacent attenuation steps From 0 dB to GMIN 22 0.5 -0.75 -3 -5 23 -31 1 0 0.1 0.5 14 0.5 15 1 400 800 2400 TDA7718N Electrical characteristics (continued) Parameter Test condition Min. Typ. Max. Unit 16 1.5 - dB dB Hz Hz Hz 24 -30 1.5 +0.75 2 3 5 dB dB dB dB dB mV mV VDC Soft mute AMUTE Mute attenuation T1 T2 T3 T4 - 80 0.35 0.7 5.6 12.3 2.5 32 3 100 0.48 0.96 7.6 15.3 45 3.3 0.65 1.3 9.6 18.3 1 58 3.6 dB ms ms ms ms V V k V TD Delay time VTH Low RPU VPU Low threshold for SM pin Internal pull-up resistor Internal pull-up voltage VTH High High threshold for SM pin Bass control fC1 Fc Center frequency fC2 fC3 fC4 Q1 QBASS Quality factor Q2 Q3 Q4 CRANGE Control range ASTEP DCGAIN Step resolution Bass-DC-gain DC = off DC = on, gain = 15 dB 14 0.5 -1 4.3 60 80 100 200 1 1.25 1.5 2 15 1 0 4.7 16 1.5 +1 5.1 Hz Hz Hz Hz dB dB dB dB 10/40 Doc ID 16502 Rev 1 TDA7718N Table 5. Symbol Middle control CRANGE Control range ASTEP Step resolution fC1 fc Center frequency fC2 fC3 fC4 Q1 QMIDDLE Quality factor Treble control CRANGE Clipping level ASTEP Step resolution fC1 fc Center frequency fC2 fC3 fC4 Speaker attenuators GMAX AMAX ASTEP AMUTE EE Max gain Max attenuation Step resolution Mute attenuation Attenuation set error DC steps Adjacent attenuation steps 14 0.5 80 Q2 Q3 Electrical specifications Electrical characteristics (continued) Parameter Test condition Min. Typ. Max. Unit 14 0.5 - 15 1 500 1 1.5 2.5 0.75 1 1.25 16 1.5 - dB dB Hz kHz kHz kHz - 14 0.5 - 15 1 10 12.5 15 17.5 16 1.5 - dB dB kHz kHz kHz kHz 15 -79 1 90 0.1 16 -74 1.5 2 5 dB dB dB dB dB mV VDC Audio outputs VCL ROUT RL CL VDC Clipping level Output impedance Output load resistance Output load capacitor DC voltage level d = 0.3 %; byte8_D6=1 d = 1 %; byte8_D6=0 2 2.2 2 3.8 30 4.0 100 10 4.2 VRMS VRMS k nF V Subwoofer lowpass fLP1 fLP Lowpass corner frequency fLP2 fLP3 fLP4 55 85 120 160 Hz Hz Hz Hz Doc ID 16502 Rev 1 11/40 Electrical specifications Table 5. Symbol TDA7718N Electrical characteristics (continued) Parameter Test condition Min. Typ. Max. Unit DC offset detection circuit V1 Vth Zero comp. window size V2 V3 V4 tsp Max rejected spike length ICHDCErr DCErr charge current IDISDCErr DCErr discharge current VOutH VOutH General BW=20 Hz to 20 kHz AWeighted, all gain = 0 dB BW=20 Hz - 20 kHz AWeighted, Output muted all gain = 0 dB, A-weighted; Vo = 2 VRMS VIN =1 VRMS; all stages 0 dB 98 12 7 104 0.01 90 22 12 0.1 V V dB % dB DCErr high voltage DCErr low voltage 10 30 50 70 2 5 10 15 2 4 3 25 50 75 100 11 22 33 44 5 5 3.3 100 40 70 100 130 30 50 70 90 8 9 3.6 300 mV mV mV mV s s s s A mA V mV eNO Output noise S/N D SC Signal to noise ratio Distortion Channel separation left/right 12/40 Doc ID 16502 Rev 1 TDA7718N Description of the audioprocessor 4 4.1 Description of the audioprocessor Input stages One quasi-differential stereo input, one full-differential stereo input and maximum five single-ended inputs are available. 4.1.1 Quasi-differential stereo input (QD1) The QD input is implemented as a buffered quasi-differential stereo stage with 100 k inputimpedance at each input. There is -3 dB attenuation at QD input stage. 4.1.2 Single-ended stereo input (SE1, SE2, SE3) The input-impedance at each input is 100 k and the attenuation is fixed to -3 dB for incoming signals. 4.1.3 Full-differential stereo input or single-ended input (FD1/QD2/SE4+SE5) This device provides a full-differential stereo input stage (FD1) or 2nd quasi-differential stereo input stage. The full differential is a buffered full-differential stereo stage with 100 k input-impedance at each input. When using as QD2 application, it needs to connect the two QD2G pins together from external and the input impedance at QDG becomes 50 k. This stage can be also configured as 2 single-ended stereo input stages (SE4 and SE5). The configuration is done with the input selector control bits and the selection of FD1 and QD2 is controlled by a separate bit. There is -3 dB attenuation at the input stage. Figure 3 shows the block diagram of this input stage. Doc ID 16502 Rev 1 13/40 Description of the audioprocessor Figure 3. FD / QD / SE block diagram TDA7718N 14/40 Doc ID 16502 Rev 1 TDA7718N Description of the audioprocessor 4.2 Loudness There are four parameters programmable in the loudness stage. 4.2.1 Loudness attenuation Figure 4 shows the attenuation as a function of frequency at fP = 400 Hz. Figure 4. Loudness attenuation @ fP = 400 Hz. 4.2.2 Peak frequency Figure 5 shows the four possible peak-frequencies at 400, 800 and 2400 Hz. Figure 5. Loudness center frequencies @ attn. = 15 dB. Doc ID 16502 Rev 1 15/40 Description of the audioprocessor TDA7718N 4.2.3 High frequency boost Figure 6 shows the different Loudness shapes in low and high frequency boost. Figure 6. Loudness attenuation, fc = 2.4 kHz 4.2.4 Flat mode In flat mode the loudness stage works as a 0 dB to -15 dB attenuator. 16/40 Doc ID 16502 Rev 1 TDA7718N Description of the audioprocessor 4.3 SoftMute The digitally controlled SoftMute stage allows muting/demuting the signal with a I2C bus programmable slope. The mute process can either be activated by the SoftMute pin or by the I2C bus. This slope is realized in a special S-shaped curve to mute slow in the critical regions (see Figure 7). For timing purposes the bit 0 of the I2C bus output register is set to 1 from the start of muting until the end of demuting. Figure 7. SoftMute timing 1 EXT. MUTE +SIGNAL REF -SIGNAL 1 I2C BUS OUT D97AU634 Time Note: Please notice that a started mute-action is always terminated and could not be interrupted by a change of the mute -signal. 4.4 SoftStep volume When the volume-level is changed audible clicks could appear at the output. The root cause of those clicks could either be a DC-offset before the volume-stage or the sudden change of the envelope of the audio signal. With the SoftStep-feature both kinds of clicks could be reduced to a minimum and are no more audible. The blend-time from one step to the next is programmable as 5 ms or 10 ms. The SoftStep control is described in detail in Chapter 4.9. Doc ID 16502 Rev 1 17/40 Description of the audioprocessor TDA7718N 4.5 Bass There are four parameters programmable in the bass stage: 4.5.1 Bass attenuation Figure 8 shows the attenuation as a function of frequency at a center frequency of 80 Hz. Figure 8. Bass control @ fC = 80 Hz, Q = 1 4.5.2 Bass center frequency Figure 9 shows the four possible center frequencies 60, 80, 100 and 200 Hz. Figure 9. Bass center frequencies @ gain = 14 dB, Q = 1 18/40 Doc ID 16502 Rev 1 TDA7718N Description of the audioprocessor 4.5.3 Quality factors Figure 10 shows the four possible quality factors 1, 1.25, 1.5 and 2. Figure 10. Bass quality factors @ gain = 14 dB, fC = 80 Hz 4.5.4 DC mode In this mode the DC-gain is increased by 4.4 dB. In addition the programmed center frequency and quality factor is decreased by 25 % which can be used to reach alternative center frequencies or quality factors. Figure 11. Bass normal and DC mode @ gain = 14 dB, fC = 80 Hz 1. The center frequency, Q and DC-mode can be set fully independently. Doc ID 16502 Rev 1 19/40 Description of the audioprocessor TDA7718N 4.6 Middle There are three parameters programmable in the middle stage: 4.6.1 Middle attenuation Figure 12 shows the attenuation as a function of frequency at a center frequency of 1 kHz. Figure 12. Middle control @ fC = 1 kHz, Q = 1 4.6.2 Middle center frequency Figure 13 shows the four possible center frequencies 500 Hz, 1 kHz, 1.5 kHz and 2.5 kHz. Figure 13. Middle center frequencies @ gain = 14 dB, Q = 1 20/40 Doc ID 16502 Rev 1 TDA7718N Description of the audioprocessor 4.6.3 Quality factors Figure 14 shows the three possible quality factors 0.75, 1 and 1.25. Figure 14. Middle quality factors @ gain = 14 dB, fC = 1 kHz 4.7 Treble There are two parameters programmable in the treble stage: 4.7.1 Treble attenuation Figure 15 shows the attenuation as a function of frequency at a center frequency of 17.5 kHz. Figure 15. Treble control @ fC = 17.5 kHz. Doc ID 16502 Rev 1 21/40 Description of the audioprocessor TDA7718N 4.7.2 Center frequency Figure 16 shows the four possible center frequencies 10 k, 12.5 k, 15 k and 17.5 kHz. Figure 16. Treble center frequencies @ gain = 14 dB 4.8 Subwoofer filter The subwoofer lowpass filter has Butterworth characteristics with programmable cut-off frequency (55 Hz / 85 Hz / 120 Hz / 160 Hz). The output phase can be selected between 0 deg and 180 deg. The input of subwoofer takes signal from bass filter output or output of input mux. Figure 17. Subwoofer cut frequencies 22/40 Doc ID 16502 Rev 1 TDA7718N Description of the audioprocessor 4.9 Softstep control In this device, the softstep function is available for volume, speaker, loudness, treble, middle and bass block. With softstep function, the audible noise of DC offset or the sudden change of signal can be avoided when adjusting gain setting of the block. For each block, the softstep function is controlled by softstep on/off control bit in the control table. The softstep transient time selection (5 ms or 10 ms) is common for all blocks and it is controlled by softstep time control bit. The softstep operation of all blocks has a common centralized control. In this case, a new softstep operation can not be started before the completion previous softstep. There are two different modes to activate the softstep operation. The softstep operation can be started right after I2C data sending, or the softstep can be activated in parallel after data sending of several different blocks. The two modes are controlled by the `act bit' (it is normally bit7 of the byte.) of each byte. When act bit is `0', which means action, the softstep is activated right after the date byte is sent. When the act bit is `1', which means wait, the block goes to wait for softstep status. In this case, the block will wait for some other block to activate the operation. The softstep operation of all blocks in wait status will be done together with the block which activate the softstep. With this mode, all specific blocks can do the softstep in parallel. This avoids waiting when the softstep is operated one by one. Chip Addr Sub Addr 0xxxxxxx | Softstep start here Chip Addr Sub Addr 1xxxxxxx 1xxxxxxx ...... 0xxxxxxx | Softstep start here for all 4.10 DC offset detector Using the DC offset detection circuit (Figure 18) an offset voltage difference between the audio power amplifier and the APR's Front and Rear outputs can be detected, preventing serious damage to the loudspeakers. The circuit compares whether the signal crosses the zero level inside the audio power at the same time as in the speaker cell. The output of the zero-window-comparator of the power amplifier must be connected with the WinIn-input of the APR. The WinIn-input has an internal pull-up resistor connected to 5.5 V. It is recommended to drive this pin with open-collector outputs only. To compensate for errors at low frequencies the WinTC-pin are implemented, with external capacitors introducing the same delay = 7.5 k * Cext as the AC-coupling between the APR and the power amplifier introduces. For the zero window comparators, the time constant for spike rejection as well as the threshold are programmable. For electrical characteristics see Chapter 3 on page 9. A low-active DC-offset error signal appears at the DCErr output if the next conditions are both true: a) b) Front and rear outputs are inside zero crossing windows. The Input voltage VWinIn is logic low whenever at least one output of the power amplifier is outside the zero crossing windows. Doc ID 16502 Rev 1 23/40 Description of the audioprocessor TDA7718N After power-on, the external attached capacitor is rapidly charged (fast-charge) to overcome a false indication. Figure 18. DC offset detection circuit (simplified) 24/40 Doc ID 16502 Rev 1 TDA7718N Description of the audioprocessor 4.11 Audioprocessor testing In the test mode, which can be activated by setting bit D7 of the I2C subaddress byte and bit D0 of the testing audioprocessor byte, several internal signals are available at the SE1L pin. In this mode, the input resistance of 100 k is disconnected from the pin. Internal signals available for testing are listed in the data-byte specification. Figure 19. Test circuit 100nF SE1L 100nF SE1L SE1R 100nF WnIn DCErr SDA SCL VCC 100nF 10uF SE1R SE2L 100nF SE2L SE2R 100nF SE2R SE3L 100nF SE3L SE3R 100nF SE3R QD1L 22u MUTE QD1L QD1G 100nF TSSOP28 WINTC 4.7u QD1G QD1R 4.7u OUTLF 4.7u OUTLF OUTLR 4.7u QD1R FD1L+/QD2L/SE4L 4.7u OUTLR OUTRR 4.7u FD1L+/QD2L/SE4L FD1L-/QD2G/SE4R 4.7u OUTRR OUTRF 4.7u FD1L-/QD2G/SE4R FD1R-/QD2G/SE5L 4.7u OUTRF OUTSWL 4.7u FD1R-/QD2G/SE5L FD1R+/QD2R/SE5R OUTSWL OUTSWR FD1R+/QD2R/SE5R CREF 10uF OUTSWR GND Doc ID 16502 Rev 1 25/40 I2C bus specification TDA7718N 5 5.1 I2C bus specification Interface protocol The interface protocol comprises: a start condition (S) a chip address byte (the LSB determines read/write transmission) a subaddress byte a sequence of data (N-bytes + acknowledge) a stop condition (P) the max. clock speed is 400 kbit/s 3.3 V logic compatible Figure 20. I2C bus interface protocol 1. S = Start 2. ACK = Acknowledge 5.2 I2C bus electrical characteristics Table 6. Symbol fSCL VIH VIL tHD,STA tSU,STO tLOW tHIGH tF tR tHD,DAT tSU,DAT I2C bus electrical characteristics Parameter SCL clock frequency High level input voltage Low level input voltage Hold time for START Setup time for STOP Low period for SCL clock High period for SCL clock Fall time for SCL/SDA Rise time for SCL/SDA Data hold time Data setup time Min 2.4 0.6 0.6 1.3 0.6 0 100 Max 400 0.8 300 300 Unit kHz V V s s s s ns ns ns ns 26/40 Doc ID 16502 Rev 1 TDA7718N Figure 21. I2C bus data I2C bus specification 5.2.1 S 10 Receive mode 0010 0 R/W ACK TS X AI A4 A3 A2 A1 A0 ACK DATA ACK P S = Start R/W = "0" -> Receive Mode (Chip can be programmed by P) "1" -> Transmission Mode (Data could be received by P) ACK = Acknowledge P = Stop TS = Testing mode AI = Auto increment 5.2.2 S 1 0 Transmission mode 0 0 1 0 0 R/W ACK X X X X X X BZ SM ACK P SM = Soft mute activated for main channel BZ = Softstep Busy (`0' = Busy) X = Not used The transmitted data is automatic updated after each ACK. Transmission can be repeated without new chip address. 5.2.3 Reset condition A Power-On-Reset is invoked if the supply voltage is below than 3.5 V. After that the registers are initialized to the default data written in following tables. Doc ID 16502 Rev 1 27/40 I2C bus specification Table 7. MSB I2 I1 I0 A4 A3 A2 A1 TDA7718N Subaddress (receive mode) LSB Function A0 Testing mode Off On Not used Auto increment mode Off On Main selector Not used Not used Not used Soft mute / others Soft step I Soft step II / DC-detector Loudness Volume / output gain Treble Middle Bass Subwoofer / middle / bass Speaker attenuator left front Speaker attenuator right front Speaker attenuator left rear Speaker attenuator right rear Subwoofer attenuator left Subwoofer attenuator right Testing audio processor 1 Testing audio processor 2 Testing audio processor 3 0 1 - x - 0 1 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 28/40 Doc ID 16502 Rev 1 TDA7718N I2C bus specification 5.3 Table 8. MSB D7 Data byte specification Main selector (0) LSB Function D6 D5 D4 D3 D2 D1 D0 Main source selector SE1 SE3 QD1 QD2 / FD1 SE2 SE4 SE5 Mute FD / QD2 selection FD QD2 Main source input gain select 0 dB 3 dB Subwoofer flat Off On Not used - - - - - 0 0 0 0 1 1 1 1 - 0 0 1 1 0 0 1 1 - 0 1 0 1 0 1 0 1 - - - - - 0 1 - - - - 0 1 - - - - x x 0 1 - - - - - Not used (1-3) Doc ID 16502 Rev 1 29/40 I2C bus specification Table 9. MSB D7 D6 D5 D4 D3 D2 D1 TDA7718N Soft mute / others (4) LSB Function D0 Soft mute On Off Pin influence for mute Pin and IIC IIC Soft mute time 0.48 ms 0.96 ms 7.68 ms 15.36 ms Subwoofer input source Input mux Bass output Subwoofer enable (OUTSWL & OUTSWR) On Off Fast charge On Off Anti-alias filter On Off (bypass) - - - - - - - 0 1 - - - - - - - 0 1 - - - - 0 0 1 1 - 0 1 0 1 - - - - - - 0 1 - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - 30/40 Doc ID 16502 Rev 1 TDA7718N Table 10. MSB D7 D6 D5 D4 D3 D2 D1 I2C bus specification SoftStep I (5) LSB Function D0 Loudness soft step On Off Volume soft step On Off Treble soft step On Off Middle soft step On Off Bass soft step On Off Speaker LF soft step On Off Speaker RF soft step On Off Speaker LR soft step On Off - - - - - - - 0 1 - - - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - Doc ID 16502 Rev 1 31/40 I2C bus specification Table 11. MSB D7 D6 D5 D4 D3 D2 D1 TDA7718N SoftStep II / DC detector (6) LSB Function D0 Speaker RR soft step On Off Subwoofer left soft step On Off Subwoofer right soft step On Off Soft step time 5 ms 10 ms Zero-comparator window size 100 mV 75 mV 50 mV 25 mV Spike rejection time constant 11 s 22 s 33 s 44 s - - - - - - - 0 1 - - - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - 0 0 1 1 0 1 0 1 - - - - 0 0 1 1 0 1 0 1 - - - - - - 32/40 Doc ID 16502 Rev 1 TDA7718N Table 12. MSB D7 D6 D5 D4 D3 0 0 : 1 1 D2 0 0 : 1 1 D1 0 0 : 1 1 I2C bus specification Loudness (7) LSB Function D0 0 1 : 0 1 Attenuation 0 dB -1 dB : -14 dB -15 dB Center frequency Flat 400 Hz 800 Hz 2400 Hz High boost On Off Soft step action Act Wait - - - - - - 0 0 1 1 - 0 1 0 1 - - - - - - 0 1 - - - - - 0 1 - - - - - - Table 13. MSB D7 Volume / output gain (8) LSB Function D6 D5 0 0 : 0 0 : 0 0 : 0 1 : 1 : 1 D4 0 0 : 0 1 : 1 1 : 1 0 : 0 : 1 D3 0 0 : 1 0 : 0 1 : 1 0 : 1 : 1 D2 0 0 : 1 0 : 1 0 : 1 0 : 1 : 1 D1 0 0 : 1 0 : 1 0 : 1 0 : 1 : 1 D0 0 1 : 1 0 : 1 0 : 1 0 : 1 : 1 Gain/attenuation +0 dB +1 dB : +15 dB +16 dB : +23 dB Not used : Not used -0 dB : -15 dB : -31 dB Output gain 1 dB 0 dB Soft step action Act Wait - - - 0 1 - 0 1 - - - - - - Doc ID 16502 Rev 1 33/40 I2C bus specification Table 14. MSB D7 D6 D5 D4 0 0 : 0 0 1 1 : 1 1 D3 0 0 : 1 1 1 1 : 0 0 D2 0 0 : 1 1 1 1 : 0 0 D1 0 0 : 1 1 1 1 : 0 0 TDA7718N Treble filter (9) LSB Function D0 0 1 : 0 1 1 0 : 1 0 Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB Treble center frequency 10.0 kHz 12.5 kHz 15.0 kHz 17.5 kHz Soft step action Act Wait - - - - 0 0 1 1 - 0 1 0 1 - - - - - - 0 1 - - - - - Table 15. MSB D7 Middle filter (10) LSB Function D6 D5 D4 D3 D2 D1 D0 Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB Middle Q factor 0.75 1 1.25 Reserved Soft step action Act Wait - - - 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 - 0 0 1 1 - 0 1 0 1 - - - - - - 0 1 - - - - - 34/40 Doc ID 16502 Rev 1 TDA7718N Table 16. MSB D7 D6 D5 D4 0 0 : 0 0 1 1 : 1 1 D3 0 0 : 1 1 1 1 : 0 0 D2 0 0 : 1 1 1 1 : 0 0 D1 0 0 : 1 1 1 1 : 0 0 I2C bus specification Bass filter (11) LSB Function D0 0 1 : 0 1 1 0 : 1 0 Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB Bass Q factor 1.0 1.25 1.5 2.0 Soft step action Act Wait - - - - 0 0 1 1 - 0 1 0 1 - - - - - - 0 1 - - - - - Table 17. MSB D7 Subwoofer / middle / bass (12) LSB Function D6 D5 D4 D3 D2 D1 0 0 1 1 D0 0 1 0 1 Subwoofer cut-off frequency 55 Hz 85 Hz 120 Hz 160 Hz Subwoofer output phase 180 deg 0 deg Middle center frequency 500 Hz 1000 Hz 1500 Hz 2500 Hz Bass center frequency 60 Hz 80 Hz 100 Hz 200 Hz Bass DC mode On Off - - - - - - - - - - - 0 1 - - - 0 0 1 1 0 1 0 1 - - - - 0 0 1 1 - 0 1 0 1 - - - - - - 0 1 - - - - - Doc ID 16502 Rev 1 35/40 I2C bus specification Table 18. MSB D7 D6 0 0 : 0 0 0 : 1 1 1 D5 0 0 : 0 0 0 : 0 0 1 D4 0 0 : 0 1 1 : 1 1 x D3 0 0 : 1 0 0 : 1 1 x D2 0 0 : 1 0 0 : 1 1 x D1 0 0 : 1 0 0 : 1 1 x - TDA7718N Speaker attenuation (FL/FR/RL/RR/SWL/SWR) (13-18) LSB Function D0 0 1 : 1 0 1 : 0 1 x Gain/attenuation 0 dB 1 dB : +15 dB -0 dB -1 dB : -78 dB -79 dB mute Soft step action Act Wait - 0 1 Table 19. MSB D7 - Testing audio processor 1 (19) LSB Function D6 D5 D4 D3 D2 D1 D0 0 1 Audio processor testing mode Off On Test multiplexer at SE1L (1) SSCLK REQ SMCLK DCDet Vth High DCDet Vth Low IntZeroErr Ref5V5 VGB1.95 Clock200k SDCLK VrefDCO Clock fast mode (2) On Off Clock source (2) External Internal (200 kHz) Attenuator gain clock control (2) On Off - - - 0 0 0 0 0 0 0 0 1 1 1 - 0 0 0 0 1 1 1 1 0 0 0 - 0 0 1 1 0 0 1 1 0 0 1 - 0 1 0 1 0 1 0 1 0 1 0 - - - - 0 1 - - - 0 1 - - - - - - 0 1 1. - - - - - - The control bit needs both I2C test mode on & sub-address test mode on. 2. The control bit does not depend on test mode. 36/40 Doc ID 16502 Rev 1 TDA7718N Table 20. MSB D7 D6 D5 D4 D3 D2 D1 - I2C bus specification Testing audio processor 2 (20) LSB Function D0 0 1 Test architecture (1) Normal Split Oscillator clock (2) 400 kHz 800 kHz Softstep curve (2) S-Curve Linear curve Manual set busy signal (1) Auto Auto 0 1 Request for clk generator (1) Allow Allow Stopped Stopped No DCO spike rejection(1) On Off Not used - - - - - - 0 1 - - - - - - 0 1 - - - - 0 0 1 1 0 0 1 1 - 0 1 0 1 0 1 0 1 - - - - - - - - - - x x 0 1 - - - - 1. The control bit needs sub-address test mode on. 2. The control bit does not depend on test mode. Table 21. MSB D7 - Testing audio processor 3 (21) LSB Function D6 D5 D4 D3 D2 D1 D0 0 1 Enable clock for FL/FR/RL/RR/SWL/SWR On Off Enable clock for volume On Off Enable clock for treble and bass On Off Enable clock for loudness and middle On Off Not used - - - - - - 0 1 - - - - - - 0 1 - - x x x x 0 1 - - - Doc ID 16502 Rev 1 37/40 Package information TDA7718N 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 22. TSSOP28 mechanical data and package dimensions mm DIM. MIN. A A1 A2 b c D1 E E11 e L L1 k aaa 0.450 0.050 0.800 0.190 0.090 9.600 6.200 4.300 9.700 6.400 4.400 0.650 0.600 1.000 0.750 0.018 1.000 TYP. MAX. 1.200 0.150 1.050 0.300 0.200 9.800 6.600 4.500 0.002 0.031 0.007 0.004 0.378 0.244 0.170 0.382 0.252 0.173 0.026 0.024 0.039 0.030 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.008 0.386 0.260 0.177 inch OUTLINE AND MECHANICAL DATA 0 (min.), 8 (max.) 0.100 0.004 TSSOP28 Thin Shrink Small Outline Package JEDEC MO-153-AC Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. 0128292 B 38/40 Doc ID 16502 Rev 1 TDA7718N Revision history 7 Revision history Table 22. Date 21-Oct-2009 Document revision history Revision 1 Initial release. Changes Doc ID 16502 Rev 1 39/40 TDA7718N Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 40/40 Doc ID 16502 Rev 1 |
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