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| S1D13743 Mobile Graphics Engine Hardware Functional Specification Document Number: X70A-A-001-02 Status: Revision 2.7 Issue Date: 2010/05/18 (c) SEIKO EPSON CORPORATION 2004 - 2010. All Rights Reserved. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . 2.1 Integrated Frame Buffer 2.2 CPU Interface . . . . 2.3 Input Data Formats . . 2.4 Display Support . . . . 2.5 Display Modes . . . . 2.6 Display Features . . . 2.7 Clock Source . . . . . 2.8 Miscellaneous . . . . . . . . . . . . . .. . . . . . . . . .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 .8 .8 .8 .8 .8 .9 .9 .9 2 3 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pins . . . . . . . . . . . . . . . . . 4.1 Pinout Diagrams . . . . . . . 4.2 Pin Descriptions . . . . . . . 4.2.1 Intel 80 Host Interface . . . . 4.2.2 LCD Interface . . . . . . . . 4.2.3 Clocks . . . . . . . . . . . . 4.2.4 Miscellaneous . . . . . . . . 4.2.5 Power And Ground . . . . . 4.3 Summary of Configuration Options . . . . . . . . . ... .. .. ... ... ... ... ... .. .... .... .... ..... ..... ..... ..... ..... .... ... .. .. ... ... ... ... ... .. . . . . . . . . . ...... ..... ..... ....... ....... ....... ....... ....... ..... . . . . . . . . . ....... ...... ...... ........ ........ ........ ........ ........ ...... 11 11 13 14 15 15 16 17 18 5 Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 Intel 80 Data Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 LCD Interface Data Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 20 D.C. Characteristics . . . . . . . . . 6.1 Absolute Maximum Ratings . . . . 6.2 Recommended Operating Conditions 6.3 Electrical Characteristics . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . 21 21 21 22 24 24 24 25 27 28 28 6 7 A.C. Characteristics . . . . . . . . . . . . 7.1 Clock Timing . . . . . . . . . . . 7.1.1 Input Clocks . . . . . . . . . . . . . 7.1.2 PLL Clock . . . . . . . . . . . . . . 7.2 RESET# Timing . . . . . . . . . . 7.3 Host interface Timing . . . . . . . . 7.3.1 Intel 80 Interface Timing - 1.8 Volt . .... .... ..... ..... .... .... ..... ... .. ... ... .. .. ... ...... ..... ....... ....... ..... ..... ....... ....... ...... ........ ........ ...... ...... ........ Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 4 Epson Research and Development Vancouver Design Center 7.3.2 Intel 80 Interface Timing - 3.3 Volt . . . . . . . 7.3.3 Definition of Transition Time to Hi-Z State . . . 7.4 Display Interface . . . . . . . . . . . . . . . 7.4.1 TFT Power-On Sequence . . . . . . . . . . . . 7.4.2 TFT Power-Off Sequence . . . . . . . . . . . . 7.4.3 Generic 18/24-Bit TFT Panel Timing . . . . . . 8 9 . . . . . . ... ... .. ... ... ... . . . . . . ... ... .. ... ... ... . . . . . . ... ... .. ... ... ... . . . . . . ... ... .. ... ... ... . . . . . . . . 30 . . 32 . .33 . . 34 . . 35 . . 36 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Clocks . . . . . . . . . . . . . 9.1 Clock Descriptions . . . . 9.2 PLL Block Diagram . . . 9.3 Clocks versus Functions . . 9.4 Setting SYSCLK and PCLK . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . ... .. .. .. .. ... .. .. .. ... ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . .40 .40 .41 .42 .43 10 Registers . . . . . . . . . . . . . . . . . 10.1 Register Mapping . . . . . . . . . 10.2 Register Set . . . . . . . . . . . . 10.3 Register Descriptions . . . . . . . . 10.3.1 Read-Only Configuration Registers 10.3.2 Clock Configuration Registers . . 10.3.3 Panel Configuration Registers . . . 10.3.4 Input Mode Register . . . . . . . . 10.3.5 Display Mode Registers . . . . . . 10.3.6 Window Settings . . . . . . . . . . 10.3.7 Memory Access . . . . . . . . . . 10.3.8 Gamma Correction Registers . . . 10.3.9 Miscellaneous Registers . . . . . . 10.3.10 General Purpose IO Pins Registers ... .. .. .. ... ... ... ... ... ... ... ... ... ... .... .... .... .... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ...... ..... ..... ..... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... . . . . . .44 . . . . .44 . . . . .45 . . . . .46 . . . . . . 46 . . . . . . 47 . . . . . . 52 . . . . . . 55 . . . . . . 59 . . . . . . 63 . . . . . . 65 . . . . . . 67 . . . . . . 69 . . . . . . 71 11 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12 RGB Input Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 13 Intel 80, 8-bit Interface Color Formats . . . . . . . 13.1 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors 13.2 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 13.3 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors . . . . . ... .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. ... .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. ... .. .. .. .. .. . . . . . . . . . . .75 .75 .76 .77 .78 .78 .79 .80 .81 .82 14 Intel 80, 16-bit Interface Color Formats . . . . . . . . . . . 14.1 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors . . . . . . 14.2 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 14.3 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 14.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors 14.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 5 15 YUV Timing . . . . . . . . . . . . . . . . . . . . . . . 15.1 YUV 4:2:2 with Intel 80, 8-bit Interface . . . . . . 15.2 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface . . 15.3 YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface . 15.4 YUV 4:2:2 with Intel 80, 16-bit Interface . . . . . . 15.5 YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface . 15.6 YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. . . . . . . . . . . . . . . . 83 . 84 . 84 . 85 . 86 . 87 . 88 16 Gamma Correction Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . 89 16.1 Gamma Correction Programming Example . . . . . . . . . . . . . . . . . . . 90 17 Display Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18 SwivelViewTM . . . . . . . . . . . . 18.1 Concept . . . . . . . . . . . 18.2 90 SwivelView . . . . . . . 18.2.1 Register Programming . . . 18.3 180 SwivelView . . . . . . . 18.3.1 Register Programming . . . 18.4 270 SwivelView . . . . . . . 18.4.1 Register Programming . . . . . . . . . . . ... .. .. ... .. ... .. ... .... .... .... ..... .... ..... .... ..... ... .. .. ... .. ... .. ... . . . . . . . . ...... ..... ..... ....... ..... ....... ..... ....... ...... ..... ....... ....... ....... ....... ....... ....... . . . . . . . . . . . . . . . . ....... ...... ...... ........ ...... ........ ...... ........ 95 95 96 96 97 97 98 98 19 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . 19.1 Using the Intel 80 Interface . . . . . . . . . . . . . 19.1.1 Register Write Procedure . . . . . . . . . . . . . . . 19.1.2 Register Read Procedure . . . . . . . . . . . . . . . 19.1.3 New Window Aperture Write Procedure . . . . . . . 19.1.4 Opening Multiple Windows . . . . . . . . . . . . . . 19.1.5 Update Window using existing Window Coordinates 19.1.6 Individual Memory Location Reads . . . . . . . . . . . . . . . . . 99 . . . . . . 99 . . . . . . . . 100 . . . . . . . . 101 . . . . . . . . 102 . . . . . . . . 104 . . . . . . . . 104 . . . . . . . . 104 20 Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 20.1 Double Buffer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 105 20.2 Double Buffering Limitations . . . . . . . . . . . . . . . . . . . . . . . . 107 21 Interfacing the S1D13743 and a TFT Panel . . . . . . . 21.1 Overview . . . . . . . . . . . . . . . . . . . 21.1.1 Electrical Interface . . . . . . . . . . . . . . . . . 21.1.2 S1D13743 Register Settings for 352x416 TFT Panel 21.2 Host Bus Timing . . . . . . . . . . . . . . . . 21.2.1 Host Bus Timing for 352x416 TFT Panel . . . . . . 21.3 Panel Timing . . . . . . . . . . . . . . . . . . 21.3.1 Panel Timing for 352x416 Panel . . . . . . . . . . 21.4 Example Play.exe Scripts . . . . . . . . . . . . . . . . . . . . . . ...... ..... ....... ....... ..... ....... ..... ....... ..... . . . . . . . . . . . . . . . . 108 . . . . . . 108 . . . . . . . . 108 . . . . . . . . 109 . . . . . . 111 . . . . . . . . 112 . . . . . . 113 . . . . . . . . 114 . . . . . . 114 Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 6 Epson Research and Development Vancouver Design Center 22 PLL Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 120 22.1 Guidelines for PLL Power Layout . . . . . . . . . . . . . . . . . . . . . . 120 23 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 24 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 25 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 25.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 7 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13743 Embedded Memory LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com. 1.2 Overview Description The S1D13743 is a color mobile graphics engine with an embedded 464K byte display buffer. The S1D13743 supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into 24 bpp display memory allowing for fast screen updates. Products requiring a rotated display image can take advantage of the SwivelViewTM feature which provides hardware rotation of the display memory transparent to the software application. Resolutions supported include 352x440 @ 24 bpp single buffered or 320x240 @ 24 bpp double-buffered. The S1D13743 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 8 Epson Research and Development Vancouver Design Center 2 Features 2.1 Integrated Frame Buffer * Embedded 464K byte SRAM display buffer 2.2 CPU Interface * 8/16-bit Intel 80 interface (used for display or register data) * Chip select is used to select device. When inactive, any input data/command is ignored. 2.3 Input Data Formats * RGB: 8:8:8, 6:6:6, 5:6:5 Note All input data is converted and stored as RGB 8:8:8 (see Section 12, "RGB Input Data Conversion" on page 74 for further information) * YUV: 4:2:2, 4:2:0 (Internal YUV to RGB Converter converts and stores data as 24 bpp) 2.4 Display Support * Active Matrix TFT interface * 18/24-bit interface * Frame Rate Modulation using 24 bpp data when configured for an 18-bit LCD panel. 2.5 Display Modes * 24 bit-per-pixel (bpp) color depth Note All data is stored as 24 bpp. 18-bit panels are supported using the 18 msb's when FRM is disabled or all 24 bits when FRM is enabled. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 9 2.6 Display Features * All display writes are handled by window apertures/position for complete or partial display updates. All window coordinates are referenced from the top left corner of the displayed image. Even for a rotated display, the top-left corner is maintained and no translation needs to take place. * SwivelViewTM: 90, 180, 270 counter-clockwise hardware rotation of the display image. All displayed windows can have independent rotation. No additional programming necessary when enabling these modes. * Double-Buffering is available to prevent image tearing during streaming input. To be supported, resolutions must fit within 228K bytes (1/2 of the available display buffer). A typical resolution is 320x240 @ 24 bpp. * Pixel Doubling uses horizontal and vertical averaging to achieve smooth doubling of a single window. Pixel doubling may be applied to only a single window at any one time. * Pixel Halving: no limitation on number of windows. 2.7 Clock Source * Internal programmable PLL * Single MHz clock input: CLKI * CLKI is available as CLKOUT (separate CLKOUTEN pin associated with output) * output state = 0 when disabled 2.8 Miscellaneous * Hardware / Software Power Save mode * Input pin to enable/disable Power Save Mode * General Purpose Input/Output pins are available (GPIO[7:0]) * INT pin is associated with selectable GPIO inputs * Package: S1D13743B00C S1D13743F00A FCBGA8 121-pin package QFP20 144-pin package Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 10 Epson Research and Development Vancouver Design Center 3 Block Diagram MClk Data Control Intel 80 8/16 IF MClk YUV Converter MClk YUV to RGB MClk Rotation (Pixel Halving) Registers RegWrClk MClk Clocks Test Mux Double Buffer Controller PClk LCD Ctc MClk PClk PClk FRM LCD IF MClk Memory Controller PClk Gamma Correction LCD Disp Pipe Figure 3-1: Block Diagram S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 11 4 Pins 4.1 Pinout Diagrams A NC NC CLKOUT CLKI MD3 MD4 MD5 MD6 MD7 NC NC B NC MD2 MD12 CLKOUTEN MD13 MD14 MD15 MD8 MD9 MD10 NC C MD0 MD11 MD1 IOVDD VSS VSS CS# WE# RD# D/C# DE D RESET# TE GPIO_INT PLLVDD VCP PLLVSS COREVDD IOVDD HS VS PCLK E TEST1 TEST2 TESTEN COREVDD VSS VSS VSS PIOVDD NC NC NC F TEST0 SCANEN CNF0 VSS VSS VSS VSS NC NC NC NC G GPIO0 GPIO1 CNF1 PIOVDD VSS VSS COREVDD NC NC NC NC H GPIO2 GPIO3 CNF2 IOVDD PIOVDD COREVDD PIOVDD NC NC VD23 VD22 J GPIO4 GPIO5 PWRSVE VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 K NC GPIO6 GPIO7 VD13 VD12 VD11 VD10 VD9 VD8 VD7 NC L NC NC VD6 VD5 VD4 VD3 VD2 VD1 VD0 NC NC 1 2 3 4 5 6 7 8 9 10 11 Figure 4-1: S1D13743 FCBGA Pinout (Top View) Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 12 Epson Research and Development Vancouver Design Center MD1 MD2 MD0 IOVDD VSS MD11 MD12 GPIO_INT IOVDD VSS TE RESET# VSS COREVDD TESTEN TEST0 VSS IOVDD TEST1 TEST2 NC SCANEN VSS IOVDD GPIO0 GPIO1 GPIO2 GPIO3 VSS IOVDD CNF0 CNF1 CNF2 VSS COREVDD NC 108 109 NC CLKOUT NC CLKOUTEN VSS COREVDD CLKI VSS NC NC IOVDD PLLVDD VCP PLLVSS NC MD13 MD3 MD14 MD4 IOVDD VSS CS# MD15 MD5 COREVDD VSS MD6 MD8 WE# MD7 IOVDD VSS MD9 RD# MD10 D/C# 108 107 106 105 104 103 102 101 100 99 73 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 72 GPIO4 GPIO5 PWRSVE VSS IOVDD GPIO6 GPIO7 VSS COREVDD VD6 VD5 VD13 VD21 VSS PIOVDD VD4 VD12 VD20 VD3 VSS COREVDD VD11 VD19 VD2 VD10 VSS PIOVDD VD18 VD9 VD1 VSS COREVDD VD17 VD0 VD8 NC 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 INDEX 144 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 36 S1D13743 X70A-A-001-02 Revision 2.7 PIOVDD VSS DE HS VS COREVDD VSS PCLK PIOVDD VSS NC VD23 VD22 VD15 VD14 NC NC PIOVDD VSS VD16 VD7 NC NC NC NC COREVDD VSS PIOVDD NC NC NC NC NC NC NC NC Figure 4-2: S1D13743 QFP20 Pinout (Top View) Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 13 4.2 Pin Descriptions Key: Pin Types I O IO P = = = = Input Output Bi-Directional (Input/Output) Power pin RESET# / Power Save Status H = High level output L = Low level output Hi-Z = High Impedance Table 4-3 Cell Description Item HI HIS HID HO HB HBD HB_DSEL LIDS LITR 1 2 Description H System LVCMOS3 Input Buffer H System LVCMOS Schmitt Input Buffer H System LVCMOS Input Buffer with pull-down resistor H System LVCOMOS Output buffer H System LVCMOS Bidirectional Buffer H System LVCMOS Bidirectional Buffer with pull-down resistor H System LVCMOS Bidirectional Buffer with Drive Selector L System2 LVCMOS Schmitt Input Buffer with pull-down resistor L System Transparent Input Buffer 1 H System is IOVDD and PIOVDD (see Section 6, "D.C. Characteristics" on page 21). L System is COREVDD (see Section 6, "D.C. Characteristics" on page 21). 3 LVCMOS is Low Voltage CMOS (see Section 6, "D.C. Characteristics" on page 21). Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 14 Epson Research and Development Vancouver Design Center 4.2.1 Intel 80 Host Interface Table 4-1: Host Interface Pin Descriptions Pin Name Type FCBGA Pin # QFP Pin # 131,126, 124,102, 103,143, 141,136, 138,135, 132,127, 125,107, 108,106 137 142 130 144 Cell IO Voltage RESET# State Power Save Status Description MD[15:0] IO B7, B6, B5, B3, C2, B10, B9, B8, A9, A8, A7, A6, A5, B2, C3, C1 C8 C9 C7 C10 Intel 80 Host Data lines 15-0. HB IOVDD Hi-Z Hi-Z Note: The Host Data Lines can be swapped (i.e. D15 = D0) using the CNF0 pin. For details, see Section 4.3, "Summary of Configuration Options" on page 18. This input pin is the Write Enable signal. This input pin is the Read Enable signal. This input pin is the Chip Select signal. This input pin selects between Intel 80 address and data. Tearing Effect: this pin will reflect the VSYNC, HSYNC or the OR'd combination status of the display. This interrupt pin is associated with selected GPIO pins when configured as inputs or outputs. See Section 10.3.10, "General Purpose IO Pins Registers" on page 71 for operational description. This active low input sets all internal registers to the default state and forces all signals to their inactive states. WE# RD# CS# D/C# I I I I HI HI HI HI IOVDD IOVDD IOVDD IOVDD Input Input Input Input Input Input Input Input TE O D2 98 HO IOVDD L L GPIO_INT O D3 101 HO IOVDD L L RESET# I D1 97 HIS IOVDD Input Input S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 15 4.2.2 LCD Interface Table 4-2: LCD Interface Pin Descriptions Pin Name Type FCBGA Pin # H10, H11, J4, J5, J6, J7, J8, J9, J10, J11, K4, K5, K6, K7, K8, K9, K10, L3, L4, L5, L6, L7, L8, L9 D10 D9 D11 C11 QFP Pin # 12,13,60, 55,50,45, 40,20,14, 15,61,56, 51,48,44, 38,21,63, 62,57,54, 49,43,39 5 4 8 3 Cell IO Voltage RESET# State Power Save Status Description Panel Data lines pins 23-0. Note: The Panel Data Lines can be swapped (i.e. VD23 = VD0) using the VD Data Swap bit, REG[14h] bit 7. Note: The VD output drive is selectable between 2.5mA and 6.5mA using the CNF2 pin. For details, see Section 4.3, "Summary of Configuration Options" on page 18. PIOVDD PIOVDD PIOVDD PIOVDD H H CLKI L L L L L This output pin is the Vertical Sync pulse. This output pin is the Horizontal Sync pulse. This output pin is the Data Clock. This output pin is the Data Enable. VD[23:0] IO HB_ DSEL PIOVDD L L VS HS PCLK DE O O O O HO HO HO HO Note The LCD interface requires a separate power rail (PIOVDD) to support the configurable IO drive. For details, see the CNF2 description in Section 4.3, "Summary of Configuration Options" on page 18. Note The input function of VD[23:0] is used for production test only. 4.2.3 Clocks Table 4-3: Clock Input Pin Descriptions Pin Name Type FCBGA Pin # A4 QFP Pin # 115 Cell IO Voltage IOVDD RESET# State Input Power Save Status Input Description MHz input for PLL operation or MHz input if PLL is bypassed. This output pin represents the CLKI pin if enabled by CLKOUTEN. When disabled, the output is low. Note: This output is not affected by the various power save modes. CLKOUTEN I B4 112 HI IOVDD Input Input This pin enables/disables the CLKOUT pin. CLKI I HIS CLKOUT O A3 110 HO IOVDD L CLKI Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 16 Epson Research and Development Vancouver Design Center 4.2.4 Miscellaneous Table 4-4: Miscellaneous Pin Descriptions Pin Name Type FCBGA Pin # QFP Pin # Cell IO Voltage RESET# State Power Save Status Description These inputs are used for power-up configuration. For further details, see Section 4.3, "Summary of Configuration Options" on page 18. Note: These pins must be connected directly to IOVDD or VSS. This is the Test Enable input and is used for production test only. This pin should be left unconnected for normal operation. CNF[2:0] I H3, G3, F3 76,77,78 HI IOVDD Input Input TESTEN I E3 94 LIDS IOVDD -- -- GPIO[7:0] IO K3, K2, J2, 66,67,71,72, J1, H2, H1, 81,82,83,84 G2, G1 HBD IOVDD L These pins are general purpose input/output Pull-down pins. These pins have internal pull-down Active resistors which can be controlled using REG[64h]. This pin enables/disables the Standby Power Pull-down Save Mode. Active This pin has an internal pull-down resistor which is always active. These are Test Function pins and are used for production test only. These pins should be left unconnected for normal operation. This is the Test Scan Enable input and is used for production test only. This pin should be left unconnected for normal operation. This is the PLL VCP Test pin and is used for production test only. This pin should be left unconnected for normal operation. PWRSVE I J3 70 HID IOVDD Input TEST[2:0] I E2, E1, F1 89,90,93 HID IOVDD -- -- SCANEN I F2 87 HID IOVDD -- -- VCP I D5 121 LITR PLLVDD -- -- NC -- A1, A2, A10, A11, B1, B11, E9, E10, E11, F8, F9, F10, F11, G8, G9, G10, G11, H8, H9, K1, K11, L1, L2, L10, L11 11,16,17,22, 23,24,25,29, 30,31,32,33, 34,35,36,37, 73,88,109, 111,117, 118,123 -- -- -- -- These pins are not connected. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 17 4.2.5 Power And Ground Table 4-5: Power And Ground Pin Descriptions Pin Name COREVDD IOVDD PIOVDD PLLVDD PLLVSS Type P P P P P FCBGA Pin # D7, E4, G7, H6 C4, D8, H4 E8, G4, H5, H7 D4 D6 C5, C6, E5, E6, E7, F4, F5, F6, F7, G5, G6 QFP Pin # 6,26,41,52,64,74, 95,114,133 68,79,85,91,100, 105,119,128,139 1,9,18,28,46,58 120 122 2,7,10,19,27,42, 47,53,59,65,69, 75,80,86,92,96, 99,104,113,116, 129,134,140 Cell P P P P P Core power supply IO power supply for the host interface IO power supply for the panel interface PLL power supply GND for PLL Description VSS P P GND Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 18 Epson Research and Development Vancouver Design Center 4.3 Summary of Configuration Options These pins are used for power-up configuration and must be connected directly to IOVDD or VSS. Changing the state of these pins is only permitted when RESET# is low (active). The status of these pins can be read in REG[02h] using the CNF[2:0] Status bits. Table 4-6: Summary of Power-On/Reset Options Configuration Input CNF0 CNF1 CNF2 Power-On/Reset State 1 (connected to IOVDD) Host Data Lines are normal: If CNF1 = 1b, then D15 = D15, etc. If CNF1 = 0b, then D7 = D7, etc. Host Data is 16-bit (see Note) PIOVDD output current = 6.5mA 0 (Connected to VSS) Host Data Lines are swapped: If CNF1 = 1b, then D15 = D0, etc. If CNF1 = 0b, then D7 = D0, etc. Host Data is 8-bit (see Note) PIOVDD output current = 2.5mA Note When CNF1 = 0b, all register access is 8-bit only. When CNF1 = 1b (16-bit), all register access is 8-bit ONLY (most significant byte on the data bus is ignored) except for the Memory Data Port (REG[48h] ~ REG[49h]) which is 16-bit. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 19 5 Pin Mapping 5.1 Intel 80 Data Pins Intel 80 data pin mapping is controlled by CNF[1:0]. For details on CNF[1:0], see Section 4.3, "Summary of Configuration Options" on page 18. Table 5-1: Intel 80 Data Pin Mapping Pin Name MD15 * * * MD8 MD7 * * * MD0 16-Bit Data No Swap (CNF1=1b, CNF0=1b) MD15 * * * MD8 MD7 * * * MD0 16-Bit Data Swapped (CNF1=1b, CNF0=0b) MD0 * * * MD7 MD8 * * * MD15 8-Bit Data No Swap (CNF1=0b, CNF0=1b) Hi-Z * * * Hi-Z MD7 * * * MD0 8-Bit Data Swapped (CNF1=0b, CNF0=0b) Hi-Z * * * Hi-Z MD0 * * * MD7 Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 20 Epson Research and Development Vancouver Design Center 5.2 LCD Interface Data Pins LCD interface data pin mapping is controlled by REG[14h] bit 7. Table 5-2: LCD Interface Data Pin Mapping for 24-bit Panels Pin Name VD23 * * * VD18 VD17 * * * VD0 24-Bit Data No Swap REG[14h] bit 7 = 0b VD23 * * * VD18 VD17 * * * VD0 24-Bit Data Swapped REG[14h] bit 7 = 1b VD0 * * * VD5 VD6 * * * VD23 Table 5-3: LCD Interface Data Pin Mapping for 18-bit Panels Pin Name VD23 * * * VD18 VD17 * * * VD0 VD17 * * * VD0 VD0 * * * VD17 Driven Low 18-Bit Data No Swap REG[14h] bit 7 = 0b 18-Bit Data Swapped REG[14h] bit 7 = 1b S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 21 6 D.C. Characteristics 6.1 Absolute Maximum Ratings Table 6-1: Absolute Maximum Ratings Symbol Core VDD PLL VDD IO VDD PIO VDD VIN VOUT IOUT Parameter Core Supply Voltage PLL Supply Voltage Host IO Supply Voltage Panel IO Supply Voltage Input Signal Voltage Output Signal Voltage Output Signal Current VSS - 0.3 ~ 2.0 VSS - 0.3 ~ 2.0 Core VDD ~ 4.0 Core VDD ~ 4.0 VSS - 0.3 ~ IO VDD + 0.3 VSS - 0.3 ~ IO VDD + 0.3 10 Rating Units V V V V V V mA 6.2 Recommended Operating Conditions Table 6-2: Recommended Operating Conditions Symbol Core VDD PLL VDD IO VDD PIO VDD VIN TOPR Parameter Core Supply Voltage PLL Supply Voltage Host IO Supply Voltage Panel IO Supply Voltage Input Voltage Operating Temperature Condition VSS = 0 V VSS = 0 V VSS = 0 V VSS = 0 V -- -- Min 1.40 1.40 1.65 1.65 VSS -40 Typ 1.50 1.50 -- -- -- +25 Max 1.60 1.60 3.6 3.6 IO VDD +85 Units V V V V V C Note There are no special Power On/Off requirements with respect to sequencing the various VDD pins. There are also no special requirements for the IO signals, however, Inputs should not be floating. If the input signals were to power up in a valid cycle, the S1D13743 would decode the cycle. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 22 Epson Research and Development Vancouver Design Center 6.3 Electrical Characteristics The following characteristics are for: IO VDD, VSS = 0V, TOPR = -40 to +85C. Table 6-3: Electrical Characteristics for IOVDD or PIOVDD = 1.8V 0.15V Symbol IQALL IPLL ICORE PCORE PPLL PPIO PHIO IIZ IOZ IOVOH2 PIOVOH2 PIOVOH4 IOVOL2 PIOVOL2 PIOVOL4 IOVIH PIOVIH IOVIL PIOVIL IOVT+ IOVTIO VH RPU1 RPD1 RPU2 RPD2 CIO Parameter Quiescent Current PLL Current Operation Peak Current Core Typical Operating Power PLL Typical Operating Power PIO Typical Operating Power HIO Typical Operating Power Input Leakage Current Output Leakage Current High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Low Level Output Voltage High Level Input Voltage High Level Input Voltage Low Level Input Voltage Low Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage Pull-Up Resistance Type1 Pull-Down Resistance Type1 Pull-Up Resistance Type2 Pull-Down Resistance Type2 Pin Capacitance -- -- IOVDD = min IOH2 = -2.5mA PIOVDD = min IOH2 = -2.5mA PIOVDD = min IOH2 = -6.5mA IOVDD = min IOL2 = 2.5mA PIOVDD = min IOL2 = 2.5mA PIOVDD = min IOL2 = 6.5mA CMOS Input CMOS Input CMOS Input CMOS Input CMOS Schmitt CMOS Schmitt CMOS Schmitt VI = VSS VI = VDD VI = VSS VI = VDD f = 1MHz, VDD = 0V see Note 1 Condition CLKI stopped (grounded), Sleep Mode enabled, all power supplies active fPLL = 54MHz COREVDD Power Pin Min -- -- -- -- -- -- -- -5 -5 IOVDD - 0.40 PIOVDD - 0.40 PIOVDD - 0.40 VSS VSS VSS 1.27 1.27 -- -- 0.57 0.33 0.24 40 40 80 80 -- Typ 100 500 -- 9.2 667 2.7 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 100 200 200 -- Max -- 1000 74 -- -- -- -- 5 5 IOVDD PIOVDD PIOVDD 0.40 0.40 0.40 -- -- 0.57 0.57 1.56 1.27 -- 240 240 480 480 8 Units A A mA mW W mW W A A V V V V V V V V V V V V V k k k k pF Note 1. Typical Operating Current Environment: 352x416 18-bit TFT panel 24bpp memory storage CLKI = 19.2MHz SYSCLK = 48.5MHz (PLL) PCLK = divide by 4 VCORE = 1.5V VHIO = 1.8V VPIO = 1.8V S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 23 The following characteristics are for: IOVDD, VSS = 0V, TOPR = -40 to +85C. Table 6-4: Electrical Characteristics for IOVDD or PIOVDD = 3.3V 0.3V Symbol IQALL IPLL ICORE IIZ IOZ IOVOH2 PIOVOH2 PIOVOH4 IOVOL2 PIOVOL2 PIOVOL4 IOVIH PIOVIH IOVIL PIOVIL IOVT+ IOVTIO VH RPU1 RPD1 RPU2 RPD2 CIO Parameter Quiescent Current PLL Current Operation Peak Current Input Leakage Current Output Leakage Current High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Low Level Output Voltage High Level Input Voltage High Level Input Voltage Low Level Input Voltage Low Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage Pull-Up Resistance Type1 Pull-Down Resistance Type1 Pull-Up Resistance Type2 Pull-Down Resistance Type2 Pin Capacitance Condition Quiescent Conditions fPLL = 54MHz COREVDD Power Pin -- -- IOVDD = min IOH2 = -4.0mA PIOVDD = min IOH2 = -4.0mA PIOVDD = min IOH2 = -12.0mA IOVDD = min IOL2 = 4.0mA PIOVDD = min IOL2 = 4.0mA PIOVDD = min IOL2 = 12.0mA CMOS Input CMOS Input CMOS Input CMOS Input CMOS Schmitt CMOS Schmitt CMOS Schmitt VI = VSS VI = VDD VI = VSS VI = VDD f = 1MHz, VDD = 0V Min -- -- -- -5 -5 IOVDD - 0.40 PIOVDD - 0.40 PIOVDD - 0.40 VSS VSS VSS 2.20 2.20 -- -- 1.40 0.60 0.45 20 20 40 40 -- Typ 160 500 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 50 100 100 -- Max -- 1000 74 5 5 IOVDD PIOVDD PIOVDD 0.40 0.40 0.40 -- -- 0.80 0.80 2.70 1.80 -- 120 120 240 240 8 Units A A mA A A V V V V V V V V V V V V V k k k k pF Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 24 Epson Research and Development Vancouver Design Center 7 A.C. Characteristics 7.1 Clock Timing 7.1.1 Input Clocks t1 t2 90% VIH CLKI VIL 10% t3 tOSC t5 CLKI tOSC t4 tOSC Figure 7-1 Clock Input Required (CLKI) S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 25 Table 7-1 Clock Input Requirements (CLKI) Parameter Input clock frequency - PLL used for System Clock fOSC (see note 1) Input clock frequency - CLKI used for System Clock Input clock period tOSC t1 Input clock pulse width high t2 Input clock pulse width low t3 Input clock rise time (10% ~ 90%) t4 Input clock fall time (90% ~ 10%) t5 Input clock period jitter (see Notes 2 and 4) t6 Input clock cycle jitter (see Notes 3 and 4) (see Note 6) Symbol Min 1 0 -- 0.4tOSC 0.4tOSC -- -- -300 -300 Typ -- -- 1/fOSC -- -- -- -- Max 33 68.59 -- 0.6tOSC 0.6tOSC 5.0 5.0 300 300 Units MHz MHz s s s ns ns ps ps 1. The minimum System Clock frequency required for correct operation depends on the cycle length of the Intel 80 interface. See Section 9.4, "Setting SYSCLK and PCLK" on page 43 for more details. 2. The input clock period jitter is the displacement relative to the center period (reciprocal of the center frequency). 3. The input clock cycle jitter is the difference in period between adjacent cycles. 4. The jitter characteristics must satisfy both the t5 and t6 characteristics. 5. Input Duty cycle is not critical and can be 40/60. 6. t6 = 2 x tOSC 7.1.2 PLL Clock The PLL circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The jitter of the input clock waveform should be as small as possible. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 26 Epson Research and Development Vancouver Design Center PLL Enable 10 ms Lock In Time PLL Stable MHz Reference Clock PLL xxMHz Output (xx = 44.28~66.53MHz) Jitter (ns) Lock in time 10 ms Time (ms) The PLL frequency will ramp between the OFF state and the programmed frequency. To guarantee the lowest possible clock jitter, 10ms is required for stabilization. Note: PLL minimum frequency = 44.28MHz (Based on Intel 80 cycle length. Refer to Section 8.4 for more information) PLL maximum frequency = 66.53MHz Figure 7-2: PLL Start-Up Time Table 7-2: PLL Clock Requirements Symbol fPLL tPJref tPDuty tPStal Parameter PLL output clock frequency PLL output clock period jitter PLL output clock duty cycle PLL output stable time Min 44.28 (Note 1) -3 40 Max 66.53 3 60 10 Units MHz % % ms 1. Refer to Section 9.4, "Setting SYSCLK and PCLK" on page 43. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 27 7.2 RESET# Timing t1 RESET# tCLKI CLKI Figure 7-3 S1D13743 RESET# Timing Table 7-3 S1D13743 RESET# Timing Symbol t1 Parameter Active Reset Pulse Width Min 1 Max -- Units CLKI Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 28 Epson Research and Development Vancouver Design Center 7.3 Host interface Timing 7.3.1 Intel 80 Interface Timing - 1.8 Volt D/C# (Note 1) twcs tast CS# (Note 2) twl twc WE# tr2w tw2r tdst MD[15:0] write (Note 3) tdht twh tch tch twah tcsf tcsf trcs trc trl trah RD# trh trdd MD[15:0] read (Note 3) trdv trodh trrdz tcodh tcrdz Note 1: The D/C# input pin is used to distinguish between Address and Data. Note 2: The CS# pin can be kept low between write and read pulses as the register addresses will auto-increment. The register address will auto-increment in word increments for all register access except the Memory Data Port. Writes to the Memory Data Port will not increment the register address to support burst data writes to memory. Note 3: When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 29 Table 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt Signal D/C# Symbol tast twah trah twcs CS# trcs tch tcsf twc WE# twl twh tw2r tr2w trc RD# trl trh tdst tdht trodh trrdz tcodh tcrdz MD[15:0] (Note 4) trdv Parameter Address setup time (read/write) Address hold time (write) Address hold time (read) Chip Select setup time (write) Chip Select setup time (read) Chip Select hold time (read/write) Chip Select Wait time (read/write) Register Write cycle LUT write cycle Memory write cycle Pulse low duration Pulse high duration WR# rising edge to RD# falling edge RD# rising edge to WR# falling edge Read cycle Pulse low duration Pulse high duration for Registers Pulse high duration for Memory and LUT Write data setup time Write data hold time Read data hold time from RD# rising edge RD# rising edge to MD High-Z Read data hold time from CS# rising edge CS# rising edge to MD High-Z RD# falling edge to MD valid for Registers RD# falling edge to MD valid for LUT RD# falling edge to MD valid for Memory RD# falling edge to MD valid for Registers RD# falling edge to MD valid for LUT RD# falling edge to MD valid for Memory trdd RD# falling edge to MD driven RD# falling edge to MD driven Min 1 6 30 twl trl 1 0 12 2SYSCLK + 2 2SYSCLK + 2 5 twc - twl 12 27 trl + trh trdv 36 1SYSCLK + 25 2 7 11 1 4 3 Max 32 8 17 4SYSCLK + 27 5SYSCLK + 20 12 4SYSCLK + 22 5SYSCLK + 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL=30pF CL = 8pF CL = 8pF CL=30pF Note 3 Note 1 Note 2 Description Note 1. For a read cycle after a write cycle, MD[15:0] must be driven Hi-Z a maximum of trdd after the falling edge of RD#. 2. For a write cycle after a read cycle, MD[15:0] should not be driven by the host until trrdz after the rising edge of RD#. 3. Assumes CS# remains low. After the rising edge of RD#, if CS# goes high before trrdz then MD[15:0] will go to High-Z according to tcrdz. 4. When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[7:0] are used for all accesses except for the Memory Data Port when MD[15:0] are used. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 30 Epson Research and Development Vancouver Design Center 7.3.2 Intel 80 Interface Timing - 3.3 Volt D/C# (Note 1) twcs tast CS# (Note 2) twl twc WE# tr2w tw2r tdst MD[15:0] write (Note 3) trcs trc trl RD# trh trdd MD[15:0] read (Note 3) trdv trodh trah tdht twh tch tch twah tcsf tcsf trrdz tcodh tcrdz Note 1: The D/C# input pin is used to distinguish between Address and Data. Note 2: The CS# pin can be kept low between write and read pulses as the register addresses will auto-increment. The register address will auto-increment in word increments for all register access except the Memory Data Port. Writes to the Memory Data Port will not increment the register address to support burst data writes to memory. Note 3: When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 31 Table 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt Signal D/C# Symbol tast twah trah twcs CS# trcs tch tcsf twc WE# twl twh tw2r tr2w trc RD# trl trh tdst tdht trodh trrdz tcodh tcrdz MD[15:0] (Note 4) trdv Parameter Address setup time (read/write) Address hold time (write) Address hold time (read) Chip Select setup time (write) Chip Select setup time (read) Chip Select hold time (read/write) Chip Select Wait time (read/write) Register Write cycle LUT write cycle Memory write cycle Pulse low duration Pulse high duration WR# rising edge to RD# falling edge RD# rising edge to WR# falling edge Read cycle Pulse low duration Pulse high duration for Registers Pulse high duration for Memory and LUT Write data setup time Write data hold time Read data hold time from RD# rising edge RD# rising edge to MD High-Z Read data hold time from CS# rising edge CS# rising edge to MD High-Z RD# falling edge to MD valid for Registers RD# falling edge to MD valid for LUT RD# falling edge to MD valid for Memory RD# falling edge to MD valid for Registers RD# falling edge to MD valid for LUT RD# falling edge to MD valid for Memory trdd RD# falling edge to MD driven RD# falling edge to MD driven Min 2 6 31 twl trl 0 1 10 2SYSCLK + 2 2SYSCLK + 2 5 twc - twl 12 27 trl + trh trdv 36 1SYSCLK + 26 2 7 11 -- 0.5 -- -- -- -- -- -- -- 3 2 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31 -- 8 12 4SYSCLK + 22 5SYSCLK + 15 10 4SYSCLK + 19 5SYSCLK + 12 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL=30pF CL = 8pF CL = 8pF CL=30pF Note 3 Note 1 Note 2 Description Note 1. For a read cycle after a write cycle, MD[15:0] must be driven Hi-Z a maximum of trdd after the falling edge of RD#. 2. For a write cycle after a read cycle, MD[15:0] should not be driven by the host until trrdz after the rising edge of RD#. 3. Assumes CS# remains low. After the rising edge of RD#, if CS# goes high before trrdz then MD[15:0] will go to High-Z according to tcrdz. 4. When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[7:0] are used for all accesses except for the Memory Data Port when MD[15:0] are used. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 32 Epson Research and Development Vancouver Design Center 7.3.3 Definition of Transition Time to Hi-Z State Due to the difficulty of Hi-Z impedance measurement for high speed signals, transition time from High/Low to Hi-Z specified as follows. * High to Hi-Z delay time: tpHZ, delay time when a gate voltage of final stage of the Pch-MOSFET turns to 0.8 x IOVDD (Pch-MOSFET is off). Total delay time to Hi-Z is calculated as follows: Internal logic delay + tpHZ (from High to Hi-Z) * Low to Hi-Z delay time: tpLZ, delay time when a gate voltage of final stage of the NchMOSFET turns to 0.2 x IOVDD (Nch-MOSFET is off). Total delay time to Hi-Z is calculated as follows: Internal logic delay + tpHZ (from High to Hi-Z) The functional model of a final stage of the Tri state Output Cell is shown in Figure 7-6: "Definition of transition time to Hi-Z state". Tri state Output Cell to measure tpHZ P IOVDD EN X A VSS N to measure tpLZ Volt IOVDD 0.8 IOVDD EN P Volt IOVDD EN N 1/2IOVDD 0.2 IOVDD Time tpHZ 1/2IOVDD Time tpLZ Figure 7-6: Definition of Transition Time to Hi-Z State S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 33 7.4 Display Interface The timing parameters required to drive a flat panel display are shown below. Timing details for each supported panel type are provided in the remainder of this section. HT TE DE TE DE VDISP HNDP HDISP HPS HSW VPS VNDP Symbol HDISP HNDP HPS HSW VDISP VNDP VPS VSW VSW Horizontal Display Width Horizontal Non-Display Period HS Pulse Start Position HS Pulse Width Vertical Display Height Vertical Non-Display Period VS Pulse Start Position VS Pulse Width 1. TS = 1/fPCLK Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 VDISP Description HDISP Figure 7-7: Panel Timing Parameters Table 7-6: Panel Timing Parameter Definition and Register Summary Derived From REG[16h] bits 6-0 x 8 REG[18h] bits 6-0 REG[22h] bits 6-0 REG[20h] bits 6-0 REG[1Ch] bits 1-0, REG[1Ah] bits 7-0 REG[1Eh] bits 7-0 REG[26h] bits 7-0 REG[24h] bits 5-0 Lines (HT) Ts (Note 1) Units S1D13743 X70A-A-001-02 Page 34 Epson Research and Development Vancouver Design Center 7.4.1 TFT Power-On Sequence Power Save Mode Enable* (REG[56h] bits 1-0) t1 LCD Signals** *The LCD power-on sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit 0 to 0, or by disabling the PWRSVE pin (see REG[56h] bit 7). **LCD Signals include: VD[23:0], PCLK, HS, VS, and DE. Figure 7-8: TFT Power-On Sequence Timing Table 7-7: TFT Power-On Sequence Timing Symbol t1 Parameter Power Save Mode disabled to LCD signals active Min 0 Max 20 Units ns S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 35 7.4.2 TFT Power-Off Sequence Power Save Mode Enable* (REG[56h] bits 1-0) t1 LCD Signals** *The LCD power-off sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit 0 to 1, or by enabling the PWRSVE pin (see REG[56h] bit 7). **LCD Signals include: VD[23:0], PCLK, HS, VS, and DE. Figure 7-9: TFT Power-Off Sequence Timing Table 7-8: TFT Power-Off Sequence Timing Symbol t1 Parameter Power Save Mode enabled to LCD signals low Min 0 Max 20 Units ns Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 36 Epson Research and Development Vancouver Design Center 7.4.3 Generic 18/24-Bit TFT Panel Timing t1 t2 VS t3 HS t18 DE t17 t4 HS t5 t6 DE t9 t10 t11 PCLK REG[2Ah] b7=1 t9 t10 t11 PCLK REG[2Ah] b7=0 t15 t16 VD[17:0] VD[23:0] invalid 1 2 320 invalid t12 t13 t14 t12 t13 t14 t7 t8 Figure 7-10: 18/24-Bit TFT A.C. Timing Note HS, VS, PCLK all have Polarity Select bits via registers S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 37 Table 7-9: 18/24-Bit TFT A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 Parameter VS cycle time VS pulse width low VS falling edge to HS falling edge phase difference HS cycle time HS pulse width low HS Falling edge to DE active DE pulse width DE falling edge to HS falling edge PCLK period PCLK pulse width low PCLK pulse width high HS setup to PCLK falling edge DE to PCLK rising edge setup time DE hold from PCLK rising edge Data setup to PCLK rising edge Data hold from PCLK rising edge DE Stop setup to VS start Vertical Non-Display Period Min -- -- -- -- -- -- -- -- 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- Typ VDISP + VNDP VSW HPS HDISP + HNDP HSW HNDP-HPS HDISP HPS -- -- -- -- -- -- -- -- VPS VNDP Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units Lines Lines Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts 1. Ts = pixel clock period Note In 24-bit mode, the data is always guaranteed to be launched on the correct edge of PCLK. In this mode, the frequency of PCLK is 1/2 the programmed internal value. If it is desired that HS and VS are always launched on the same edge of PCLK as the data, then HNDP, HSW, and HSS should be programmed with even values. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 38 Epson Research and Development Vancouver Design Center 8 Memory The S1D13743 contains 464K bytes of embedded SRAM. The SRAM consists of two banks, the first is 304K bytes and the second is 160K bytes in size, each bank being mapped at contiguous addresses. 00000h 304K Bytes 464K Bytes 4BFFFh 4C000h 160K Bytes 73FFFh Figure 8-1: S1D13743 Physical Memory All data written into memory, regardless of input data format, is in RGB 8:8:8 format. The following tables show how the pixel data is stored in the S1D13743 memory. Table 8-1: Memory Map for Single Buffer (REG[36h] bit 6 = 0b) Memory Address 00000h 00001h 00002h 00003h * * * 4C000h 4C001h * * * 73FFFh Description green [7:0] for pixel 1 red [7:0] for pixel 1 green [7:0] for pixel 2 red [7:0] for pixel 2 * * * blue [7:0] for pixel 1 blue [7:0] for pixel 2 * * * * S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 39 Table 8-2: Memory Map for Double Buffer (REG[36h] bit 6 = 1b) Memory Address 00000h 00001h 00002h 00003h * * * 26000h 26001h 26002h 26003h * * * 4C000h 4C001h * * * 60000h 60001h * * * 73FFFh Description green [7:0] for pixel 1, buffer 1 red [7:0] for pixel 1, buffer 1 green [7:0] for pixel 2, buffer 1 red [7:0] for pixel 2, buffer 1 * * * green [7:0] for pixel 1, buffer 2 red [7:0] for pixel 1, buffer 2 green [7:0] for pixel 2, buffer 2 red [7:0] for pixel 2, buffer 2 * * * blue [7:0] for pixel 1, buffer 1 blue [7:0] for pixel 2, buffer 1 * * * blue [7:0] for pixel 1, buffer 2 blue [7:0] for pixel 2, buffer 2 * * * * Pixel 1 Pixel 2 Display Figure 8-2: Display Pixel Position Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 40 Epson Research and Development Vancouver Design Center 9 Clocks 9.1 Clock Descriptions Internal PLL Enable Clock Source Select (REG[12h] bit 0) Glitch Free PLL MHz 1 0 SYSCLK CLKI External Clock Source Divider 1 2 3 32 PCLK Divide Select (REG[12h] bits 7-3) CLKOUT * * * PCLK CLKOUTEN Figure 9-1: S1D13743 Clock Block Diagram S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 41 9.2 PLL Block Diagram VCP REG[04h] bits 5-0 CP[4:0] REG[08h] bits 7-3 VC[3:0] REG[0Ah] bits 7-4 AMON CLKI M-Divider PLLCLK PFD CP VCO MUX Loop Filter RS[3:0] REG[0Ah] bits 3-0 CS[1:0] REG[0Ch] bits 1-0 TCK REG[08h] bit 0 REG[0Eh] bits 6-0 V-Divider L-Counter N-Counter MUX Where: PFD = Phase Frequency Detector CP = Charge Pump VCO = Voltage Controlled Oscillator Loop Filter = Low Pass Filter TEST Control = Internal Control Logic MUX SYSCLK REFCK 1/32 TOUT Figure 9-2: PLL Block Diagram Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 42 Epson Research and Development Vancouver Design Center 9.3 Clocks versus Functions The following table summarizes the internal clocks that are required for various S1D13743 functions. Table 9-1: Internal Clock Requirements Function Register Read/Write Memory Read/Write Look-Up Table Register Read/Write Power Save LCD Output Internal SYSCLK No Yes Yes No Yes Internal PCLK No No No No Yes Note Register accesses do not require an internal clock as the S1D13743 creates a clock from the bus cycle alone. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 43 9.4 Setting SYSCLK and PCLK The period of the system clock, TSYSCLK, must be set such that it falls within the following range: For PLL: For CLKI: 15.03ns < TSYSCLK < (TBBC - 0.976) x 0.485ns 14.58ns < TSYSCLK < (TBBC - 0.976) x 0.5ns where TBBC is the minimum back-to-back cycle time of the Intel 80 Interface. For example, if the minimum back-to-back cycle time of the Intel 80 Interface is 47.5ns, then: For PLL: For CLKI: 15.03ns < TSYSCLK < 22.584ns 14.58ns < TSYSCLK < 23.262ns Therefore, For PLL: For CLKI: 44.28MHz < fSYSCLK < 66.53MHz 42.99MHz < fSYSCLK < 68.59MHz Care should be taken when setting TSYSCLK so that the desired PCLK frequency, fPCLK, can be achieved. PCLK is an integer divided version of SYSCLK. The following graph shows the suggested setting for SYSCLK for a given value of PCLK for TBBC = 47.5ns. 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 6 SysClk/3 SYSCLK Frequency (MHz) SysClk/4 SysClk/5 SysClk/6 SysClk/7 SysClk/2 8 10 12 14 16 18 20 22 24 26 PCLK Frequency (MHz) Figure 9-3: Setting of SYSCLK for a Desired PCLK Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 44 Epson Research and Development Vancouver Design Center 10 Registers This section discusses how and where to access the S1D13743 registers. It also provides detailed information about the layout and usage of each register. Burst data writes to the register space are supported for all register write accesses, except write accesses to the Memory Data Port (REG[48h] ~ REG[49h]) and the Gamma Correction Table Data Register [REG[54h]). All writes to these registers will autoincrement the internal memory address only. 10.1 Register Mapping All registers and memory are accessed via the Intel 80 interface. All accesses are 8-bit only except for the Memory Data Port (REG[48h ~ 49h]) which is accessed according to the configuration of the CNF1 pin (16-bit for CNF1 = 1b, 8-bit for CFN1 = 0b). For further information on this setting, see Section 4.3, "Summary of Configuration Options" on page 18. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 45 10.2 Register Set The S1D13743 registers are listed in the following table. Table 10-1: S1D13743 Register Set Register REG[00h] Revision Code Register REG[04h] PLL M-Divider Register REG[08h] PLL Setting Register 1 REG[0Ch] PLL Setting Register 3 REG[10h] REG[14h] Panel Type Register REG[18h] Horizontal Non-Display Period Register (HNDP) REG[1Ch] Vertical Display Height Register 1 (VDISP) REG[20h] HS Pulse Width Register (HSW) REG[24h] VS Pulse Width Register (VSW) REG[28h] PCLK Polarity Register REG[2Ah] Input Mode Register REG[2Eh] Input YUV/RGB Translate Mode Register 1 REG[32h] V Data Fix Register REG[34h] Display Mode Register REG[38h] Window X Start Position Register 0 REG[3Ch] Window Y Start Position Register 0 REG[40h] Window X End Position Register 0 REG[44h] Window Y End Position Register 0 REG[48h] Memory Data Port Register 0 REG[4Ah] Memory Read Address Register 0 REG[4Eh] Memory Read Address Register 2 REG[50h] Gamma Correction Enable Register REG[54h] Gamma Correction Table Data Register REG[56h] Power Save Register REG[5Ah] General Purpose IO Pins Configuration Register 0 REG[5Eh] GPIO Positive Edge Interrupt Trigger Register REG[62h] GPIO Interrupt Status Register Pg Read-Only Configuration Registers 46 47 48 49 49 52 52 53 53 54 54 Register Pg 46 48 48 49 50 52 53 53 54 54 REG[02h] Configuration Readback Register REG[06h] PLL Setting Register 0 REG[0Ah] PLL Setting Register 2 REG[0Eh] PLL Setting Register 4 REG[12h] Clock Source Select Register REG[16h] Horizontal Display Width Register (HDISP) REG[1Ah] Vertical Display Height Register 0 (VDISP) REG[1Eh] Vertical Non-Display Period Register (VNDP) REG[22h] HS Pulse Start Position Register (HPS) REG[26h] VS Pulse Start Position Register (VPS) Clock Configuration Registers Panel Configuration Registers Input Mode Register 55 57 58 REG[2Ch] Input YUV/RGB Translate Mode Register 0 REG[30h] U Data Fix Register 56 58 Display Mode Registers 59 63 63 64 64 65 66 66 REG[36h] Special Effects Register REG[3Ah] Window X Start Position Register 1 REG[3Eh] Window Y Start Position Register 1 REG[42h] Window X End Position Register 1 REG[46h] Window Y End Position Register 1 REG[49h] Memory Data Port Register 1 REG[4Ch] Memory Read Address Register 1 60 63 63 64 64 65 66 Window Settings Memory Access Gamma Correction Registers 67 68 REG[52h] Gamma Correction Table Index Register 68 Miscellaneous Registers 69 71 71 72 REG[58h] Non-Display Period Control / Status Register REG[5Ch] General Purpose IO Pins Status/Control Register 0 REG[60h] GPIO Negative Edge Interrupt Trigger Register REG[64h] GPIO Pull-down Control Register 69 71 72 72 General Purpose IO Pins Registers Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 46 Epson Research and Development Vancouver Design Center 10.3 Register Descriptions All reserved bits must be set to the default value. Writing a non-default value to a reserved bit may produce undefined results. Bits marked as n/a have no hardware effect. Unless specified otherwise, all register bits are set to 0b during power-on reset. 10.3.1 Read-Only Configuration Registers REG[00h] Revision Code Register Default = 98h Product Code bits 5-0 7 6 5 4 3 2 1 Read Only Revision Code bits 1-0 0 bits 7-2 Product Code bits [5:0] (Read Only) These read-only bits indicate the product code. The product code for the S1D13743 is 100110b. Revision Code bits [1:0] (Read Only) These read-only bits indicates the revision code. The revision code is 00b. bits 1-0 REG[02h] Configuration Readback Register Default = xxh n/a 7 6 5 4 3 CNF2 Status 2 CNF1 Status 1 Read Only CNF0 Status 0 bits 2-0 CNF[2:0] Status (Read Only) These read-only status bits return the status of the configuration pins CNF[2:0]. For details on CNF[2:0] functionality, see Section 4.3, "Summary of Configuration Options" on page 18. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 47 10.3.2 Clock Configuration Registers REG[04h] PLL M-Divider Register Default = 00h PLL Lock (RO) 7 n/a 6 5 4 3 M-Divider bits 5-0 2 1 0 Read/Write bit 7 PLL Lock (Read Only) This bit indicates the status of the PLL output. When this bit = 0, the PLL output is not stable. In this state read/write access to the display buffer is prohibited. When this bit = 1, the PLL output is stable. M-Divider bits [5:0] These bits determine the divide ratio between CLKI and the actual input clock to the PLL Note bits 5-0 The internal input clock to the PLL (PLLCLK) must be between 1 MHz and 2 MHz. Depending on CLKI, these bits will have to be set accordingly. Note Values higher than 20h are not allowed. Table 10-2: PLL M-Divide Selection REG[04h] Bits 5-0 0h 01h 02h 03h * * * 20h 21h to 3Fh M-Divide Ratio 1:1 2:1 3:1 4:1 * * * 33:1 Reserved Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 48 Epson Research and Development Vancouver Design Center REG[06h] PLL Setting Register 0 Default = 00h PLL Setting Register 0 bits 7-0 7 6 5 4 3 2 1 Read/Write 0 This register must be programmed with the value F8h. REG[08h] PLL Setting Register 1 Default = 00h PLL Setting Register 1 bits 7-0 7 6 5 4 3 2 1 0 Read/Write This register must be programmed with the value 80h. REG[0Ah] PLL Setting Register 2 Default = 00h PLL Setting Register 2 bits 7-0 7 6 5 4 3 2 1 0 Read/Write This register must be programmed with the value 28h. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 49 REG[0Ch] PLL Setting Register 3 Default = 00h PLL Setting Register 3 bits 7-0 7 6 5 4 3 2 1 Read/Write 0 This register must be programmed with the value 00h. REG[0Eh] PLL Setting Register 4 Default = 00h n/a 7 6 5 4 L-Counter bits 6-0 3 2 1 0 Read/Write bits 6-0 L-Counter bits [6:0] These bits are used to configure the PLL Output (in MHz) and must be set according to the following formula. PLL Output = (L-Counter + 1) x PLLCLK = LL x PLLCLK Where: PLL Output is the desired PLL output frequency (in MHz). L-Counter is the value of this register (in decimal). PLLCLK is the internal input clock to the PLL (in MHz). Table 10-3 PLL Setting Example Target Frequency (MHz) 53 60 * 53 60 LL 53 60 * 53 60 CLKI Input Clock (MHz) 12 12 * 19.2 19.2 M-Divider REG[04h] bits 5-0 0Bh 0Bh * 12h 12h M-Divide Ratio 12:1 12:1 * 19:1 19:1 PLLCLK (MHz) 1.0 1.0 * 1.0105 1.0105 POUT (MHz) 53 60 * 53.53 60.63 REG[10h] Default = 00h n/a 7 6 5 4 3 2 1 Read/Write 0 Writes to this register have no effect on hardware. During Auto Increment, a dummy write must be performed to this register. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 50 Epson Research and Development Vancouver Design Center REG[12h] Clock Source Select Register Default = 00h PCLK Divide Select bits 4-0 7 6 5 4 3 2 n/a 1 Read/Write SYSCLK Source Select 0 bits 7-3 PCLK Divide Select bits [4:0] These bits specify the divide ratio for the panel clock (PCLK) frequency. The clock source for PCLK is SYSCLK. All resulting clock frequencies will maintain a 50/50 duty cycle regardless of divide ratio. Table 10-4 PCLK Divide Ratio Selection REG[12h] bits 7-3 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b PCLK Divide Ratio Reserved 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10:1 11:1 12:1 13:1 14:1 15:1 16:1 REG[12h] bits 7-3 10000b 10001b 10010b 10011b 10100b 10101b 10110b 10111b 11000b 11001b 11010b 11011b 11100b 11101b 11110b 11111b PCLK Divide Ratio 17:1 18:1 19:1 20:1 21:1 22:1 23:1 24:1 25:1 26:1 27:1 28:1 29:1 30:1 31:1 32:1 S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 51 bit 0 SYSCLK Source Select This bit selects the source of the system clock (SYSCLK) for the S1D13743. When this bit = 0, the SYSCLK source is the external CLKI input. When this bit = 1, the SYSCLK source is the internal PLL. If the PLL is selected as the SYSCLK source (REG[12h] bit 0 = 1b), the PLL must be configured using REG[06h], REG[08h], REG[0Ah], REG[0Ch], REG[0Eh] and REG[10h] before setting these bits. Note The PLL output will become stable after 10ms. The display memory and the Gamma Correction Table must not be accessed before PLL output is stable. The PLL Lock bit, REG[04h] bit 7, can be used to determine if the PLL output is stable. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 52 Epson Research and Development Vancouver Design Center 10.3.3 Panel Configuration Registers REG[14h] Panel Type Register Default = 00h VD Data Swap 7 6 5 4 n/a 3 2 1 Read/Write Panel Data Width 0 bit 7 VD Data Swap This bit determines whether the panel data lines (VD[23:0]) are swapped. If enabled, the data swap is from the msb to the lsb on the active output pins as shown in Table 5-2: "LCD Interface Data Pin Mapping for 24-bit Panels," on page 20 and Table 5-3: "LCD Interface Data Pin Mapping for 18-bit Panels," on page 20. When this bit = 0, the data lines are normal (i.e. output pin VD23 = VD23, etc.). When this bit = 1, the data lines are swapped (i.e. output pin VD23 = VD0, etc.). Panel Data Width This bit specifies the data width for the LCD interface. When this bit = 0, the LCD interface is configured as 18-bit (1 pixel / clock). When this bit = 1, the LCD interface is configured as 24-bit (1 pixel / clock). bit 0 REG[16h] Horizontal Display Width Register (HDISP) Default = 01h n/a 7 6 5 4 Horizontal Display Width bits 6-0 3 2 1 Read/Write 0 bits 6-0 Horizontal Display Width bits [6:0] These bits specify the Horizontal Display Width (HDISP) for the LCD panel, in 8 pixel resolution. HDISP in number of pixels = (REG[16h] bits 6-0) x 8 Note The minimum Horizontal Display Width is 8 pixels (REG[16h] bits 6-0 = 01h). REG[18h] Horizontal Non-Display Period Register (HNDP) Default = 00h n/a 7 6 5 4 Horizontal Non-Display Period bits 6-0 3 2 1 Read/Write 0 bits 6-0 Horizontal Non-Display Period bits [6:0] These bits specify the Horizontal Non-Display Period (HNDP), in pixels. HNDP in pixels = REG[18h] bits 6-0 Note The minimum Horizontal Non-Display Period is 3 Pixels (REG[18h] bits 6-0 = 03h). HS Start + HS Width <= HNDP S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 53 REG[1Ah] Vertical Display Height Register 0 (VDISP) Default = 01h Vertical Display Height bits 7-0 7 6 5 4 3 2 1 Read/Write 0 REG[1Ch] Vertical Display Height Register 1 (VDISP) Default = 00h n/a 7 6 5 4 3 2 1 Read/Write Vertical Display Height bits 9-8 0 REG[1Ch] bits 1-0 REG[1Ah] bits 7-0 Vertical Display Height bits [9:0] These bits specify the Vertical Display Height (VDISP) for the LCD panel, in lines. VDISP in lines = (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0) Note The minimum Vertical Display Height is 1 line (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0 = 001h). REG[1Eh] Vertical Non-Display Period Register (VNDP) Default = 01h Vertical Non-Display Period bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 Vertical Non-Display Period bits [7:0] These bits specify the Vertical Non-Display Period (VNDP) for the LCD panel, in lines. VNDP in lines = REG[1Eh] bits 7-0 Note The minimum Vertical Non-Display Period is 2 lines (REG[1Eh] bits 7-0 = 02h). REG[20h] HS Pulse Width Register (HSW) Default = 00h HS Pulse Polarity 7 6 5 4 HS Pulse Width bits 6-0 3 2 1 Read/Write 0 bit 7 HS Pulse Polarity This bit selects the polarity of the horizontal sync signal. This bit is set according to the horizontal sync signal of the panel. When this bit = 0, the horizontal sync signal is active low. When this bit = 1, the horizontal sync signal is active high. HS Pulse Width bits [6:0] These bits specify the width of the horizontal sync signal for the LCD panel (HSW), in pixels. The horizontal sync signal is typically HS, depending on the panel type. HSW in pixels = REG[20h] bits 6-0 bits 6-0 Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 54 Epson Research and Development Vancouver Design Center REG[22h] HS Pulse Start Position Register (HPS) Default = 00h n/a 7 6 5 4 HS Pulse Start Position bits 6-0 3 2 1 Read/Write 0 bits 6-0 HS Pulse Start Position bits [6:0] These bits specify the start position of the horizontal sync signal with respect to the start of Horizontal Non-Display period (HPS), in pixels. HPS in pixels = REG[22h] bits 6-0 REG[24h] VS Pulse Width Register (VSW) Default = 00h VS Pulse Polarity 7 n/a 6 5 4 VS Pulse Width bits 5-0 3 2 1 Read/Write 0 bit 7 VS Pulse Polarity This bit selects the polarity of the vertical sync signal. This bit is set according to the vertical sync signal of the panel. When this bit = 0, the vertical sync signal is active low. When this bit = 1, the vertical sync signal is active high. VS Pulse Width bits [5:0] These bits specify the width of vertical sync signal for the panel (VSW), in lines. The vertical sync signal is typically VS, depending on the panel type. VSW in lines = REG[24h] bits 5-0 bits 5-0 REG[26h] VS Pulse Start Position Register (VPS) Default = 00h VS Pulse Start Position bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 VS Pulse Start Position bits [7:0] These bits specify the start position of the vertical sync signal with respect to the start of Vertical Non-Display period (VPS), in lines. VPS in lines = REG[26h] bits 7-0 REG[28h] PCLK Polarity Register Default = 00h PCLK Polarity 7 6 5 4 n/a 3 2 1 Read/Write 0 bit 7 PCLK Polarity This bit selects the polarity of PCLK. When this bit = 0, data is output on the rising edge of PCLK. When this bit = 1, data is output on the falling edge of PCLK. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 55 10.3.4 Input Mode Register REG[2Ah] Input Mode Register Default = 01h n/a 7 6 5 4 3 Input Data Format bits 3-0 2 1 0 Read/Write bits 3-0 Input Data Format bits [3:0] These bits select the input data format. For further information on Input Data Format and Memory Data Format, see Section 13, "Intel 80, 8-bit Interface Color Formats" on page 75, Section 14, "Intel 80, 16-bit Interface Color Formats" on page 78 and Section 15, "YUV Timing" on page 83. Table 10-5: Input Data Type Selection REG[2Ah] bits 3-0 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b ~ 1111b Input Data Type Reserved RGB 5:6:5 RGB 6:6:6 Mode 1 RGB 8:8:8 Mode 1 Reserved Reserved RGB 6:6:6 Mode 2 RGB 8:8:8 Mode 2 YUV 4:2:2 YUV 4:2:0 Reserved Note All input data is stored as 24 bpp. Note For YUV 4:2:2 and YUV 4:2:0 settings, the image width must be a multiple of 2 and 4 respectively. For YUV 4:2:0 the height must be a multiple of 2. For RGB 6:6:6 and RGB 8:8:8 Mode 1, if the image width is odd, the red pixel data in the last word in each line will be ignored. The red pixel data will need to be re-written on the following transfer along with the green data. See Figure 14-2: "18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors," on page 79 or Figure 14-4: "24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors," on page 81. Note RGB 6:6:6 mode 2 and RGB 8:8:8 mode 2 settings are not available for 8-bit host interface. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 56 Epson Research and Development Vancouver Design Center REG[2Ch] Input YUV/RGB Translate Mode Register 0 Default = 00h Reserved 7 YRC Reset 6 5 UV Fix bits 1-0 4 3 2 n/a 1 Read/Write 0 bit 7 bit 6 Reserved The default value for this bit is 0b. YRC Reset This bit performs a software reset of the YRC (YUV to RGB Converter). To perform a reset, write a 1b to enter reset, and then write a 0b to return from the reset state. For Reads: When this bit = 0, the YRC is not in a reset state. When this bit = 1, the YRC is in a reset state. For Writes: Writing a 0 to this bit returns the YRC from the reset state. Writing a 1 to this bit initiates a software reset of the YRC. UV Fix Select bits [1:0] These bits control the UV input to the YRC (YUV to RGB Converter). Table 10-6: UV Fix Selection REG[2Ch] Bits 5-4 00b 01b 10b 11b UV Input to the YRC Original U data, original V data U data = REG[32h] bits 7-0, original V data Original U data, V data = REG[34h] bits 7-0 U data = REG[32h] bits 7-0, V data = REG[34h] bits 7-0 bits 5-4 S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 57 REG[2Eh] Input YUV/RGB Translate Mode Register 1 Default = 05h Reserved 7 6 YUV Input Data Type Select bits 1-0 5 4 Reserved 3 2 1 Read/Write YUV/RGB Transfer Mode bits 2-0 0 bits 7-6 bits 5-4 Reserved The default value for these bits is 00b. YUV Input Data Type Select bits [1:0] These bits specify the data type of the YUV input to the YUV to RGB Converter (YRC). Table 10-7: YUV Data Type Selection REG[2Eh] bits 5-4 00b YRC Input Data Range 0 Y 255 -128 U 127 -128 V 127 16 Y 235 -113 U 112 -113 V 112 0 Y 255 0 U 255 0 V 255 16 Y 235 16 U 240 16 V 240 01b 10b 11b bit 3 Reserved The default value for this bit is 0b. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 58 Epson Research and Development Vancouver Design Center bits 2-0 YUV/RGB Transfer Mode bits [2:0] These bits specify the YUV/RGB Transfer mode. Recommended settings are provided for various specifications. Table 10-8: YUV/RGB Transfer Mode Selection REG[2Eh] bits 2-0 000b 001b 010b 011b 100b 101b (Default) 110b 111b YUV/RGB Specification Reserved Recommended for ITU-R BT.709 Reserved Reserved Recommended for ITU-R BT.470-6 System M Recommended for ITU-R BT.470-6 System B, G (Recommended for ITU-R BT.601-5) SMPTE 170M SMPTE 240M(1987) REG[30h] U Data Fix Register Default = 00h U Data Fix bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 U Data Fix bits [7:0] These bits only have an effect when the UV Fix Select bits are set to 01b or 11b (REG[2Ch] bits 5-4 = 01b or 11b). The U data input to the YRC (YUV to RGB Converter) is fixed to the value of these bits. REG[32h] V Data Fix Register Default = 00h V Data Fix bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 V Data Fix bits [7:0] These bits only have an effect when the UV Fix Select bits are set to 10b or 11b (REG[2Ch] bits 5-4 = 10b or 11b). The V data input to the YRC (YUV to RGB Converter) is fixed to the value of these bits. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 59 10.3.5 Display Mode Registers REG[34h] Display Mode Register Default = 08h Display Blank 7 6 FRM Mode Select bits 2-0 5 4 Reserved 3 n/a 2 1 Read/Write SwivelView Mode Select bits 1-0 0 bit 7 Display Blank This bit blanks the display by disabling the LCD display pipeline and forcing all LCD data outputs to zero. When this bit = 0, the LCD display pipeline is enabled and the display is active. When this bit = 1, the LCD display pipeline is disabled and the display is blanked. FRM Mode Select bits [2:0] These bits select the FRM mode. Note bits 6-4 When the output is 24 bpp, set REG[34] bits 6-4 = 000b Table 10-9: FRM Mode Selection REG[34h] bits 6-4 000b 001b 010b 011b 100b 101b 110b 111b FRM Mode Selected Normal mode 18 bpp Bypass FRM Reserved Dithering Reserved FRM + Dithering Reserved bit 3 Reserved The default value for this bit is 1b. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 60 Epson Research and Development Vancouver Design Center bits 1-0 Window SwivelView Mode Select bits [1:0] These bits select the SwivelViewTM orientation that will be applied to the window. Each window on the active display can have independent rotation, as the rotation is performed prior to writing to the display buffer. Table 10-10: SwivelView Mode Select Options REG[34h] bits 1-0 00b 01b 10b 11b SwivelView Orientation 0 (Normal) 90 180 270 REG[36h] Special Effects Register Default = 00h Window Data Type 7 Double Buffer Enable 6 5 4 n/a 3 2 Read/Write Window Pixel Sizing bits 1-0 1 0 bit 7 Window Data Type This bit is used in conjunction with the Double Buffer Enable bit (REG[36h] bit 6) and determines whether the data being input from the host will be double-buffered. This bit must be set before the window data is written, as the window coordinates will be latched internally to be used by the display pipe during display cycles. When this bit = 0, the data being written from the Host is intended for single buffer only. When this bit = 1, the data being written from the Host is intended for double buffer operation. Table 10-11: Window Data Type / Buffer Selection REG[36h] Bit 7 REG[36h] Bit 6 Use Case 0b 0b Single buffered window with no double buffering anywhere on the display. Use this to write a single buffered window while preventing tearing in a 0b 1b previously defined double buffered window. 1b 0b Reserved 1b 1b Use this to write data to be double buffered. Note While double buffering is enabled, the window coordinates should not be modified. Note If the Input Data Format is YUV 4:2:0 (REG[2Ah] bits 3-0 = 1001b), the Window Data Type bit must not be changed while the YYC is busy (REG[58h] bit 4 = 1b). S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 61 bit 6 Double Buffer Enable This bit is used in conjunction with the Window Data Type bit (REG[36h] bit 7) and controls the Double Buffer architecture. Double buffering is intended to prevent visual tearing when updating the display from streaming input sources. This bit must be set before the window data is written, as the window coordinates will be latched internally to be used by the display pipe during display cycles. When this bit = 0, the double buffer architecture is disabled. When this bit =1, the double buffer architecture is enabled. This feature is only available if the memory size resulting from the display size and color depth will fit within the 1/2 the allowable size for the display buffer. For a summary of Window Data Type / Double Buffer options, see Table 10-11: "Window Data Type / Buffer Selection," on page 60. Note While double buffering is enabled, the window coordinates should not be modified. Note Only one window can be double-buffered. All other windows are single buffered. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 62 Epson Research and Development Vancouver Design Center bits 1-0 Window Pixel Sizing bits [1:0] These bits control resizing of the window data. These bits must be set before the window data is written, as the window coordinates will be latched internally to be used by the display pipe during display cycles. Table 10-12: Window Pixel Sizing REG[36h] bits 1-0 00b 01b 10b 11b Result No Resizing Pixel Doubling Pixel Halving Reserved Note Only 1 active window can have pixel doubling enabled. The pixel doubling design uses horizontal and vertical averaging for smooth doubling. The following figure provides an example of the resizing options. All resizing is performed with respect to the top left corner. Display Original Window Pixel Halved Window Pixel Doubled Window Figure 10-1: Sizing Example Note To disable pixel doubling for a window that is currently pixel doubled, either: 1. Overwrite any part of the pixel doubled window with a new window. 2. Write a new pixel doubled window. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 63 10.3.6 Window Settings REG[38h] Window X Start Position Register 0 Default = 00h Window X Start Position bits 7-0 7 6 5 4 3 2 1 0 Read/Write REG[3Ah] Window X Start Position Register 1 Default = 00h n/a 7 6 5 4 3 2 1 Read/Write Window X Start Position bits 9-8 0 REG[3Ah] bits 1-0 REG[38h] bits 7-0 Window X Start Position bits [9:0] These bits determine the X start position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation (see REG[34h] bits 1-0), the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled (see REG[36h] bits 1-0), these bits should be programmed with the pre-resized coordinates. REG[3Ch] Window Y Start Position Register 0 Default = 00h Window Y Start Position bits 7-0 7 6 5 4 3 2 1 Read/Write 0 REG[3Eh] Window Y Start Position Register 1 Default = 00h n/a 7 6 5 4 3 2 1 Read/Write Window Y Start Position bits 9-8 0 REG[3Eh] bits 1-0 REG[3Ch] bits 7-0 Window Y Start Position bits [9:0] These bits determine the Y start position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation (see REG[34h] bits 1-0), the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled (see REG[36h] bits 1-0), these registers should be programmed with the pre-resized coordinates. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 64 Epson Research and Development Vancouver Design Center REG[40h] Window X End Position Register 0 Default = 00h Window X End Position bits 7-0 7 6 5 4 3 2 1 Read/Write 0 REG[42h] Window X End Position Register 1 Default = 00h n/a 7 6 5 4 3 2 1 Read/Write Window X End Position bits 9-8 0 REG[42h] bits 1-0 REG[40h] bits 7-0 Window X End Position bits [9:0] These bits determine the X end position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation (see REG[34h] bits 1-0), the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled (see REG[36h] bits 1-0), these registers should be programmed with the pre-resized coordinates. REG[44h] Window Y End Position Register 0 Default = 00h Window Y End Position bits 7-0 7 6 5 4 3 2 1 Read/Write 0 REG[46h] Window Y End Position Register 1 Default = 00h n/a 7 6 5 4 3 2 1 Read/Write Window Y End Position bits 9-8 0 REG[46h] bits 1-0 REG[44h] bits 7-0 Window Y End Position bits [9:0] These bits determine the Y end position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation (see REG[34h] bits 1-0), the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled (see REG[36h] bits 1-0), these registers should be programmed with the pre-resized coordinates. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 65 10.3.7 Memory Access REG[48h] Memory Data Port Register 0 Default = not applicable Memory Data Port bits 7-0 7 6 5 4 3 2 1 0 Read/Write REG[49h] Memory Data Port Register 1 Default = not applicable Memory Data Port bits 15-8 7 6 5 4 3 2 1 Read/Write 0 REG[48h] bits 7-0 REG[49h] bits 15-8 Memory Data Port bits [7:0] These bits specify the lsb of the data word. Memory Data Port bits [15:8] These bits specify the msb of the data word. Note If CNF1=0 (8-bit interface), REG[49h] is not used. Note Burst data writes are supported through these registers. Register auto-increment is automatically disabled once reaching this address. All writes to this register will auto-increment the internal memory address only. Note Panel dimension registers must be set before writing any window data. Note Upon writing the last pixel in the defined window, these bits will automatically point back to the first pixel in the window. Therefore, there is no need to re-initialize the pointers. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 66 Epson Research and Development Vancouver Design Center REG[4Ah] Memory Read Address Register 0 Default = 00h Memory Read Address bits 7-0 7 6 5 4 3 2 1 Read/Write 0 REG[4Ch] Memory Read Address Register 1 Default = 00h Memory Read Address bits 15-8 7 6 5 4 3 2 1 Read/Write 0 REG[4Eh] Memory Read Address Register 2 Default = 00h n/a 7 6 5 4 3 2 1 Read/Write Memory Read Address bit 18-16 0 REG[4Eh] bits 2-0 REG[4Ch] bits 7-0 REG[4Ah] bits 7-0 Memory Read Address bits [18:0] These bits are used for individual memory location reads only. Individual memory location writes are not supported. After a completed memory access, these bits are automatically incremented. Note If 16-bit interface is used (CNF1 = 1), all reads will be on even byte boundaries. Memory Read Address bit 0 is ignored and internally forced to 0b. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 67 10.3.8 Gamma Correction Registers Note Gamma correction is implemented as a look-up table. RGB input data (YUV input data is converted to RGB) is used to look-up the values from the programmed tables. The Gamma LUT's are placed on the display read path and the 24-bit output goes to the LCD interface. Note The Gamma Correction Tables should not be accessed during display period as this will result in visual anomalies. All updates to the LUTs should be performed during non-display period or when the LUTs are disabled and not in use. REG[50h] Gamma Correction Enable Register Default = 00h n/a 7 6 5 4 3 Look-Up Table Access Mode bits 1-0 2 1 Read/Write Gamma Correction Enable 0 bits 2-1 Look-Up Table Access Mode bits [1:0] These bits specify the mode used to access the Look-Up Table (LUT). Table 10-13: Look-Up Table Access Mode REG[50h] bits 2-1 00b 01b 10b 11b Description Writing is done to all Red, Green, & Blue tables. Reading is done from the Red table. Reading and writing are done from/to the Red table. Reading and writing are done from/to the Green table. Reading and writing are done from/to the Blue table. bit 0 Gamma Correction Enable This bit controls gamma correction. When this bit = 0, gamma correction is disabled and the input data will bypass the gamma correction look-up table. When this bit = 1, gamma correction is enabled and the input data will go through the gamma correction look-up table. Note The Gamma Correction Tables should not be accessed during display period as this will result in visual anomalies. All updates to the LUTs should be performed during non-display period or when the LUTs are disabled and not in use. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 68 Epson Research and Development Vancouver Design Center REG[52h] Gamma Correction Table Index Register Default = 00h Gamma Correction Table Index bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 Gamma Correction Table Index bits [7:0] These bits specify the index of the gamma correction look-up table where the subsequent read/write will start. REG[54h] Gamma Correction Table Data Register Default = not applicable Gamma Correction Table Data bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 Gamma Correction Table Data bits [7:0] When writing to these bits, the index to the internal Gamma Correction Table Data is automatically incremented by 1 for each write to the Gamma Correction Table Data register. This allows the continuous writes to the Gamma Correction Table while only having to write the Gamma Correction Table Index, REG[52h], once before the first write. Note When performing auto-increment writes, all 256 positions of each LUT must be written. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 69 10.3.9 Miscellaneous Registers REG[56h] Power Save Register Default = 00h PWRSVE Input Pin Function 7 6 5 n/a 4 3 2 Sleep Mode Enable/Disable 1 Read/Write Standby Mode Enable/Disable 0 bit 7 PWRSVE Input Pin Function This bit determines the functionality of the PWRSVE input pin. When this bit = 0, the PWRSVE pin is OR'd with the Sleep Mode Enable/Disable bit (REG[56h] bit 1) and setting either to 1 will enable Sleep Mode. When this bit = 1, the PWRSVE pin is OR'd with the Standby Mode Enable/Disable bit (REG[56h] bit 0) and setting either to 1 will enable Standby Mode. Sleep Mode Enable/Disable This bit controls the Sleep power save mode. Sleep mode can also be controlled by the PWRSVE pin when REG[56h] bit 7 = 0b. When this bit = 0, Sleep Mode is disabled (normal operation). When this bit = 1, Sleep Mode is enabled. When Sleep Mode is enabled, all internal blocks including the PLL are disabled. When Sleep Mode is disabled, the PLL requires approximately 10ms lock time before any memory access should be attempted. The PLL Lock bit, REG[04h] bit 7, can be read to verify when the PLL becomes stable. bit 1 bit 0 Standby Mode Enable/Disable This bit controls the Standby power save mode. Standby mode can also be controlled by the PWRSVE pin when REG[56h] bit 7 = 1b. When this bit = 0, Standby Mode is disabled (normal operation). When this bit = 1, Standby Mode is enabled. When Standby Mode is enabled, all internal blocks are disabled except for the PLL. When Standby Mode is disabled, the chip can be accessed immediately. REG[58h] Non-Display Period Control / Status Register Default = 00h Vertical NonDisplay Period Status (RO) 7 Horizontal NonDisplay Period Status (RO) 6 VDP OR'd with HDP Status (RO) 5 YYC Last Line 4 n/a 3 TE Output Pin Enable 2 Read/Write TE Output Pin Function Select bits 1-0 1 0 bit 7 Vertical Non-Display Period Status (Read Only) This bit indicates whether the LCD panel output is in a vertical non-display period (VNDP). VNDP is defined as the time between the last pixel on the last line of one frame to the first pixel on the first line of the next frame. When this bit = 0, the LCD panel output is in a Vertical Display Period. When this bit = 1, the LCD panel output is in a Vertical Non-Display Period. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 70 Epson Research and Development Vancouver Design Center bit 6 Horizontal Non-Display Period Status (Read Only) This bit indicates whether the LCD panel output is in a horizontal non-display period (HNDP). HNDP is defined as the time between the last pixel in line n to the first pixel in line n+1. When this bit = 0, the LCD panel output is in a Horizontal Non-Display Period. When this bit = 1, the LCD panel output is in a Horizontal Display Period. VP OR'd with HDP Status (Read Only) This bit indicates whether the LCD panel is in a display period or a non-display period. When this bit = 0, the LCD panel is in a Display period. When this bit = 1, the LCD panel is in either a Horizontal or Vertical Non-Display period. YYC Last Line This bit indicates the status of the YYC (YUV to YUV Converter). If the Input Data Format is YUV 4:2:0 (REG[2Ah] bits 3-0 = 1001b), this bit goes high 5 MCLKs after the Intel 80 interface completes writing the last pixel of the current window. The bit goes low once the YYC returns to an idle state. At this point, a new window can be written. When this bit = 0, the YYC is idle. When this bit = 1, the YYC is converting YUV 4:2:0 data. When doing back-to-back window writes with a different dimension or format, and the first window is YUV 4:2:0, this bit must be low (0) before starting to write the second window. bit 5 bit 4 bit 2 TE Output Pin Enable This bit controls the TE output pin. When this bit = 0, the TE output pin is disabled. When this bit = 1, the TE output pin is enabled. TE Output Pin Function Select bits [1:0] These bits select which function is indicated by the TE output pin. Table 10-14: TE Output Pin Function Selection REG[58h] bits 1-0 00b 01b 10b 11b TE Output Pin Function Reserved Horizontal Non-Display Period Vertical Non-Display Period HS OR'd with VS bits 1-0 S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 71 10.3.10 General Purpose IO Pins Registers REG[5Ah] General Purpose IO Pins Configuration Register 0 Default =00h GPIO7 Configuration 7 GPIO6 Configuration 6 GPIO5 Configuration 5 GPIO4 Configuration 4 GPIO3 Configuration 3 GPIO2 Configuration 2 GPIO1 Configuration 1 Read/Write GPIO0 Configuration 0 bits 7-0 GPIO[7:0] Configuration These bits configure the corresponding GPIO[7:0] pin between inputs or outputs. When this bit = 0 (normal operation), the corresponding GPIO pin is configured as an input. When this bit = 1, the corresponding GPIO pin is configured as an output. REG[5Ch] General Purpose IO Pins Status/Control Register 0 Default = 00h GPIO7 Status 7 GPIO6 Status 6 GPIO5 Status 5 GPIO4 Status 4 GPIO3 Status 3 GPIO2 Status 2 GPIO1 Status 1 Read/Write GPIO0 Status 0 bits 7-0 GPIO[7:0] Status When the corresponding GPIO[7:0] pin is configured as an output (see REG[5Ah]), writing a 1b to this bit drives GPIOx high and writing a 0b to this bit drives GPIOx low. When the corresponding GPIO[7:0] pin is configured as an input (see REG[5Ah]), a read from this bit returns the raw status of GPIOx. REG[5Eh] GPIO Positive Edge Interrupt Trigger Register Default = 00h GPIO7 Positive Edge Interrupt Trigger 7 GPIO6 Positive Edge Interrupt Trigger 6 GPIO5 Positive Edge Interrupt Trigger 5 GPIO4 Positive Edge Interrupt Trigger 4 GPIO3 Positive Edge Interrupt Trigger 3 GPIO2 Positive Edge Interrupt Trigger 2 GPIO1 Positive Edge Interrupt Trigger 1 Read/Write GPIO0 Positive Edge Interrupt Trigger 0 bits 7-0 GPIO[7:0] Positive Edge Interrupt Trigger This bit determines whether the associated GPIO interrupt is triggered on the positive edge (when the GPIOx pin changes from 0 to 1). When this bit = 0, the associated GPIO interrupt (GPIO_INT) is not triggered on the positive edge. When this bit = 1, the associated GPIO interrupt (GPIO_INT) is triggered on the positive edge. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 72 Epson Research and Development Vancouver Design Center REG[60h] GPIO Negative Edge Interrupt Trigger Register Default = 00h GPIO7 Negative Edge Interrupt Trigger 7 GPIO6 Negative Edge Interrupt Trigger 6 GPIO5 Negative Edge Interrupt Trigger 5 GPIO4 Negative Edge Interrupt Trigger 4 GPIO3 Negative Edge Interrupt Trigger 3 GPIO2 Negative Edge Interrupt Trigger 2 GPIO1 Negative Edge Interrupt Trigger 1 Read/Write GPIO0 Negative Edge Interrupt Trigger 0 bits 7-0 GPIO[7:0] Negative Edge Interrupt Trigger This bit determines whether the associated GPIO interrupt is triggered on the negative edge (when the GPIOx pin changes from 1 to 0). When this bit = 0, the associated GPIOx interrupt (GPIO_INT) is not triggered on the negative edge. When this bit = 1, the associated GPIOx interrupt (GPIO_INT) is triggered on the negative edge. REG[62h] GPIO Interrupt Status Register Default = 00h GPIO7 Interrupt Status 7 GPIO6 Interrupt Status 6 GPIO5 Interrupt Status 5 GPIO4 Interrupt Status 4 GPIO3 Interrupt Status 3 GPIO2 Interrupt Status 2 GPIO1 Interrupt Status 1 Read/Write GPIO0 Interrupt Status 0 bits 7-0 GPIO[7:0] Interrupt Status If GPIOs are configured to generate an Interrupt (see REG[5Eh] and REG[60h]), these status bits will indicate which GPIO generated the interrupt. To clear the corresponding GPIO[7:0] Interrupt Status bit, write a 1b then a 0b to the bit. REG[64h] GPIO Pull-down Control Register Default = FFh GPIO7 Pull-down Control 7 GPIO6 Pull-down Control 6 GPIO5 Pull-down Control 5 GPIO4 Pull-down Control 4 GPIO3 Pull-down Control 3 GPIO2 Pull-down Control 2 GPIO1 Pull-down Control 1 Read/Write GPIO0 Pull-down Control 0 bits 7-0 GPIO[7:0] Pull-down Control All GPIO[7:0] pins have internal pull-down resistors. These bits individually control the state of the corresponding pull-down resistor. When the bit = 0, the pull-down resistor for the corresponding GPIO pin is inactive. When the bit = 1, the pull-down resistor for the corresponding GPIO pin is active. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 73 11 Frame Rate Calculation The following formula is used to calculate the display frame rate. f PCLK FrameRate = ------------------------------( HT ) x ( VT ) Where: fPCLK = PClk frequency (Hz) HT = Horizontal Total = Horizontal Display Width + Horizontal Non-Display Period = Vertical Total = Vertical Display Height + Vertical Non-Display Period VT Note For definitions of panel timing parameters, see Section 7.4, "Display Interface" on page 33. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 74 Epson Research and Development Vancouver Design Center 12 RGB Input Data Conversion All RGB input data is converted to RGB 8:8:8 and stored as follows. For further information see Section 8, "Memory" on page 38. Table 12-1: RGB 5:6:5 to RGB 8:8:8 Conversion Memory Format Pixel Byte 2 1 0 Bit 7 R4 G5 B4 Bit 6 R3 G4 B3 Bit 5 R2 G3 B2 Bit 4 R1 G2 B1 Bit 3 R0 G1 B0 Bit 2 R4 G0 B4 Bit 1 R3 G5 B3 Bit 0 R2 G4 B2 Table 12-2: RGB 6:6:6 to RGB 8:8:8 Conversion Memory Format Pixel Byte 2 1 0 Bit 7 R5 G5 B5 Bit 6 R4 G4 B4 Bit 5 R3 G3 B3 Bit 4 R2 G2 B2 Bit 3 R1 G1 B1 Bit 2 R0 G0 B0 Bit 1 R5 G5 B5 Bit 0 R4 G4 B4 Table 12-3: RGB 8:8:8 Memory Format Pixel Byte 2 1 0 Bit 7 R7 G7 B7 Bit 6 R6 G6 B6 Bit 5 R5 G5 B5 Bit 4 R4 G4 B4 Bit 3 R3 G3 B3 Bit 2 R2 G2 B2 Bit 1 R1 G1 B1 Bit 0 R0 G0 B0 S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 75 13 Intel 80, 8-bit Interface Color Formats 13.1 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors CS# D/C# WR# RD# MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n Pixel Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0 for Green data and MSB = Bit 4, LSB = Bit 0 for Red and Blue data. Figure 13-1: 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 76 Epson Research and Development Vancouver Design Center 13.2 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors CS# D/C# WR# RD# MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. Figure 13-2: 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 77 13.3 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors CS# D/C# WR# RD# MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R1, Bit 7 R1, Bit 6 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 7 G1, Bit 6 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 7 B1, Bit 6 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 7 R2, Bit 6 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. Figure 13-3: 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 78 Epson Research and Development Vancouver Design Center 14 Intel 80, 16-bit Interface Color Formats 14.1 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors CS# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n Pixel n + 1 Pixel n + 2 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0 for Green data and MSB = Bit 4, LSB = Bit 0 for Red and Blue data. Figure 14-1: 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 79 14.2 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors CS# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. Figure 14-2: 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 80 Epson Research and Development Vancouver Design Center 14.3 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors CS# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. Figure 14-3: 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 81 14.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors CS# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R1, Bit 7 R1, Bit 6 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 7 G1, Bit 6 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 7 B1, Bit 6 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 7 R2, Bit 6 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 7 G2, Bit 6 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 7 B2, Bit 6 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. Figure 14-4: 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 82 Epson Research and Development Vancouver Design Center 14.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors CS# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R1, Bit 7 R1, Bit 6 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 7 G1, Bit 6 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 7 B1, Bit 6 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 7 R2, Bit 6 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. Figure 14-5: 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 83 15 YUV Timing Format Definition * The number of pixels per line is always even * The YCBCR colorspace is defined in ITU-R BT601.4 * YUV 4:2:2 format U11Y11V11Y12U13Y13V13Y14... * YUV 4:2:0 format Odd Line: UY11Y12... Even Line: VY21Y22... Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line. YUV 4:2:2 U11 Odd Line Y11 V11 Y12 U13 Y13 V13 Y14 U21 Even Line Y21 V21 Y22 U23 Y23 V23 Y24 YUV 4:2:0 Odd Line (must start with this line) Y11 U/V Y12 Y13 U/V Y14 Even Line Y21 Y22 Y23 Y24 Figure 15-1: YUV Format Definition Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 84 Epson Research and Development Vancouver Design Center 15.1 YUV 4:2:2 with Intel 80, 8-bit Interface CS# RESET# D/C# WR# RD# MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 U (11,12) Y11 V (11,12) Y12 U (13,14) Y13 (13,14) V Y14 Figure 15-2: YUV 4:2:2 with Intel 80, 8-bit Interface 15.2 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface CS# RESET# D/C# WR# RD# MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 U (11,12,21,22) Y11 Y12 U (13,14,23,24) Y13 Y14 U (15,16,25,26) Y15 Figure 15-3: YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 85 15.3 YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface CS# RESET# D/C# WR# RD# MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V (11,12,21,22) Y21 Y22 V (13,14,23,24) Y23 Y24 V (15,16,25,26) Y25 Figure 15-4: YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 86 Epson Research and Development Vancouver Design Center 15.4 YUV 4:2:2 with Intel 80, 16-bit Interface CS# RESET# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 U11 V11 U13 V13 U15 V15 U17 V17 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Figure 15-5: YUV 4:2:2 with Intel 80, 16-bit Interface S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 87 15.5 YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface CS# RESET# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 U (11,12,21,22) Y12 Y13 U (15,16,25,26) Y16 Y17 Y11 U (13,14,23,24)) Y14 Y15 U (17,18,27,28) Y18 Figure 15-6: YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 88 Epson Research and Development Vancouver Design Center 15.6 YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface CS# RESET# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V (11,12,21,22) Y22 Y23 V (15,16,25,26) Y26 Y27 Y21 V (13,14,23,24) Y24 Y25 V (17,18,27,28) Y28 Figure 15-7: YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 89 16 Gamma Correction Look-Up Table Architecture The following figure is intended to show the display data output path only. The following diagram shows the architecture for 24 bpp using the LUT. Red Look-Up Table 256x8 00h 01h 02h 03h 04h 05h 06h 07h F8h F9h FAh FBh FCh FDh FEh FFh 8-bit Red Data from Display Buffer Green Look-Up Table 256x8 00h 01h 02h 03h 04h 05h 06h 07h F8h F9h FAh FBh FCh FDh FEh FFh 8-bit Green Data from Display Buffer Blue Look-Up Table 256x8 00h 01h 02h 03h 04h 05h 06h 07h F8h F9h FAh FBh FCh FDh FEh FFh 8-bit Blue Data from Display Buffer 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 8-bit Red Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 8-bit Green Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 8-bit Blue Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 Figure 16-1: Look-Up Table Architecture (24 bpp using LUT) Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 90 Epson Research and Development Vancouver Design Center 16.1 Gamma Correction Programming Example The following procedure should be used to setup and program the Gamma Correction Look-Up Table. * Disable the LUTs or only access during a non-display period to avoid visual anomalies. * Write the register "address" for the Gamma Correction Enable register (REG[50h]) * Write data to set the desired LUT Access Mode (see REG[50h] bits 2-1) * Write data to set the LUT Index to "x" (auto-increment is already enabled, therefore the Gamma Correction Table Index register "address" does not have to be written) * Write data to the Gamma Correction Table Data register (data value for Index "x") * Write data to the Gamma Correction Table Data register (data value for Index "x+1") * Continue until all 256 positions have been written * Enable Gamma Correction (REG[50h] bit 0 = 1) S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 91 17 Display Data Format Table 17-1: 24-Bit Data Format (Non-Swapped, REG[14h] bit 7 = 0b) Pin Name VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 Cycle Count 1 R0 R0 7 2 R17 R16 R15 R14 R13 R12 R11 R10 G17 G16 G15 G14 G13 G12 G11 G10 B17 B16 B15 B14 B13 B12 B11 B10 3 R27 R26 R25 R24 R23 R22 R21 R20 G27 G26 G25 G24 G23 G22 G21 G20 B27 B26 B25 B24 B23 B22 B21 B20 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... n Rn7 Rn6 Rn5 Rn4 Rn3 Rn2 Rn1 Rn0 Gn7 Gn6 Gn5 Gn4 Gn3 Gn2 Gn1 Gn0 Bn7 Bn6 Bn5 Bn4 Bn3 Bn2 Bn1 Bn0 R06 5 R04 R03 R02 R0 1 R00 G07 G06 G0 5 G04 G03 G02 G0 1 G00 B07 B06 B05 B04 B03 B02 B01 B00 Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 92 Epson Research and Development Vancouver Design Center Table 17-2: 24-Bit Data Format (Swapped, REG[14h] bit 7 = 1b) Pin Name VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 Cycle Count 1 B00 B01 B02 B03 B04 B05 B06 B07 G00 G01 G02 G03 G04 G05 G06 G07 R00 R01 R02 R03 R04 R05 R06 R07 2 B10 B11 B12 B13 B14 B15 B16 B17 G10 G11 G12 G13 G14 G15 G16 G17 R10 R11 R12 R13 R14 R15 R16 R17 3 B20 B21 B22 B23 B24 B25 B26 B27 G20 G21 G22 G23 G24 G25 G26 G27 R20 R21 R22 R23 R24 R25 R26 R27 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... n Bn0 Bn1 Bn2 Bn3 Bn4 Bn5 Bn6 Bn7 Gn0 Gn1 Gn2 Gn3 Gn4 Gn5 Gn6 Gn7 Rn0 Rn1 Rn2 Rn3 Rn4 Rn5 Rn6 Rn7 S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 93 Table 17-3: 18-Bit Data Format (Non-Swapped, REG[14h] bit 7 = 0b) Pin Name VD[23:18] VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 R0 R0 7 Cycle Count 1 2 R17 R16 R15 R14 R13 R12 G17 G16 G15 G14 G13 G12 B17 B16 B15 B14 B13 B12 3 Low R27 R26 R25 R24 R23 R22 G27 G26 G25 G24 G23 G22 B27 B26 B25 B24 B23 B22 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... Rn7 Rn6 Rn5 Rn4 Rn3 Rn2 Gn7 Gn6 Gn5 Gn4 Gn3 Gn2 Bn7 Bn6 Bn5 Bn4 Bn3 Bn2 R06 5 ... n R04 R03 R02 G0 7 G06 G05 G04 G0 3 G02 B07 B06 B05 B04 B03 B02 Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 94 Epson Research and Development Vancouver Design Center Table 17-4: 18-Bit Data Format (Swapped, REG[14h] bit 7 = 1b) Pin Name VD[23:18] VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 B02 B03 B04 B05 B06 B07 G02 G03 G04 G05 G06 G07 R02 R03 R04 R05 R06 R07 B12 B13 B14 B15 B16 B17 G12 G13 G14 G15 G16 G17 R12 R13 R14 R15 R16 R17 Cycle Count 1 2 3 Low B22 B23 B24 B25 B26 B27 G22 G23 G24 G25 G26 G27 R22 R23 R24 R25 R26 R27 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... Bn2 Bn3 Bn4 Bn5 Bn6 Bn7 Gn2 Gn3 Gn4 Gn5 Gn6 Gn7 Rn2 Rn3 Rn4 Rn5 Rn6 Rn7 ... n S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 95 18 SwivelViewTM 18.1 Concept Most computer displays are refreshed in landscape orientation - from left to right and top to bottom. Computer images are stored in the same manner. SwivelViewTM is designed to rotate the displayed image on a LCD by 90, 180, or 270 in a counter-clockwise direction. The rotation is done in hardware and is transparent to the user for all display buffer writes. By processing the rotation in hardware, SwivelViewTM offers a performance advantage over software rotation of the displayed image. The actual address translation is performed during the Host Write and the image data is, therefore, stored in memory in it's rotated orientation. Due to this design of the rotation logic, each Window written to the S1D13743 can be independently rotated with respect to each other. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 96 Epson Research and Development Vancouver Design Center 18.2 90 SwivelView The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13743 in the following sense: A-B-C-D. The display is refreshed in the following sense: B-D-A-C. physical memory start address A B display start address (panel origin) D A SwivelView window C 320 480 image refreshed by the S1D13743 image seen by programmer = image in display buffer Figure 18-1: Relationship Between The Screen Image and the Image Refreshed in 90 SwivelView 18.2.1 Register Programming There are no special programming requirements other than simply enabling the rotation itself (see REG[34h] bits 1-0). All Start Addresses and Line Offsets are automatically calculated by hardware. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 C 320 SwivelView window 480 D B Epson Research and Development Vancouver Design Center Page 97 18.3 180 SwivelView The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13743 in the following sense: A-B-C-D. The display is refreshed in the following sense: D-C-B-A. display start address (panel origin) physical memory start address A SwivelView window C 480 image seen by programmer = image in display buffer D B 320 480 image refreshed by the S1D13743 Figure 18-2: Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView 18.3.1 Register Programming There are no special programming requirements other than simply enabling the rotation itself (see REG[34h] bits 1-0). All Start Addresses and Line Offsets are automatically calculated by hardware. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 320 A S1D13743 X70A-A-001-02 C SwivelView window D B Page 98 Epson Research and Development Vancouver Design Center 18.4 270 SwivelView The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13743 in the following sense: A-B-C-D. The display is refreshed in the following sense: C-A-D-B. physical memory start address A B A C display start address (panel origin) D C 320 image seen by programmer = image in display buffer D 480 image refreshed by the S1D13743 Figure 18-3: Relationship Between The Screen Image and the Image Refreshed in 270 SwivelView 18.4.1 Register Programming There are no special programming requirements other than simply enabling the rotation itself (see REG[34h] bits 1-0). All Start Addresses and Line Offsets are automatically calculated by hardware. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 320 B SwivelView window 480 SwivelView window Epson Research and Development Vancouver Design Center Page 99 19 Host Interface 19.1 Using the Intel 80 Interface Accessing the S1D13743 through the Intel 80 host interface is a multiple step process. All Registers and Memory are accessed through the register space. Note All Register accesses are 8-bit only, except for the Memory Data Port. If the Host interface is 16-bits wide (CNF1 = 1b), the lsbs (MD[7:0]) are used for all registers except the Memory Data Port. For the Memory Data Port (REG[48h, 49h]), both registers are used when the host interface is 16-bits wide (CNF1 = 1b) and only REG[48h] is used when it is 8-bits wide (CNF1 = 0b). First, perform a single "Address Write" to setup the register address. Next, perform a "Data Read/Write" to specify the data to be stored or read from the registers or memory specified in the "Address Write" cycle. Subsequent data read/writes without an Address Write to change the register address, will automatically "auto" increment the register address, or the internal memory address if accessing the Memory Data Port (REG[48h], REG[49h]). To write display data to a Window Aperture, specify the Window coordinates followed by burst data writes to the Memory Data Port to fill the window. In this sequence, the internal memory addressing is automatic (see examples). The Memory Data Port is located directly following the Window coordinates to minimize the number of Address Writes. To read display data, perform an Address Write to the Memory Address Port (3 bytes) and then read data from the Memory Data Port. Sequential reads will auto-increment the internal memory address Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 100 Epson Research and Development Vancouver Design Center 19.1.1 Register Write Procedure 1. Perform an address write to setup register address bits 7-0. 2. Perform a data write to update the register. 3. Additional data writes can be performed as the register addresses will be auto-incremented. CS# D/C# RD# WE# MD[7:0] Address bits 7-0 Write Data Write Data Write Data Write 1 2 3 4 Figure 19-1: Register Write Example Procedure S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 101 19.1.2 Register Read Procedure 1. Perform an address write to setup register address bits 7-0. 2. Perform a data read to get the register value. 3. Additional data reads can be performed as the register addresses will be auto-incremented. CS# D/C# WE# MD[7:0] Write RD# MD[7:0] Read Address bits 7-0 Write Data Read Data Read Data Read 1 2 3 4 Figure 19-2: Register Read Example Procedure Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 102 Epson Research and Development Vancouver Design Center 19.1.3 New Window Aperture Write Procedure The S1D13743 has a special procedure to minimize setup accesses when bursting window data. 1. Set the panel dimension registers before writing any window data. 2. Perform an address write to point to the first window register (Window X Start Position Register 0, REG[38h]). 3. Perform "data" writes to the next eight, 8-bit registers (REG[38h] ~ REG[46h]). This will setup all the window coordinates. Note The register addresses will be auto-incremented after each data write and will point at Memory Data Port Register 0 (REG[48h]) when done. 4. Perform burst data writes to fill the window (the register address will already be pointing at the Memory Data Port). The Memory Data Port Register is located in the 9th register address after the Window X Start Position. Writes to the Memory Data Port will auto-increment the internal memory address only. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 Window X Start Register Address Window X Start Data Window x Start Data Window X End Data Window X End Data Window Y Start Data Window Y Start Data Window Y End Data Window Y End Data Display Data CS# D/C# RD# WE# Figure 19-3: Sequential Memory Write Example MD[7:0] Revision 2.7 S1D13743 X70A-A-001-02 Page 103 Page 104 Epson Research and Development Vancouver Design Center 19.1.4 Opening Multiple Windows 1. Repeat the steps outlined in Section 19.1.3, "New Window Aperture Write Procedure" on page 102 with new window coordinates for each new window. 2. Non-pixel doubled windows can overlap with the last one being written considered the top. 19.1.5 Update Window using existing Window Coordinates 1. Perform an address write to point to Memory Data Port Register 0 (REG[48h]). 2. Perform burst data writes to fill the window. Note In this case, the previous coordinates of the Window Aperture are used. Each write to the Memory Data Port will auto-increment the internally memory address only. 19.1.6 Individual Memory Location Reads Note This function is for test purposes only and serves no practical use in a system. 1. Write the physical address of the memory location to read from to the Memory Read Address Registers (REG[4Ah] ~ REG[4Eh]). For a 16-bit bus, the LSB of this address is ignored. 2. Perform a read from the Memory Data Port (REG[48h] ~ REG[49h]). 3. Continuous reads from the Memory Data Port will cause the address in the Memory Read Address registers to increment, thereby supporting burst reads. Note To access the 8 lsb's for each 24-bit value, you must know the physical address as they are stored at different locations as compared to the upper 16-bits. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 105 20 Double Buffering 20.1 Double Buffer Controller Double buffering is provided to prevent tearing of streaming video data. All static (nonvideo) image data will always be written to the upper half (Buffer 1) of the frame buffer. When video is being input, the first frame will be written to the lower half (Buffer 2) of the double buffer. The second frame will be written to Buffer 1. While video data is being input, the static part of the image going to the LCD will still always come from Buffer 1. The source of the video window will come from either Buffer 1 or Buffer 2, depending on which one was the last to be completely updated. The switching of the buffer read/write pointers can only occur once per frame, at the beginning of the vertical non-display period. The pointers will only switch if: a video frame had completed being updated within the last output frame period, and no new video frame is currently being written. Because of this, each time the user finishes writing a frame of video data, they should wait until the next vertical non-display period before writing the next frame. This can be accomplished by using the TE pin or by polling the Vertical Display Period Status (REG[58h] bit 7). Alternatively, if the user can guarantee that the maximum input video frame rate is 1/2 the LCD frame rate and that the burst length for writing a video frame is less than one LCD frame period, then no checking for the vertical non-display period is required. If attention is not paid to allowing the pointers to switch, then frames may be dropped. Switch buffer pointers since a frame completed being updated in the last LCD frame period Switch buffer pointers since a frame completed being updated in the last LCD frame period Switch buffer pointers since a frame completed being updated in the last LCD frame period Don't switch buffer pointers since a frame is currently being written. Vertical Non-Display Period Input Video Frame Burst Read Buffer Pointer Write Buffer Pointer Figure 20-1: Switching of Buffer Pointers To use the double buffer feature: * Set appropriate bits in the Special Effects Register, REG[36h] bits 7-6 to 11b. * Setup the Window Position Registers, REG[38h] ~ REG[46h]. * Write the video data to the Memory Data Port, REG[48h] ~ REG[49h]. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 106 Epson Research and Development Vancouver Design Center It is also possible to update a static window while double buffering is enabled, even in the middle of a video stream. To do this: * Write the last pixel of the current frame of video data. * Set the appropriate bits in the Special Effects Register, REG[36h] bits 7-6 to 01b. * Setup the Window Position Registers, REG[38h] ~ REG[46h]. * Write the static data to the Memory Data Port, REG[48h] ~ REG[49h]. This allows a static image to be written at any time, while still preventing the double buffered window from tearing. Once the static window has been written, the user can go back to writing the streaming video data by following the steps described above for using the double buffer feature. Buffer 1 Background image Buffer 1 Background image Output Input Buffer 1 Input Background image Buffer 1 PIP Background image Output Output Output Buffer 2 Buffer 2 Buffer 2 Buffer 2 Input Time 1: The main/background image is in Buffer 1. Buffer 2 is empty. The data output to the LCD comes entirely from Buffer 1. Time 2: The main/background image is in Buffer 1. Buffer 2 is written with video data. The data output to the LCD comes entirely from Buffer 1. Time 3: The main/background image is in Buffer 1, but part of this data is destructively overwritten by the second frame of video data. The static image data from Buffer 1 is sent to the LCD, but the video window comes from Buffer 2. Time 4: A static PIP is destructively written into Buffer 1. Since the most recently updated video frame is in Buffer 1, the entire image output to the LCD comes from Buffer 1. There may be tearing in the PIP window, but the video window will not tear. Figure 20-2: Double Buffer Example S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 107 20.2 Double Buffering Limitations There are some limitations to double buffering: * Consider the case where there is a video stream being input and the user wants to place a static PIP over all or some part of the video window. The user can write the PIP, but when the video stream is continued, it will destructively overwrite the PIP, so that it will appear as though the PIP is under the video window. * Consider the case where there is a video stream which stops after the last frame of video is sent. The final frame of video will continue to be displayed on the LCD. Assume that this last frame is stored in Buffer 2. Now, if the user disables double buffering, the buffer read pointer will immediately reset to Buffer 1. This means that the 2nd to last frame will now be displayed instead of the last frame. * The user must either wait for a vertical non-display period between writing frames of video data, or guarantee that their maximum input frame rate is 1/2 the LCD frame rate and that the length of time it takes to burst write a frame of video data is less than one LCD frame period. * Only one window can be double buffered at a time. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 108 Epson Research and Development Vancouver Design Center 21 Interfacing the S1D13743 and a TFT Panel This section describes the hardware and software environment required to interface the S1D13743 Mobile Graphics Engine and a 352x416 TFT Panel. The designs described in this section are presented only as examples of how such interfaces might be implemented. 21.1 Overview The S1D13743 was designed to directly support the Sanyo LC13015 and requires no additional hardware and minimal programming. The S1D13743 register settings and electrical interface is described below. 21.1.1 Electrical Interface Table 21-1: Pin Mapping S1D13743 Pin Name HS VS PCLK DE VD[17:0] S1D13743 Pin Number D9 D10 D11 C11 J8, J9, J10, J11, K4, K5, K6, K7, K8, K9, K10, L3, L4, L5, L6, L7, L8, L9 LCD13015 Pin Name HS VS PCLK DE R5, R4, R3, R2, R1, R0, G5, G4, G3, G2, G1, G0, B5, B4, B3, B2, B1, B0 S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 109 21.1.2 S1D13743 Register Settings for 352x416 TFT Panel Note The registers listed below are only those associated with panel specific timing issues All other registers are not shown here. Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line. Table 21-2: Example Register Settings for 352x416 TFT Panel Register All REG[56h] REG[04h] REG[06h] REG[08h] REG[0Ah] REG[0Ch] REG[0Eh] REG[12h] REG[14h] REG[16h] REG[18h] REG[1Ah] REG[1Ch] REG[1Eh] REG[20h] REG[22h] REG[24h] REG[26h] REG[28h] REG[2Ah] REG[56h] REG[04h] bit 7 REG[38h] REG[3Ah] REG[3Ch] REG[3Eh] REG[40h] REG[42h] Value default 02h 12h F8h 80h 28h 00h 2Fh 19h 0h 2Ch 5Ah A0h 01h 06h 14h 2Dh 02h 01h 80h 01h 00h -- 00h 00h 00h 00h 5Fh 01h LL = 48, resulting SYSCLK = LL x PLL input clock = 48MHz set PCLK divide, PCLK = 12.1MHz set SYSCLK source = PLL no panel data swap, 18-bit panel HDP = 352 pixels HNDP = 90 pixels VDP = 416 lines VNDP = 6 lines HS Pulse Width = 20 pixels HS Start Position = 45 pixels VS Width = 2 lines VS Start Position (VFP) = 1 line PCLK Polarity: data output on falling edge set input data mode to RGB 5:6:5 disable sleep mode wait for PLL to lock - poll REG[04h] bit 7 Window X Start Position = 0 Window Y Start Position = 0 Window X End Position = 351 Comment Come out of reset - all registers set to default values enter sleep mode (or use PWRSVE pin) set PLL M-Divider. CLKI = 19.2MHz, PLL input clock = CLKI/19 = 1.01MHz. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 110 Epson Research and Development Vancouver Design Center Table 21-2: Example Register Settings for 352x416 TFT Panel (Continued) Register REG[44h] REG[46h] REG[48h] REG[49h] Value 9Fh 01h Comment Window Y End Position = 415 Write the image data to the Memory Data Port, REG[48h] and REG[49h]. The image will immediately begin to appear on the LCD. Note The above values are intended as examples. This example assumes that CLKI = 19.2MHz and that the PLL is used to generate SYSCLK. Actual settings can vary and still remain within the LCD panel timing requirements. S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 111 21.2 Host Bus Timing D/C# 1/2IOVDD 1/2IOVDD tast tcs CS# 1/2IOVDD taht 1/2IOVDD tcsf tcsf twrl twc WE# 1/2IOVDD 1/2IOVDD 1/2IOVDD twrh 1/2IOVDD tdst MD[15:0] write 1/2IOVDD tdht 1/2IOVDD trcs trc trdl RD# 1/2IOVDD taht 1/2IOVDD trdh todh 1/2IOVDD trat MD[15:0] read tddt Note: The D/C# input pin is used to distinguish between Address and Data. Note: The register address will auto-increment in word increments for all register access except the Gamma Correction Table Data register and Memory Data Port. Writes to the Gamma Correction Table Data register and Memory Data Port will not increment the register address to support burst data writes to the gamma correction table and to memory. Figure 21-1: Intel 80 Input A.C. Characteristics Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 112 Epson Research and Development Vancouver Design Center 21.2.1 Host Bus Timing for 352x416 TFT Panel Table 21-3: Intel 80 Input A.C. Characteristics (352x416 Panel Timings) Signal D/C# Symbol tast taht tcs CS# trcs tcsf twc WE# twrh twrl trc RD# trdh trdl tdst tdht trat (See note) todh (See note) tddt (See note) Parameter Address setup time Address hold time Chip Select setup time (write) Chip Select setup time (read) Chip Select Wait time Write cycle (rising edge to next rising edge) Pulse high duration Pulse low duration Read cycle for Registers Read cycle for Memory Read cycle for LUT Pulse high duration Pulse low duration for Registers Pulse low duration for Memory Pulse low duration for LUT Data setup time Data hold time Read falling edge to Data valid for Registers Read falling edge to Data valid for Memory Read falling edge to Data valid for LUT Read hold time Read falling edge to Data driven MD[15:0] Min 1.4 0.3 0.6 + twrl 1.3 + trdl 9.2 42.6 Note 1 0.1 42.6 122.1 + trdh 108.1 + trdh Note 2 10.2 122.1 108.1 0.3 6.4 -- -- -- 10.7 3.0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12.2 122.1 108.1 32.1 12.3 ns ns ns ns ns ns ns ns ns ns For maximum CL=30pF For minimum CL=8pF ns ns ns ns Unit Description ns ns ns ns ns ns SYSCLK = 48MHz, PCLK = 12MHz, CLKI = 12MHz 1. twrh min = long enough to satisfy twc 2. trdh min = long enough to satisfy trc S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 113 21.3 Panel Timing t1 t2 VS t3 HS t4 HS t5 t6 DE t9 t10 t11 PCLK REG[28h] bit 7=1 t9 t10 t11 PCLK REG[28h] bit 7=0 t15 t16 VD[17:0] invalid 1 Note: 1 pixel/clock Mode 2 320 invalid t12 t13 t14 t12 t13 t14 t7 t8 Figure 21-2: 18-Bit TFT A.C. Timing Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 114 Epson Research and Development Vancouver Design Center 21.3.1 Panel Timing for 352x416 Panel Table 21-4: 18-Bit TFT A.C. Timing (352x416 Panel Timing) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 Parameter VS cycle time VS pulse width low VS falling edge to HS falling edge phase difference HS cycle time HS pulse width low HS Falling edge to DE active DE pulse width DE falling edge to HS falling edge PCLK period PCLK pulse width low PCLK pulse width high HS setup to PCLK falling edge DE to PCLK rising edge setup time DE hold from PCLK rising edge Data setup to PCLK rising edge Data hold from PCLK rising edge Min -- -- 0 -- -- -- -- -- 83.3 41.7 41.7 41.7 41.7 41.7 41.7 41.7 Typ 15.54 73.67 -- 36.83 1.67 3.75 29.3 3.75 -- -- -- -- -- -- -- -- Max -- -- 36.75 -- -- -- -- -- -- -- -- -- -- -- -- -- Units ms us us us us us us us ns ns ns ns ns ns ns ns 1. Ts = pixel clock period = 83.3 ns (12MHz PCLK) 21.4 Example Play.exe Scripts The following example scripts are written for the PLAY.EXE program. The script Demo.txt will initialize the S1D13743, then display horizontal bars at different rotations, and then display a PIP+ window. Demo.txt verbose cmd:off out:on set:off halt 0 '============================================================================== ' _DEMO_.txt - Play script for 13743 to demonstrate various features. ' ' This demonstration code is written in the Play.exe script language so that ' various steps can be easily observed. Some steps such as the initialization ' and the memory fills use Play intrinsic commands. These operation of these ' commands are easily determined. '============================================================================== ' Initialize the registers to the default state by ' running the register list generated by 13743CFG '---------------------------------------------------------init ' Set the window to the full screen and clear the display '---------------------------------------------------------SetWin.txt S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 115 f WIN 0 ' ROTATE 0 '---------------------------------------------------------print "Color bars at SwivelView 0\n" x 34 0 DrawBarsA.txt Pause.txt ' ROTATE 90 ' NOTE: There is a bug with the Fill WINdow command in ' Play which causes the 90 and 270 degree fills ' to be filled incorrectly. This will be corrected. '---------------------------------------------------------print "Color bars at SwivelView 90\n" x 34 1 DrawBarsB.txt Pause.txt ' ROTATE 180 '---------------------------------------------------------print "Color bars at SwivelView 180\n" x 34 2 DrawBarsA.txt Pause.txt ' ROTATE 270 ' NOTE: There is a bug with the Fill WINdow command in ' Play which causes the 90 and 270 degree fills ' to be filled incorrectly. This will be corrected. '---------------------------------------------------------print "Color bars at SwivelView 270\n" x 34 3 DrawBarsB.txt Pause.txt ' PIP '---------------------------------------------------------print "Draw Color bars in a PIP (small window)\n" x 34 0 SetWin.txt f WIN 0 DrawBarsA.txt DrawPIP.txt 50 50 100 128 Pause.txt section END Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 116 Epson Research and Development Vancouver Design Center DrawBarsA.txt verbose cmd:off out:on set:off '============================================================================== ' DrawBars.txt - Play script for the 13743 ' ' This script draws eight equally sized horizontal ' bars on the display. '============================================================================== set set set set set set $Height $Lines $StartX $StartY $EndX $EndY ((reg[1C] << 8) + (reg[1A])) ($Height / 8) 0 0 width $Lines 0 8 set $Color set $Bars section LOOP SetWin.txt $StartX $StartY $EndX $EndY f WIN $Color set $StartY ($StartY + $Lines) set $EndY ($EndY + $Lines) set $Color ($Color + 0821) set $Bars ($Bars - 1) if $Bars!=0 then goto LOOP S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 117 DrawBarsB.txt verbose cmd:off out:on set:off '============================================================================== ' DrawBarsB.txt - Play script for the 13743 ' ' This script draws horizontal bars in SwivelView 90 and SwivelView 270 ' display modes. '============================================================================== set set set set set set $Height $Lines $StartX $StartY $EndX $EndY (reg[16] * 8) ($Height / 8) 0 0 height $Lines 0 8 set $Color set $Bars section LOOP SetWin.txt $StartX $StartY $EndX $EndY f WIN $Color set $StartY ($StartY + $Lines) set $EndY ($EndY + $Lines) set $Color ($Color + 0821) set $Bars ($Bars - 1) if $Bars!=0 then goto LOOP Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 118 Epson Research and Development Vancouver Design Center DrawPIP.txt verbose cmd:off out:on set:off '============================================================================== ' DrawPIP.txt - Play script for the 13743 ' ' This script draws eight equally sized horizontal bars on the display. '============================================================================== set set set set $StartX arg[1].nt $StartY arg[2].nt $Width arg[3].nt $Height arg[4].nt set $Lines ($Height / 8) set $Color set $Bars 0 8 section LOOP SetWin.txt $StartX f WIN $Color set $StartY ($StartY + $Lines) set $Color ($Color + 0821) set $Bars ($Bars - 1) if $Bars!=0 then goto LOOP $StartY $Width $Lines Pause.txt verbose cmd:off out:on set:off halt 0 print "Paused . . . press any key to continue\n" input line S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 119 SetWin.txt verbose cmd:off out:on set:off '-----------------------------------------------------------------------------' SetWin.txt - Play script for the 13743 ' ' This script is functionally identical to the Play command 'win'. Call this ' script to set the 13743 window co-ordinates as specified by the arguments. ' ' Syntax: SetWin X Y W H ' Where: X - Left edge window X position ' Y - Top edge window Y position ' W- Window width ' H - Window height ' ' Example: SetWin 0 0 100 100 ' Sets the window to start at 0,0 and end at 100, 100 ' ' SetWin ' Sets the window size to the size of the display ' ' win SX:0 SY:0 EX:width EY:height '-----------------------------------------------------------------------------' Set the default window values to the display size. set $SX 0 set $SY 0 set $EX (width - 1) SET $EY (height - 1) ' Use non-default values ONLY if all four arguments are given if (argn!=5) then goto SETWINDOW set set set set $SX $SY $EX $EY arg[1].n arg[2].n (arg[1].n + arg[3].n - 1) (arg[2].n + arg[4].n - 1) section SETWINDOW ' Change the register window settings x 38 $SX x 3A ($SX >> 8) x 3C $SY x 3E ($SY >> 8) x 40 $EX x 42 ($EX >> 8) x 44 $EY x 46 ($EY >> 8) Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 120 Epson Research and Development Vancouver Design Center 22 PLL Power Supply Considerations The PLL circuit is an analog circuit which is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The following are guidelines which, if followed, will result in cleaner power to the PLL, this will result in a cleaner and more stable clock. Even a partial implementation of these guidelines will give results. 22.1 Guidelines for PLL Power Layout The PLL circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The following are guidelines which, if followed, will result in cleaner power to the PLL, resulting in a cleaner and more stable clock. Even a partial implementation of these guidelines will give results. Optional, but recommended To Digital IOVDD Plane L1 Voltage Regulator PLL power traces must split from the digital traces very close to the regulator C3 C2 PLLVDD C1 S1D13743 PLLVSS L2 To Digital VSS Plane Notes: * PLLVDD and PLLVSS traces should be as short as possible * PLLVDD and PLLVSS must be separated from the digital supply * Digital power and ground to L1 and L2 should be short parallel traces on the same side of the board to reduce any loop area that can induce noise Typical Values: L1, L2 isolation bead C1 ~10uf bypass C2 1nf bypass C3 .1uf bypass Actual values may be different and subject to validation Figure 22-1: PLL Power Layout S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 121 * Place the ferrite beads (L1 and L2) parallel to each other with minimal clearance between them. Both bypass caps (C2 and C3) should be as close as possible to the inductors. The traces from C3 to the power planes should be short parallel traces on the same side of the board with just the normal small clearance between them. Any significant loop area here will induce noise. If there is a voltage regulator on the board, try to run these power traces directly to the regulator instead of dropping to the power planes (still follow above rules about parallel traces). * The analog ground point where bypass cap (C2) connects to the ground isolation inductor (L2) becomes the analog ground central point for a ground star topology. None of the components connect directly to the analog ground pin of the MGE (PLLVSS) except for a single short trace from C2 to the PLLVSS pin. The ground side of the large bypass capacitor (C1) should also have a direct connection to the star point. * The same star topology rules used for analog ground apply to the analog power connection where L2 connects to C2. * All of the trace lengths should be as short as possible. * If possible, have all the PLL traces on the same outside layer of the board. The only exception is C1, which can be put on the other side of the board if necessary. C1 does not have to be as close to the analog ground and power star points as the other components. * If possible, include a partial plane under the PLL area only (area under PLL components and traces). The solid analog plane should be grounded to the C2 (bypass) pad. This plane won't help if it is too large. It is strictly an electrostatic shield against coupling from other layers' signals in the same board area. If such an analog plane is not possible, try to have the layer below the PLL components be a digital power plane instead of a signal layer. * If possible, keep other board signals from running right next to PLL pin vias on any layer. * Wherever possible use thick traces, especially with the analog ground and power star connections to either side of C2. Try to make them as wide as the component pads - thin traces are more inductive. It is likely that manufacturing rules will prohibit routing the ground and power star connections as suggested. For instance, four wide traces converging on a single pad could have reflow problems during assembly because of the thermal effect of all the copper traces around the capacitor pad. One solution might be to have only a single trace connecting to the pad and then have all the other traces connecting to this wide trace a minimum distance away from the pad. Another solution might be to have the traces connect to the pad, but with thermal relief around the pad to break up the copper connection. Ultimately the board must also be manufacturable, so best effort is acceptable. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 122 Epson Research and Development Vancouver Design Center 23 Mechanical Data TOP VIEW 8.00.20 A1 corner Die Size Die Size 0.65 L K J H G F E D C B A A1 corner 1 2 3 4 5 6 7 8 9 1011 0.75 0.65 0.30.05 BOTTOM VIEW 0.23 0.75 SIDE VIEW 1.0 max. 8.00.20 units = mm Figure 23-1: S1D13743 FCBGA 121-pin Package S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 123 HD D 108 109 73 72 INDEX 144 1 36 c A1 yS L L1 Symbol E D HE HD Amax A1 A2 e b c Dimension in Millimeters Min -- -- -- -- -- -- -- -- 0.17 0.09 0 0.3 -- -- Nom 20 20 22 22 -- 0.1 1.4 0.5 -- -- -- -- 1 -- Max -- -- -- -- 1.7 -- -- -- 0.27 0.2 10 0.75 -- 0.08 37 A2 Amax e b L L1 y HE E units = mm Figure 23-2: S1D13743 QFP20 144-pin Package Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 124 Epson Research and Development Vancouver Design Center Number of row and column not fixed units = mm Y Package Center Line Index Mark 2.78 1.88 D743 (13) B (1) (4) 2.63 1.73 D D D B (14) (5) 21.95 0.8 JAP AN (15) (20) (6) B B (21) (16) (7) X X' 1.05 B B B D EE D (17) (22) (23) (24) (8) (18) (19) (9) (10) A = 0.3 B = 0.4 C = 0.6 D = 0.1 E = 0.05 C A C A C A 0.74 Package Center Line Item Logo Specified Device Name Die Revision Code Package Type Process and Package Revision Code [Blank] Control Code Year of Manufacture Month of Manufacture W/F Lot No. JAPAN No. (1) (2) ~ (5) (6) (7) (8) (9) ~ (10) (10) ~ (16) (11) (12) (13) ~ (16) (17) ~ (21) Y' Notes C: FCBGA Last number of A.D. 1-9: JAN-SEP X: OCT, Y: NOV, Z: DEC Figure 23-3: S1D13743 FCBGA 121-pin Package Marking S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 125 units = mm Y X X' Y Package Center Line Pin 1 Y' 8.0 (1) 0.3 (2) 2.0 (3) (4) (5) (6) 1.2 AB A B A B A B A X (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) A X' 1.5 A C B C B C B C B C B C BD DB C B C B C B C B C B C (20) (21) (22) (23) (24) (25) (26) (27) (28) 1.2 Package Center Line AB AB A B A B A B AB A B A B A Y' A = 0.8 B = 0.25 C = 1.0 D = 0.5 Item Logo Specified JAPAN Device Name Control Code Year of Manufacture Week of Manufacture W/F Lot No. No. (1) (2) ~ (6) (7) ~ (19) (20) ~ (28) (21) ~ (22) (23) ~ (24) (25) ~ (28) Notes EPSON S1D13743F00A2 Last two numbers of A.D. Calendar Week of the Year Figure 23-4: S1D13743 QFP 144-pin Package Marking Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 126 Epson Research and Development Vancouver Design Center 24 References The following documents contain additional information related to the S1D13743. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. * S1D13743 Product Brief (X70A-C-001-xx) * S5U13743P00C100 Evaluation Board User Manual (X70A-G-001-xx) S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 127 25 Sales and Technical Support AMERICA EPSON ELECTRONICS AMERICA, INC. 2580 Orchard Parkway San Jose , CA 95131,USA Phone: +1-800-228-3964 ASIA EPSON (CHINA) CO., LTD. 7F, Jinbao Bldg., No.89 Jinbao St., Beijing 100005, CHINA Phone: +86-10-8522-1199 FAX: +86-10-8522-1125 FAX: +1-408-922-0238 SHANGHAI BRANCH EUROPE EPSON EUROPE ELECTRONICS GmbH Riesstrasse 15, 80992 Munich, GERMANY Phone: +49-89-14005-0 FAX: +49-89-14005-110 7F, Block B, High-Tech Bldg., 900, Yishan Road, Shanghai 200233, CHINA Phone: +86-21-5423-5577 FAX: +86-21-5423-4677 SHENZHEN BRANCH 12F, Dawning Mansion, Keji South 12th Road, Hi-Tech Park, Shenzhen 518057, CHINA Phone: +86-755-2699-3828 FAX: +86-755-2699-3838 EPSON HONG KONG LTD. 20/F, Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 FAX: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 FAX: +65-6271-3182 SEIKO EPSON CORP. KOREA OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: +82-2-784-6027 FAX: +82-2-767-3677 SEIKO EPSON CORP. SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept. IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 FAX: +81-42-587-5117 25.1 Ordering Information To order the S1D13743 Mobile Graphics Engine, contact the Epson sales representative in your area. Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 128 Epson Research and Development Vancouver Design Center Change Record X70A-A-001-02 Revision 2.7 - Issued: 2010/05/18 * section 4.2.3 Clocks - remove "Input frequency range: 1MHz ~ 33MHz" from CLKI description * section 7.1.1 Input Clocks - in table 7-1 Clock Input Requirements (CLKI), change fosc Input clock frequency - PLL used for System Clock max value to "33" from "66" X70A-A-001-02 Revision 2.6 - Issued: 2009/09/29 * all changes from the last revision are highlighted in Red * section 6.3 Electrical Characteristics - in Table 6-4, change Operational Peak Current max value to "74 uA" * section 7.4.3 Generic 18/24-Bit TFT Panel Timing - in figure 7-10, 18/24-Bit TFT A.C. Timing, remove references to 1 pixel/clock and 2 pixel/clock modes, remove VD[23:0] timing waveform, add VD[23:0] to VD[17:0] timing waveform * section 8 Memory - for Tables 8-1 and 8-2, change red data to odd addresses and green data to even addresses * section 9.4 Setting SYSCLK and PCLK - add CLKI information to this section * section 9.4 Setting SYSCLK and PCLK - remove "5 x 9.5" from "For example, if the..." * section 23 - in Figure 23-1, change Side View ball height to 0.23mm * section 26 Sales and Technical Support - changes to Epson offices and addresses X70A-A-001-02 Revision 2.5 - Issued: 2008/05/07 * all changes from the last revision are highlighted in Red * Set revision to 2.5 to align with Japan revision numbering * section 8 Memory - add this section and renumber all following sections * REG[48h] ~ REG[49h] - remove "The data read back from memory will be byte swapped (i.e. if 12 34 56 78 is written to memory, data read back will be 34 12 78 56)" from the first note * REG[4Ah] ~ REG[4Eh] - add note "If 16-bit interface is used (CNF1 = 1), all reads will..." * section 12 RGB Input Data Conversion - delete paragraph "The actual data storage is complex due to the memory structure..." and add reference to section 8 X70A-A-001-02 Revision 2.04 - Issued: 2007/09/18 * all changes from the last revision of the spec are highlighted in Red * section 7.3.1 ~ 7.3.2, added note and clarified the usage of MD[15:8] pins in the Host Timing figures and tables S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 129 * section 18.1.3, updated the X/Y Start/End data order in the Sequential Memory Write Example Sequence figure and moved it to section 18.1.3 * section 24, added References * section 25, added Sales and Technical Support addresses X70A-A-001-02 Revision 2.03 (Issued 2006/09/25) * all changes from the last revision of the spec are highlighted in Red * section 11 RGB Input Data Conversion - add this section and re-number following sections X70A-A-001-02 Revision 2.02 (Issued 2006/08/23) * all changes from the last revision of the spec are highlighted in Red * globally add QFP20 144-pin package information * section 4.2.4 Miscellaneous - change PWRSVE pin Powersave status to "Pull-down Active" and change description to "This pin has an internal..." * section 5.2 LCD Interface Data Pins - correct typos in table 5-3, change Hi-Z to Driven Low * section 6.3 Electrical Characteristics - add table 6-4 Electrical Characteristics for IOVDD or PIOVDD = 3.3V 0.3V * section 7.2 RESET# Timing - add CLKI signal to figure * section 7.3.1 Intel 80 Interface Timing - 1.8 Volt - rewrite section for 1.8 volts * section 7.3.2 Intel 80 Interface Timing - 3.3 Volt - add this section X70A-A-001-02 Revision 2.01 (Issued 2006/04/28) * all changes from the last revision of the spec are highlighted in Red * updated EPSON tagline * section 4.2.1 Intel 80 Host Interface - for GPIO_INT add reference to General Purpose IO Pins Registers to pin description. * section 4.2.4 Miscellaneous - for GPIO[7:0] rewrite pin description, for PWRSVE rewrite pin description for no pull-down resistor * section 4.2.4, change SCANEN pin description IO Voltage from "VSS" to "IOVDD" * section 7.2 RESET# Timing - add this section * section 17.1.2, for the Host Interface section changed the references in the figure from "D[15:0]" to "MD[15:0]" X70A-A-001-02 Revision 2.0 * section 6.3 Electrical Characteristics - in table 6-3, define the conditions for Quiescent Current X70A-A-001-01 Revision 1.07 Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 130 Epson Research and Development Vancouver Design Center * All changes from the previous Revision are in red * section 7.3.3 Generic 18/24-Bit TFT Panel Timing - correct typos in section, change 36bit to 24-bit, change VD[35:0] to VD[23:0] in figure X70A-A-001-01 Revision 1.06 * All changes from the previous Revision are in red text * section 6.3 Electrical Characteristics - table 6-3 Electrical Characteristics for IOVDD or PIOVDD = 1.8V 0.15V, break PTotal out to separate power types (PCORE, PPLL, PPIO, PHIO) and make change to note under table X70A-A-001-01 Revision 1.05 * figure 21-2 S1D13743 Package Marking - add process condition change to Package Revision Code * table 21-1 S1D13743 Product Marking - add ES information to table * section 22 ESD Test Results - add this section X70A-A-001-01 Revision 1.04 * section 6.3 Electrical Characteristics - add max value for ICORE and rewrite note at bottom of table X70A-A-001-01 Revision 1.03 * section 21 Mechanical Data - Table 21-1 S1D13743 Product Marking, correct typo in second row first column - change TS1 to TS2 X70A-A-001-01 Revision 1.02 * section 21 Mechanical Data - add Table 21-1 S1D13743 Product Marking X70A-A-001-01 Revision 1.01 * section 21 Mechanical Data - add Figure 21-2 S1D13743 Package Marking X70A-A-001-01 Revision 1.0 * Release as Revision 1.0 (2005/01/18) X70A-A-001-00 Revision 0.07 * section 4.2.2 LCD Interface - change PCLK RESET# State to CLKI * section 6 D.C. Characteristics - add PIOVDD to tables and update Table 6-3 Electrical Characteristics, change section 6.2 note "There are no special Power On/Off requirements..." and add section 6.3 note "1. Typical Operating Current Environment..." * section 7.3.3 18/24-Bit TFT Panel Timing - add t17 and t18 to figure and table, remove t3 min and max, change t3 typ to "HPS", and correct typo - t8 typ to "HPS" from "HSS" in table * section 8.4 Setting SYSCLK and PCLK - change first equation to "14.94ns < TSYSCLK < (TBBC - 0.976) x 0.485ns" from "14.94ns < TSYSCLK < (TBBC - 0.976) / 2.06ns" S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 131 * REG[04h] - change register name from "PLL M-Divider Register 0" to "PLL M-Divider Register" * REG[18h] - change minimum register value in note to 3 * REG[2Ah] - add note "For YUV 4:2:2 and YUV 4:2:0 settings, the width..." * REG[2Ah] - add note "RGB 6:6:6 mode 2 and RGB 8:8:8 mode 2..." * REG[34h] bits 6-4 - for 000b change FRM Mode Selected to Normal Mode, and add note "When the output is 24 bpp..." * REG[36h] bit 7 - add note "While double buffering is enabled..." * REG[36h] bit 6 - add note "While double buffering is enabled..." * REG[48h] ~ REG[49h] - add note "Data read back from memory will be byte swapped" * REG[56h] bit 1, fixed reference to REG[56h] bit 7 state, should be "Sleep mode can also be controlled by the PWRSVE pin when REG[56h] bit 7 = 0b." instead of "Sleep mode can also be controlled by the PWRSVE pin when REG[56h] bit 7 = 1b." * REG[56h] bit 0, fixed reference to REG[56h] bit 7 state, should be "Standby mode can also be controlled by the PWRSVE pin when REG[56h] bit 7 = 1b." instead of "Standby mode can also be controlled by the PWRSVE pin when REG[56h] bit 7 = 0b." * REG[58h] bit 6 - swap "When this bit =..." descriptions * REG[58h] bit 5 - rename bit to "VP OR'd with HDP Status (Read Only)" * section 12 Intel 80, 16-bit Interface Color Formats - remove color from all Figures in section * section 13 YUV Timing - add format definition to this section * section 13 YUV Timing - remove color from all Figures in section * section 13.1 YUV 4:2:2 with Intel 80, 8-bit Interface, figure 13-1, correct U, V figure * section 15 Display Data Format - Table 15-3 18-Bit Data Format (Non-Swapped, REG[14h] bit 7 = 0b), and Table 15-4 18-Bit Data Format (Swapped, REG[14h] bit 7 = 1b) change VD[23:18] value from Hi-Z to Low * section 19.1.2 S1D13743 Register Settings for 352x416 TFT Panel - change REG[06h] value to F8h and REG[0Ah] value to 28h * section 19.1.2 S1D13742 Register Settings for 352x416 TFT Panel - add note "When a window is setup for YUV data..." X70A-A-001-00 Revision 0.06 * figure 4-1, changed "S1D13743 Proposed Pinout..." to "S1D13743 Pinout..." * section 7.1.1 Input Clocks - Table 7-1 Clock Input Requirements (CLKI) - change fOSC Input clock frequency - PLL used for System Clock max to 66 MHz * section 7.3, corrected the formulas for HNDP (should be "REG[18h] bits 6-0" instead of "REG[18h] bits 5-0"), HSW (should be "REG[20h] bits 6-0" instead of "REG[20h] bits 5-0"), and VSW (should be "REG[24h] bits 5-0" instead of "REG[24h] bits 6-0") Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 132 Epson Research and Development Vancouver Design Center * section 7.3.1, added information about PWRSVE pin to TFT Power-On sequence note 1 * section 7.3.1, in second note changed LCD pins VD[35:0] to VD[23:0] * section 7.3.2, added information about PWRSVE pin to TFT Power-Off sequence note 1 * section 7.3.2, in second note changed LCD pins VD[35:0] to VD[23:0] * section 7.3.3, added 18-bit panel data (VD[17:0]) * section 7.3.3, fixed REG reference for PCLK Polarity, should be "REG[28h] bit 7" instead of "REG[2Ah] bit 7" * section 8.1, removed arrow pointing down from the Clock Source Select * section 9.2, added register set summary table * REG[04h] bits 5-0, updated the M-Divide Ratio table to read "REG[04h] bits 5-0" instead of "bits 6-0" and changed the maximum value from 7Fh to 3Fh * REG[06h] ~ REG[0Ch], changed the bit descriptions for the PLL Setting Registers 0-3, reserved all individual bit descriptions and added specific programming values for each register * REG[14h] bit 7, combined the note under the VD Data Swap bit into the main bit description and added references to the exact tables * REG[2Ah] - remove text "bit 7-4 Reserved" * REG[2Ch] bit 6, updated the YRC Reset bit description * REG[34h] bit 7, updated the Display Blank bit description * REG[48h] ~ REG[49h], changed the default value for the Memory Data Port Registers to "not applicable" * REG[54h], changed the default value for the Gamma Correction Table Data Register to "not applicable" * REG[58h] bit 4, updated the YYC Last Line bit description and removed reference to the MESSI interface (should be Intel 80 interface) * REG[5Ah] ~ REG[64h], minor wording clarifications to the GPIO registers * section 10, changed "Horizontal Period" to "Horizontal Display Width" and "Vertical Period" to "Vertical Display Height" * section 10, added cross reference to Display Interface timing section for Panel Timing Parameter definitions * section 11, updated the Intel 80, 8-bit Interface Color Formats diagrams to use the proper 13743 pin names * section 12, updated the Intel 80, 16-bit Interface Color Formats diagrams to use the proper 13743 pin names * section 13, updated the YUV Timing diagrams to use the proper 13743 pin names * section 14, added data input to LUT S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 Epson Research and Development Vancouver Design Center Page 133 * section 14.1, reworded some of the steps in the Gamma Correction Programming Example * section 17, minor wording changes to clarify the Host Interface usage examples X70A-A-001-00 Revision 0.05 * section 7.1.1 Input Clocks - Table 7-1 Clock Input Requirements (CLKI) - change Input clock frequency - PLL max to 66.53 MHz, and Input clock frequency - CLKI max to 68.59 MHz. * section 7.1.2 PLL Clock - change all PLL output min to 44.28 MHz. and all PLL output max to 66.53 MHz, * section 7.2.1 Intel 80 Interface Timing - Table 7-3 Intel 80 Input A.C. Characteristics change todh min to 11.0, and tddt min to 2.7 and max to 18.0 * section 8.4 Setting SYSCLK and PCLK - change first equation to "15.03ns < TSYSCLK < (TBBC - 0.976) / 2.06 ns", second equation to "15.03ns < TSYSCLK < 22.584ns", and third equation to "44.28MHz < fSYSCLK < 66.53MHz" X70A-A-001-00 Revision 0.04 * section 2.6 Display Features -change third bullet text paragraph "... must fit inside 232K bytes..." to "... must fit inside 228K bytes..." * section 7.1.1 Input Clocks - Table 7-1 Clock Input Requirements (CLKI) - change fOSC Max, t3 max, t4 max, t5 min/max, t6 min/max, add note 6 * section 7.1.2 PLL Clock - Figure 7-2 PLL Start-Up Time, Table 7-2 PLL Clock Requirements - change PLL output to min 44.26, max 66.95 * section 7.2.1 Intel 80 Interface Timing - Table 7-3 Intel 80 Input A.C. Characteristics change todh and tddt min and max * section 8.4 Setting SYSCLK and PCLK - replace numbers in equations with new, replace Figure 8-3 Setting of SYSCLK for a Desired PCLK * section 9 Registers - correct register address typos in introduction * section 9.1 Register Mapping- correct register address typos * REG[18h] - add to note "Minimum value of this register = 4 Pixels" * REG[34h] - add bits 6-3 and change register default to 08h * REG[54h] - change register default to ??h * section 17 Host Interface - correct register address typos in introduction note * section 17.1.5 Individual Memory Location Reads - delete step 1 and re-number steps, changes to note X70A-A-001-00 Revision 0.03 * Engineering changes added Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 S1D13743 X70A-A-001-02 Page 134 Epson Research and Development Vancouver Design Center X70A-A-001-00 Revision 0.01 * initial draft of the S1D13743 specification S1D13743 X70A-A-001-02 Revision 2.7 Hardware Functional Specification Issue Date: 2010/05/18 |
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