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M64898GP
PLL Frequency Synthesizer with DC/DC Converter For PC
REJ03F0168-0200 Rev.2.00 Jun 14, 2006
Description
The M64898GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR /PC. It contains the prescaler with operating up to 1.3 GHz, 4 band drivers and DC/DC converter for Tuning voltage.
Features
* * * * * * * * * Built-in DC/DC converter for Tuning voltage 4 integrated PNP band drivers (IO = 30 mA, Vsat = 0.2 V Typ.@VCC1 to 10 V) Built-in prescaler with input amplifier (max = 1.3 GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X'tal 4 MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64892/M64893 Automatic switching of tuning step according to the number of data bits (62.5 kHz at 18 bits, 32.25 kHz at 19 bits) Built-in Power on reset system Small package (SSOP)
Application
PC, TV, VCR tuners
Recommended Operating Condition
* Supply voltage range VCC1 = 4.5 to 5.5 V VCC2 = VCC1 to 10 V * Rated supply voltage VCC1 = 5 V VCC2 = VCC1
Rev.2.00 Jun 14, 2006 page 1 of 13
M64898GP
Block Diagram
VCC1 3 CNT 15 VDC 9 Ipk 10
SQ Xin 20 OSC fREF Divider Selector 2
-
DIV.
R 11 SWE
Latch fin 1
AMP
1/8 Latch 15
+
Vreg
12 +B 13 Vtu OS 14 Vin
1/32, 1/33
15-bit Programmable Divider
Phase Detector
Charge Pump CP TEST Latch
CLK 17 DATA 18 ENA 19 Bias/Band Switch Driver 4 18/19-bit Shift Register Control 5
Lock Detector
16 LD/ftest
Power-on Reset 4 VCC2 5 BS4 6 BS3 7 BS2 8 BS1 2 GND
Rev.2.00 Jun 14, 2006 page 2 of 13
M64898GP
Pin Arrangement
M64898GP fin GND VCC1 VCC2 BS4 BS3 BS2
BS1 VDC
1
20 Xin 19 ENA 18 DATA 17 CLK 16 LD/ftest 15 CONT 14 Vin
13 Vtu
2 3 4 5 6 7
8 9
12 +B 11 SWE
Ipk 10 (Top view)
Outline: PLSP0020JA-A (20P2E-A)
Rev.2.00 Jun 14, 2006 page 3 of 13
M64898GP
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol fin GND VCC1 VCC2 BS4 BS3 BS2 BS1 VDC lpk Pin Name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0 V. Power supply voltage terminal. 5.0 V 0.5 V Power supply for band switching, VCC1 to 10 V PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF. DC/DC power supply voltage terminal. 5.0 V 0.5V When potential difference with VDC terminal becomes more than 0.33 V by current limiting detector of DC/DC converter, the listing rises with off. DC/DC converter oscillator output. Power supply voltage for tuning voltage. This supplies the tuning voltage. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fREF), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. Lock detector output. When loop of phase locked loop locked it, it rise with "H" level in "L" level or unlock. In control byte data input, the programmable freq. divider output and reference freq. output is selected by the test mode. Set up reference frequency divider ratio. In "L" level, set it up in 1/640 (19 Bit) in setting "opening" in 1/1024 (19 Bit) or 1/512 (18 Bit). Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. This normally at a "L". When this is at "H", data and clock signals are received. Data is read into the latch when the enable signal after the 18th signal of the clock signal falls or when the 19th pulse of the clock signal falls. 4.0 MHz crystal oscillator connected.
DC/DC power supply voltage Peak current detect
11 12 13 14
SWE +B Vtu Vin
Switching output Power supply voltage Tuning output Filter input (charge pump output)
15
LD/ftest
Lock detect/Test port
16
CONT
fREF Switch
17 18 19
CLOCK DATA ENABLE
Clock input Data input Enable input
20
Xin
This is connected to the crystal oscillator.
Rev.2.00 Jun 14, 2006 page 4 of 13
M64898GP
Absolute Maximum Ratings
(Ta = -20C to +75C, unless otherwise noted)
Item Supply voltage 1 Supply voltage 2 Input voltage Output voltage Voltage applied when the band output is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature Symbol VCC1 VCC2 VI VO VBSOFF IBSON tBSON Pd Topr Tstg Ratings 6.0 10.8 6.0 6.0 10.8 40.0 10 255 -20 to +75 -40 to +125 Unit V V V V V mA s mW C C Condition Pin 3 Pin 4 Not to exceed VCC1 fREF output
per 1 band output circuit 40mA per 1 band output circuit 3 circuits are pn at same time. Ta=75C
Recommended Operation Conditions
(Ta = -20C to +75C, unless otherwise noted)
Item Supply voltage 1 Supply voltage 2 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Symbol VCC1 VCC2 fopr1 fopr2 IBDL Ratings 4.5 to 5.5 VCC1 to 10.0 4.0 80 to 1300 0 to 30 Unit V V V MHz mA Conditions Pin 3 Pin 4 Crystal oscillation circuit Normally 1 circuit is on. 2 circuit on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time.
Rev.2.00 Jun 14, 2006 page 5 of 13
M64898GP
Electrical Characteristics
(Ta = -20C to +75C, unless otherwise noted, VCC1 = 5.0 V, VCC2 = 9.0 V)
Item Input termina ls "H" input voltage "L" input voltage "L" input voltage "H" input current "L" input current "L" input current "L" input current "H" input current "L" input current Output voltage Leak current Output voltage "H" Output voltage "L" Charge pump "H" output current Leak current Supply current 1 4 circus OFF Supply current 1 circus ON, 2 Output open Symbol VIH VIL1 VIL2 IIH IIL1 IIL2 IIL3 VOH VOL VBS IOlk1 VtoH VtoL Icpo IcpLK ICC1 ICC2A ICC2B Test Pin 17 to 19 15 17 to 19 17 to 19 15 17, 19 18 16 16 5 to 8 5 to 8 13 13 14 14 3 4 4 Min. 3.0 -- -- -- -- -- -- 5.0 11.6 -- 30.5 -- -- -- -- -- -- Limits Typ. -- -- -- -- -50 -6 -18 -- 0.3 11.8 -- -- 0.2 270 -- 20 -- 4.0 Max. VCC1 + 0.3 0.4 1.5 10 -80 -10 -30 -- 0.5 -- -10 -- 0.4 370 50 30 0.3 6.0 Unit V V V A A A A V V V A V V A nA mA mA mA mA Test Conditions
Lock output Band SW Tuning output
VCC1 = 5.5V, Vi = 4.0V VCC1 = 5.5V, Vi = 0V VCC1 = 5.5V, Vi = 0.5V VCC1 = 5.5V, Vi = 0.5V VCC1 = 5.5V VCC1 = 5.5V VCC2 = 9V, IO = -30mA VCC2 = 9V, Band SW is OFF VO = 0V +B = 31V +B = 31V VCC1 = 5.0V, VO = 2.5V VCC1 = 5.0V, VO = 2.5V VCC1 = 5.5V VCC2 = 9V VCC2 = 9V VCC2 = 9V, IO = -30mA
4 -- 34.0 36.0 Output current 30 ICC2C mA DC/DC Converter Supply current (action) ICCdc 9 -- 1.3 3.0 Output voltage Vdo 12 28 31 35 OSC frequency fOSC 11 -- 571 -- Current limit detect voltage Vipk 10 -- 330 -- Note: The typical values are at VCC1 = 5.0 V, VCC2 = 9.0 V, Ta = +25C.
mA V kHz mV
VCC1 = 5.5V VCC1 = 5.5V VCC1 = 5.5V VCC1 = 5.5V
Rev.2.00 Jun 14, 2006 page 6 of 13
M64898GP
Switching Characteristics
(Ta = -20C to +75C, unless otherwise noted, VCC1 = 5.0 V, VCC2 = 9.0 V)
Item Prescaler operating frequency Operating input voltage Symbol fopr Vin Test Pin 1 1 Min. 80 -24 -27 -15 1 2 1 3 3 1 -- -- 5 5 Limits Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 1300 4 4 4 -- -- -- -- -- -- 1 1 -- -- Unit MHz dBm Test Conditions VCC1 = 4.5 to 5.5V Vin = Vinmin to Vinmax VCC1 = 4.5 to 5.5V 80 to 100MHz 100 to 950MHz
Clock pulse width Data setup time Data hold time Enable setup time Enable hold time Enable data interval time Rise time Fall time Next enable prohibit time Next clock prohibit time
tPWC tSU (D) tH (D) tSU (E) tH (E) tINT tR tF tBT tBCL
17 18 18 18 18 19, 18 17, 18, 19 17, 18, 19 19 17, 19
s s s s s s s s s s
950 to 1300MHz VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V
Rev.2.00 Jun 14, 2006 page 7 of 13
M64898GP
Method of Setting Data
The programmable divider ratio uses 15 bits. Setting up the band switching output uses 4 bits. The test mode data uses 8 bits. The total bits used are 27 bits. Data is read in when the enable signal is "H" and the clock signal falls. The band switching data is read in at the 4th pulse of the clock signal. The programmable counter data is read into the latch by the fall of the enable signal after the 18th pulse of the clock signal or the fall of the 19th pulse of the clock signal. When the enable signal goes to "L" before the 18th pulse of the enable signal, only the band SW data is updated and other data is ignored. Automatic judgment facility comes being it, and, as for Shift resister, CONT terminal rises by 18/19 bits at the time of "L". At the time of data of 18 bits, M9 bit of Programmable divider is done reset of, and it is established in reference frequency divider ratio is established 1/512. At the time of 19 bits, reference frequency divider ratio is established in 1/1024. When reference frequency divider ratio was established in 1/640 by 19 bits at the time if "opening" CONT terminal, and it became "L" before 19 pulses enable signal, only band SW data are renewed, and other data are ignored. 1. Transfer of the 18th bit data (CONT terminal is "L") Data is latched by the fall of the enable signal after the 18th clock signal. At this time, the divider of the 1/512 of the reference frequency is used.
ENA
BS4 BS3 BS2 BS1 28 M8 27 M7 26 M6 25 M5 24 M4 23 M3 22 M2 21 M1 20 M0 24 S4 23 S3 22 S2 21 S1 20 S0
DATA CLK
Band Switch Data
M Counter Divider Ratio Setting Read Into Latch
S Counter Divider Ratio Setting Read Into Latch
2. Transfer of the 19th bit data (CONT terminal is "L" or "open") The data is latched at the 19th pulse of the clock signal. Reference frequency divider ratio is established in 1/1024 in case of "L" CONT terminal at this time. Reference frequency divider ratio is established in 1/640 in case of "opening" CONT terminal. Invalid the clock signal after 19th pulse. Note: When CONT terminal is "L", to change reference frequency, set up as ENA in "L" after 19th pulse of clock signal by all means.
ENA
BS4 BS3 BS2 BS1 29 M9 28 M8 27 M7 26 M6 25 M5 24 M4 23 M3 22 M2 21 M1 20 M0 24 S4 23 S3 22 S2 21 S1 20 S0
DATA CLK
Band Switch Data
M Counter Divider Ratio Setting Read Into Latch
S Counter Divider Ratio Setting Read Into Latch
Rev.2.00 Jun 14, 2006 page 8 of 13
M64898GP
How to Set The Dividing Ratio of The Programmable Divider
1. Transfer of the 18th bit data (CONT terminal is "L") Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N = 8 * (32 M + S) M: 9 bit main counter divider S: 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32 * M * 511 0 * S * 31 Therefore, the range of divider N is 8,192 to 131,064. The tuning frequency fVCO is given in the following equations. fVCO = fREF * N = 7.8125 * 8 * (32 M + S) = 62.5 * (32 M + S) (kHz) Therefore, the tuning frequency range is 64 MHz to 1023.9375 MHz. 2. Transfer of the 19th bit data (CONT terminal is "L") Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N = 8 * (32 M + S) M: 10 bit main counter divider S: 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32 * M * 1023 0 * S * 31 Therefore, the range of divider N is 8,192 to 262,136. The tuning frequency fVCO is given in the following equations. fVCO = fREF * N = 3.90625 * 8 * (32 M + S) = 31.25 * (32 M + S) (kHz) Therefore, the tuning frequency range is 32 MHz to 1023.96875 MHz. 3. Transfer of the 19th data (CONT terminal is "open") Total divider N is given by the following formulas in addition to the prescaler used in the previous stage. N = 8 * (32M + S) M: 10 bit main counter divider S: 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. 32 * M * 1023 0 * S * 31 Therefore, the range of divider N is 8,192 to 262,136. The tuning frequency fVCO is given in the following equations. fVCO = fREF * N = 6.25 * 8 * (32 M + S) = 50.0 * (32 M + S) (kHz) But, the tuning frequency range is 51.2 MHz to 1300 MHz from the maximum prescaler operating frequency.
Rev.2.00 Jun 14, 2006 page 9 of 13
M64898GP
Test Mode Data Set Up Method
The data for the test mode uses 20 to 27 bits. Data is latched when the 27th clock signal falls. 1. When transferring 3-wire 27 bit data
ENA
1 19 20 M Counter Divider Ratio Setting S Counter Divider Ratio Setting X X T2 T1 T0 RSa RSb OS Test Data Setting Read Into Latch
CLK
Band Switch Data
2. Test Mode Bit Set Up X : Random, 0 or 1 normal "0" T0, T1 & T2 : Set up test modes RSa, Rsa : Set the frequency divider of the reference frequency OS : Set up the tuning amplifier Setting Up for The Test mode
T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge Pump Normal operation High impedance Sink Source High impedance High impedance Pin 12 Condition LD LD LD LD fREF f1/N Mode Normal operation Test mode Test mode Test mode Test mode Test mode
RSa, RSb: Set Up for The Reference Frequency Divider Ratio
RSa 1 0 X RSb 1 1 0 Divider Ratio 1/512 1/1024 1/640
OS: Set Up The Tuning Amplifier
OS 0 1 Tuning Voltage Output ON OFF Mode Normal Test
Power On Reset Operation
(Initial state the power is turned ON) BS4 to BS1 Charge pump Tuning amplifier Charge pump current Frequency divider ratio Lock detect : OFF : High impedance : OFF : 270 A : 1/1024 :H
Charge pump current is replaced by 70 A when locks it by automatic change facility.
Rev.2.00 Jun 14, 2006 page 10 of 13
M64898GP
Timing Diagram
tr 90% 1.5 V 10% tINT tINT 90% 10% tBT tf VIH VIL VIH 10% tr 90% 10% tr tH(D) 90% 10% tf tH(E) tBCL tf VIH VIL VIL
ENABLE
DATA
1.5 V 10%
90%
90%
CLOCK
tPWC tSU(D) tSU(E)
1.5 V
Crystal Oscillator Connection Diagram
20 18 pF 4 MHz Crystal oscillator characteristics Actual resistance: less than 300 Load capacitance: 20 pF
Rev.2.00 Jun 14, 2006 page 11 of 13
M64898GP
Application Example
Built-in PLL Tuner IF AGC
IF
AGC
VHF UHF 4-Band Tuner
AFT
+B
BS4
BS3
BS2
BS1
Lo
VT
33 H 0.01
+
0.1 100 p 43
56 k 1000 p 680 p 56 k 0.1 14
VCC1 to 9 V 22 k 68 H 13 9 10 11
M64898GP
4
5
6
7
8
1 AMP
Bias Circuit
Band Driver 4
1/8 1/32 1/33 Charge Pump Phase Detector
+
Q S
R
Power-on Reset
-
3 +5 V Main Counter 9/10 Swallow Counter 18/19-bit Shift Resister Data Latch VCC1 =5V
+
Vreg Selector
OSC Divider
12 1.5 2
5
Lock Detector
51 k
15 18 p 20 4 MHz
19
17
18
16
1000 p
DATA CLK MCU
ENA
LD/ftest
Units R: C: F
Note: Filter constant is for reference. Add a capacitor to stabilize the filter circuit.
Rev.2.00 Jun 14, 2006 page 12 of 13
M64898GP
Package Dimensions
JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JA-A Previous Code 20P2E-A MASS[Typ.] 0.08g
20
11
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1
Index mark
10
c
A2 A1
*2
D
Reference Dimension in Millimeters Symbol
*3
e
bp
Detail F
y
D E A2 A A1 bp c HE e y L
Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0 0.1 0.2 0.17 0.22 0.32 0.13 0.15 0.2 0 10 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7
Min 6.4 4.3
Rev.2.00 Jun 14, 2006 page 13 of 13
A
L
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