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SWL-A20S Datasheet
SWL-A20S Datasheet
Atheros AR6002 WLAN Solution REV 6
Samsung Electro-Mechanics
2009-09-10
Summary
This datasheet presents the general performance and specifications of SWL-A20S IEEE 802.11b/g Wireless LAN module.
(c) 2009 Samsung Electro-Mechanics. All rights reserved The names of actual companies and products mentioned herein may be the trademarks of their respective owners. This document is subject to change without notice No part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Samsung Electro-Mechanics.
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Table of Contents
1 GENERAL DESCRIPTION..................................................................................................... 3 1.1 FUNCTIONAL DESCRIPTION .....................................................................................................3 1.2 FEATURES ..........................................................................................................................3 1.3 BLOCK DIAGRAM ..................................................................................................................4 2 DIMENSION AND PIN ASSIGNMENTS................................................................................ 5 2.1 MECHANICAL DIMENSION .......................................................................................................5 2.2 PIN ASSIGNMENTS................................................................................................................6 3 PIN DESCRIPTIONS............................................................................................................ 8 3.1 INTERFACE, I/O, CONTROL AND CLOCK PINS................................................................................8 3.2 POWER SUPPLY PINS.............................................................................................................9 4 ELECTRICAL CHARACTERISTICS...................................................................................... 10 4.1 DC CHARACTERISTICS ......................................................................................................... 10 4.2 ENVIRONMENTAL CHARACTERISTICS......................................................................................... 10 4.3 POWER CONSUMPTION......................................................................................................... 11 5 RF SPECIFICATIONS ........................................................................................................ 12 5.1 RECEIVER RF SPECIFICATIONS ............................................................................................... 12 5.2 TRANSMITTER RF SPECIFICATIONS .......................................................................................... 13 6 ASSEMBLY RECOMMENDATIONS ..................................................................................... 14 6.1 PRINTED CIRCUIT BOARD AND STENCIL DESIGN .......................................................................... 14 6.2 REFLOW AND SOLDERING ..................................................................................................... 15 7 ADDITIONAL INFORMATION ........................................................................................... 17 7.1 HOST INTERFACE CONFIGURATION .......................................................................................... 17 7.2 POWER ON/OFF SEQUENCES ................................................................................................. 17 7.3 REFERENCE AND SLEEP CLOCK REQUIREMENTS ............................................................................ 20 8 9 APPLICATION REFERENCE DESIGN ................................................................................. 22 MARKING INFORMATION ................................................................................................ 23
REVISION HISTORY ................................................................................................................ 24
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1 General Description
1.1 Functional Description
SWL-A20S is the compact size and low power System-in-Package (SiP) for IEEE 802.11b/g wireless LAN (WLAN) aimed at embedded and mobile applications. SWL-A20S is based on Atheros AR6002 solution. SWL-A20S supports both SDIO1.1 and GSPI host interface.
1.2
Features
IEEE Std 802.11b/g Standard Compliant Includes all the base-band and radio functionality, from host interface up to antenna, needs only external antenna Small dimensions (9.5 x 9.5 x 1.6 mm) with an LGA - 52pin peripheral footprint Low Power Consumption Cellular Coexistence Supported Standard 2,3 and 4 wire Bluetooth coexistence handshake supported Host Interface: SDIO and GSPI RoHS Compliant
1.2.1 Power Management
Supply voltage range 1.2V 1.8V VBATT SDIO Interface Voltage Power Consumption WLAN 600 mW (@11b Continuous Tx) 130 mW (@ Continuous Rx) 1.2V +/-5% (ripple Vpp<15mV) 1.8V +/-5% (ripple Vpp<45mV) 3.2~4.2V (Recommend 3.3V, ripple Vpp<15mV) Need to meet SDIO High signal level
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1.2.2 Radio Transceiver
Fully compliant with IEEE 802.11/b/g Receiver sensitivity (< 8% PER) at 11 Mbit/sec data rate: -87 dBm Receiver sensitivity (< 10% PER) at 54 Mbit/sec data rate: -74 dBm Blocking filter for suppression of CDMA, GSM, PCS and WCDMA interfering signals Transmitter output power in 802.11b mode: +15 dBm Transmitter output power in 802.11g mode at 6~24Mbps: +15 dBm
1.2.3 Applications
Smart phone/feature phones with embedded WLAN connectivity Personal digital assistants (PDA) SDIO WLAN Network Interface Cards (NIC) Voice over IP (VoIP) cordless phones Mobile gaming devices Portable media players (PMP) including networked MP3 player Networked digital camera and photo frames Digital media adapter and receiver Networked TV, set-top box, DVD recorder, personal video recorder (PVR), media drive, and other consumer electronics appliances
1.3
Block Diagram
Main Clock
From Battery 1.2V BPF PA
PMU
(Power Management Unit)
1.8V SP2T-SW
VDD_SDIO
BT Coex. WiFi SDIO/SPI
32.768KHz
ANT1
AR6002GZ (Atheros)
EEPROM
BPF Balun
Figure 1-1 SWL-A20S Hardware block diagram
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2 Dimension and Pin Assignments
2.1 Mechanical Dimension

Figure 2-1 SWL-A20S Mechanical Dimension
Parameter X Y Height
Min. 9.4 9.4
Nom. 9.5 9.5
Max. 9.6 9.6 1.60
Unit mm mm mm
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2.2
Pin Assignments
Figure 2-2 SWL-A20S Pin Assignments (Top View)
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No. 1 2 3 4 5 6 7 8 9 10 11 12 13
Name DVDD_GPIO_0 BT_CLK_EN GND WOW DVDD_GPIO_1 CLK_REQ GND SYS_RST_L SDIO_DATA[0] GND SDIO_CLK GND SDIO_DATA[1]
No. 14 15 16 17 18 19 20 21 22 23 24 25 26
Name SDIO_DATA[2] GND SDIO_CMD SDIO_DATA[3] GND LF_XTALI GPIO_5 GND GPIO_4 DVDD_BT GND DVDD12 BT_ACTIVE
No. 27 28 29 30 31 32 33 34 35 36 37 38 39
Name GND BT_PRIORITY BT_FREQ GND WLAN_ACTIVE DVDD_SDIO AVDD18 GND RF_IN_OUT_1 GND VBAT2 VBAT1 GND
No. 40 41 42 43 44 45 46 47 48 49 50 51 52
Name CHIP_PWD_L TXDO RXDO GND AVDD12 GND XTALI XTALO GND GND GND GND GND
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3 Pin Descriptions
3.1
Pin # 11 16 9 13 14 17 35 47 46 6 19 26 28 29 31 40 8 4 41 42 22 20 2
Interface, I/O, Control and Clock Pins
Pin Name SDIO_CLK SDIO_CMD SDIO_DATA[0] SDIO_DATA[1] SDIO_DATA[2] SDIO_DATA[3] RF_IN_OUT_1 XTALO XTALI CLK_REQ LF_XTALI BT_ACTIVE BT_PRIORITY BT_FREQ WLAN_ACTIVE CHIP_PWD_L SYS_RST_L WOW TXD0 RXD0 GPIO_4 GPIO_5 BT_CLK_EN
Type Description SDIO Interface SDIO input clock from Host I (up to 25MHz) SDIO command IO SDIO data bit [0] IO SDIO data bit [1] IO SDIO data bit [2] IO SDIO data bit [3] IO Antenna RF Port RF antenna port for 2.4G; 50Ohm IO Clock Interface Reference crystal output Crystal External clock source input Output Crystal Reference crystal input Input External clock request O 32KHz crystal input I Bluetooth Coexistence Interface I I I O Miscellaneous Pins I AR6002 Reset I wake-on-wireless(WOW) O Tx Data from module O Rx data from serial transceiver IO board Mode configuration(For SDIO "H") IO Mode configuration(For SDIO "H") IO Indicate BT is working I Circuit Reset
Supply DVDD_SDIO DVDD_SDIO DVDD_SDIO DVDD_SDIO DVDD_SDIO DVDD_SDIO DVDD_SDIO DVDD_BT DVDD_BT DVDD_BT DVDD_BT DVDD_BT
DI DIO DIO DIO DIO DIO RF IO DO DI DI DI DI DO DI DI DO DO DIO DIO DIO DI
PU PU PU PU PU PD -
PD PU PD PU PU -
DVDD_SDIO DVDD_SDIO DVDD_GPIO1 DVDD_GPIO0 DVDD_GPIO0 DVDD_SDIO DVDD_SDIO -
"Type" Column: I=Input, O=Output, IO=Bi-directional "Circuit" Column: DI=Digital Input, DO=Digital Output, DIO=Digital Bi-directional "Reset" Column: PL=Plain, PD=Pull-down, PU=Pull-up
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3.2
Pin # 32 37 38 23 1 5 25 44 33 3 7 10 12 15 18 21 24 27 30 34 36 39 43 45 48 49 50 51 52
Power Supply Pins
Pin Name DVDD_SDIO VBAT2 VBAT1 DVDD_BT DVDD_GPIO_0 DVDD_GPIO_1 DVDD12 AVDD12 AVDD18 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Description SDIO interface voltage (Meet SDIO signal level) PA supply voltage Internal LDO supply voltage BT-Coexistence IO Supply (Meet BT IO level) GPIO supply voltage for TXDO, RXDO, Internal EEPROM GPIO supply voltage for WOW Meet host WOW level 1.2V Digital core Analog 1.2V Analog 1.8V Min. 1.71 3.2 3.2 1.71 1.71 1.71 1.14 1.14 1.71 Nom. 2.6 3.3 3.3 2.6 1.8 2.6 1.2 1.2 1.8 Max. 3.46 4.2 4.2 3.46 3.46 3.46 1.26 1.26 1.89 Unit V V V V V V V V V -
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4 Electrical Characteristics
4.1 DC Characteristics
4.1.1 Absolute Maximum Ratings
Symbol VBAT1 VBAT2 DVDD_BT DVDD_GPIO_0 DVDD_GPIO_1 DVDD12 AVDD12 AVDD18 Parameter Internal LDO supply voltage PA supply voltage BT-Coexistence IO level Some GPIO supply voltage Some GPIO supply voltage 1.2V Digital core Analog 1.2V Analog 1.8V Conditions Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max. 4.35 4.35 4.0 4.0 4.0 1.35 1.35 2.5 Unit V V V V V V V V
4.2
Environmental Characteristics
Parameter Electro-static discharge voltage Operating temperature Storage temperature Conditions HBM Min. -2000 -20 -30 Max. 2000 70 85 Unit V C C
Symbol ESD Top Tstg
*HBM : Human Body Model ESD Class 1C
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4.3
Power Consumption
Parameter Conditions Min. Nom. 39 Tx 99% @11b Tx 15dBm 62 5.5 116 46 Tx 99% @11g Tx 15dBm 62 5.5 110 62 Rx @Max gain 27 5.5 0.1 Max. Unit mA mA uA mA mA mA uA mA mA mA uA mA
Tx mode (11b Max current) 1.2V 1.8V IO Part (General 2.6V) VBAT1 + VBAT2 Tx mode (11g Max current) 1.2V 1.8V IO Part (General 2.6V) VBAT1 + VBAT2 Rx mode 1.2V 1.8V IO Part (General 2.6V) VBAT1 + VBAT2 Sleep mode 1.2V 1.8V IO Part (General 2.6V) VBAT1 + VBAT2 0.488 0.013 5.5 0.003 mA mA uA mA
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5 RF Specifications
All measurements are made under nominal supply voltage and room temperature conditions.
5.1
Receiver RF Specifications
Min. Nom. -96 -92 -90 -87 -92 -91 -90 -88 -84 -80 -76 -74 -10* -20* 35* 35* 35* 35* 16* 16* 13* 11* 8* 4* 0* -1* Max. -80* -80* -76* -76* -82* -81* -79* -77* -74* -70* -66* -65* Unit dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB
Parameter Conditions Minimum receiver sensitivity in 802.11 mode 1Mbps PER<8%, Packet size= 1024bytes 2Mbps Minimum receiver sensitivity in 802.11b mode 5.5Mbps PER<8%, Packet size= 1024bytes 11Mbps Minimum receiver sensitivity in 802.11g mode 6Mbps 9Mbps 12Mbps PER<10%, 18Mbps Packet size= 24Mbps 1024bytes 36Mbps 48Mbps 54Mbps Maximum input level Maximum input signal level in 802.11b PER<8% Maximum input signal level in 802.11g PER<10% Adjacent channel rejection (ACR) in 802.11 mode 1Mbps PER<8%, Packet size= 1024bytes 2Mbps Adjacent channel rejection (ACR) in 802.11b mode 5.5Mbps PER<8%, Packet size= 1024bytes 11Mbps Adjacent channel rejection (ACR) in 802.11g mode 6Mbps 9Mbps 12Mbps PER<10%, 18Mbps Packet size= 24Mbps 1024bytes 36Mbps 48Mbps 54Mbps
"*" Indicate IEEE 802.11 specifications
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5.2
Transmitter RF Specifications
Parameter Conditions Min Nom Max Unit
Linear average output power in 802.11b mode As specified in Average output power@1~11Mbps IEEE802.11 Chap.17~19 Linear average output power in 802.11g mode Average output power@6~24Mbps Average output power@36Mbps Average output power@48Mbps Average output power@54Mbps Transmit spectrum mask Margin to 802.11b spectrum mask Margin to 802.11g spectrum mask Maximum output power As specified in IEEE802.11 Chap.17~19
13
15
17
dBm
13 13 12 11
15 15 14 13
17 17 16 15
dBm dBm dBm dBm
0 0
dB dB
Transmit modulation accuracy in 802.11b mode 1Mbps 2Mbps 5.5Mbps 11Mbps Transmit modulation accuracy in 802.11g mode 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps Transmit power-on ramp time from 10% to 90% output power Transmit power-down ramp time from 90% to 10% output power
Frame-to-Frame output power has +/-1.5dB fluctuation from the average output power
35 As specified in IEEE802.11b 35 35 35
% % % %
Mandatory Option Mandatory Option Mandatory Option Option Option
-5 -8 -10 -13 -16 -19 -22 -25
dB dB dB dB dB dB dB dB
Transmit power-on and power-down ramp time in 802.11b mode 2 2 usec usec
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6 Assembly Recommendations
6.1 Printed Circuit Board and Stencil Design
Figure 6-1 PCB and Stencil Design (Top View) Dimension Label A B C D E F G Nom. 9.700 9.700 0.900 0.350 0.680 0.330 0.375 Unit mm mm mm mm mm mm mm Dimension Label H I J K L M Nom. 1.300 1.600 0.700 0.700 0.050 1.200 Unit mm mm mm mm mm mm
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6.1.1 PCB Finish
The SWL-A20S can be mounted on a variety of PCB finishes such as immersion gold (Ni/Au) or Hot air solder level (HASL) or Organic Surface Protection (OSP). Ni/Au finish is recommended. OSP is not recommended in cases that OSP does not withstand a Pb-free or a double-sided reflow application.
6.2
Reflow and Soldering
6.2.1 Solder Paste
Standard (No-clean) Sn/Pb (63%/37%) or Pb-free solder pastes should be used for soldering the package. Solder pastes should be selected based on their printing and reflow behavior. For Pb-free solder paste it is recommended to use "SAC" type solder paste (e.g. SnAg3.8Cu0.7) with melting point of 217C.
6.2.2 Reflow Profile
Industrial convection reflow oven should be used to mount the packages. The profile depends on the printed circuit board and other components that are used in the customer application. For maximum peak temperature JEDEC specification should be followed. Following reflow profile and constraints are recommended for eutectic Sn/Pb and Pb-free reflow solders
Figure 6-1 Recommended Reflow Temperature Profile
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Eutectic Sn/Pb Average ramp-up rate (TSmax to Tp) Preheat -Temperature Min(TSmin) -Temperature Max(TSmax) -Time(TSmin to TSmax) Time maintained above: -Temperature(TL) -Time(tL) Max. Peak Temperature(Tp) 183 C 60-90 seconds 240 +/-5 C 10-30 seconds >180C: 2 C /second max. <180C: 6 C /second max. 205 C 4-5 minutes 100 C 150 C 60-120 seconds 2C /second max
Pb-free 2C /second max
150 C 200 C 75-90 seconds(0.75/second) 217 C 70-90 seconds 255 5 C (max 260C)
Ramp-Down Rate Minimum Peak Temperature(Tpmin) Time 25 C to Tp
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Time within 5 Temperature(tP)
of actual Peak
20-30 seconds >180C: 2 C /second max. <180C: 6 C /second max. 230 C 4-5 minutes
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7 Additional Information
7.1
GPIO4 0 1
Host Interface Configuration
GPIO5 0 1 Configuration GSPI Mode SDIO Mode
7.2
Power On/Off Sequences
The CHIP_PWD_L or SYS_RST_L ports can be used to reset the chip. If CHIP_PWD_L is used to reset the chip, a ~20ms delay occurs before the AR6002 is ready. In addition, unlike SYS_RST_L, CHIP_PWD_L can be used to put the AR6002 into CHIP_PWD power state. Figure 7-1, Figure 7-2 and Figure 7-3 show the CHIP_PWD_L, SYS_RST_L, and power supply domain timing diagrams. Table 7-1 describes the symbols used in these figures. It is recommended that for power savings, CHIP_PWD_L be driven low and all I/O supplies remain in place when A20S is not in use. The core 1.2V supply can be left on or off. For proper reset, if any supplies have been turned off, CHIP_PWD_L (or SYS_RST_L) must remain low, or toggled after, until all supplies have stabilized. The AR6002 has an internal pull-down on CHIP_PWD_L, so when the host pulls it high, the pad sinks current. The amount of current ranges from ~10uA to ~40uA. As a result, the solution power consumption is at least 18~132uW higher than the chip power consumption in non-CHIP_PWD states. The AR6002 has an internal pull-up on SYS_RST_L, thus to minimize CHIP_PWD power consumption, customer designs should not tie CHIP_PWD_L and SYS_RST_L together.
I/O Supply
1.2V Supply
CHIP_PWD_L
SYS_RST_L
Ta Tb Tc Td
Figure 7-1 Power-Up/Power-Down Timing While Asserting CHIP_PWD_L
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I/O Supply
1.2V Supply
CHIP_PWD_L
SYS_RST_L
Ta Te Tr Tc Td
Figure 7-2 Power-Up/Power-Down Timing While Asserting SYS_RST_L
I/O Supply
1.2V Supply
CHIP_PWD_L
SYS_RST_L
Tf Tg
Figure 7-3 Reset and Power Cycle Timing
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I/O Supply = AVDD18, DVDD_SDIO, DVDD_BT, DVDD_GPIO_0, DVDD_GPIO_1, VBAT1 1.2V Supply = DVDD12, AVDD12 Symbol Ta Tb Tc Td Te Tf Tg Description Time between I/O supply valid* and 1.2V supply valid Time between 1.2V supply valid and CHIP_PWD_L deassertion Time between CHIP_PWD_L or SYS_RST_L assertion and 1.2V supply invalid Time between 1.2V supply invalid and I/O supply invalid Time between 1.2V supply valid and SYS_RST_L assertion Length of SYS_RST_L pulse Length of CHIP_PWD_L pulse Table 7-1 Timing Diagram Definitions Min 0 us 5 us 0 us 0 0 1 5 us us us us
"*" Supply valid represents the voltage level has reached 90% level.
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7.3
Reference and Sleep Clock requirements
7.3.1 Low-Frequency/Sleep/32KHz clock
LF-XTALI is pin used for the 32KHz sleep clock of SWL-A20S WLAN section. The 32KHz sleep clock line is DC-coupled into LF-XTALI pin. The LF-XTALI input clock timing and voltage requirements are shown below.
Figure 7-4 LF-XTALI Input clock timing Symbol CK1 CK2 CK3 CK4 CK5 CK6 CK7 Description Frequency Fall Time Rise Time Duty Cycle (High-to-Low Ratio) Frequency Stability Input High Voltage Input Low Voltage Min. 15 -50 0.8*DVDD_BT -0.3 Nom. 32.768 Max. 100 100 85 50 DVDD_BT+0.2 DVDD_BT*0.2 Unit KHz ns ns % ppm V V
7.3.2 Reference clock
XTALI and XTALO are the pins used for the reference clock. The reference clock is the primary clock source for the SWL-A20S. SWL-A20S can support 26MHz reference clock. Reference clock source may come from either an external crystal or oscillator source.
Three hardware solutions are used for the reference clock External crystal option(use KSS CX3225SB CX-101F or equivalent) External reference clock option(i.e., XO,VCXO, or VCTCXO) Host reference drive option
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For the last two options, the CLK_REQ output from the SWL-A20S can enable the clock reference source or assert a request to the host. Also, for the latter two options, the phase noise requirements for the SWL-A20S at the XTALO pin are shown below. -145dBc/Hz at 20KHz -150dBc/Hz at 100KHz -155dBc/Hz at 200KHz
The external reference clock option or host reference drive option voltage requirements are shown below.
Figure 7-5 External reference clock option or Host reference drive option Symbol CK2 CK3 CK4 CK5 CK6 CK7 Description Fall Time Rise Time Duty Cycle (High-to-Low Ratio) Frequency Stability Input High Voltage Input Low Voltage Min. 40 -20 0.75 -0.55 Nom. Max. 0.1*Period 0.1*Period 60 20 3.46 0.3 Unit ns ns % ppm V V
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8 Application Reference Design
Main Clock (from Phone Ref Clock) Recommended Voltage Recommended Voltage 3.2~ 3.6V 3.2 ~ 3.6V
AVDD12
VBATT(3.0~4.2V)
VBATT(3.0~4.2V)
Clock Option1
Clock Option2
C8 AVDD12 1uF R15 1M 0.1uF CHIP_PWD_L C9
C4 1uF
C16 1uF
RF In/Out (50ohm System)
TCXO TCXO
XTALO Y1 XTALI R13 10K C14 5pF 3 1
XTALI
XTALI R2
XTALO
XTALO 0
26.0000MHZ
C15 10pF 48 47 46 45 44 43 42 41 40 39 38 37 AVDD18
XTALO
RXDO
TXDO
AVDD12
CHIP_PWD_L
DVDD_GPIO_0 1 C3 1uF WOW 2 3 4 5 C19 1uF SY S_RST_L WLAN_SDIO_D[0] R5 0R WLAN_SDIO_CLK R12 0R WLAN_CLK_REQ 6 7 8 9 10 11 12
VBAT1
VBAT2
GND
GND
XTALI
GND
GND
C6 1uF GND 36 35 34 33 32 31 30
C5 0.1uF
M SM Interface Voltage (Normally 2.6~ 2.9V)
DVDD_SDIO
M eet to WOW High level
DVDD_GPIO_1
DVDD_GPIO_0 BT_CLK_EN
RF_IN_OUT_1 GND
GND AVDD18 WOW DVDD_SDIO DVDD_GPIO_1 CLK_REQ GND BT_FREQ SY S_RST_L BT_PRIORITY SDIO_DATA_0 GND GND BT_ACTIVE SDIO_CLK SDIO_DATA_1 SDIO_DATA_2 SDIO_CMD GND SDIO_DATA_3 DVDD12 DVDD_BT LF_XTALI GND GND GND GND U1 WLAN_ACTIVE GND
SWL-A20S
C18 29 28 27 26 25 52 51 50 49 C13 1uF DVDD12 WLAN_ACTIVE BT_FREQ BT_PRIORITY BT_ACTIVE 1uF
BT coexistence Interface, If not used, they should be pull-down
Optional
GPIO_5
GPIO_4
GND
GND
GND
13
14
15
16
17
18
19
20
21
22
23
24
GND
WLAN_SDIO_CMD
WLAN_SDIO_D[1]
WLAN_SDIO_D[2]
WLAN_SDIO_D[3]
Figure 8-1 Reference Schematic for SWL-A20S SDIO Interface Application
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R8 R9 0R 0R 0R 0R R10 R11
DVDD_BT
DVDD_SDIO R7 10K R6 NP
Pin Setting for Mode Configuration (SDIO) 1) R7 = 0R, R6 = NP : SDIO(default) 2) R7 = NP, R6 = 0R : SPI
R4 LF_XTALI 0
C20 1uF
C12 NP
32.768KHz
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9
Marking Information
08 YY
No. YY MM DD a b c d
04 MM
15 DD
A a
A b
0 c
0 d
Description Year: 20XX, XX: 00~99 (ex. 08 = 2008) Month: XX: 01~12 (ex. 04 = April) Day: XX: 1~31 (ex. 15: 15st) Manufacture lot Revision information Factory information (0:SEMCO, 1:SEMTHAI) Product sub-code
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Revision History
Revision 1 2 3 Date 2008-04-05 2008-04-23 2008-07-07 Descriptions Created Modified Printed circuit board and stencil design Added the viewpoint in the dimension and pin assignments Added sleep current, page 11 Updated RF Specification, page 13 Updated Additional information, page 18 Updated Sleep clock requirement, page 23 Updated Power Consumption, page 11 Corrected typing error, page 19 Added min/max value for average output power, page14 Added frame-to-frame power fluctuation specification, page14 Corrected typing error, page 11 Updated Reflow and Soldering, page 17 Updated Power on/off sequences, page 19 Updated 1.8V Ripple spec, page 3 Updated Sleep current, page 11 Updated reference clock level, page 21 Updated Application reference design, page 22
4
2008-09-10
5
2009-3-14
6
2009-09-10
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