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C-5 Network Processor Data Sheet
TM
Supporting C-5 Network Processor Version D0
Feature List Complete programmability
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Programmability at all levels of the protocol stack: Layers 2-7 Examples of C-5 enabled systems: - Multiservice Access Platforms (MSAPs) - Optical edge switch/routers - IP Gigabit/Terabit routers - WAN Customer Premises Equipment (CPE) - Load balancing web server switches
17 programmable RISC Cores (for cell/packet forwarding) 32 programmable Serial Data Processors (for processing bit streams) Up to 133 million table lookups per second Three internal buses for 60Gb of aggregate bandwidth
High functional integration
838 pin Ball Grid Array (BGA) package 16 Channel Processors including: - Embedded OC-3c, OC-12, OC-12c SONET framers - Programmable MAC interface - RISC Cores - Programmable pin PHY interfaces Embedded coprocessors for table lookup (classification), buffer memory (payload control), and queue management (CoS/QoS implementation) Dedicated Fabric Processor and port Embedded RISC Executive Processor Integrated 32bit/66MHz PCI bus
Simple programming model
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C/C++ programmable Standard instruction set Standard Applications Programming Interface (C-Ware APITM) Comprehensive C-WareTM Software Toolset (easy to program, debug, and tune applications)
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Maximum system flexibility
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Software implementation of functions from physical interfaces through switching fabric support Reprogram to support new functionality and ratified standards, improving your time-in-marketTM metric Deliver new services to market through simple software upgrades -- no forklift
Stable programming interfaces
Supports generic communications programming interfaces to simplify programming and allow future reuse of code across generations of the processor Network Processing Forum (NPF), (formerly CPIX), Charter member
Massive processing power
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Operating frequencies: 166MHz, 200MHz, and 233MHz 5Gbps of bandwidth (for non-blocking throughput) More than 3,000MIPs of computing power (for adding services throughout the protocol stack) Up to 15 million packets per second transmitted at wire speed
Third-party support
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Support for virtually any third-party protocol stack, PHY or fabric interface, and industry standard tools Smart Networks Alliance Program ensures a wide range of verified solutions
C-Port Corporation 120 Water Street N. Andover, MA 01845 www.cportcorp.com
Copyright (c) 2002 C-Port Corporation. All rights reserved. No part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from C-Port Corporation. C-Port Corporation reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of C-Port Corporation to provide notification of such revision or change. C-Port Corporation provides this documentation without warranty, term, or condition of any kind, either implied or expressed, including, but not limited to, the implied warranties, terms or conditions of merchantability, satisfactory quality, and fitness for a particular purpose. C-Port may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. Unless otherwise indicated, C-Port registered trademarks are registered in the United States and may or may not be registered in other countries. C-5, C-Port, the C-Port logo, C-Ware, C-Ware APIs, and C-Ware Partner are all trademarks of C-Port Corporation. Part Number: 4-004 January 21, 2002
January 21, 2002 -- Preliminary Version
C-Port Confidential
Contents
List of Figures List of Tables About This Guide
Data Sheet Description and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CHAPTER 1
Functional Description
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Channel Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Executive Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Fabric Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table Lookup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 External Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Queue Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CHAPTER 2
Signal Descriptions
Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin Descriptions Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LVTTL and LVPECL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DS1/T1 Framer Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10/100 Ethernet (RMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Gigabit Ethernet (GMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Gigabit Ethernet and Fibre Channel TBI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SONET OC-3 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SONET OC-12 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Executive Processor System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4
CONTENTS
PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals Grouped by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDcode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Description Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33 34 35 37 38 42 44 45 45 48 48 49 58 58 59 59 60 61 61
CHAPTER 3
Electrical Specifications
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/DS3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications . . . . . . . . . . . . . . . . . . OC-3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC-12 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executive Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Speed Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 64 65 66 67 69 69 71 72 73 74 76 77 78 78 80 81 82
January 21, 2002-- Preliminary Version
C-Port Confidential
CONTENTS
5
Fabric Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 BMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TLU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 QMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
CHAPTER 4
Mechanical Specifications
Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Package Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Typical Reflow Profile for the C-5 Switch Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
C-Port Confidential
Preliminary Version -- January 21, 2002
6
CONTENTS
January 21, 2002-- Preliminary Version
C-Port Confidential
List of Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
C-5 Network Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin Locations (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 GMII/TBI Transmit and Receive Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PROM Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PROM Interface Timing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power and Ground Connections (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Observe-Only Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Cell Design That Can Be Used for Both Input and Output Pins. . . . . . . . . . . . . . . . . . . . . . . . 60 Bringup Clock Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Thermal Performance for C-5 Network Processor Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Test Loading Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 System Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DS1/DS3 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10/100 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Gigabit Ethernet and TBI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 OC-3 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 OC-12 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PCI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 MDIO Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Low Speed Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PROM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Fabric Processor Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 BMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TLU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 QMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 C-5 Network Processor BGA Package Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 C-5 Network Processor BGA Package (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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January 21, 2002
C-Port Confidential
List of Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C-5 Network Processor Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TLU SRAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CP Physical Interface Signals and Pins (Grouped by Clusters) . . . . . . . . . . . . . . . . . . . . . . . . 25 DS1/T1 Framer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10/100 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel . . . . . . 27 Gigabit Ethernet (GMII/MII) Signals One Cluster Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gigabit Ethernet and Fibre Channel TBI Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OC-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OC-12 Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Serial Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General System Interface Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Fabric Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Utopia1*, 2, 3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . 39 Utopia1*, 2, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . 39 PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . . . . . . . . . . 40 Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . . . . . . . . . . 40 BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Memory Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 QMU SRAM Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Power Supply Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines . . . . . . . . . . . . . . 48 No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Signals Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 JTAG Internal Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 JTAG Identification Code and Its Sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Instruction Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 C-5 Network Processor Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
C-5 Network Processor Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .64 C-5 Network Processor DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 C-5 Network Processor Capacitance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 C-5 Network Processor Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .67 System Clock Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 DS1/DS3 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 10/100 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Gigabit GMII/MII Ethernet Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Gigabit TBI Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 OC-3 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 OC-12 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 PCI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 MDIO Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Low Speed Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 PROM Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Fabric Processor Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 BMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Signal Groups in BMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 TLU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Signal Groups in TLU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 QMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Signal Groups in QMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Package Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 C-5 Network Processor Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
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About This Guide
Data Sheet Description and Organization
This data sheet describes the C-5 Network processor, Version D0. It provides hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications. The data sheet is divided into the following topics:
* * * * Revision History
Functional Description Signal Descriptions Electrical Specifications Mechanical Specifications
Table 1 shows the revision history for this data sheet, providing a description of the changes.
Table 1 C-5 Network Processor Data Sheet Revision History
Revision Date
March 10, 2000
Change
First printing for the C-5 NP.
Page No.
12
ABOUT THIS GUIDE
Table 1 C-5 Network Processor Data Sheet Revision History
Revision Date
June 12, 2000
Change
Chapter 2 contains the following revisions: * LVTTL and LVPECL specifications have been added. * Several of the tables listing pin configurations have had their descriptions updated. Check each application's configuration table as required. * CPn3+1 is RCLKN (5/25/00), not NC (3/10/00) * Mechanism for EPROM signaling has changed. * XPUHOT functionality is clarified * QCPA is a NC (5/25/00), not Address Parity (3/10/00) * The power and ground connections illustration has been updated. Chapter 3 contains the following revisions: * Many values listed in individual timing diagrams and specification tables have updated or corrected. Check each specification table as required. * Low speed serial interface timing specifications have been added. * PROM I/F timing specifications are changed QMU timing specification for Tqdo has been changed from 2.2 to 1.5. Updated BMU section to reflect change to external Pipeline Architecture, Single Data Rate Synchronous DRAM. Operating temperatiure range added. Power sequencing diagram updated. BMU timing diagram updated. TLU timing diagram updated. QMU timing diagram updated.
Page No.
17 18 - 39 25 31 31 36 38
61 - 78 71 72 77 12 54 56 75 77 78
June 14, 2000 July 17, 2000 August 8, 2000
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Revision History
13
Table 1 C-5 Network Processor Data Sheet Revision History
Revision Date
March 26, 2001
Change
Chapter 1 contains the following revisions: * Fabric Processor Interface Frequency changed from 100 MHz to 110 MHz thruoughout. * TLU interface memory was incorrectly noted at 64 MBytes. Changed to 32 MBytes. The maximum amount of memory supported by the TLU is 32MBytes in four banks. Chapter 2 contains the following revisions: * Buffer Management Unit (BMU) has 161 pins * Added Figure 5. PROM Interface Timing Outline * Added Figure 7. Observe-Only Cell * Added Figure 8. Cell Design That Can Be Used for Both Input and Output Pins * PROM Interface Timing Outline added. * Numerous changes in tables 17, 18 and 19 * Data lines incorrectly noted at 128. The useful configuration is 139 data lines and all 12 address lines. * The TLU SRAM interface was incorrectly noted at 64 MBytes. Changed to 32 MBytes. Chapter 3 contains the following revisions: * Table 40, Gigabit Ethernet (TBI) Timing Description, Tcgr min value of -1.0 removed. * Figure 16, OC 12 Clock Duty Cycle was added * Tc12d added to Table 42 * Figure 17, Executive Processor PCI Timing Diagram PGNTX is only an input. PGNTX Output removed. * Tpgo, Tpgz, Tpgv removed from Table 43. Chapter 4 contains the following revisions: * Mechanical specs changed.
Page No.
Thru-out
18
19
21 37 57
36 39, 40 41 42
71 73 73 74 75
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ABOUT THIS GUIDE
Table 1 C-5 Network Processor Data Sheet Revision History
Revision Date
October 1, 2001
Change
Chapter 2 contains the following revisions: * LVTTL and LVPECL conform to the JEDEC JESD8-BSpecification * Table 3 changed to note LVPECL differential signal * Table 10 LVPECL change * Table 11 CPn_6 and CPn+1_6 changed * Table 21 changed to reflect pin G14 used for signal MDQML * Table 27 changed to reflect total number of NC pins for D0 * Table 28 changed to reflect G14 receiving signal MDQML * C-Port web site support address added Chapter 3 contains the following revisions * Table 32 Storage / max junction temperatures added * Table 34 LVPECL high and low voltage min / max added * Table 36 Power dissipation, PD min, max, typical changed Chapter 4 contains the following revisions * Added "Marking Codes" * Added "Reflow" profile
Page No.
23 23 31 31 32 42 48 61 63 65 67 91 91
January 21, 2002
Chapter 1 contains the following revisions: * Table 2 contain revised TLU SRAM Configuration 19 specifications Chapter 2 contains the following revisions: * TLU SRAM Interface Signals: Table 22 and Table 23 changed 44 to reflect Memory Bank Selection Chapter 3 contains the following revisions: * Table 48, Table 49 and Table 51 contain revised timing 84 thru 86 specifications
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Chapter 1
Functional Description
Block Diagram
The C-5TM network processor, has an architecture specifically designed for networking applications. Figure 1 shows a block diagram of the C-5 NP, including its potential external interfaces. The following sections describe each component of the C-5 NP. For more information about the architecture of the C-5 NP, see the C-5 Network Processor Architecture Guide.
Figure 1 C-5 Network Processor Block Diagram
SRAM Fabric SRAM External Host CPU (optional) External PROM (optional) SDRAM
Control Logic (optional) Table Lookup Unit
PCI Serial PROM
Fabric Processor
Executive Processor Buffer Mgmt Unit
Queue Mgmt Unit
Buses (60Gbps Bandwidth)
C-5 NP
CP-0
Cluster PHY
CP-1
CP-2
CP-3
CP-12 CP-13 CP-14 CP-15
Cluster
Channel Processors
Processor Boundary
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY Interface Examples: 10/100 Ethernet Gigabit Ethernet OC-3 OC-12
16
The main components of the C-5 NP are:
* * * * * * Channel Processors
Channel Processors Executive Processor Fabric Processor Buffer Management Unit Table Lookup Unit Queue Management Unit
The C-5 NP contains sixteen programmable Channel Processors (CPs) that receive, process, and transmit network data. The number of CPs per port is configurable, depending on the line interface. Typically one CP is assigned to each port for medium bandwidth applications (Fast Ethernet to OC-3). Multiple CPs can be assigned to a port in a configuration called channel aggregation in high bandwidth applications (greater than OC-3). Multiple logical ports can be assigned to a single CP, with the addition of an external multiplexor, for low bandwidth applications, such as DS1 to DS3. The C-5 NP's architecture supports a variety of industry-standard serial and parallel protocols and individual port data rates including:
* * * * * *
10Mb Ethernet (RMII) 100Mb Ethernet (RMII) 1Gb Ethernet (GMII and TBI) OC-3 OC-12 DS1/DS3, supported through the use of external framers/multiplexors
The C-5 NP's programmability can also support a variety of special interfaces, such as various xDSL encapsulations and proprietary protocols. Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet processing and a set of microprogrammable, special-purpose processors, called Serial Data Processors (SDPs), that provide features such as Ethernet MAC and SONET framing, multichannel HDLC, and ATM cell delineation. This means you usually only need to include PHYs to complete the system.
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Executive Processor
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Executive Processor
The Executive Processor (XP) serves as a centralized computing resource for the C-5 NP and manages the system interfaces. The XP performs conventional supervisory tasks in the C-5 NP, including:
* * * * *
System Interfaces
Reset and initialization of the C-5 NP Program loading and control of CPs Centralized exception handling Management of a host interface through the PCI Management of system interfaces (PCI, Serial Bus, PROM)
The system interfaces to the XP are:
* *
PCI -- Provides an industry standard 32bit 33/66MHz PCI channel used for chip-level shared resources. The PCI has both initiator and target capabilities. The PCI interface is typically connected to a host processor. Serial Bus Interface -- Provides a general purpose bi-directional, two-wire serial bus and I/O port that allows the C-5 NP to control external logic with either of two standard protocols: - The MDIO (high-speed) protocol: uses a 16bit data format with 10bits of addressing and supports transfers up to 25MHz. - The low-speed protocol: uses an 8bit data format followed by an acknowledge bit and supports transfers up to 400kbps. Software is used to select which protocol to use, by setting the appropriate bits in the Serial Bus Configuration Register. When a serial bus transfer is active, an external pin is driven by the C-5 NP to indicate which protocol is being used (SPLD=0 indicates MDIO protocol; SPLD=1 indicates low-speed protocol). Both SIDA and SICL are bi-directional lines that are connected, via an external pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH because of the pull-up resistor. The output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism.
*
PROM Interface -- Allows the XP to boot from nonvolatile, flash memory. The PROM interface is a low-speed, serial I/O port that runs at 1/2 to 1/16 the core clock rate. The maximum PROM size is 8MBytes, and a 16bit wide configuration is required. External
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board logic is required to perform serial-to-parallel conversion for PROM address outputs and parallel-to-serial conversion for PROM data inputs.
Fabric Processor
The Fabric Processor (FP) acts as a high-speed network interface port with advanced functionality. It allows the C-5 NP to interface to an application-specific switching solution internal to your design. The FP port supports the bidirectional transfer of packets, frames, or cells from the C-5 NP to a hardware interface that provides connectivity to other network processors or other similar line processing hardware. There are numerous parameters that can be configured within the FP to allow the interface to be adapted to different fabric protocols. The FP is Utopia-1, 2 and Utopia-3, IBM PRIZMA, and PowerX (Csix-L0) compatible. The FP can be configured to run at any frequency up to 110MHz, and the receive and transmit data buses are 16 or 32 bits wide. This allows a wide range of supported bandwidths to and from the switching fabric, all the way up to 3200Mbps full duplex bandwidth.
Buffer Management Unit
The Buffer Management Unit (BMU) interfaces the C-5 NP to external pipeline architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It is also used as second level storage in the XP memory hierarchy. The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two internal control bits, and nine SECDED (single error correction-double error detection) ECC (error correction code) bits. The interface is compliant with the PC100 standard and operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the C-5 Network Processor Architecture Guide for more details). The C-5 NP uses auto-refresh mode and the interface, (which is not configurable), transfers four bits of data for each read and write using a sequential burst type. Some of these parameters are programmed into the SDRAMs' mode register and can be applied only once per power cycle. The ECC functionality can be enabled or disabled via configuration register writes. If needed, the interface can narrowed to 128bits by disabling ECC and providing board pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU
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Table Lookup Unit
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supports SDRAM devices that use 12 address lines. Internal address calculation paths limit the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.
Table Lookup Unit
The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used for statistics accumulation and retrieval and as general data storage. The TLU simultaneously supports multiple application-defined tables and multiple search strategies, such as those needed for routing, circuit switching, and QoS lookup tasks. The C-5 NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules (at frequencies to 133MHz) for storage of its tables. These modules allow implementation of tables with 220 x 64bit entries at a cycle time of up to 7.5 nanoseconds using 4Mbit SRAM technology. The maximum amount of memory supported by the TLU is 32MBytes in four banks.
Table 2 TLU SRAM Configurations
SRAM Technology*
1Mbit (32k x 32) 2Mbit (64k x 32) 4Mbit (256k x 18) 8Mbit (512k x 18 16Mbit (1M x 18)
*
Min Table Size (One Bank)
256kBytes 512kBytes 2MBytes 4MBytes 8MBytes
No. of Parts
2 2 4 4 4
Maximum Table Size (Four Banks)
1MBytes 2MBytes 8MBytes 16MBytes 32MBytes
No. of Parts
8 8 16 16 16
For (n x 32) parts, divide total memory and number of parts by two.
External Mode Queue Management Unit
There is support for external devices. Refer to the C-5e Archictecture Guide.
The Queue Management Unit (QMU) autonomously manages a number of application-defined descriptor queues. It handles inter-CP and inter-C-5 NP descriptor flows by providing switching and buffering. It also performs descriptor replication for multicast applications. A number of queues can be assigned to each CPRC for QoS-based services. The QMU provides a queuing engine internal to the chip and uses external SRAM to store the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and 16, 384 descriptor buffers. A descriptor buffer holds an application-defined "descriptor" ,
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which is a structure that defines the payload buffer handle and other attributes of the forwarded cell or packet. The QMU's external SRAM interface uses ZBT synchronous SRAMs organized in a single bank of up to 128k, 32bit words. This interface runs at half (1/2) the core clock frequency.
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Chapter 2
Signal Descriptions
Signal Summary
There are ten functional groupings of signals in the C-5 network processor:
* * *
Clock -- 11 pins Channel Processors (CP0 - CP15) -- 16x7 = 112 pins Executive Processor (XP) -- 57 pins - PCI Interface -- 50 pins - PROM Interface -- 4 pins - Serial Bus Interface -- 2 pins - General System Interface -- 1 pin
* * * * * * *
Fabric Processor (FP) -- 80 pins Buffer Management Unit (BMU) -- 161 pins Table Lookup Unit (TLU) -- 100 pins Queue Management Unit (QMU) -- 55 pins Power -- 233 pins Test -- 18 pins No connection (NC) -- 11 pins
Two of the sections (CPs and FP) are configurable, depending on the type of device being implemented.
22
CHAPTER 2: SIGNAL DESCRIPTIONS
Pinout Diagram
The C-5 NP contains 838 pins as shown in Figure 2. These pin numbers are referenced throughout the remaining chapter.
Figure 2 Pin Locations (Bottom View)
C-5 Network Processor
AC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
1 2 3 4 5 6 7 8 9
838 Total Pins
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
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Pin Descriptions Grouped by Function
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Pin Descriptions Grouped by Function
The C-5 NP pins are categorized in groups, reflecting interfaces to the chip:
* * * * * * * * * *
Clock Signals CP Interface Signals Executive Processor System Interface Signals Fabric Processor Interface Signals BMU SDRAM Interface Signals TLU SRAM Interface Signals QMU SRAM Interface Signals Power Supply Signals Test Signals No Connection Pins
LVTTL and LVPECL Specifications
C-5 NP pins are the following types:
* *
Low Voltage TTL-Compatible (LVTTL). The C-5 NP's LVTTL pins conform to the JEDEC JESD8-B specification. Low Voltage Positive Emitter Coupled Logic (LVPECL). The C-5 NP's LVPECL pins conform to the JEDEC JESD8-2 specification.
Clock Signals
Table 3 describes the C-5 NP clock signals.
Table 3 Clock and Reference Signals
Signal Name
SCLK* SCLKX* CCLK0 CCLK1 CCLK2 CCLK3 CCLK4 CCLK5
Pin #
H15 G15 K12 J13 J15 I12 I14 H13
Total
1 1 1 1 1 1 1 1
Type
LVPECL LVPECL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
I/O
I I I I I I I I
Signal Description
Core Clock Rate (Differential) 1_544MHZ_CLK (T1) 2_048MHZ_CLK (E1) 34_368MHZ_CLK (E3) 44_736MHZ_CLK (T3) 50MHZ_CLK (100Mbit Ethernet) 106_25MHZ_CLK (Fibre Channel)
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 3 Clock and Reference Signals (continued)
Signal Name
CCLK6 CCLK7 CPREF
Pin #
K14 K16 L13
Total
1 1 1
Type
LVTTL LVTTL LVPECL
I/O
I I I
Signal Description
125MHZ_CLK (Gigabit Ethernet) 155_52MHZ_CLK (OC-3) Reference
Total
*
11
SCLK and SCLKX must not be AC-coupled. The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP. Clock inputs associated with a specific protocol should be wired to ground when that protocol is not used by the C-5 NP. It is also possible to use one or more CCLKn inputs for other frequencies. Contact your C-Port representative for more information. If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must be wired to an external reference, as specified in Table 34 on page 65. If none of the CPs are configured for LVPECL operation, then the CPREF pin can be left unconnected. It is acceptable to tie the CPREF pin high or low through a resistor, or into the specified reference, but this is not required.
CP Interface Signals
The C-5 NP's 16 CPs support various network physical interfaces, providing a serial interface to the PHY layer. Interfaces are configured via bits in the C-5 NP register set. Many interfaces are possible by programming the configuration registers. CPs can be used individually or in a cluster (four CPs) to implement the various interfaces. Table 4 provides a quick reference of all the CP pins organized by clusters. There are seven physical I/O pins associated with each CP. All pins are capable of receiving data, with some configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can be configured as differential pairs for LVPECL compatibility. In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for receive and four for transmit) or four CPs that share the transmit and receive functions for non-wire speed applications. During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the SDPs, with each getting access to the necessary I/O pins. The signals for the following CP physical interfaces are included in this section:
* *
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* * * *
Gigabit Ethernet (GMII) Configuration Gigabit Ethernet and Fibre Channel TBI Configuration SONET OC-3 Transceiver Interface Configuration SONET OC-12 Transceiver Interface Configuration
Table 4 CP Physical Interface Signals and Pins (Grouped by Clusters)
CP Cluster 1 Signal
CP0_0 CP0_1 CP0_2 CP0_3 CP0_4 CP0_5 CP0_6 CP1_0 CP1_1 CP1_2 CP1_3 CP1_4 CP1_5 CP1_6 CP2_0 CP2_1 CP2_2 CP2_3 CP2_4 CP2_5 CP2_6 CP3_0 CP3_1 CP3_2
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CP Cluster 2 Signal
CP4_0 CP4_1 CP4_2 CP4_3 CP4_4 CP4_5 CP4_6 CP5_0 CP5_1 CP5_2 CP5_3 CP5_4 CP5_5 CP5_6 CP6_0 CP6_1 CP6_2 CP6_3 CP6_4 CP6_5 CP6_6 CP7_0 CP7_1 CP7_2
CP Cluster 3 Signal
CP8_0 CP8_1 CP8_2 CP8_3 CP8_4 CP8_5 CP8_6 CP9_0 CP9_1 CP9_2 CP9_3 CP9_4 CP9_5 CP9_6 CP10_0 CP10_1 CP10_2 CP10_3 CP10_4 CP10_5 CP10_6 CP11_0 CP11_1 CP11_2
CP Cluster 4 Signal
CP12_0 CP12_1 CP12_2 CP12_3 CP12_4 CP12_5 CP12_6 CP13_0 CP13_1 CP13_2 CP13_3 CP13_4 CP13_5 CP13_6 CP14_0 CP14_1 CP14_2 CP14_3 CP14_4 CP14_5 CP14_6 CP15_0 CP15_1 CP15_2
Pin #
AC28 AC26 AC24 AC22 AC20 AC18 AC16 AC02 AC04 AC06 AC08 AC10 AC12 AC14 AB29 AB28 AB27 AB26 AB25 AB24 AB23 AB01 AB02 AB03
Pin #
AB22 AB21 AB20 AB19 AB18 AB17 AB16 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AA28 AA26 AA24 AA22 AA20 AA18 AA16 AA02 AA04 AA06
Pin #
Z29 Z28 Z27 Z26 Z25 Z24 Z23 Z01 Z02 Z03 Z04 Z05 Z06 Z07 Z22 Z21 Z20 Z19 Z18 Z17 Z16 Z08 Z09 Z10
Pin #
Y28 Y26 Y24 Y22 Y20 Y18 Y16 Y02 Y04 Y06 Y08 Y10 Y12 Y14 X29 X28 X27 X26 X25 X24 X23 X01 X02 X03
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Table 4 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued)
CP Cluster 1 Signal
CP3_3 CP3_4 CP3_5 CP3_6
CP Cluster 2 Signal
CP7_3 CP7_4 CP7_5 CP7_6
CP Cluster 3 Signal
CP11_3 CP11_4 CP11_5 CP11_6
CP Cluster 4 Signal
CP15_3 CP15_4 CP15_5 CP15_6
Pin #
AB04 AB05 AB06 AB07
Pin #
AA08 AA10 AA12 AA14
Pin #
Z11 Z12 Z13 Z14
Pin #
X04 X05 X06 X07
DS1/T1 Framer Interface Configuration
Table 5 describes the serial framer interface signals. For each CP (0-15), you can implement one serial Framer interface.
Table 5 DS1/T1 Framer Interface Signals
Signal Name* Pin # Total
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 1 1 1 1 1 1 1 7
Type
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc
I/O
O I O O I I nc
Label
TCLK RCLK TData TFrame RData RFrame nc
Signal Description
Transmit Clock (1.544MHz) Receive Clock (1.544MHz) Transmit Data Transmit Frame Synchronization Receive Data Receive Frame Synchronization nc
Total Pins
*
n can be from 0 to 15. See Table 4. Reference Table 4 for pin numbers for the actual cluster(s) you are configuring.
10/100 Ethernet (RMII) Configuration
Table 6 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface (RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
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Table 6 10/100 Ethernet Signals
Signal Name* Pin #
CPn_0 CPn_1 Table 4 Table 4
Total
1 1
Type
LVTTL LVTTL
I/O
O I
Label
REF_CLK CRS_DV
Signal Description
Transmit and Receive Clock (50MHz) Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... RX_DV indicates that a receive frame is in progress and the data present on the RXD pins is valid. It is asserted if this signal is a 1 for more than one cycle. Transmit Data 0 (first on wire) Transmit Data 1 (second on wire) Receive Data 0 (first on wire) Receive Data 1 (second on wire) Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable.
CPn_2 CPn_3 CPn_4 CPn_5 CPn_6
Table 4 Table 4 Table 4 Table 4 Table 4
1 1 1 1 1 7
LVTTL LVTTL LVTTL LVTTL LVTTL
O O I I O
TXD(0) TXD(1) RXD(0) RXD(1) TX_EN
Total Pins
*
n can be from 0 to 15. See Table 4.
Gigabit Ethernet (GMII) Configuration
Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways: 1 Use one CP cluster when density is more important than wire-speed performance because you can then implement up to four Gigabit Ethernet ports per C-5 NP. 2 Use two CP clusters for wire-speed performance and additional processing power. You can implement up to two Gigabit Ethernet ports per C-5 NP. Table 7 lists the possible CP cluster combinations you can use and Figure 3 shows receive and transmit pin configurations by cluster. Table 8 lists the signals and pinouts for Gigabit Ethernet (GMII).
Table 7 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel
Cluster
0 1 2 3
*
Single Cluster Mode (TBI or GMII)
Port 1 Tx and Rx Port 2 Tx and Rx Port 3 Tx and Rx Port 4 Tx and Rx
Two Cluster Mode (GMII)*
Port 1 Tx Port 1 Rx Port 2 Tx Port 2 Rx
The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3 transmits.
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Figure 3 GMII/TBI Transmit and Receive Pin Configurations
Single Cluster Mode Pin Configuration Tx Two Cluster Mode Pin Configuration
Cluster 0
Rx Tx
} Port 1 } Port 2 } Port 3 } Port 4
Tx
Cluster 0
Rx
nc
Tx
Cluster 1
Rx Tx
Cluster 1
nc
Rx Tx
Cluster 2 Cluster 3
Rx Tx Rx
Cluster 2 Cluster 3 nc = not connected
Rx
nc
Tx
nc
Rx
} }
Port 1
Port 2
The unused CP pins in the two cluster configurations should be wired to ground using a resistor.
Table 8 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
Signal Name* Pin # Total
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1
Type
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL
I/O
O I O O O O O nc I O O O O
Label
T_CLK TCLKI TXD(0) TXD(1) TXD(2) TXD(3) TX_EN nc COL TXD(4) TXD(5) TXD(6) TXD(7)
Signal Description
GMII Transmit Clock (125MHz). This clock is used to synchronize the transmit data. MII transmit clock. Transmit data aligned to this clock input from phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT Transmit Data (byte-wide data, least significant bit) Transmit Data Transmit Data Transmit Data Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable. nc Collision. Asserted when both RX_DV and TX_EN are valid during half duplex operation. Transmit Data Transmit Data Transmit Data Transmit Data (byte-wide receive data, most significant bit)
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Table 8 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)
Signal Name* Pin # Total
CPn+1_6 Table 4 1
Type
LVTTL
I/O
O
Label
TX_ER
Signal Description
Transmit Error. Asserting TX_ER when TX_EN is a 1 causes transmission of the designated "bad code" in lieu of the normal encoded data on the twisted pair data. nc Receive Clock (125MHz) Receive Data (byte-wide receive data, least significant bit) Receive Data Receive Data Receive Data Receive Data Valid. Indicates that there is a receive frame in progress and that the data present on the RXD signals is valid. nc Carrier Sense. Indicates traffic is on the link. CRS is asserted when a non-idle condition is detected on the receive data stream. CRS is deasserted when an end of frame or idle condition is detected. Receive Data Receive Data Receive Data Receive Data (most significant bit) Receive Error Detected. Indicates that there has been an error received in the receive frame.
CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1
Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1
nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL I I I I I I nc I
nc RCLK RXD(0) RXD(1) RXD(2) RXD(3) RX_DV nc CRS
CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6
Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 28
LVTTL LVTTL LVTTL LVTTL LVTTL
I I I I I
RXD(4) RXD(5) RXD(6) RXD(7) RX_ER
Total Pins
*
n can be 0, 4, 8, or 12. Reference Table 4 for pin numbers for the actual cluster(s) you are configuring.
Gigabit Ethernet and Fibre Channel TBI Configuration
1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same way as Gigabit Ethernet (GMII). Table 7 shows the possible CP pin combinations you can use and Figure 3 shows receive and transmit pin configurations by cluster. Table 9 shows the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI.
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The unused pins for the two cluster configurations should be wired down using a resistor.
Table 9 Gigabit Ethernet and Fibre Channel TBI Signals Example
Signal Name* Pin # Total Type
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1 CPn+3_2 CPn+3_3 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 Table 4 1 LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL
I/O
O nc O O O O O nc nc O O O O O nc I I I I I I nc I I I
Label
TCLK nc TXD(9) TXD(8) TXD(7) TXD(6) TXD(1) nc nc TXD(5) TXD(4) TXD(3) TXD(2) TXD(0) nc RCLK RXD(9) RXD(8) RXD(7) RXD(6) RXD(1) nc RCLKN RXD(5) RXD(4)
Signal Description
Transmit Clock (125MHz). This clock is used to synchronize the transmit data. nc Transmit Data (ten bits wide, last on wire) Transmit Data Transmit Data Transmit Data Transmit Data nc nc Transmit Data Transmit Data Transmit Data Transmit Data Transmit Data (ten bits wide, first on wire) nc Receive Clock (62.5 MHz) Receive Data (ten bits wide, last on wire) Receive Data Receive Data Receive Data Receive Data nc Receive Clock Inverted Receive Data Receive Data
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Table 9 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)
Signal Name* Pin # Total Type
CPn+3_4 CPn+3_5 CPn+3_6 Table 4 1 Table 4 1 Table 4 1 28 LVTTL LVTTL LVTTL
I/O
I I I
Label
RXD(3) RXD(2) RXD(0)
Signal Description
Receive Data Receive Data Receive Data (ten bits wide, first on wire)
Total Pins
*
n can be 0, 4, 8, or 12 Reference Table 4 for pin numbers for the actual cluster(s) you are configuring.
SONET OC-3 Transceiver Interface Configuration
Table 10 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each CP (0-15), you can implement a single OC-3 interface.
Table 10 OC-3 Signals
Signal Name* Pin #
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4
Total Type
1 1 1 1 1 1 1 7
I/O
Label
RCLK_H RCLK_L TXD_H TXD_L RXD_H RXD_L SIGNAL_DET
Signal Description
Receive Clock noninverted side of pair (155.52MHz) Receive Clock inverted side of pair (155.52MHz) Transmit Data noninverted side of pair Transmit Data inverted side of pair Receive Data noninverted side of pair Receive Data inverted side of pair A light level above a certain threshold is present at the optical receiver - single ended LVPECL.
LVPECL I LVPECL I LVPECL O LVPECL O LVPECL I LVPECL I LVPECL I
Total Pins
*
n can be from 0 to 15. Reference Table 4 for pin numbers for the actual cluster(s) you are configuring.
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SONET OC-12 Transceiver Interface Configuration
SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a CP within a cluster spends half its time performing receive functions, and the other half performing transmit functions. Table 11 shows a CP Cluster configured for one OC-12 interface.
Table 11 OC-12 Signals Example
Signal Name* Pin #
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4 Table 4
Total Type
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc nc
I/O
O I O O O O 0 nc nc O O O O nc nc I I I I I I nc nc
Label
TCLK TCLK1 TXD(0) TXD(1) TXD(2) TXD(3) 00F nc nc TXD(4) TXD(5) TXD(6) TXD(7) nc nc RCLK RXD(0) RXD(1) RXD(2) RXD(3) FP nc nc
Signal Description
Deskewed Transmit Clock (77.76MHz). This clock is used to synchronize the transmit data. Transceiver Transmit Clock. This clock sets the frequency of the transmit data and is typically sourced by the PHY chip. Transmit Data (byte-wide data, least significant bit) Transmit Data Transmit Data Transmit Data Out of Frame nc nc Transmit Data Transmit Data Transmit Data Transmit Data (byte-wide data, most significant bit) nc nc Receive Clock (77.76MHz) Receive Data (byte-wide receive data, least significant bit) Receive Data Receive Data Receive Data Frame Synchronization Pulse. This is valid during the third A2 of the receive SONET frame. nc nc
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Table 11 OC-12 Signals Example (continued)
Signal Name* Pin #
CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6 Table 4 Table 4 Table 4 Table 4 Table 4
Total Type
1 1 1 1 1 28 LVTTL LVTTL LVTTL LVTTL nc
I/O
I I I I nc
Label
RXD(4) RXD(5) RXD(6) RXD(7) nc
Signal Description
Receive Data Receive Data Receive Data Receive Data (most significant bit) nc
Total Pins
*
n can be 0, 4, 8, or 12 Reference Table 4 for pin numbers for a different cluster.
Executive Processor System Interface Signals
The XP's system interface manages the supervisory controls for the network interfaces, as well as the set of pins that provide interfaces to other components in the system that are not memories or network interfaces. It is also the primary interface used for initializing the C-5 NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM interface signals.
PCI Signals
The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or 66MHz. The PCI is fully compliant with PCVI Specification revision 2.1. Table 12 describes the PCI signals.
Table 12 PCI Signals
Signal Name
PAD0 - PAD31
Pin #
Total Type
PCI
I/O
I/O
Signal Description
Multiplexed Address/Data Bus. These signals are multiplexed address and data bits. The C-5 NP receives addresses as target and drives addresses as master. It drives the data and receives read data as master. Command byte enables. These signals are multiplexed command and byte enabled signals. The C-5 NP receives byte enables as target and drives byte enables as master. Parity. This signal carries even parity for AD and CBE# pins. It has the same receive and drive characteristics as the address and data bus, except that it is one PCI cycle later. Cycle frame
T22, R21, P21, T21, R20, P20, T20, 32 R19, Q20, S20, R18, P19, T19, R17, P18, T18, R16, Q18, S18, S16, P17, T17, R15, P16, T16, S14, Q16, T15, R14, P15, T14, Q14 N21, N20, M20, O20 4
PCBEX0 - PCBEX3
PCI
I/O
PPAR
P14
1
PCI
I/O
PFRAMEX
K20
1
PCI
I/O
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Table 12 PCI Signals (continued)
Signal Name
PTRDYX PIRDYX PSTOPX PDEVSELX PPERRX PSERRX PCLK PRSTX PREQX PGNTX PIDSEL PINTA
Pin #
L20 L19 K18 N18 M18 L18 L15 N17 L17 N19 O18 O16
Total Type
1 1 1 1 1 1 1 1 1 1 1 1 50 PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI
I/O
I/O I/O I/O I/O I/O I/O I I O I I O
Signal Description
Target ready for data transfer Initiator ready for data transfer Target transaction stop request Target device selected Bus parity error System error Bus clock Bus reset Initiator bus request (arbitration) Initiator bus grant (arbitration) Initialization device select Interrupt
Total Pins
Serial Interface Signals
The Serial interface is a bidirectional two-wire serial bus. It can use one of the following formats: 1 An 8bit data format followed by an acknowledge bit, which supports transfers at up to 400kbps (low speed). 2 a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports transfers up to 25MHz (high speed). The signals and pins are identical for both the high and low speed protocols. Which of the two data rates used is selected by the state of the PROM interface's SPLD signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is selected. The bus only supports a single master hierarchy that can operate as either a receiver or a transmitter. The bus also supports collision detection and arbitration, and an integrated addressing and data-transfer protocol. Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages
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of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism.
Table 13 Serial Port Signals
Signal Name
SICL SIDA
Pin #
O14 N14
Total Type
1 1 2 LVTTL LVTTL
I/O
I/O I/O
Signal Description
Serial Clock line Serial Data line
Total Pins
PROM Interface Signals
The PROM interface is a low speed I/O port that allows the C-5 NP to communicate through external logic to PROM. The PROM clock is 1/2 to 1/16 the core clock rate. The maximum PROM size is 4MBytes x 16, and configuration is required. The PROM signals are listed in Table 14.
Table 14 PROM Interface Signals
Signal Name
SPDO SPDI SPLD
Pin #
N15 N16 M16
Total Type
1 1 1 LVTTL LVTTL LVTTL
I/O
O I O
Signal Description
Serial Data Out Serial Data In When load is asserted on a positive clock edge, the external logic performs a parallel load. On each positive clock edge when load is de-asserted, the shift registers shift. When the PROM interface is idle: * if SPLD is asserted HI it indicates low speed serial protocol,
*
SPCK M14 1 4 LVTTL O
if asserted LOW it indicates MDIO serial protocol.
Clock
Total Pins
Figure 4 shows the connections between the PROM Interface and external board logic. The application is required to provide an external shift register with parallel-in and parallel-out capabilities, and a parallel load register. Both devices should be positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When SPLD is deasserted the shift register shifts.
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Figure 4 PROM Interface Diagram
21
C-5 Network Processor
0 PROM_ADDR<21:1> 21
CE
External Logic
SPDO
21
6
1 0 SPDI
21
60
15 31 16 PROM _H_Word PROM _Return_Data 15
Internal Shift Register 21 0
External Shift Register 0
CE
PROM_ADDR<21:1>
PROM _LO_Word 21 PROM Clock Gen. SPCLK PROM Sequencer SPLD PROM PROM_Data 1 16
The PROM interface operates in the following manner (Note that two accesses are piplined together to execute one 32-bit fetch). The steps are shown in Figure 5. 1 The PROM_ADDR is loaded into the network processor internal shift register. 2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles. 3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register. 4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift register. 5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register and the first PROM_DATA into the external shift register. 6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network processor internal shift register. 7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network processor PROM_RETURN_DATA register and the second PROM_DATA into the external shift register.
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8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the network processor internal shift register. 9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the network processor PROM_RETURN_DATA register.
Figure 5 PROM Interface Timing Outline
XP PROM Interface outline SPLD SPDTO
Q< Q< Q< Q<
A5
A1
A2
A3
A4
SPDTI XP PROM Interface detail
1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9
D1
D2
D3
10 11 12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
SPCLK SPLD SPDTO
x
A1
AAAAAAAAAAAA 20 19 18 17 16 15 14 13 12 11 10 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A CE 0
A2
A3
A4
1
2
The PROM_ADDR is loaded into the C-5's internal shift register. The PROM_ADDR is shifted into the external shift register. (SPCLK Rising Edge used for shifting)
3
5 4
The PROM_DATA is loaded into the external shift register. D1
x DDDDDDD 15 14 13 12 11 10 9 D 8 D 7 D 6 D 5 DD 43 D 2 D 1 D 0 x x x x x x
The PROM_ADDR is loaded into the external presentation register. The PROM_DATA is presenting.
D2
SPDTI
6
8 7
The PROM_DATA is shifted into the C-5's Internal shift register.
9
The PROM_DATA is loaded into the C-5's internal PROM_RETURN_DATA register.
General System Interface Signal
Table 15 provides the signal for the Executive Processor reset power status and I/O clock. The C-5 NP can be powered up with the XP either running or with the XP in reset mode similar to the CPs. When the XP remains in reset mode, an external host can be used to control the initialization of the C-5 NP.
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Table 15 General System Interface Signal
Signal Name
XPUHOT
Pin #
J19
Total
1
Type
LVTTL
I/O
I
Signal Description
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low equals reset and High equals active. During normal operation, this is an external interrupt.
Total Pins
1
Fabric Processor Interface Signals
The FP consists of two logical signal interfaces: a receive data interface and a transmit data interface, each with its own control and clocking signals. The interface has the following characteristics:
* *
The interface clocks FRXCLK and FTXCLK can have a different frequency from the core C-5 NP clock frequency. The Fabric Data Processor (FDP) has synchronizing FIFOs at its interface boundary to allow for a fabric interface frequency from 10MHz to 110MHz. The receive clock FRXCLK and the transmit clock FTXCLK must share the same frequency. The synchronization logic internal to the FP requires related clock domains on the transmit and receive interfaces. Each of the two clocks can have different phase alignment, however, because they are generated externally.
Each data bus can be run at widths of 16 or 32 bits of data (FIN0 - FIN31 and FOUT0 FOUT31) per clock. The extra data pins in each configuration remain unused. The output pins are driven to a known state, and the input pins should also be pulled to a known state.
Table 16 Fabric Interface Signals
Signal Name
FIN0 - FIN31
Pin #
Total
Type
LVTTL
I/O
I
Signal Description
Fabric Data Bus In
W2, V1, T1, V2, U2, V3, T3, T2, W4, V4, V5, U4, T4, 32 W6, V6, U6, T5, T6, V7, T7, X8, W8, V8, V9, U8, X9, V10, U10, X10, W10, X11, V11 W28, V29, T29, V28, U28, V27, T27, T28, W26, V26, V25, U26, T26, W24, V24, U24, T25, T24, V23, T23, X22, W22, V22, V21, U22, X21, V20, U20, X20, W20, X19, V19 W14 W16 U12, W12, V12, X12, X13, V13, X14 U18, W18, V18, X18, X17, V17, X16 32
FOUT0 - FOUT31
LVTTL
O
Fabric Data Bus Out
FRXCLK FTXCLK FRXCTL0 - FRXCTL6 FTXCTL0 - FTXCTL6
1 1 7 7 80
LVTTL LVTTL LVTTL LVTTL
I I I, O I, O
Receive Clock Transmit Clock Receive Control Signals Transmit Control Signals
Total Pins
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The following tables list the Fabric Interface pin mappings:
* * * *
Receive Signals C-5 Network Processor
FRXCTL0 FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6
*
Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in Table 17 Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in Table 18 PRIZMA Mode mappings are listed in Table 19 (PRIZMA mode is an example of Utopia3
PHY mode)
Power X Mode mappings are listed in Table 20
Table 17 Utopia1*, 2*, 3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping
Transmit Signals I/O
Output Input Input Input Input Input Input
Utopia
RxEnb* RxClav RxSOC n/a n/a n/a RxPrty
Note
Pullup or nc Pulldown Pulldown Pullup or Pulldown
C-5 Network Processor
FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6
I/O
Output Input Output nc nc nc Output
Utopia
TxEnb* TxClav TxSOC nc nc nc TxPrty
Note
Pullup or nc Pulldown Pulldown
cell size must be 4Byte aligned.
Table 18 Utopia1*, 2*, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping
Receive Signals C-5 Network Processor
FRXCTL0 FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5
Transmit Signals I/O
Input Output Input Input Input Input
Utopia
TxEnb* TxClav TxSOC n/a n/a n/a
Note
Pullup Pulldown or nc Pulldown Pullup or Pulldown Pullup or Pulldown Pullup or Pulldown
C-5 Network Processor
FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5
I/O
Input Output Output nc nc nc
Utopia
RxEnb* RxClav RxSOC nc nc nc
Note
Pullup Pulldown or nc Pulldown
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Table 18 Utopia1*, 2*, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping
Receive Signals C-5 Network Processor
FRXCTL6
*
Transmit Signals I/O
Input
Utopia
TxPrty
Note
C-5 Network Processor
FTXCTL6
I/O
Output
Utopia
RxPrty
Note
cell size must be 4Byte aligned.
When configuring two C-5 network processors back-to-back using the Fabric Port, set up the transmit side of each C-5 network processor in Utopia ATM mode and the receive side of each C-5 network processor in Utopia PHY mode.
Table 19 PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping
Receive Signals C-5 Network Processor
FRXCTL0
Transmit Signals I/O
Input
Utopia
TxEnb*
Note
C-5 Network Processor
I/O
Input
Utopia
RxEnb*
Note
pulldown (not connected to fabric) nc Pulldown
pulldown FTXCTL0 (not connected to fabric) nc Pulldown Pullup or Pulldown Pullup or Pulldown Pullup or Pulldown FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6
FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6
Output Input Input Input Input Input
TxClav TxSOP n/a n/a n/a TxPrty or nc
Output Output nc nc nc Output
RxClav RxSOP nc nc nc RxPrty or nc
Table 20 Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping
Receive Signals C-5 Network Processor
FRXCTL0 FRXCTL1 FRXCTL2
Transmit Signals I/O
Input Input Input
Power X
RxCtrl[0] RxCtrl[1] RxCtrl[2]
Note
Pulldown Pulldown Pulldown
C-5 Network Processor
FTXCTL0 FTXCTL1 FTXCTL2
I/O
Output Output Output
Power X
TxCtrl[0] TxCtrl[1] TxCtrl[2]
Note
Pulldown or nc Pulldown or nc Pulldown or nc
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Table 20 Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping
Receive Signals C-5 Network Processor
FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6
Transmit Signals I/O
Input Input Input Input
Power X
RxPrty[3] RxPrty[2] RxPrty[1] RxPrty[0]
Note
C-5 Network Processor
FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6
I/O
Output Output Output Output
Power X
TxPrty[3] TxPrty[2] TxPrty[1] TxPrty[0]
Note
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CHAPTER 2: SIGNAL DESCRIPTIONS
BMU SDRAM Interface Signals
The BMU and SDRAM interface signals are described in Table 21. The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines and all 12 address lines must be connected to the SDRAM in order for the BMU to be able to read and write external SDRAM properly.
Table 21 BMU SDRAM Interface Signals
Signal Name
MD0 - MD129
Pin #
R29, Q28, P28, S28, R28, P29, R27, Q26, P26, S26, R26, P27, R25, Q24, P24, S24, R24, P25, S22, R23, R22, N29, M28, L28, J29, O28, N28, L29, K28, N27, M26, L26, J28, O26, N26, L27, K26, N25, M24, L24, J27, O24, N24, L25, K24, P22, M22, K22, J23, Q22, N23, L22, J25, O22, L23, J26, J22, P23, N22, L21, J24, B29, D29, F29, A28, C28, E28, G28, B28, D28, F28, B27, D27, F27, A26, C26, E26, B26, D26, F26, G26, B25, D25, F25, A24, C24, E24, B24, D24, F24, B23, D23, F23, G24, A22, C22, E22, B22, D22, F22, B21, D21, F21, A20, C20, E20, G22, B20, D20, F20, B19, D19, F19, A18, C18, E18, B18, D18, F18, G20, B17, D17, F17, A16, C16, E16, B16, D16, F16, B15
Total Type
130 LVTTL
I/O
I/O
Signal Description
Data Lines In
MDECC0 - MDECC8 G16, F15, F14, E14, D15, D14, C14, B14, A14 MA0 - MA11 H22, I22, H23, H24, I24, H25, H26, I26, H27, H28, I28, H29
9 12
LVTTL LVTTL
I/O O
Stored as data, ECC bits Address Outputs: A0-A11 are sampled during the ACTIVE command and READ/WRITE to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a LOAD MODE REGISTER command Bank Address Outputs: BA0 and BA1 define which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied Reserved Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. NOTE: MCSX is considered part of the command code.
MBA0 - MBA1
G18, H19
2
LVTTL
O
MCLK MCASX
I16 J21
1 1
nc LVTTL
nc O
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Table 21 BMU SDRAM Interface Signals (continued)
Signal Name
MRASX
Pin #
I20
Total Type
1 LVTTL
I/O
O
Signal Description
Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. MCSX is considered part of the command code. Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. MCSX is considered part of the command code. Chip Select: MCSX enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when MCSX is registered HIGH. MCSX provides the external bank selection on systems with multiple banks. MCSX is considered part of the command code. Input/Output Mask: MDQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when MDQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a high Z state (two-clock latency) when MDQM is sampled HIGH during the READ cycle. NOTE: MDQML is an identical copy of MDQM used to drive the loading on SDRAM configurations with 2 DQM pins. Clock: MDCLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of the MDCLK. MDCLK also increments the internal burst counter and controls the output registers.
MWEX
J20
1
LVTTL
O
MCSX
H20
1
LVTTL
O
MDQM MDQML
H21 G14
1 1
LVTTL LVTTL
O O
MDCLK
J17
1
LVTTL
I
Total Pins
161
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CHAPTER 2: SIGNAL DESCRIPTIONS
TLU SRAM Interface Signals
The TLU SRAM interface supports up to 32MBytes of SRAM at frequencies to 133MHz using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to 64Mbits. The TLU SRAM interface signals are described in Table 22.
Table 22 TLU SRAM Interface Signals
Signal Name
TD0 - TD63
Pin #
Total
Type
LVTTL
I/O
I/O
Signal Description
TLU Memory Data
N1, L1, J1, H1, M2, K2, I2, G2, N2, L2, J2, H2, L3, J3, 64 H3, G4, 04, M4, K4, I4, L4, J4, H4, G6, N5, L5, J5, H5, N6, L6, I6, H6, K6, J6, M6, H7, L7, J7, H8, N8, M8, K8, I8, G8, N7, L8, J8, H9, L9, J9, J10, G10, P9, O8, L10, H10, O10, N9, L11, I10, M10, K10, J11, H11 R1, P1, S2, Q2, O2, R2, P2, R3, P3, N3, S4, Q4, R4, P4, 22 N4, R5, P5, S6, R6, Q6, P6, O6 T8, Q8, R7, P7 P8, R8, S8, T9 Q10, R9, S10, T10 M12 4 4 4 1 99 Table 23 Memory Bank Selection
TA0 - TA21 TA18x - TA21x TCE0X - TCE3X TWE0X - TWE3X TCLKI
LVTTL LVTTL LVTTL LVTTL LVTTL
O O O O I
TLU Memory Address Data Parity TLU Memory Chip Enable TLU Memory Write Enable TLU Clock Input
Total Pins
Chip Select (Signals TA18x through TA21x) Size CE2
4Mbit 8Mbit 16Mbit TA18x TA19x TA20x
Bank 1 CE2x
TA19 TA20 TA21
Bank 2 CE2
TA18 TA19 TA20
Bank 3 CE2
TA18x TA19x TA20x
Bank 4 CE2
TA18 TA19 TA20
CE2x
TA19 TA20 TA21
CE2x
TA19x TA20x TA21x
CE2x
TA19x TA20x TA21x
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QMU SRAM Interface Signals
The QMU signals are described in Table 24. The QMU's clock frequency is 1/2 the internal core clock frequency.
Table 24 QMU SRAM Interface Signals
Signal Name
QCPAR QCLK QCMD0 - QCMD15 QDPAR QDATA0 - QDATA31
Pin #
A10 G12 B10, C10, D10, E10, F10, B11, D11, F11, A12, B12, C12, D12, E12, B13, D13, F13 A8 D1, F1, F2, B2, C2, D2, E2, B3, D3, F3, A4, B4, C4, D4, E4, F4, B5, D5, F5, A6, B6, C6, D6, E6, F6, B7, D7, F7, C8, D8, E8, F8 B9 D9 F9 B8
Total Type
1 1 16 1 32 nc LVTTL LVTTL LVTTL LVTTL
I/O* Signal Description
nc O O I/O I/O Not used Clock Signal to the memory ICs Memory Address [15: 0] to the memory ICs Data parity Memory Data
QSFLOW QXCTRL0 QXCTRL1 QXRQST
1 1 1 1 55
LVTTL LVTTL LVTTL nc
O O O nc
Not Used Rd/Wr (Read is true high, write is true low) Memory Address [16] to the memory ICs Reserved Note: Requires Pullup or Pulldown.
Total Pins
*During normal (non-scan) operation.
Power Supply Signals
Table 25 Power Supply Signals
Power supply and ground signals are described in Table 25 and their pinouts are shown in Figure 6.
Signal Name
VDD
Pin #
Total
Type
P
Signal Description
Core Supply Voltage (1.8V Input)
A3, A11, A15, A23, A27, C1, C5, C13, C17, C25, C29, 78 E3, E7, E15, E19, E27, G5, G9, G17, G21, G29, I7, I11, I19, I23, J12, K1, K9, K13, K21, K25, L14, M3, M11, M15, M23, M27, O1, O5, O13, O17, O25, O29, Q3, Q7, Q15, Q19, Q27, S5, S9, S17, S21, S29, U7, U11, U19, U23, W1, W9, W13, W21, W25, Y3, Y11, Y15, Y23, Y27, AA1, AA5, AA13, AA17, AA25, AA29, AC3, AC7, AC15, AC19, AC27 A7, A19, C9, C21, E11, E23, F12, G1, G13, G25, H14, I3, 39 I15, I27, J16, K5, K17, K29, M7, M19, O9, O21, Q11, Q23, S1, S13, S25, U3, U15, U27, W5, W17, W29, Y7, Y19, AA9, AA21, AC11, AC23
VDD33
P
I/O Supply Voltage (3.3V Input)
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Table 25 Power Supply Signals (continued)
Signal Name
VSS
Pin #
Total
Type
P
Signal Description
Ground
A5, A9, A13, A17, A21, A25, A29, C3, C7, C11, C15, 116 C19, C23, C27, E1, E5, E9, E13, E17, E21, E25, E29, G3, G7, G11, G19, G23, G27, H12, H16, I1, I5, I9, I13, I17, I21, I25, I29, J14, J18, K3, K7, K11, K15, K19, K23, K27, L16, M1, M5, M9, M13, M17, M21, M25, M29, O3, O7, O11, O15, O19, O23, O27, Q1, Q5, Q9, Q13, Q17, Q21, Q25, Q29, S3, S7, S11, S15, S19, S23, S27, U1, U5, U9, U13, U17, U21, U25, U29, W3, W7, W11, W15, W19, W23, W27, Y1, Y5, Y9, Y13, Y17, Y21, Y25, Y29, AA3, AA7, AA11, AA15, AA19, AA23, AA27, AC1, AC5, AC9, AC13, AC17, AC21, AC25, AC29 234
Total Pins
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Figure 6 Power and Ground Connections (Bottom View)
AC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
VSS (Ground) - 0.0V VDD (Core Supply) - 2.5V VDD33 (I/O Supply) - 3.3V Other
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Test Signals
Test signals are described in Table 26 and their pinouts are shown in Figure 6.
Table 26 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
Signal Name
JTCK JTMS*
Pin #
T11 Z15
Total
1 1
Type
LVTTL LVTTL
Signal Description
Test Clock Test Mode Select. High selects modes as defined in the IEEE 1149.1 JTAG specification. Test Reset (low active) Test Data In Test Data Out Turns off all output drivers when High 1X or 2X Clock Mode Select. Low selects 1X, High selects 2X. Scan Enable. High enables scan test. Scan Out Pins
JTRSTX JTDI JTDO JHIGHZ JCLKBYP JSE JS00-JS09
X15 AB15 V15 T12 T13 S12 L12, N13, N12, P13, P12, Q12, R13, R12, R11, R10
1 1 1 1 1 1 10 18
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
Total Pins
*
According to the IEEE 1149.1 specification, the JTMS, JTRST, and JTDI pins must have internal pullups. While the C-5 NP does not currently have pads with pullups, customers can pull up these three pins on the board.
During JTAG, SCLK and SCLKX must remain as differential inputs.
No Connection Pins
Table 27 No Connection Pins
No connection pins are listed in Table 27.
Signal Name
NC1 - NC11
Pin #
I18, H17, H18, N10, P10, N11, P11, U14, V14, U16, V16
Total
11 11
Type
nc
Signal Description
Reserved for future functionality
Total Pins
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Signals Grouped by Pin Number
The C-5 NP signals are listed by pin number in Table 28.
Table 28 Signals Listed by Pin Number
Pin
A1 A2 A3 A4 A5 A6 A7 A8
Function
Not present Not present VDD QDATA10 VSS QDATA19 VDD33 QDPAR
Pin
A9 A10 A11 A12 A13 A14 A15 A16
Function
VSS QCPAR VDD QCMD8 VSS MECC8 VDD MD123
Pin
A17 A18 A19 A20 A21 A22 A23 A24
Function
VSS MD113 VDD33 MD103 VSS MD94 VDD MD84
Pin
A25 A26 A27 A28 A29
Function
VSS MD74 VDD MD64 VSS
A 1-29
B 1-29
B1 B2 B3 B4 B5 B6 B7 B8 Not present QDATA3 QDATA7 QDATA11 QDATA16 QDATA20 QDATA25 QXRQST B9 B10 B11 B12 B13 B14 B15 B16 QSFLOW QCMD0 QCMD5 QCMD9 QCMD13 MECC7 MD129 MD126 B17 B18 B19 B20 B21 B22 B23 B24 MD120 MD116 MD110 MD107 MD100 MD97 MD90 MD87 B25 B26 B27 B28 B29 MD81 MD77 MD71 MD68 MD61
C 1-29
C1 C2 C3 C4 C5 C6 VDD QDATA4 VSS QDATA12 VDD QDATA21 C9 C10 C11 C12 C13 C14 VDD33 QCMD1 VSS QCMD10 VDD MECC6 C17 C18 C19 C20 C21 C22 VDD MD114 VSS MD104 VDD33 MD95 C25 CB26 C27 C28 C29 VDD MD75 VSS MD65 VDD
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Table 28 Signals Listed by Pin Number (continued)
Pin
C7 C8
Function
VSS QDATA28
Pin
C15 C16
Function
VSS MD124
Pin
C23 C24
Function
VSS MD85
Pin
Function
D 1-29
D1 D2 D3 D4 D5 D6 D7 D8 QDATA0 QDATA5 QDATA8 QDATA13 QDATA17 QDATA22 QDATA26 QDATA29 D9 D10 D11 D12 D13 D14 D15 D16 QXCTRL0 QCMD2 QCMD6 QCMD11 QCMD14 MECC5 MECC4 MD127 D17 D18 D19 D20 D21 D22 D23 D24 MD121 MD117 MD111 MD108 MD101 MD98 MD91 MD88 D25 D26 D27 D28 D29 MD82 MD78 MD72 MD69 MD62
E 1-29
E1 E2 E3 E4 E5 E6 E7 E8 VSS QDATA6 VDD QDATA14 VSS QDATA23 VDD QDATA30 E9 E10 E11 E12 E13 E14 E15 E16 VSS QCMD3 VDD33 QCMD12 VSS MECC3 VDD MD125 E17 E18 E19 E20 E21 E22 E23 E24 VSS MD115 VDD MD105 VSS MD96 VDD33 MD86 E25 E26 E27 E28 E29 VSS MD76 VDD MD66 VSS
F 1-29
F1 F2 F3 F4 F5 F6 F7 QDATA1 QDATA2 QDATA9 QDATA15 QDATA18 QDATA24 QDATA27 F9 F10 F11 F12 F13 F14 F15 QXCTRL1 QCMD4 QCMD7 VDD33 QCMD15 MECC2 MECC1 F17 F18 F19 F20 F21 F22 F23 MD122 MD118 MD112 MD109 MD102 MD99 MD92 F25 F26 F27 F28 F29 MD83 MD79 MD73 MD70 MD63
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Table 28 Signals Listed by Pin Number (continued)
Pin
F8
Function
QDATA31
Pin
F16
Function
MD128
Pin
F24
Function
MD89
Pin
Function
G 1-29
G1 G2 G3 G4 G5 G6 G7 G8 VDD33 TD7 VSS TD15 VDD TD23 VSS TD43 G9 G10 G11 G12 G13 G14 G15 G16 VDD TD51 VSS QCLK VDD33 MDQML SCLKX MECC0 G17 G18 G19 G20 G21 G22 G23 G24 VDD MBA0 VSS MD119 VDD MD106 VSS MD93 G25 G26 G27 G28 G29 VDD33 MD80 VSS MD67 VDD
H 1-29
H1 H2 H3 H4 H5 H6 H7 H8 TD3 TD11 TD14 TD22 TD27 TD31 TD35 TD38 H9 H10 H11 H12 H13 H14 H15 H16 TD47 TD55 TD63 VSS CCLK5 VDD33 SCLK VSS H17 H18 H19 H20 H21 H22 H23 H24 NC2 NC3 MBA1 MCSX MDQM MA0 MA2 MA3 H25 H26 H27 H28 H29 MA5 MA6 MA8 MA9 MA11
I 1-29
I1 I2 I3 I4 I5 I6 I7 I8 VSS TD6 VDD33 TD19 VSS TD30 VDD TD42 I9 I10 I11 I12 I13 I14 I15 I16 VSS TD59 VDD CCLK3 VSS CCLK4 VDD33 MCLK I17 I18 I19 I20 I21 I22 I23 I24 VSS NC1 VDD MRASX VSS MA1 VDD MA4 I25 I26 I27 I28 I29 VSS MA7 VDD33 MA10 VSS
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Table 28 Signals Listed by Pin Number (continued)
Pin
J1 J2 J3 J4 J5 J6 J7 J8
Function
TD2 TD10 TD13 TD21 TD26 TD33 TD37 TD46
Pin
J9 J10 J11 J12 J13 J14 J15 J16
Function
TD49 TD50 TD62 VDD CCLK1 VSS CCLK2 VDD33
Pin J 1-29
J17 J18 J19 J20 J21 J22 J23 J24
Function
MDCLK VSS XPUHOT MWEX MCASX MD56 MD48 MD60
Pin
J25 J26 J27 J28 J29
Function
MD52 MD55 MD40 MD32 MD24
K 1-29
K1 K2 K3 K4 K5 K6 K7 K8 VDD TD5 VSS TD18 VDD33 TD32 VSS TD41 K9 K10 K11 K12 K13 K14 K15 K16 VDD TD61 VSS CCLK0 VDD CCLK6 VSS CCLK7 K17 K18 K19 K20 K21 K22 K23 K24 VDD33 PSTOPX VSS PFRAMEX VDD MD47 VSS MD44 K25 K26 K27 K28 K29 VDD MD36 VSS MD28 VDD33
L 1-29
L1 L2 L3 L4 L5 L6 L7 L8 TD1 TD9 TD12 TD20 TD25 TD29 TD36 TD45 L9 L10 L11 L12 L13 L14 L15 L16 TD48 TD54 TD58 JSO0 CPREF VDD PCLK VSS L17 L18 L19 L20 L21 L22 L23 L24 PREQX PSERRX PIRDYX PTRDYX MD59 MD51 MD54 MD39 L25 L26 L27 L28 L29 MD43 MD31 MD35 MD23 MD27
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Table 28 Signals Listed by Pin Number (continued)
Pin
M1 M2 M3 M4 M5 M6 M7 M8
Function
VSS TD4 VDD TD17 VSS TD34 VDD33 TD40
Pin
M9 M10 M11 M12 M13 M14 M15 M16
Function
VSS TD60 VDD TCLKI VSS SPCK VDD SPLD
Pin
M17 M18 M19 M20 M21 M22 M23 M24
Function
VSS PPERRX VDD33 PCBEX2 VSS MD46 VDD MD38
Pin
M25 M26 M27 M28 M29
Function
VSS MD30 VDD MD22 VSS
M 1-29
N 1-29
N1 N2 N3 N4 N5 N6 N7 N8 TD0 TD8 TA9 TA14 TD24 TD28 TD44 TD39 N9 N10 N11 N12 N13 N14 N15 N16 TD57 NC4 NC6 JSO2 JSO1 SIDA SPDO SPDI N17 N18 N19 N20 N21 N22 N23 N24 PRSTX PDEVSELX PGNTX PCBEX1 PCBEX0 MD58 MD50 MD42 N25 N26 N27 N28 N29 MD37 MD34 MD29 MD26 MD21
O 1-29
O1 O2 O3 O4 O5 O6 O7 O8 VDD TA4 VSS TD16 VDD TA21 VSS TD53 O9 O10 O11 O12 O13 O14 O15 O16 VDD33 TD56 VSS TCLKO VDD SICL VSS PINTA O17 O18 O19 O20 O21 O22 O23 O24 VDD PIDSEL VSS PCBEX3 VDD33 MD53 VSS MD41 O25 O26 O27 O28 O29 VDD MD33 VSS MD25 VDD
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Table 28 Signals Listed by Pin Number (continued)
Pin
P1 P2 P3 P4 P5 P6 P7 P8
Function
TA1 TA6 TA8 TA13 TA16 TA20 TA21X TCE0X
Pin
P9 P10 P11 P12 P13 P14 P15 P16
Function
TD52 NC5 NC7 JSO4 JSO3 PPAR PAD29 PAD23
Pin
P17 P18 P19 P20 P21 P22 P23 P24
Function
PAD20 PAD14 PAD11 PAD5 PAD2 MD45 MD57 MD14
Pin
P25 P26 P27 P28 P29
Function
MD17 MD8 MD11 MD2 MD5
P 1-29
Q 1-29
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VSS TA3 VDD TA11 VSS TA19 VDD TA19X Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 VSS TWE0X VDD33 JSO5 VSS PAD31 VDD PAD26 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS PAD17 VDD PAD8 VSS MD49 VDD33 MD13 Q25 Q26 Q27 Q28 Q29 VSS MD7 VDD MD1 VSS
R 1-29
R1 R2 R3 R4 R5 R6 R7 R8 TA0 TA5 TA7 TA12 TA15 TA18 TA20X TCE1X R9 R10 R11 R12 R13 R14 R15 R16 TWE1X JSO9 JSO8 JSO7 JSO6 PAD28 PAD22 PAD16 R17 R18 R19 R20 R21 R22 R23 R24 PAD13 PAD10 PAD7 PAD4 PAD1 MD20 MD19 MD16 R25 R26 R27 R28 R29 MD12 MD10 MD6 MD4 MD0
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Table 28 Signals Listed by Pin Number (continued)
Pin
S1 S2 S3 S4 S5 S6 S7 S8
Function
VDD33 TA2 VSS TA10 VDD TA17 VSS TCE2X
Pin
S9 S10 S11 S12 S13 S14 S15 S16
Function
VDD TWE2X VSS JSE VDD33 PAD25 VSS PAD19
Pin
S17 S18 S19 S20 S21 S22 S23 S24
Function
VDD PAD18 VSS PAD9 VDD MD18 VSS MD15
Pin
S25 S26 S27 S28 S29
Function
VDD33 MD9 VSS MD3 VDD
S 1-29
T 1-29
T1 T2 T3 T4 T5 T6 T7 T8 FIN2 FIN7 FIN6 FIN12 FIN16 FIN17 FIN19 TA18X T9 T10 T11 T12 T13 T14 T15 T16 TCE3X TWE3X JTCK JHIGHZ JCLKBYP PAD30 PAD27 PAD24 T17 T18 T19 T20 T21 T22 T23 T24 PAD21 PAD15 PAD12 PAD6 PAD3 PAD0 FOUT19 FOUT17 T25 T26 TT27 T28 T29 FOUT16 FOUT12 FOUT6 FOUT7 FOUT2
U 1-29
U1 U2 U3 U4 U5 U6 U7 U8 VSS FIN4 VDD33 FIN11 VSS FIN15 VDD FIN24 U9 U10 U11 U12 U13 U14 U15 U16 VSS FIN27 VDD FRXCTL0 VSS NC8 VDD33 NC10 U17 U18 U19 U20 U21 U22 U23 U24 VSS FTXCTL0 VDD FOUT27 VSS FOUT24 VDD FOUT15 U25 U26 U27 U28 U29 VSS FOUT11 VDD33 FOUT4 VSS
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Table 28 Signals Listed by Pin Number (continued)
Pin
V1 V2 V3 V4 V5 V6 V7 V8
Function
FIN1 FIN3 FIN5 FIN9 FIN10 FIN14 FIN18 FIN22
Pin
V9 V10 V11 V12 V13 V14 V15 V16
Function
FIN23 FIN26 FIN31 FRXCTL2 FRXCTL5 NC9 JTDO NC11
Pin
V17 V18 V19 V20 V21 V22 V23 V24
Function
FTXCTL5 FTXCTL2 FOUT31 FOUT26 FOUT23 FOUT22 FOUT18 FOUT14
Pin
V25 V26 V27 V28 V29
Function
FOUT10 FOUT9 FOUT5 FOUT3 FOUT1
V 1-29
W 1-29
W1 W2 W3 W4 W5 W6 W7 W8 VDD FIN0 VSS FIN8 VDD33 FIN13 VSS FIN21 W9 W10 W11 W12 W13 W14 W15 W16 VDD FIN29 VSS FRXCTL1 VDD FRXCLK VSS FTXCLK W17 W18 W19 W20 W21 W22 W23 W24 VDD33 FTXCTL1 VSS FOUT29 VDD FOUT21 VSS FOUT13 W25 W26 W27 W28 W29 VDD FOUT8 VSS FOUT0 VDD33
X 1-29
X1 X2 X3 X4 X5 X6 X7 X8 CP15_0 CP15_1 CP15_2 CP15_3 CP15_4 CP15_5 CP15_6 FIN20 X9 X10 X11 X12 X13 X14 X15 X16 FIN25 FIN28 FIN30 FRXCTL3 FRXCTL4 FRXCTL6 JTRSTX FTXCTL6 X17 X18 X19 X20 X21 X22 X23 X24 FTXCTL4 FTXCTL3 FOUT30 FOUT28 FOUT25 FOUT20 CP14_6 CP14_5 X25 X26 X27 X28 X29 CP14_4 CP14_3 CP14_2 CP14_1 CP14_0
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Table 28 Signals Listed by Pin Number (continued)
Pin
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
Function
VSS CP13_0 VDD CP13_1 VSS CP13_2 VDD33 CP13_3
Pin
Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16
Function
VSS CP13_4 VDD CP13_5 VSS CP13_6 VDD CP12_6
Pin
Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24
Function
VSS CP12_5 VDD33 CP12_4 VSS CP12_3 VDD CP12_2
Pin
Y25 Y26 Y27 Y28 Y29
Function
VSS CP12_1 VDD CP12_0 VSS
Y 1-29
Z 1-29
Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 CP9_0 CP9_1 CP9_2 CP9_3 CP9_4 CP9_5 CP9_6 CP11_0 Z9 Z10 Z11 Z12 Z13 Z14 Z15 Z16 CP11_1 CP11_2 CP11_3 CP11_4 CP11_5 CP11_6 JTMS CP10_6 Z17 Z18 Z19 Z20 Z21 Z22 Z23 Z24 CP10_5 CP10_4 CP10_3 CP10_2 CP10_1 CP10_0 CP8_6 CP8_5 Z25 Z26 Z27 Z28 Z29 CP8_4 CP8_3 CP8_2 CP8_1 CP8_0
AA 1-29
AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 VDD CP7_0 VSS CP7_1 VDD CP7_2 VSS CP7_3 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 VDD33 CP7_4 VSS CP7_5 VDD CP7_6 VSS CP6_6 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 VDD CP6_5 VSS CP6_4 VDD33 CP6_3 VSS CP6_2 AA25 AA26 AA27 AA28 AA29 VDD CP6_1 VSS CP6_0 VDD
AB 1-29
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Table 28 Signals Listed by Pin Number (continued)
Pin
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8
Function
CP3_0 CP3_1 CP3_2 CP3_3 CP3_4 CP3_5 CP3_6 CP5_0
Pin
AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16
Function
CP5_1 CP5_2 CP5_3 CP5_4 CP5_5 CP5_6 JTDI CP4_6
Pin
AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24
Function
CP4_5 CP4_4 CP4_3 CP4_2 CP4_1 CP4_0 CP2_6 CP2_5
Pin
AB25 AB26 AB27 AB28 AB29
Function
CP2_4 CP2_3 CP2_2 CP2_1 CP2_0
AC 1-29
AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 VSS CP1_0 VDD CP1_1 VSS CP1_2 VDD CP1_3 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 VSS CP1_4 VDD33 CP1_5 VSS CP1_6 VDD CP0_6 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 VSS CP0_5 VDD CP0_4 VSS CP0_3 VDD33 CP0_2 AC25 AC26 AC27 AC28 AC29 VSS CP0_1 VDD CP0_0 VSS
JTAG Support
The C-5 NP contains JTAG test logic compliant with the IEEE 1149.1 specification. All required public instructions are implemented, as well as some optional instructions. This section contains information regarding the pinout, instructions, identification codes, and boundary scan cell types.
Pinout
The C-5 NP uses the standard JTAG pins including the optional test reset pin. Table 26 describes the pins and their functions. Note that pins for JTRSTX, JTDI, and JTMS require external pullups on the board. These ports do not have internal pullups as required by the 1149.1 specification.
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JTAG Data Registers
The C-5 NP contains the standard internal registers as specified in IEEE 1149.1. These registers are described in Table 29.
Table 29 JTAG Internal Register Descriptions
Register Name
Bypass Boundary Device Identification
Register Length
1 1807 32
Description
Standard JTAG bypass register Boundary Scan Register Standard JTAG IDCODE Register
Boundary Scan Cell Types
The C-5 NP boundary scan register contains only two cell types. All input cells are observe only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE 1149.1-1990 specification, the BC_4 cell is shown in Figure 7 and the BC_1 cell is shown in Figure 8.
Figure 7 Observe-Only Cell
To next cell
From System Pin G1 0 1 From last cell Shift DR Clock DR
To System Logic
1D C1
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Figure 8 Cell Design That Can Be Used for Both Input and Output Pins
Node To next cell G1 0 1 G1 0 1 From last cell Clock DR To System Logic
Shift DR From System Pin
1D C1
1D C1 Update DR
IDcode Register
The C-5 NP implements a standard 32bit JTAG identification register. Table 30 lists the value of the code for full identification and its sub-components.
Table 30 JTAG Identification Code and Its Sub-components
Field Name
Version Part Number Manufacturer Identity LSB
Width
4 16 11 1
Bit Positions
31-28 27-12 11-1 0
Binary Value
0000 0000_0000_0000_0010 001_1001_0110 1
The concatenated 32bit value is hexidecimal 0000232d.
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JTAG Instruction Register
The C-5 NP contains a 4bit instruction register. Table 31 lists the instructions that are supported.
Table 31 Instruction Register Instructions
Instruction Mnemonic
Extest Idcode Sample/Preload Highz Clamp Bypass Reserved* Reserved* Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass
*
Selected Register
Boundary Scan Identification Register Boundary Scan Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register
Instruction Opcode
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
There are two reserved instructions intended for C-Port Corporation's internal use. These should not be programmed by users.
Boundary Scan Description Language
In order to simplify board test, C-Port Corporation has provided a boundary scan description language (BSDL) file in the C-Port web site support area that describes the complete set of instructions, boundary scan order, and identification code value in an industry standard format. This information can be found at: http://e-www.motorola.com/webapp/sps/site/homepage.jsp?nodeId=03M0ylgx1Ks.
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Chapter 3
Electrical Specifications
Absolute Maximum Ratings
Table 32 lists the absolute maximum ratings for the C-5 network processor. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" (Table 33) is possible. Exposure to conditions beyond Table 32 can:Reduce device reliability
*
Result in premature device failure, even with no immediate sign of failure
Prolonged exposure to conditions at or near the absolute maximum ratings could also result in reduced useful life and reliability of the C-5 NP.
Table 32 C-5 Network Processor Absolute Maximum Ratings
Parameter
VDD33 Supply Voltage (3.3V input)* VDD Supply Voltage (1.8V input)* Voltage on any pin Static Discharge Voltage Storage Temperature Absolute Maximum Junction Temperature
*
Min
-0.5 -0.5 -0.5 2000/500 -40 -40
Max
+5 +2.8 VDD33 + 0.5 +125 +125
Unit
V V V V C C
Voltages are relative to Ground Not to exceed VDD + 2.5V
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Recommended Operating Conditions
The recommended operating conditions describe an environment the C-5 NP network processor is expected to encounter during normal operation. Table 33 delineates the recommended operating parameters for the C-5 NP.
Table 33 C-5 Network Processor Recommended Operating Conditions
Parameter
VDD33 Supply Voltage VDD Supply Voltage IDD33 - VDD33 Supply Current IDD - VDD Supply Current Tj Junction Temperature
*
Min
3.135 1.7
Max
3.465 1.9 1.5* 14*
Unit
V V A A C
-40
100
Peak values to be used by power supply designer.
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DC Characteristics
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DC Characteristics
The DC electrical characteristics define the input operating conditions for proper operation and the output responses to applied DC signals and switch characteristics over specified voltage and temperature ranges. The DC electrical characteristics are specified within the recommended operating conditions including operating temperature and power supply range as stated in this data sheet. Table 34 outlines the C-5 NP DC characteristics.
Table 34 C-5 Network Processor DC Characteristics
Parameter*
LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Output High Voltage LVTTL Output Low Voltage LVTTL Input Current LVPECL Input High Voltage LVPECL Input Low Voltage LVPECL Output High Voltage LVPECL Output Low Voltage LVPECL Input Current CPREF
*
Min
2.0 -0.3 2.4
Max
VDD33+.3 0.8 0.4
Unit
V V V V A V V V V A V
Notes
@IOH = -2mA @IOL = +2mA VIN = 0V or VDD33
-5 VDD33 -1.165 -0.3 VDD33 -1.025 VDD33 -1.810 -5 VDD33 -1.38
+5 VDD33+.3V VDD33 -1.475 VDD33 -0.880 VDD33 -1.620 +5 VDD33 -1.26
Load = 50ohm to VDD33 - 2V Load = 50ohm to VDD33 - 2V Single-ended LVPECL reference
All voltages are relative to Ground unless otherwise indicated.
Each control input pin has a capacitance associated with it. The capacitance at the control input is due to the package and the input circuitry connected to the pin. Capacitance is based on these conditions: TA = 25C; VDD33 = 3.3V; f = 1MHz. Table 35 provides capacitance data.
Table 35 C-5 Network Processor Capacitance Data
Parameter
Input/Output Pins Input Pins Clock Pins
Typical
7 6 6
Max
8 7 7
Unit
pF pF pF
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Power Sequencing
The VDD rail must be kept within 2.5V of the VDD33 rail. However, this rule can be violated for periods up to one second, as is typical during power sequencing, as long as:
* *
The VDD is not clamped to ground or some other low voltage. The number of power cycling events averages to less than once per day over the lifetime of the product.
It is intended that the VDD and VDD33 rail be sequenced to their final value together for most applications. It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running or begin running during power sequencing to propagate reset inside the C-5 NP. Figure 9 indicates the relationship between the clocks and PRSTX. There is no requirement that the asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be asserted within 100s of power initiation. Typically, reset is held low during power initiation.
Figure 9 Bringup Clock Timing Diagram
VDD, VDD33
100s
PRSTX
)(
1ms
TCLKI, PCLK, SCLK, SCLKX, MDCLK, FTXCLK, FRXCLK
100s
)(
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Power and Thermal Characteristics
Table 36 provides the derived power and thermal characteristics for the production version (Revision D0) of the C-5 NP.
Table 36 C-5 Network Processor Power and Thermal Characteristics
Parameter
Power Dissipation, PD
Min
10.5 11.5 12.5 14.5
Typ
15.0 16.0 17.5 20.0
Max
18.0 19.0 20.5 23.0 100
Units
W
Test Conditions
166MHz core clock (See Note 1) 180MHz core clock (See Note 1) 200MHz core clock (See Note 1) 233MHz core clock (See Note 1)
Maximum Junction Temperature, TJ Thermal Resistance, junction to case, JC Thermal Resistance, junction to ambient, JA Thermal Resistance, junction to printed circuit board, JB Thermal Resistance, Junction through Board to Ambient, JBA Effective Thermal Resistance, effective 0.24 1.87 4.8 6.0
oC oC/W oC/W oC/W
See Note 2 See Note 2 See Note 2 See Note 2
1.43
oC/W
See Note 3
Notes for Table 36: 1 Estimated power dissipation (+/-10%) is derived from measurements on the C-5 NP Revision D00 under following conditions:
* * * * * *
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BMU memory operating at 125MHz. TLU memory operating at 133MHz. VDD = 1.8V, VDD33 = 3.3V, TJ at approximately 50o C. "Minimum" PD based on idle condition (clocks running and no programs executing). "Typical" PD based on test application that implements Fast Ethernet forwarding actively running on all CPs. "Maximum" PD based on projected maximum consumption for any high-bandwidth communications application executing on all CPs, FP, and XP.
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2 Thermal performance specifications based on following conditions:
*
Printed circuit board is based on the C-Ware Development System's C-5 NP Switch Module reference design, with specifications of: - 14 total layers (5 planes). Planes at least 100mm x 100mm below the C-5 NP before any interruptions. - FR4 board material, Cu signal and plane material. - 0.5mils signal layer thickness, 1.4mils plane layer thickness. - Thermal resistance, board to ambient (BA) of 1.2 oC/W.
*
Custom heat sink design has the following characteristics: - Dimensions: 100mm x 80mm x 10mm (height) - Thermal resistance heat sink to ambient (SA) of 1.6 oC/W @200 LFM. Figure 10 provides the characteristic thermal resistance curve for this head sink for various airflow rates. - Thermal resistance case to heat sink (CS) of 0.03 oC/W (Chomerics T705 thermal material). - Note that target heat sink design is for low profile (10mm height) applications. Significantly better thermal performance is possible with taller and/or wider designs. Contact your C-Port representative for heat sink options.
3 Effective Thermal Resistance (effective = JAJB / (JA + JB)) reflects the total thermal performance of the heat sink and board, as outlined in Note 2 above.
Figure 10 Thermal Performance for C-5 Network Processor Heat Sink (see step 2 above)
3
Thermal Resistance (C/W)
2
1
0 0 200 400 600 800 1000 Velocity (ft/min)
Theoretical calculation of thermal resistance as a function of airflow velocity across heat sink
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AC Timing Specifications
AC timing specifications consist of input requirements and output responses. The input requirements include setup and hold times, pulse widths, and high and low times. The output responses include delays from clock to signal. The AC timing specifications are defined separately for each interface to the C-5 NP Unless otherwise noted, all AC specifications were tested within the functional operating range. See Figure 11. Output timing specifications for LVTTL pins are given with a 10pF load on the output. Other loads can be simulated with the IBIS model available from C-Port. The LVPECL driver is specified into a 50 load terminated to a (VDD33 - 2V) reference.
Figure 11 Test Loading Conditions
LVTTL DUT 10pF
VDD33
+2V
LVPECL DUT 50
Clock Timing Specifications
The system clock timing is shown in Figure 12 and described in Table 37.
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Figure 12 System Clock Timing Diagram
Cycle 1 SCLK SCLKX Tsc Tsh Tsl Cycle 2 Cycle 3 Cycle 4 Cycle 5
CCLKn TccN Tcch Tccl
Table 37 System Clock Timing Description
Min Symbol Parameter
Tsc System Cycle Time
Max 1X Clk Mode 2X Clk Mode Unit Comment
ns 166MHz core clock 200MHz core clock 233MHz core clock Duty cycle* Duty cycle ns ns ns ns ns ns ns ns 60% 60% 60% 60% T1 E1 E3 T3 RMII Fibre Channel GMII OC-3 % cycle pulse is high % cycle pulse is low 3.0 2.5 2.14 30 30 647.67 488.28 29.097 22.353 20.00 9.412 8.00 6.43 55 55 70 70
1X Clk Mode 2X Clk Mode Typ
6.0 5.0 4.3 45 45
Tsh Tsl Tcc0 Tcc1 Tcc2 Tcc3 Tcc4 Tcc5 Tcc6 Tcc7 Tcch Tccl
*
Sys Clk High Pulse Sys Clk Low Pulse CCLK0 Cycle Time CCLK1 Cycle Time CCLK2 Cycle Time CCLK3 Cycle Time CCLK4 Cycle Time CCLK5 Cycle Time CCLK6 Cycle Time CCLK7 Cycle Time CCLKm High Time CCLKm Low Time
40% 40%
40% 40%
Pulse duty cycle measured at crossing voltage of SCLK/SCLKX The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP . Clock inputs associated with a specific protocol should be tied to ground when that protocol is not used by the C-5 NP . It is also possible to use one or more CCLKn inputs for other frequencies; contact your C-Port representative for more information.
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Unused clocks should be pulled to a known state (ground) through a resistor. If you are using a clock generator, disabling the output should not cause a tristate. If it does, then the line should be pulled down.
CP Timing Specifications
This section describes the timing for the following CP interfaces:
* * * * *
DS1/DS3 10/100 Ethernet Gigabit Ethernet OC-3 OC-12
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DS1/DS3 Timing Specifications
The DS1/DS3 interface timing is shown in Figure 13 and described in Table 38.
Figure 13 DS1/DS3 Ethernet Timing Diagram
Cycle 1 CPn_0 (TCLK) Tcdt CPn_2/3 (Tx) Tcdo Cycle 2 CPn_1 (RCLK) Tcdr CPn_4/5 (Rx) Tcds Tcdh Cycle 3 Cycle 4 Cycle 5 Cycle 2 Cycle 3 Cycle 4 Cycle 5
Table 38 DS1/DS3 Ethernet Timing Description
Symbol Parameter
Tcdt Tcdo Tcdr Tcds Tcdh DS1/DS3 Transmit Cycle Time DS1/DS3 Output Time DS1/DS3 Receive Cycle Time DS1/DS3 Setup Time DS1/DS3 Hold Time
Min
3.0/3.0
Typ
647/22.4
Max
400/15.0
Unit
ns ns ns ns ns
647/22.4 2.0 2.5
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10/100 Ethernet Timing Specifications
The 10/100 Ethernet interface timing is shown in Figure 14 and described in Table 39.
Figure 14 10/100 Ethernet Timing Diagram
Cycle 1 CPn_0 (TCLK) Tcet CPn_2/3/6 (Tx) Tceo CPn_1/4/5 (Rx) Tces Tceh Cycle 2 Cycle 3 Cycle 4 Cycle 5
Table 39 10/100 Ethernet Timing Description
Symbol Parameter
Tcet Tceo Tces Tceh
*
Min
3.0 2.0 2.5
Typ
20
Max
15.0
Unit
ns ns ns ns
Transmit Cycle Time* Output Time Setup Time Hold Time
STD/Fast Ethernet
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Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications
The Gigabit GMII Ethernet interface timing is shown in Figure 15 and described in Table 40. The TBI interface timing is shown in Figure 15 and described in Table 41.
Figure 15 Gigabit Ethernet and TBI Interface Timing Diagram
GMII / TBI Tx
CPn_0 (TCLK) Tcgt CPn_2-6 (Tx) CPn+1_2-6 (Tx) Tcgo Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
MII Tx
MII CPn_1 (TCLK)
Cycle 1
Cycle 2
Cycle 3
Tcmt MII CPn_2-6 (Tx) Tcmo
TBI Rx
CPn+2_1 (RCLKN) CPn+3_1 (RCLK)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tctr Tctd CPn_2-6 (Rx) CPn+1_2-6 (Rx) Tcts Tcth
GMII Rx
CPn+2_1 (RCLK) CPn+2_2-6 (Rx) CPn+3_2-6 (Rx)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tcgr
Tcgs
Tcgh
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Table 40 Gigabit GMII/MII Ethernet Interface Timing Description
Symbol Gigabit Parameter
Tcgt Tcgo Tcgr Tcgs Tcgh Tcmt Tcmo Transmit Cycle Time, GMII Output Time, GMII Receive Cycle Time Setup Time Hold Time Transmit Cycle Time, MII Output Time, MII
Min
3.0
Typ
8.0
Max
6.0
Unit
ns ns ns ns ns
Comment
8.0 1.5 0.5 40/400 2 12
ns ms
100BaseT/10BaseT
Table 41 Gigabit TBI Interface Timing Description
Symbol TBI Parameter
Tctt Tcto Tctr Tctd Tcts Tcth
*
Min
3.0
Typ
8.0
Max
6.0*
Unit
ns ns ns ns ns ns
Transmit Cycle Time Output Time Receive Cycle Time Rclk/Rclkn Deviation Setup Time Hold Time 1.5 0.5
16.0 1.0
For Fibre Channel applications this value is 7.0ns for a transmit cycle time of 9.4ns.
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OC-3 Timing Specifications
The OC-3 interface timing is shown in Figure 16 and described in Table 42.
Figure 16 OC-3 Timing Diagram
Cycle 1 CPn_2 Tc3t CPn_3 Tc3i Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_0 CPn_1 Tc3r Tc3d CPn_4 Tc3s CPn_5 Tc3s Tc3h Tc3h
Table 42 OC-3 Timing Description
Symbol Parameter
Tc3t Tc3i Tc3r Tc3d Tc3s Tc3h
*
Min
2.0 6.0 40 2.0 2.5
Typ
6.43
Max
Unit
ns ns ns
OC-3 Transmit Cycle Time OC-3 Pulse Width OC-3 Receive Cycle Time* OC-3 Clock Duty Cycle OC-3 Setup Time OC-3 Hold Time
60
% ns ns
155.52MHz
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OC-12 Timing Specifications
The OC-12 interface timing is shown in Figure 17 and described in Table 43.
Figure 17 OC-12 Timing Diagram
Cycle 1 CPn_1 (TCLKI) Tc12i Tc12d CPn_0 (TCLK) Tc12t CPn_2-6 (Tx) Tc12o Cycle 1 Cycle 2 Cycle 3 Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_1 (RCLK) Tc12r CPn_2-6 (Rx) Tc12s Tc12h
Table 43 OC-12 Timing Description
Symbol Parameter
Tc12i Tc12d Tc12t Tc12o Tc12r Tc12s Tc12h
*
Min
40
Typ
12.86
Max
60
Unit
ns % ns ns ns ns ns
OC-12 Transmit Cycle Time* OC-3 Clock Duty Cycle OC-12 Transmit Cycle Time OC-12 Output Time OC-12 Receive Cycle Time OC-12 Setup Time OC-12 Hold Time 3.0 12.0 2.0 2.5
12.86 10.0 12.86
Input from PHY Output from C-5 NP Aligned to TCLK
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Executive Processor Timing Specifications
The XP timing specifications include:
* * * *
PCI Timing Specifications MDIO Serial Interface Timing Specifications Low Speed Serial Interface Timing Specifications PROM Interface Timing Specifications
PCI Timing Specifications
The PCI timing is shown in Figure 18 and described in Table 44.
Figure 18 PCI Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
PCLK Tpc PAD/P_ctl (output) Tpao PAD/P_ctl (input) Tpas PGNTX (input) Tpgs PIDSEL (input) Tpis Tpih Tpgh Tpah Tpaz Tpav
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Table 44 PCI Timing Description
Symbol Parameter
Tpc Tpas Tpah Tpao Tpaz Tpav Tpgs Tpgh Tpis Tpih PCI Cycle Time* PAD/P_ctl Setup PAD/P_ctl Hold PAD/P_ctl Output PAD/P_ctl Clk to Tri PAD/P_ctl Clk to Driven PGNTX Setup PGNTX Hold PIDSEL Setup PIDSEL Hold PRSTX** PINTA**
*
Min
15.0 3.0 0.0 2.0 1.8 1.3 5.1 0.0 5.0 0.0
Typ
Max
Unit
ns ns ns
6.0 5.5 5.5
ns ns ns ns ns ns ns ns ns
66MHz PCI P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX, PSTOPX, PDEVSELX, PPERRX, PSERRX Not fully tested, values based on design/characterization. ** Asynchronous
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MDIO Serial Interface Timing Specifications
The MDIO serial interface timing is shown in Figure 19 and described in Table 45.
Figure 19 MDIO Serial Interface Timing Diagram
Cycle 2 Cycle 3 Cycle 4
SICL Tsic SIDA (output) Tsods SIDA (input) Tsids Tsodh
Table 45 MDIO Serial Interface Timing Description
Symbol Parameter
Tsic Tsids Tsidh Tsods Tsodh SICL Cycle Time SIDA Input Setup SIDA Input Hold SIDA Output Setup SIDA Output Hold
Min
40 10 0.0 10 10
Typ
Max
Unit
ns ns ns ns ns
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Low Speed Serial Interface Timing Specifications
The low speed serial interface timing is shown in Figure 20 and described in Table 46.
Figure 20 Low Speed Serial Interface Timing Diagram
Cycle 2
Cycle 3
SICL Tsu:s SIDA Thd:s Thd:d Tsu:d Tcyc Tsu:stop Tbuf
Table 46 Low Speed Serial Interface Timing Description
Symbol Parameter
Tcycle Tsu:s Thd:s Tsu:d Thd:d Tsu:stop Tbuf Cmax SICL Cycle Time Set-up Time for Repeated START Condition Hold Time START Condition Data Set-up Time Data Hold Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive load for each line of the bus
Min
2500 600 600 250 0.0 600 1250
Max
Unit
ns ns ns ns ns ns ns
400
pF
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PROM Interface Timing Specifications
The PROM interface timing is shown in Figure 21 and described in Table 47.
Figure 21 PROM Interface Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SPCK Tspc SPDI Tspis SPLD Tsplo SPDO Tspdo Tspih
Table 47 PROM Interface Timing Description
Symbol Parameter
Tspc Tspis Tspih Tsplo Tspdo
*
Clock Mode
Min
40.0 10.0 0.0
Typ
Max
Unit
ns ns ns
SPCK Cycle Time SPDI Setup SPDI Hold SPLD Output SPDO Output 1X 2X 1X 2X
Tsc* 2 x Tsc* Tsc* 2 x Tsc*
Tsc + 3.0 2 x Tsc + 3.0 Tsc + 3.0 2 x Tsc + 3.0
ns ns ns ns
Tsc is the System Cycle Time. See Table 37 on page 70
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Fabric Processor Timing Specifications
Cycle 1
The FP timing specifications are shown in Figure 22 and described in Table 48.
Figure 22 Fabric Processor Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
FRXCLK Tfrc FRXCTL (output) Tfrco FRXCTL (input) Tfrcs FINn Tfrds Tfrdh Tfrch Tfrcz Tfrcv
FTXCLK Tftc FTXCTL (output) Tftco FTXCTL (input) Tftcs FOUTn Tftdo Tftch Tftcz Tftcv
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Table 48 Fabric Processor Timing Description
Symbol Parameter
Tfrc Tfrcs Tfrch Tfrco Tfrcz Tfrcv Tfrds Tfrdh Tftc Tftcs Tftch Tftco Tftcz Tftcv Tftdo
*
Min
9.0 4.0 1.5 0.5 1.0 1.8 1.3 4.0 1.5 0.5 9.0 4.0 1.5 0.5 1.0 1.7 1.3 1.0
Typ
Max
Unit
ns ns ns
Comment
Utopia2 Mode All other modes
FRX Cycle Time FRXCTL Setup FRXCTL Hold FRXCTL Output FRXCTL Clk to Tri* FRXCTL Clk to Driven* FIN Setup FIN Hold FTX Cycle Time FTXCTL Setup FTXCTL Hold FTXCTL Output FTXCTL Clk to Tri* FTXCTL Tri to Driven* FOUT Output
3.4 5.5 5.5
ns ns ns ns ns ns ns ns Utopia2 Mode All other modes Utopia2 Mode All other modes
3.6 5.5 5.5 3.6
ns ns ns ns
Not fully tested, values based on design/characterization.
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BMU Timing Specifications
The BMU timing specifications are shown in Figure 23 and described in Table 49. The BMU synchronous DRAM interface is PC100-compliant and designed to work with industry standard SDRAM components with 12 or fewer address lines. The information below is intended to provide the output, setup, and hold data required to design this interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
Figure 23 BMU Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
MDCLK Tmc M_ctl Tmco MAn Tmao MDn (output) Tmdo MDn (input) Tmds Tmdh Tmdz Tmdv
Table 49 BMU Timing Description
Symbol Parameter
Tmc Tmco Tmao Tmds Tmdh Tmdo Tmdz Tmdv
*
Min
8.0 1.2 1.2 0.5 1.0 1.2 1.8 1.4
Typ
Max
3.7 3.8
Unit
ns ns ns ns ns
BMU Cycle Time BMU Ctrl Output BMU Addr Output BMU Data Setup BMU Data Hold BMU Data Output BMU Data Clk to Tri* BMU Data Clk to Driven*
4.0 4.0 4.0
ns ns ns
Not fully tested, values based on design/characterization.
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Table 50 Signal Groups in BMU Timing Diagrams
Signal Group
Control (M_ctl) Address (MAn) Data (MDn)
Included Signals
MBA0, MBA1, MCASX, MRASX, MWEX, MCSX, MDQM MA0 - MA11 MD0 - MD129, MDECC0 - MDECC8
TLU Timing Specifications
Cycle 1
The TLU timing specifications are shown in Figure 24 and described in Table 51.
Figure 24 TLU Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
TCLKI Ttc T_ctl Ttco TAn Ttao TDn (output) Ttdo TDn (input) Ttds Ttdh Ttdz Ttdv
Table 51 TLU Timing Description
Symbol Parameter
Ttc Ttco Ttao Ttds Ttdh Ttdo Ttdz Ttdv
*
Min
7.5 1.2 1.2 0.5 1.0 1.2 2.0 1.5
Typ
Max
3.4 3.4
Unit
ns ns ns ns ns
TLU Cycle Time TLU Ctrl Output TLU Addr Output TLU Data Setup TLU Data Hold TLU Data Output TLU Data Clk to Tri* TLU Data Clk to Driven*
3.5 3.5 3.5
ns ns ns
Not fully tested, values based on design/characterization.
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Table 52 Signal Groups in TLU Timing Diagrams
Signal Group
Control (T_ctl) Address (TAn) Data (TDn)
Included Signals
TA18X - TA21X, TCE0X - TCE3X, TWE0X - TWE3X TA0 - TA21 TD0 - TD63
QMU Timing Specifications
Cycle 1
The QMU timing specifications are shown in Figure 25 and described in Table 53.
Figure 25 QMU Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
QCLK Tqc QCMDn (output) Tqco QDATAn (output) Tqdo QDATAn (input) Tqds Tqdh Tqdz Tqdv
Table 53 QMU Timing Description
Symbol Parameter
Tqc Tqco Tqds Tqdh Tqdo QMU Cycle Time QMU Ctrl Output QMU Data Setup QMU Data Hold QMU Data Output
Min
2 x Tsc 4 x Tsc 1.5 3.1 1.3 1.5
Typ
Max
Unit
ns ns
Comment
1X Clock Mode 2X Clock Mode 1X Clock Mode 2X Clock Mode
1/2 Tsc + 1.0 Tsc + 1.0 3.5 1/2 Tsc + 1.0 Tsc + 1.0
ns ns ns ns
1X Clock Mode 2X Clock Mode
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Table 53 QMU Timing Description (continued) (continued)
Symbol Parameter
Tqdz Tqdv
*
Min
1.1
Typ
Max
5.5 5.5
Unit
ns ns
Comment
QMU Data Clk to Tri*
QMU Data Clk to Driven* 0.6
Not fully tested, values based on design/characterization.
Table 54 Signal Groups in QMU Timing Diagrams
Signal Group
QCMDn QDATAn
Included Signals
QCMD0 - QCMD15, QSFLOW, QXCTRL0, QXCTRL1, QXRQST QDATA0 - QDATA31, QDPAR
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Chapter 4
Mechanical Specifications
Package Views
The C-5 network processor is an 838 pin (29 pins x 29 pins) Ball Grid Array (BGA) package as shown in the following illustrations. Table 55 defines the package measurements.
Figure 26 C-5 Network Processor BGA Package Side View
A4
A2 A3 A A1 Seating Plane
HiTCE: Green ceramic is thermally matched to FR4 circuit board. The aluminum lid is electrically connected to the grounded substrate of the C-5 NP. Neither the lid nor any heat sink connected to the lid should be part of a current-carrying path. It is acceptable, however, to connect the lid or heatsink to ground if necessary (through the standoff screws for the heat sink).
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Figure 27 C-5 Network Processor BGA Package (Bottom View)
D D1 e
AC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
e
E1
E
b
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Package Measurements
Table 55 defines the C-5 NP package measurements, providing nominal, minimum, and maximum sizes where appropriate.
Table 55 Package Measurements (Reference Figure 26 and Figure 27 for Symbols)
Symbol
A A1 A2 A3 A4 D D1 E E1 e b
Definition
Overall Ball height C4 and Die Body thickness Lid thickness Body size Ball footprint (X) Body size Ball footprint (Y) Ball pitch Ball diameter
Nom. (mm) Min. (mm) Max. (mm)
5.63 0.89 0.88 2.26 1.6 37.50 35.56 37.50 35.56 1.27 0.89 2.07 2.53 5.31 5.95
Marking Codes
Table 56 explains the marking on the C-5 NP.
Table 56 C-5 Network Processor Marking Codes
Marking (Explanation of Codes)
Top Bottom Pin 1 Marking Logo/Part#/Country of Origin/Date Code N/A Chamfered Corner
Reflow
Typical Reflow Profile for the C-5 Switch Module
1 Follow the guidelines recommended by your solder paste supplier. Flux requrements must be met for best solderability. 2 The temperature profile should be carefully characterized to ensure uniform temperature across the board and package.
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Solder ball voiding may be affected by ramp rates and dwell times below and above liquidus. 3 A nitrogen atmosphere is not required, but will make the process more robust. It can make a difference for marginally solderable PC board pads. 4 Full convection forced air furnaces work best, but IR, Convection/IR, or vapor phase can be used.
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Index
Symbols
10/100 Ethernet (RMII) Configuration 26 10/100 Ethernet Signals 27 10/100 Ethernet Timing Description 73 10/100 Ethernet Timing Diagram 73 10/100 Ethernet Timing Specifications 73
A
About This Guide 11 Absolute Maximum Ratings 63 AC Timing Specifications 69
B
Block Diagram, C-5 Network Processor 15 BMU SDRAM Interface Signals 42 BMU Signal Groups 86 BMU Timing Description 85 BMU Timing Diagram 85 BMU Timing Specifications 85 Boundary Scan Cell Types 59 Boundary Scan Description Language 61 Bringup Clock Timing Diagram 66 Buffer Management Unit 18
Channel Processors 16 Channel Processors Physical Interface Signals and Pins Grouped by Clusters 25 Clock and Reference Signals 23 Clock Signals 23 Clock Timing Specifications 69 Configuration 10/100 Ethernet (RMII) 26 DS1/T1 Framer Interface 26 FibreChannel TBI 29 Gigabit Ethernet 29 Gigabit Ethernet (GMII) 27 SONET OC-12 Transceiver Interface 32 SONET OC-3 Transceiver Interface 31 Configurations GMII/TBI Transmit and Receive Pin 28 Connections Power and Ground (Bottom View) 47 CP Timing Specifications 71
D
Data Registers JTAG 59 Data Sheet Description and Organization 11 DC Characteristics 65 Description Functional 15 Description Language Boundary Scan 61 Descriptions Signal 21 Diagram 10/100 Ethernet Timing 73 BMU Timing 85 Bringup Clock Timing 66 DS1/DS3 Ethernet Timing 72 Fabric Processor Timing 83
C
C-5 Network Processor Absolute Maximum Ratings 63 C-5 Network Processor BGA Package, Bottom View 90 C-5 Network Processor BGA Package, Side View 89 C-5 Network Processor Capacitance Data 65 C-5 Network Processor DC Characteristics 65 C-5 Network Processor Power and Thermal Characteristics 67 C-5 NP Channel Processors 16 Channel Processor Interface Signals 24
94
INDEX: E
Gigabit Ethernet (TBI) Timing 74 Low Speed Serial Interface Timing 81 MDIO Serial Interface Timing 80 OC-3 Timing 76 PCI Timing 78 Pinout 22 PROM Interface 36 PROM Interface Timing 82 QMU Timing 87 Signal Groups in BMU Timing 86 Signal Groups in QMU Timing 88 Signal Groups in TLU Timing 87 System Clock Timing 70 TLU Timing 86 Diagram, Block C-5 Network Processor 15 DS1/DS3 Ethernet Timing Description 72 DS1/DS3 Ethernet Timing Diagram 72 DS1/DS3 Timing Specifications 72 DS1/T1 Framer Interface Configuration 26 DS1/T1 Framer Interface Signals 26
G
General System Interface Signal 37 Gigabit Ethernet (GMII) Configuration 27 Gigabit Ethernet (GMII) Signals One Cluster Example 28 Gigabit Ethernet (TBI) Timing Description 75, 75 Gigabit Ethernet (TBI) Timing Diagram 74 Gigabit Ethernet and FibreChannel TBI Configuration 29 Gigabit Ethernet and FibreChannel TBI Signals Example 30 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 74 GMII/TBI Transmit and Receive Pin Configurations 28
I
IDcode Register 60 Instruction Register Instructions 61
J
JTAG Data Registers 59 JTAG Identification Code and Its Sub-components 60 JTAG Instruction Register 61 JTAG Internal Register Descriptions 59 JTAG Support Pinouts 58
E
Electrical Specifications 63 Absolute Maximum Ratings 63 Executive Processor 17 PCI 17 PROM Interface 17 Serial Bus Interface 17 System Interface Signals 33 System Interfaces 17 Executive Processor Timing Specifications 78
L
Low Speed Serial Interface Timing Description 81 Low Speed Serial Interface Timing Diagram 81 Low Speed Serial Interface Timing Specifications 81 LVPECL Specifications 23 LVTTL Specifications 23
F
Fabric Interface Pin Mapping Power X Mode 40 PRIZMA Mode 40 Utopia2/Utopia3 ATM Mode 39 Utopia2/Utopia3 PHY Mode 39 Fabric Processor 18 Fabric Processor Interface Signals 38 Fabric Processor Timing Description 84 Fabric Processor Timing Diagram 83 Fabric Processor Timing Specifications 83 Functional Description 15
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M
MDIO Serial Interface Timing Description 80 MDIO Serial Interface Timing Diagram 80 MDIO Serial Interface Timing Specifications 80 Measurements C-5 Network Processor 91 Mechanical Specifications 89 Miscellaneous Test Signals for JTAG, Scan, and Internal Test Routines 48
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INDEX: N
95
N
No Connection Pins 48
QMU Timing Description 87 QMU Timing Diagram 87 QMU Timing Specifications 87 Queue Management Unit 19
O
OC-12 Signals 32 OC-12 Timing Description 77 OC-12 Timing Specifications 77 OC-3 Signals 31 OC-3 Timing Description 76 OC-3 Timing Diagram 76 OC-3 Timing Specifications 76 Operating Conditions, Recommended 64
R
Recommended Operating Conditions 64 Register IDcode 60 JTAG Instruction 61 revision history, for this guide 11
S
Serial Interface Signals 34 Serial Port Signals 35 Signal General System Interface 37 Signal Descriptions 21 Signal Summary 21 Signals 10/100 Ethernet 27 BMU SDRAM Interface 42 Channel Processor Interface 24 Clock 23 Clock and Reference 23 DS1/T1 Framer Interface 26 Fabric Processor Interface 38 Grouped by Pin Number 49 OC-12 32 OC-3 31 PCI 33 Power Supply 45 PROM Interface 35 QMU SRAM Interface 45 Serial Interface 34 Serial Port 35 Test 48 TLU SRAM Interface 44 SONET OC-12 Transceiver Interface Configuration 32 SONET OC-3 Transceiver Interface Configuration 31 Specifications 10/100 Ethernet Timing 73 AC Timing 69 BMU Timing 85 Clock Timing 69
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P
Package Measurements 91 PCI Signals 33 PCI Timing Description 79 PCI Timing Diagram 78 PCI Timing Specifications 78 Pin Descriptions Grouped by Function 23 Pin Locations 22 Pin Number Signals Groups 49 Pinout Diagram 22 Power and Ground Connections (Bottom View) 47 Power Sequencing 66, 67 Power Supply Signals 45 Power X Mode, Fabric Interface Pin Mapping 40 PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping 40 Processor, Executive 17 Processor, Fabric 18 PROM Interface Diagram 36 PROM Interface Signals 35 PROM Interface Timing Description 82 PROM Interface Timing Diagram 82 PROM Interface Timing Outline 37 PROM Interface Timing Specifications 82
Q
QMU Signal Groups 88 QMU SRAM Interface Signals 45
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INDEX: T
CP Timing 71 DS1/DS3 Timing 72 Electrical 63 Executive Processor Timing 78 Fabric Processor Timing 83 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 74 Low Speed Serial Interface Timing 81 MDIO Serial Interface Timing 80 Mechanical 89 OC-12 Timing 77 OC-3 Timing 76 PCI Timing 78 PROM Interface Timing 82 QMU Timing 87 TLU Timing 86 XP Timing 78 System Clock Timing Description 70 System Clock Timing Diagram 70 System Interfaces Executive Processor 17
Timing Outline PROM Interface 37 TLU Signal Groups 87 TLU SRAM Interface Signals 44 TLU Timing Description 86 TLU Timing Diagram 86 TLU Timing Specifications 86 Transceiver Interface Configuration SONET OC-12 32 SONET OC-3 31 Transmit and Receive Pin Combinations for Gigabit Ethernet and FibreChannel 27
U
Utopia2/Utopia3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping 39 Utopia2/Utopia3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping 39
T
Table Lookup Unit 19 Test Signals 48 Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test Routines 48 Thermal Performance for C-5 Network Processor Heat Sink 68
X
XP Timing Specifications 78
January 21, 2002-- Preliminary Version
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C-Port Corporation 120 Water Street North Andover, MA 01845 978-773-2300 TEL 978-773-2301 FAX www.cportcorp.com www.mot-sps.com
Part Number: 4-004

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