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INTEGRATED CIRCUITS
DATA SHEET
PCF8812 65 x 102 pixels matrix LCD driver
Product specification File under Integrated Circuits, IC12 2000 Nov 22
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS Pin functions ROW 0 to ROW 64 row driver outputs COL 0 to COL 101 column driver outputs VSS1 and VSS2: negative power supply rails VDD1 to VDD3: positive power supply rails VLCDIN: LCD power supply VLCDOUT: LCD power supply VLCDSENSE: voltage multiplier regulation input (VLCD) T1 to T5: test pads SDIN: serial data line SCLK: serial clock line D/C: mode select SCE: chip enable OSC: oscillator RES: reset FUNCTIONAL DESCRIPTION Oscillator Address Counter (AC) Display Data RAM (DDRAM) Timing generator Display address counter LCD row and column drivers ADDRESSING Data structure 10 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.4 10.4.1 10.5 10.6 10.7 10.8 10.9 10.10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 INSTRUCTIONS Initialization Reset function Function set PD V H Display control D and E Set Y address of RAM Set X address of RAM Set HV-generator stages Bias system Temperature control Set VOP value LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS SERIAL INTERFACE RESET
PCF8812
APPLICATION INFORMATION CHIP INFORMATION PAD INFORMATION BONDING PAD LOCATION DEVICE PROTECTION DIAGRAM TRAY INFORMATION DATA SHEET STATUS DEFINITIONS DISCLAIMERS
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
1 FEATURES 2 APPLICATIONS
PCF8812
* 65 row and 102 column outputs * Display data RAM 65 x 102 bits * On-chip: - Configurable 5 (4, 3 and 2) voltage multiplier generating VLCD (external VLCD also possible) - Generation of intermediate LCD bias voltages - Oscillator requires no external components (external clock also possible). * External reset input pin * Serial interface maximum 4.0 Mbit/s * CMOS compatible inputs * Mux rate: 1 : 65 * Logic supply voltage range VDD1 to VSS: - 2.5 to 5.5 V. * High voltage generator supply voltage range VDD2 to VSS and VDD3 to VSS - 2.5 to 4.5 V. * Display supply voltage range VLCD to VSS: - 4.5 to 9.0 V. * Low power consumption, suitable for battery operated systems * Temperature compensation of VLCD * Temperature range: Tamb = -40 to +85 C * Slim chip layout, suited for Chip-On-Glass (COG) applications. 4 ORDERING INFORMATION
* Telecom equipment. 3 GENERAL DESCRIPTION
The PCF8812 is a low power CMOS LCD controller driver, designed to drive a graphic display of 65 rows and 102 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8812 interfaces to microcontrollers via a serial bus interface.
PACKAGE TYPE NUMBER NAME PCF8812U/2 Tray chip with bumps in tray DESCRIPTION VERSION -
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
5 BLOCK DIAGRAM
PCF8812
handbook, full pagewidth
VDD1
VDD2
VDD3
COL0 to COL101 102 COLUMN DRIVERS
ROW0 to ROW64 65 ROW DRIVERS
VLCDIN
BIAS VOLTAGE GENERATOR DATA LATCHES HIGH VOLTAGE GENERATOR 4 stages
SHIFT REGISTER
VLCDSENSE VLCDOUT VSS1 VSS2 T1 T2 T3 T4 T5
RESET DISPLAY DATA RAM (DDRAM) 65 x 102 bits
RES
OSCILLATOR
OSC
TIMING GENERATOR ADDRESS COUNTER DISPLAY ADDRESS COUNTER
DATA REGISTER
PCF8812
I/O BUFFER
MGT636
SDIN
SCLK
D/C
SCE
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
6 PINNING SYMBOL RES ROW 32 to ROW 19 ROW 0 to ROW 18 COL 0 to COL 101 ROW 50 to ROW 33 ROW 51 to ROW 64 VDD1 VDD3 VDD2 OSC SDIN D/C SCE T2 SCLK VSS2 VSS1 T1 T5 T4 VSS1 T3 VLCDIN VLCDOUT VLCDSENSE PAD 1 2 to 15 18 to 36 37 to 138 139 to 156 159 to 172 174 to 179 180 181 to 193 194 195 196 197 198 199 200 to 213 214 to 217 218 219 220 221 and 222 223 224 to 229 230 to 236 237 16, 17, 157, 158 and 173 DESCRIPTION external reset input (active LOW) LCD row driver outputs 7.1.2 LCD row driver outputs LCD column driver outputs LCD row driver outputs LCD row driver outputs supply voltage 1 supply voltage 3 supply voltage 2 oscillator input serial data input data/command input chip enable input (active LOW) test 2 output serial clock input negative power supply 2 negative power supply 1 test 1 input test 5 input test 4 input negative power supply 1 test 3 input/output LCD supply voltage voltage multiplier output voltage multiplier regulation input (VLCD) dummy pads 7 7.1 7.1.1 PIN FUNCTIONS Pin functions
PCF8812
ROW 0 TO ROW 64 ROW DRIVER OUTPUTS
These pads output the row signals. COL 0 TO COL 101 COLUMN DRIVER OUTPUTS
These pads output the column signals. 7.1.3 VSS1 AND VSS2: NEGATIVE POWER SUPPLY RAILS
The 2 supply rails VSS1 and VSS2 must be connected together. 7.1.4 VDD1 TO VDD3: POSITIVE POWER SUPPLY RAILS
VDD2 and VDD3 are the supply voltage for the internal voltage generator. Both have the same voltage and may be connected together outside of the chip. VDD1 is used as supply for the rest of the chip. VDD1 can be connected together with VDD2 and VDD3 but in this case care must be taken to respect the supply voltage range (see Chapter 13). If the internal voltage generator is not used then VDD2 and VDD3 must be connected to VDD1 or connected to power. 7.1.5 VLCDIN: LCD POWER SUPPLY
Positive power supply for the liquid crystal display. An external LCD supply voltage can be supplied using the VLCDIN pad. In this case VLCDOUT has to be left open-circuit and the internal voltage generator has to be programmed to zero. If the PCF8812 is in Power-down mode, the external LCD supply voltage has to be switched off. 7.1.6 VLCDOUT: LCD POWER SUPPLY
Positive power supply for the liquid crystal display. If the internal voltage generator is used, the two supply rails VLCDIN and VLCDOUT must be connected together. If an external supply is used this pin must be left open-circuit. 7.1.7 VLCDSENSE: VOLTAGE MULTIPLIER REGULATION (VLCD)
INPUT
VLCDSENSE is the input of the internal voltage multiplier regulation. If the internal voltage generator is used then VLCDSENSE must be connected to VLCDOUT. If a external supply voltage is used then the VLCDSENSE can be let open-circuit or connected to ground.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
7.1.8 T1 TO T5: TEST PADS 8.2 Address Counter (AC)
PCF8812
T1, T3, T4 and T5 must be connected to VSS, T2 must be left open-circuit. Not accessible to user. 7.1.9 SDIN: SERIAL DATA LINE
Serial data input line. 7.1.10 SCLK: SERIAL CLOCK LINE
The address counter assigns addresses to the display data RAM for writing. The X address X6 to X0 and the Y address Y3 to Y0 are set separately. After a write operation the address counter is automatically incremented by 1 according to the V flag (see Chapter 9). 8.3 Display Data RAM (DDRAM)
Input for the clock signal 0 to 4.0 Mbits/s. 7.1.11 D/C: MODE SELECT
Input to select either command/address or data input. 7.1.12 SCE: CHIP ENABLE
The PCF8812 contains a 65 x 102 bit static RAM which stores the display data. The RAM is divided into 8 banks of 102 bytes (8 x 8 x 102 bits) and one bank of 102 bits (1 x 102 bits). During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between the X address and the column output number. 8.4 Timing generator
The enable pin allows data to be clocked in; the signal is active LOW. 7.1.13 OSC: OSCILLATOR
When the on-chip oscillator is used this input must be connected to VDD. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to VSS the display is not clocked and may be left in a DC state. To avoid this the chip should always be put into Power-down mode before stopping the clock. 7.1.14 RES: RESET
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data buses. 8.5 Display address counter
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off and normal/inverse video) is set by bits E and D in the command `display control' (see Table 2). 8.6 LCD row and column drivers
This signal will reset the device and must be applied to properly initialize the chip; the signal is active LOW. 8 8.1 FUNCTIONAL DESCRIPTION Oscillator
The PCF8812 contains 65 row and 102 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected.
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
frame n
VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS
frame n + 1 Vstate1(t) Vstate2 (t)
ROW 0 R0 (t)
ROW 1 R1 (t)
COL 0 C0 (t)
COL 1 C1 (t)
VLCD - VSS V3 - VSS VLCD - V2 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD VLCD - VSS V3 - VSS VLCD - V2 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD
Vstate1(t)
Vstate2 (t)
0 1 2 3 4 5 6 7 8...
... 64 0 1 2 3 4 5 6 7 8...
... 64
MGT637
(1) Vstate1(t) = C1(t) - R0(t). (2) Vstate2(t) = C1(t) - R1(t).
Fig.2 Typical LCD driver waveforms.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
DDRAM
bank 0 top of LCD
bank 1
bank 2
LCD
bank 3
bank 7
bank 8
MGS395
Fig.3 DDRAM to display mapping.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
9 ADDRESSING
PCF8812
Data is downloaded in bytes into the RAM matrix of the PCF8812 as indicated in Figs.3, 4, 5 and 6. The display RAM has a matrix of 65 x 102 bits. The columns are addressed by the address pointer. The address ranges are: X0 to X101 (1100101) and Y0 to Y8 (1000). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1) the Y address increments after each byte (see Fig.6). After the last Y address (Y = 8) Y wraps around to 0 and X increments to address the next column. In horizontal addressing mode (V = 0) the X address increments after each byte (see Fig.5). After the last X address (X = 101) X wraps around to 0 and Y increments to address the next row. After the very last address (X = 101 and Y = 8) the address pointers wrap around to address (X = 0 and Y = 0). 9.1 Data structure
handbook, full pagewidth MSB
0
LSB
MSB
8
LSB
0
X address Y address
101
MGT638
Fig.4 RAM format addressing.
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 0
9 10
0
Y address
917 X address 101
8
MGS397
Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
handbook, full pagewidth
0 102 204 306 408 510 612 714 816 0
1 103 205 307 409 511 613 715 817
2 104 206 308 410 512 614 716 818 X address 917 101
0
Y address
8
MGS396
Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
10 INSTRUCTIONS The instruction format is divided into two modes: If D/C (mode select) is set LOW the current byte is interpreted as command byte (see Table 1). Figure 8 shows an example of a serial data stream for initializing the chip. If D/C is set HIGH the following bytes are stored in the display data RAM. After every data byte the address counter is incremented automatically. The level of the D/C signal is read during the last bit of the data byte. Every instruction can be sent in any order to the PCF8812. The MSB of a byte is transmitted first. Figure 8 shows one possible command stream, used to set-up the LCD driver. The serial interface is initialized when SCE is HIGH. In this state SCLK clock pulses have no effect and no power is consumed by the serial interface. A negative edge on SCE enables the serial interface and indicates the start of a data transmission. Figures 9 and 10 show the serial bus protocol: * When SCE is HIGH, SCLK clocks are ignored. During the HIGH time of SCE the serial interface is initialized (see Fig.12)
* SDIN is sampled at the positive edge of SCLK * D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1). It is read with the eighth SCLK pulse * If SCE stays LOW after the last bit of a command/data byte, the serial interface expects DB7 of the next byte at the next positive edge of SCLK (see Fig.12). If SCLK goes LOW after the last data bit (DB0), either: - A rising clock edge is required to latch the last data bit - Or the last bit is latched when SCE goes HIGH. * A reset pulse with RES interrupts the transmission. No data is written into the RAM. The registers are cleared. If SCE is LOW after the positive edge of RES, the serial interface is ready to receive bit 7 of a command/data byte (see Fig.12).
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
MSB handbook, halfpage (DB7) data
LSB (DB0) data
MGT639
Fig.7 General format of data stream.
handbook, full pagewidth
function set (H = 1)
bias system
set VOP
temperature control
function set (H = 0)
display control
Y address
X address
MGT640
Fig.8 Example of serial data stream.
handbook, full pagewidth
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGT641
Fig.9 Serial bus protocol transmission of one byte.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
handbook, full pagewidth
SCE
D/C
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGT642
Fig.10 Serial bus protocol transmission of several bytes.
handbook, full pagewidth
SCE
D/C
RES
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGT643
Fig.11 Serial bus reset function (SCE).
handbook, full pagewidth
SCE
RES
D/C
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
MGT644
Fig.12 Serial bus reset function (RES).
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Table 1 Instruction set COMMAND BYTE INSTRUCTION (H = 0 or 1) NOP Function set 0 0 0 0 0 0 0 1 0 0 0 0 0 PD 0 V 0 H no operation D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PCF8812
DESCRIPTION
power-down control; entry mode; extended instruction set control (H) writes data to display RAM
Write data (H = 0) Reserved Display control Set higher or lower programming range Vop Set Y address of RAM Set X address of RAM (H = 1) Reserved Reserved Temperature control HV-gen stages Bias system Reserved Set Vop
1
D7 0 0 0
D6 0 0 0
D5 0 0 0
D4 0 0 1
D3 0 1 0
D2 1 D 0
D1 X 0 0
D0 X E
0 0 0
do not use sets display configuration
PRS VLCD programming range select Y0 X0 sets Y address of RAM; 0Y8 sets X address part of RAM; 0 X 101 do not use do not use set temperature coefficient (TCx) # of HV-gen voltage multiplication set bias system (BSx) do not use (reserved for test)
0 0
0 1
1 X6
0 X5
0 X4
Y3 X3
Y2 X2
Y1 X1
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1
0 0 0 0 0 X
0 0 0 0 1 X
0 0 0 1 0 X
0 0 1 0 BS2 X
0 1 TC1 S1 BS1 X
1 X TC0 S0 BS0 X
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 write VOP to register
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
Table 2 Explanations for symbols in Table 1 BIT PD V H PRS D, E 00 10 01 11 TC1 to TC0 00 01 10 11 S1 to S0 00 01 10 11 VOP 6 to VOP0 BS2 to BS0 10.1 Initialization chip is active horizontal addressing use basic instruction set VLCD programming range; LOW display blank normal mode all display segments on inverse video mode VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 2 x voltage multiplier 3 x voltage multiplier 4 x voltage multiplier 5 x voltage multiplier VLCD programming bias system S1 to S0 = 00 E=0 0 1 chip is in Power-down mode vertical addressing use extended instruction set VLCD programming range; HIGH 1 0 0 0 D=0
PCF8812
RESET STATE
TC1 to TC0 = 00
VOP 6 to VOP0 = 0000000 BS2 to BS0 = 000
* Horizontal addressing (V = 0) * Normal instruction set (H = 0) * Display blank (E = D = 0) * Address counter X6 to X0 = 0; Y3 to Y0 = 0 * Temperature control mode (TC1 to TC0 = 0) * Bias system (BS2 to BS0 = 0) * VLCD is equal to 0; the HV-generator is switched off (VOP6 to VOP0 = 0 and PRS = 0) * After power-on; RAM data is undefined; the reset signal doesn't change the content of the RAM * All LCD outputs at VSS (display off).
Immediately following power-on, all internal registers as well as the RAM content are undefined; a reset pulse must be applied. Reset is accomplished by applying an external reset pulse (active LOW) at the pad RES. When reset occurs within the specified time, all internal registers are reset, however the RAM is still undefined. The state after reset is described in Section 10.2. The RES input must be 0.3VDD when VDD reaches VDD(min) (or higher) within a maximal time tVHRL after VDD going HIGH (see Fig.16). 10.2 Reset function
After reset the LCD driver has the following state: * Power-down mode (PD = 1)
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
10.3 10.3.1 Function set PD 10.3.3 H
PCF8812
* All LCD outputs at VSS (display off) * Bias generator and VLCD generator off; VLCD can be disconnected * Oscillator off (external clock possible) * Serial bus; command; etc. function * RAM contents not cleared; RAM data can be written * VLCD discharged to VSS in Power-down mode. 10.3.2 V
When H = 0 the commands `display control', `set Y address', `set X address' and set the PRS bit (low or high range of the high voltage generator) can be performed, when H = 1 the others can be executed. The commands `write data' and `function set' can be executed in both cases. 10.4 10.4.1 Display control D AND E
The bits D and E select the display mode (see Table 2). When V = 0, the horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.5. When V = 1, the vertical addressing is selected. The data is written into the DDRAM as shown in Fig.6. Table 3 Y3 0 0 0 0 0 0 0 0 1 Note 1. In bank 8 only the LSB is accessed. 10.6 Set X address of RAM X/Y address range: note 1 Y2 0 0 0 0 1 1 1 1 0 Y1 0 0 1 1 0 0 1 1 0 Y0 0 1 0 1 0 1 0 1 0 CONTENT bank 0 (display RAM) bank 1 (display RAM) bank 2 (display RAM) bank 3 (display RAM) bank 4 (display RAM) bank 5 (display RAM) bank 6 (display RAM) bank 7 (display RAM) bank 8 (display RAM) 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 ALLOWED X RANGE 10.5 Set Y address of RAM
Y3 to Y0 defines the Y address vector address of the display RAM (see Table 3).
The X address points to the columns. The range of X is 0 to 101 (65H). 10.7 Set HV-generator stages
The PCF8812 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 2 x VDD2. Other voltage multiplier factors are set via the command `Set HV-gen stages' (see Tables 1 and 2).
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
10.8 Bias system
PCF8812
1 The bias voltage levels are set in the ratio of R - R - nR - R - R giving a ----------------- bias system. Different multiplex rates (n + 4) require different factors `n' (see Table 4). This is programmed by BS2 to BS0. For MUX1 to MUX65 the optimum bias value `n' is given by: n = Table 4 65 - 3 = 5.062 = 5 resulting in 1/9 bias.
Programming the required bias system BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0 RECOMMEND MUX RATE 1 to 100 1 to 80 1 to 65 or 1 to 65 1 to 48 1 to 40 or 1 to 34 1 to 24 1 to 18 or 1 to 16 1 to 10 or 1 to 9 or 1 to 8
Table 5
LCD bias voltage BIAS VOLTAGES VLCD (n + 3) ----------------(n + 4) (n + 2) ----------------(n + 4) 2 ----------------(n + 4) 1 ----------------(n + 4) VSS VLCD
8/ 9
SYMBOL V1 V2 V3 V4 V5 V6
BIAS VOLTAGES FOR n = 5 (1/9 BIAS) x VLCD x VLCD x VLCD x VLCD
7/
9
2/
9
1/
9
VSS
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
10.9 Temperature control
PCF8812
The parameters are explained in Table 6. The maximum voltage that can be generated is dependent on the VDD2 voltage and the display load current. Two overlapping VLCD ranges are selectable via the command `HV-gen control'. For the LOW (PRS = 0) range a = a1 and for the HIGH (PRS = 1) range a = a2 with steps equal to `b' in both ranges. It should be noted that the charge pump is turned off if VOP 6 to 0 and the bit PRS are all set to zero (see Fig.14). For MUX 1 to 65 the optimum operating voltage of the liquid can be calculated as follows; 1 + 65 V LCD = -------------------------------------- x V th = 6.85 x V th 1 2 x 1 - ---------- 65 where Vth is the threshold voltage of the liquid crystal material used. Table 6 Typical values for parameters for the HV-generator programming VALUE 2.94 (PRS = 0) 6.75 (PRS = 1) 0.03 27 V V V C UNIT (3)
Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage VLCD must be increased with lower temperature to maintain optimum contrast. There are 4 different temperature coefficients available in the PCF8812 (see Fig.13). The coefficients are selected by bits TC1 to TC0. Table 6 shows the typical values of the different temperature coefficients. The coefficients are proportional to the programmed VLCD.
handbook, halfpage
MGS402
VLCD
Tcut
T
SYMBOL a1 a2
Fig.13 Temperature coefficients.
b Tcut
10.10 Set VOP value The operating voltage VLCD can be set by software. The generated voltage is dependent on temperature, programmed Temperature Coefficient (TC) and the programmed voltage at reference temperature (Tcut). V LCD ( T ) = ( a + V OP x b ) ( 1 + ( T - T cut ) x TC ) (1) The voltage at reference temperature [VLCD(T = Tcut)] can be calculated as follows: (2) V LCD ( T = T ) = ( a + V OP x b )
cut
As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9 V) the user has to ensure, while setting the VOP register and selecting the Temperature Compensation (TC), that under all conditions and including all tolerances that VLCD remains below 9 V.
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
handbook, full pagewidth
VLCD
b charge pump off a2 a1+b
a1
0H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH 00H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH LOW (PRS = 0) HIGH (PRS = 1)
MGS658
VOP 6 to 0 (programmed) [00H to 7FH; programming range LOW and HIGH].
Fig.14 VOP programming of PCF8812 (at T = Tcut).
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); see notes 1 and 2 SYMBOL VDD1 VDD2,VDD3 VLCD Vi ISS Ii,Io Ptot PO Tstg Ves PARAMETER supply voltage supply voltage for internal voltage generator supply voltage range LCD all input voltages ground supply current DC input or output current total power dissipation power dissipation per output storage temperature electrostatic handling voltage note 3 note 4 Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -50 -10 - - -65 - -
PCF8812
MAX. +6.5 +4.5 +9.0 VDD + 0.5 +50 +10 300 30 +150 1900 200 V V V V
UNIT
mA mA mW mW C V V
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. 3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 4. Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 H series inductor. 12 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
13 DC CHARACTERISTICS VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL VDD1 VDD2,VDD3 PARAMETER supply voltage supply voltage for internal voltage generator LCD input supply voltage LCD voltage internally generated (voltage generator enabled) LCD voltage externally supplied (voltage generator disabled) LCD voltage internally generated (voltage generator enabled); note 1 normal mode; VDD1 = 2.8 V; VLCD = 7.6 V; fSCLK = 0; Tamb = 25 C; no display load; 4 x charge pump; notes 2 and 3 Power-down mode; with internal or external VLCD supply voltage; note 4 ILCDIN supply current from external VLCD VDD1 = 2.8 V; VLCD = 7.6 V; fSCLK = 0; T = 25 C; no display load; notes 2, 3 and 5 CONDITIONS MIN. +2.5 +2.5 - - TYP.
PCF8812
MAX. +5.5 +4.5
UNIT V V
VLCDIN
+4.5
-
+9.0
V
VLCDOUT
LCD output supply voltage
+4.5
-
+9.0
V
IDD(tot)
total supply current
-
220
350
A
-
1.5
-
A
-
30
-
A
Logic VIL VIH IIL Rcol Rrow Vbias(col) Vbias(row) LOW-level input voltage HIGH-level input voltage input leakage current VI = VDD1 or VSS1 IL = 10 A outputs tested one at a time IL = 10 A outputs tested one at a time VSS 0.7VDD -1 - - -100 -100 - - - 12 12 0 0 0.3VDD VDD +1 V V A k k mV mV
Column and row outputs column output resistance COL 0 to COL 101 row output resistance ROW 0 to ROW 64 column bias tolerance COL 0 to COL 101 row bias tolerance ROW 0 to ROW 64 20 20 +100 +100
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Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
SYMBOL
PARAMETER
CONDITIONS
MIN. -300
TYP.
MAX.
UNIT
LCD supply voltage generator VLCD VLCD tolerance internally generated VDD1 = 2.8 V; VLCD = 7.6 V; fSCLK = 0; Tamb = 25 C; display-load = 10 A; notes 3, 6 and 7 0 +300 mV
TC
VLCD temperature coefficient VDD1 = 2.8 V; fSCLK = 0; Tamb = -20 to +70 C; display load = 10 A; note 3 coefficient 0 coefficient 1 coefficient 2 coefficient 3 - - - - 0 x 10-3 -0.76 x 10-3 -1.05 x -2.10 x 10-3 10-3 - - - - 1/C 1/C 1/C 1/C
Notes 1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock. 3. fSCLK = 0 means no serial clock. 4. During power-down all static currents are switched off. 5. If external VLCD; the display load current is not transmitted to IDD. 6. Tolerance depend on the temperature; (typical null at Tamb = 27 C, maximum tolerance values are measured at the temperate range limit, maximum tolerance is proportional to VLCD). 7. For TC1 to TC3. 14 AC CHARACTERISTICS VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fOSC fclk(ext) fframe tVHRL tRW fSCLK PARAMETER oscillator frequency external clock frequency frame frequency VDD to RES LOW RES LOW pulse width fOSC or fclk(ext) = 38 kHz; note 1 see Fig.16 see Fig.16 VDD1 = 3.0 V 10%; all signal timing is based on 20% to 80% of VDD and a maximum rise and fall time of 10 ns CONDITIONS VDD1 = 2.8 V; Tamb = -20 to +70 C MIN. 22 20 - 0 500 38 38 73 - - - TYP. MAX. 67 67 - 1 - 4.00 UNIT kHz kHz Hz s ns
Serial bus timing characteristics clock frequency 0 MHz
tcyc tPWH1 tPWL1 tS2 2000 Nov 22
clock cycle time SCLK pulse width HIGH SCLK pulse width LOW SCE set-up time 21
250 100 100 60
- - - -
- - - -
ns ns ns ns
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
SYMBOL tH2 tPWH2 tH5 tS3 tH3 tS4 tH4 Notes 1. f clk(ext) f frame = --------------520
PARAMETER SCE hold time SCE minimum HIGH time SCE start hold time D/C set-up time D/C hold time SDIN set-up time SDIN hold time note 2
CONDITIONS
MIN. 100 100 100 100 100 100 100 - - - - - - -
TYP. - - - - - - -
MAX.
UNIT ns ns ns ns ns ns ns
2. tH5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE (see Fig.15). 15 SERIAL INTERFACE
handbook, full pagewidth
t S2
t H2
t PWH2
SCE t S3 D/C t CYC t PWL1 SCLK t PWH1 t S2 t H3 (t H5 ) t H5
t S4 SDIN
t H4
MGT645
Fig.15 Serial interface timing.
2000 Nov 22
22
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
16 RESET
PCF8812
handbook, full pagewidth
VDD t RW RES t RW
VDD t VHRL RES
MGT646
t RW
t RW
Fig.16 Reset timing.
17 APPLICATION INFORMATION Table 7 STEP D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 2 start 0 0 0 1 0 0 0 0 1 SCE is going low function set; PD = 0, V = 0; select extended instruction set (H = 1 mode) set charge pump range HIGH PRS = 1 set VOP; VOP is set to 7.6 V function set; PD = 0; V = 0; select normal instruction set (H = 0 mode) display control; set normal mode (D = 1; E = 0). data write; Y and X are initialized to 0 by default, so they aren't set here
MGS405
Programming example for PCF8812 SERIAL BUS BYTE DISPLAY OPERATION
3 4 5
0 0 0
0 1 0
0 0 0
0 0 1
1 1 0
0 1 0
0 1 0
0 0 0
1 0 0
6 7
0 1
0 1
0 1
0 1
0 1
1 1
1 0
0 0
0 0
2000 Nov 22
23
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
SERIAL BUS BYTE STEP D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 8 1 1 0 1 0 0 0 0 0 data write DISPLAY OPERATION
MGS406
9
1
1
1
1
0
0
0
0
0
data write
MGS407
10
1
0
0
0
0
0
0
0
0
data write
MGS407
11
1
1
1
1
1
1
0
0
0
data write
MGS409
12
1
0
0
1
0
0
0
0
0
data write
MGS410
13
1
1
1
1
1
1
0
0
0
data write
MGS411
2000 Nov 22
24
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
SERIAL BUS BYTE STEP D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 14 0 0 0 0 0 1 1 0 1 display control; set inverse video mode (D = 1; E = 1) DISPLAY OPERATION
MGS412
15
0
1
0
0
0
0
0
0
0
set X-address of RAM; set address to 0000000
MGS412
16
1
0
0
0
0
0
0
0
0
data write
MGS414
The pinning of the PCF8812 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 65 x 102 pixels.
2000 Nov 22
25
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
handbook, full pagewidth
DISPLAY 102 x 65
32
102
33
PCF8812
VDD1 VDD3 VDD2 VSS2 VSS1
VLCDIN VLCDOUT VLCDSENSE
4 (1) CVLCD I/O CVDD VDD VSS reset
MGT647
Fig.17 Application diagram; internal charge pump is used and a single VDD.
handbook, full pagewidth
DISPLAY 102 x 65
32
102
RES
33
PCF8812
VDD1 VDD3 VDD2 VSS2 VSS1
VLCDIN VLCDOUT VLCDSENSE
4 (1) VDD2 I/O VDD1 CVDD2 CVLCD CVDD1 VSS reset
MGT648
Fig.18 Application diagram; internal charge pump is used and two separate VDD (VDD1 and VDD2).
2000 Nov 22
26
RES
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
handbook, full pagewidth
DISPLAY 102 x 65
32
102
33
PCF8812
VDD1 VDD3 VDD2 VSS2 VSS1
VLCDIN VLCDOUT VLCDSENSE
4 (1) CVDD I/O VDD VSS VLCDIN reset
MGT649
Fig.19 Application diagram; external high voltage generation is used.
The required minimum value for the external capacitors in an application with the PCF8812 are as follows: CVLCD = 100 nF (minimum) CVDD; CVDD1; CVDD2 = 1 F (minimum). Higher capacitor values are recommended for ripple reduction. 18 CHIP INFORMATION The PCF8812 is manufactured in n-well CMOS technology. The substrate is at VSS potential. 19 PAD INFORMATION Table 8 Bonding pad dimensions NAME Pad pitch Pad size; aluminium Bump dimensions Wafer thickness; including bumps Wafer thickness; without bumps 70 m 62 x 100 m 50 x 90 x 17.5 m (5) maximum 430 m 381 m typ. DIMENSION
2000 Nov 22
27
RES
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
20 BONDING PAD LOCATION Table 9 Bonding pad location All x and y coordinates are referenced to the centre of the chip (dimensions in m; see Fig.20). COORDINATES SYMBOL RES ROW 32 ROW 31 ROW 30 ROW 29 ROW 28 ROW 27 ROW 26 ROW 25 ROW 24 ROW 23 ROW 22 ROW 21 ROW 20 ROW 19 dummy pad dummy pad ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 2000 Nov 22 PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 +3870 +4270 +4340 +4410 +4480 +4550 +4620 +4690 +4760 +4830 +4900 +4970 +5040 +5110 +5180 +5320 +5355 +5005 +4935 +4865 +4795 +4725 +4655 +4585 +4515 +4445 +4375 +4305 +4235 +4165 +4095 +4025 +3955 +3885 +3815 +3745 y +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 28 SYMBOL COL 0 COL 1 COL 2 COL 3 COL 4 COL 5 COL 6 COL 7 COL 8 COL 9 COL 10 COL 11 COL 12 COL 13 COL 14 COL 15 COL 16 COL 17 COL 18 COL 19 COL 20 COL 21 COL 22 COL 23 COL 24 COL 25 COL 26 COL 27 COL 28 COL 29 COL 30 COL 31 COL 32 COL 33 COL 34 COL 35 COL 36 COL 37 COL 38 PAD x 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
PCF8812
COORDINATES y -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6
+3605 +3535 +3465 +3395 +3325 +3255 +3185 +3115 +3045 +2975 +2905 +2835 +2765 +2695 +2625 +2555 +2485 +2415 +2345 +2275 +2205 +2135 +2065 +1995 +1925 +1785 +1715 +1645 +1575 +1505 +1435 +1365 +1295 +1225 +1155 +1085 +1015 +945 +875
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
COORDINATES SYMBOL COL 39 COL 40 COL 41 COL 42 COL 43 COL 44 COL 45 COL 46 COL 47 COL 48 COL 49 COL 50 COL 51 COL 52 COL 53 COL 54 COL 55 COL 56 COL 57 COL 58 COL 59 COL 60 COL 61 COL 62 COL 63 COL 64 COL 65 COL 66 COL 67 COL 68 COL 69 COL 70 COL 71 COL 72 COL 73 COL 74 COL 75 COL 76 COL 77 PAD x 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 +805 +735 +665 +595 +525 +455 +385 +315 +245 +175 +105 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1925 -1995 y -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 COL 78 COL 79 COL 80 COL 81 COL 82 COL 83 COL 84 COL 85 COL 86 COL 87 COL 88 COL 89 COL 90 COL 91 COL 92 COL 93 COL 94 COL 95 COL 96 COL 97 COL 98 COL 99 COL 100 COL 101 ROW 50 ROW 49 ROW 48 ROW 47 ROW 46 ROW 45 ROW 44 ROW 43 ROW 42 ROW 41 ROW 40 ROW 39 ROW 38 ROW 37 ROW 36 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 SYMBOL PAD
COORDINATES x -2065 -2135 -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 -3045 -3115 -3185 -3255 -3325 -3395 -3465 -3535 -3605 -3675 -3815 -3885 -3955 -4025 -4095 -4165 -4235 -4305 -4375 -4445 -4515 -4585 -4655 -4725 -4795 y -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6 -934.6
2000 Nov 22
29
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
COORDINATES SYMBOL ROW 35 ROW 34 ROW 33 dummy pad dummy pad ROW 51 ROW 52 ROW 53 ROW 54 ROW 55 ROW 56 ROW 57 ROW 58 ROW 59 ROW 60 ROW 61 ROW 62 ROW 63 ROW 64 dummy pad VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 PAD x 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 -4865 -4935 -5005 -5355 -5320 -5180 -5110 -5040 -4970 -4900 -4830 -4760 -4690 -4620 -4550 -4480 -4410 -4340 -4270 -4050 -3890 -3810 -3730 -3650 -3570 -3490 -3250 -3090 -3010 -2930 -2850 -2770 -2690 -2610 -2530 -2450 -2370 -2290 -2210 y -934.6 -934.6 -934.6 -934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 VDD2 OSC SDIN D/C SCE T2 SCLK VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 T1 T5 T4 VSS1 VSS1 T3 VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDOUT VLCDOUT 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 SYMBOL PAD
COORDINATES x -2130 -1890 -1650 -1410 -1170 -930 -690 -530 -450 -370 -290 -210 -130 -50 +30 +110 +190 +270 +350 +430 +510 +670 +750 +830 +910 +1150 +1630 +2030 +2110 +2190 +2270 +2510 +2590 +2670 +2750 +2830 +2910 +3070 +3150 y +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6 +934.6
2000 Nov 22
30
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
PCF8812
COORDINATES SYMBOL VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDSENSE Alignment marks Circle 1 Circle 2 Circle 3 Circle 4 +5185 -5185 -4160 +4160 -910.8 -910.8 +909.7 +909.7 PAD x 232 233 234 235 236 237 +3230 +3310 +3390 +3470 +3550 +3630 y +934.6 +934.6 +934.6 +934.6 +934.6 +934.6
2000 Nov 22
31
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andbook, full pagewidth
dummy pad
dummy pad
VLCDSENSE
VLCDOUT
ROW 51
ROW 64
ROW 32
T4 VSS1 T3
VDD3
SCLK
SDIN
OSC
SCE
RES
D/C
T2
T1
T5
alignment mark
pad No.1
y
alignment mark
alignment mark
0,0
x
PC8812-1
ROW 33 ROW 50 COL 101 COL 0 ROW 18 COL 76 COL 50 COL 25 ROW 0
dummy pad
alignment mark
ROW 19
MGT653
dummy pad
dummy pad
VSS2
VSS1
VLCDIN
VDD1
VDD2
2000 Nov 22
. . . . . .
Philips Semiconductors
65 x 102 pixels matrix LCD driver
. . .
. . .
32
(1) The alignment marks are circular with a diameter of 100 m. (2) Maximum chip size: 2.1 x 10.9 mm.
. . .
. . .
. . .
. . .
. . .
. . .
Product specification
PCF8812
Fig.20 Bonding pad locations.
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
21 DEVICE PROTECTION DIAGRAM
PCF8812
handbook, full pagewidth
VDD1 VDD3 VLCDIN VLCDOUT VLCDSENSE VSS1
VDD1
T3, T2
VDD2
VSS1
VSS1 VSS2 VSS1
VSS2 VSS2 VSS1
COL 0-101/ROW 0-64 VLCDIN 1 per block
VDD1 SDIN SCLK SCE D/C OSC RES T1, T4, T5 VSS1
MGT650
VSS1
VSS1
Fig.21 Device protection diagram.
2000 Nov 22
33
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
22 TRAY INFORMATION
PCF8812
handbook, full pagewidth
x
A G H
1,1 1,2 1,3 2,1 2,2 3,1 x,1
C
y
D B
F
1,y
x,y
A K L
,,,,,,, ,,,,,,,
E M SECTION A-A
A
J
MGT651
Fig.22 Tray details.
Table 10 Tray dimensions DIMENSION A
handbook, halfpage
DESCRIPTION pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction tray width; x direction tray width; y direction distance from cut corner to pocket (1 and 1) centre distance from cut corner to pocket (1 and 1) centre tray thickness tray cross section tray cross section pocket depth no. pockets in x direction no. pockets in y direction
VALUE 13.77 mm 4.37 mm 11.04 mm 2.24 mm 50.8 mm 50.8 mm 11.68 mm 5.74 mm 3.96 mm 1.78 mm 2.49 mm 0.89 mm 3 10
B C D E F G
MGT652
PC8812
H J
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
K L M x y
Fig.23 Tray alignment.
2000 Nov 22
34
Philips Semiconductors
Product specification
65 x 102 pixels matrix LCD driver
23 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
PCF8812
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 24 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 25 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
2000 Nov 22
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 70
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/01/pp36
Date of release: 2000
Nov 22
Document order number:
9397 750 07415

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