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M464S6453CKS
Revision History
Revision 0.0 (Sept. 2001)
PC133/PC100 SODIMM
Rev. 0.0 Sept. 2001
M464S6453CKS
M464S6453CKS SDRAM SODIMM
PC133/PC100 SODIMM
64Mx64 SDRAM SODIMM based on 64Mx8, 4Banks, 8K Refresh,3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung M464S6453CKS is a 64M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S6453CKS consists of eight CMOS 64M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S6453CKS is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin M46S6453CKS edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
* Performance range Part No. M464S6453CKS-L7A/C7A M464S6453CKS-L1H/C1H M464S6453CKS-L1L/C1L * * * * * Max Freq. (Speed) 133MHz(7.5ns @CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * PCB : Height (1,200mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VSS DQ0 DQ1 DQ2 DQ3 VD D DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VD D A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VD D DQ12 DQ13 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 Pin 51 53 55 57 59 Front Pin DQ14 DQ15 VSS NC NC 52 54 56 58 60 Back DQ46 DQ47 VSS NC NC Pin Front DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **SDA VDD Pin 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **SCL VDD 95 97 99 101 103 105 107 Voltage Key 109 CLK0 62 CKE0 111 VD D 64 VDD 113 RAS 66 CAS 115 WE 68 CKE1 117 CS0 70 A12 119 CS1 72 *A13 121 DU 74 CLK1 123 VSS 76 VSS 125 NC 78 NC 127 NC 80 NC 129 VD D 82 VDD 131 DQ16 84 DQ48 133 DQ17 86 DQ49 135 DQ18 88 DQ50 137 DQ19 90 DQ51 139 VSS 92 VSS 141 DQ20 94 DQ52 143
PIN NAMES
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK1 CS0 ~ CS1 RAS CAS WE DQM0 ~ 7 VD D VSS SDA SCL DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Serial data I/O Serial clock Dont use No connection
CKE0 ~ CKE1 Clock enable input
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 Sept. 2001
M464S6453CKS
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
PC133/PC100 SODIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A12 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 D Q0 ~ 63 VDD /VSS
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
Rev. 0.0 Sept. 2001
M464S6453CKS
FUNCTIONAL BLOCK DIAGRAM
CKE1 CKE0 CS1 CS0 DQM0
PC133/PC100 SODIMM
DQM4 DQM CS0 CS1 CKE0CKE1 DQ0 DQ1 DQ2 DQ3 U0 DQ4 DQ5 DQ6 DQ7 DQM CS0 CS1 CKE0CKE1 DQ0 DQ1 DQ2 DQ3 U1 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6 DQM CS0 CS1 CKE0CKE1 DQ0 DQ1 DQ2 DQ3 U2 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQM CS0 CS1 CKE0CKE1 DQ0 DQ1 DQ2 DQ3 U3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS0 CS1 CKE0 CKE1 DQ0 DQ1 DQ2 DQ3 U7 DQ4 DQ5 DQ6 DQ7 DQM CS0 CS1 CKE0 CKE1 DQ0 DQ1 DQ2 DQ3 U6 DQ4 DQ5 DQ6 DQ7 DQM CS0 CS1 CKE0 CKE1 DQ0 DQ1 DQ2 DQ3 U5 DQ4 DQ5 DQ6 DQ7 DQM CS0 CS1 CKE0 CKE1 DQ0 DQ1 DQ2 DQ3 U4 DQ4 DQ5 DQ6 DQ7
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 & 1 10 DQn
SDRAM U0 ~ U7 SDRAM U0 ~ U7
SCL Serial PD WP SA0 SA1 SA2 SDA
SDRAM U0 ~ U7
47K
SDRAM U0 ~ U7 SDRAM U0 ~ U7 Every DQ pin of SDRAM * U0/U4 U1/U5 U2/U6 U3/U7
VDD Three 0.1 uF X7R 0603 Capacitors per each SDRAM Vss To all SDRAMs
CLK0/1
* *
Rev. 0.0 Sept. 2001
M464S6453CKS
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VD D supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD , VDDQ TSTG PD IOS
PC133/PC100 SODIMM
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 8 50 Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Symbol VD D VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 -
Recommended operating conditions (Voltage referenced to V SS = 0V, TA = 0 to 70 C) Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, T A = 23C, f = 1MHz, VREF = 1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Min 45 45 35 25 35 10 15 Max 90 90 60 45 60 25 30 Unit pF pF pF pF pF pF pF
Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1) Input capacitance (RAS, CAS, WE) Input capacitance (CKE0 ~ CKE1) Input capacitance (CLK0 ~ CLK1) Input capacitance (CS0 ~ CS1) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63)
Rev. 0.0 Sept. 2001
M464S6453CKS
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Burst length = 1 tRC tRC (min) IO = 0 mA CKE VIL(max), t C C = 10ns CKE & CLK VIL(max), t C C = CKE VIH(min), CS VIH(min), t C C = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), t C C = Input signals are stable CKE VIL(max), t C C = 10ns CKE & CLK VIL(max), t C C = CKE VIH(min), CS VIH(min), t C C = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), t C C = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC (min) CKE 0.2V C L Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Test Condition
PC133/PC100 SODIMM
Version -7A 960 -1H 960 -1L 960
Unit
Note
Operating current (One bank active) Precharge standby current in power-down mode
ICC1
mA
1
ICC2P ICC2PS ICC2N
32 32 320
mA
Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N
mA 160 96 96 480 mA
mA
Active standby current in non power-down mode (One bank active)
ICC3NS
400
mA
Operating current (Burst mode) Refresh current Self refresh current
ICC4
1120
1040
1040
mA
1
ICC5 ICC6
1840
1760 48 24
1760
mA mA mA
2
Rev. 0.0 Sept. 2001
M464S6453CKS
AC OPERATING TEST CONDITIONS
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition (VDD = 3.3V 0.3V, TA = 0 to 70 C) Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
PC133/PC100 SODIMM
Unit V V ns V
3.3V
Vtt = 1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, I OH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -7A tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS (max) tR C(min) tRDL(min) tDAL(min) tCDL(min) tB D L(min) tCCD(min) CAS latency=3 CAS latency=2 65 15 20 20 45 Version -1H 20 20 20 50 100 70 2 2 CLK + 20 ns 1 1 1 2 1 70 -1L 20 20 20 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 0.0 Sept. 2001
M464S6453CKS
PC133/PC100 SODIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE.
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in HiZ CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tC H tC L tSS tSH tSLZ tSHZ tOH tSAC Symbol Min CLK cycle time tC C 7.5 10 3 3 2.5 2.5 1.5 0.8 1 5.4 6 5.4 6 3 3 3 3 2 1 1 6 6 -7A Max 1000 Min 10 10 6 6 3 3 3 3 2 1 1 6 7 ns ns ns ns ns ns 3 3 3 3 2 -1H Max 1000 Min 10 12 6 7 ns 2 ns 1,2 -1L Max 1000 ns 1 Unit Note
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.0 Sept. 2001
M464S6453CKS
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS WE
PC133/PC100 SODIMM
A12, A11 A9 ~ A0
DQM
BA0,1
A1 0/AP
Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A8) Column address (A0 ~ A8)
3 3
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.0 Sept. 2001
M464S6453CKS
PACKAGE DIMENSIONS
PC133/PC100 SODIMM
Units : Inches (Millimeters)
2.66 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.79 (20.00) 0.24 (6.0) 2-R 0.078 Min (2.00 Min) 1.20 (30.48) 0.024 0.001 (0.600 0.050) 0.008 0.006 (0.200 0.150) 0.03 TYP (0.80 TYP)
1
59
61
143
0.13 (3.30)
0.91 (23.20)
0.10 (2.50)
0.18 (4.60) 0.083 (2.10)
1.29 (32.80)
2- 0.07 (1.80)
Z 0.15 (3.70)
2 60 62 144
Y
0.150 Max (3.80 Max) 0.125 Min (3.20 Min) (4.00 Min) 0.157 Min 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1)
0.04 0.0039 (1.00 0.10)
Detail Z
0.100 Min (2.540 Min)
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 64Mx8 SDRAM, TSOP SDRAM Part No. : K4S510832C
Rev. 0.0 Sept. 2001
M464S6453CKS
M464S6453CKS-L7A/L1H/L1L, C7A/C1H/C1L(Intel SPD 1.2B ver. based)
*Organization : 64MX64 *Composition : 64MX8 *8 *Used component part # : K4S510832K-KL7A/KC7A/KL1H/KC1H/KL1L/KC1L *# of rows in module : 2 rows *# of banks in component : 4 banks *Feature : 1,200 mil height & double sided *Refresh : 8K/64ms *Contents :
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time from clock @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 7.5ns 5.4ns Function Supported -7A -1H 128bytes 256bytes (2K-bit) SDRAM 13 10 2 Rows 64 bits LVTTL 10ns 6ns Non parity 7.8us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK 10ns 6ns -1L
PC133/PC100 SODIMM
Hex value -7A -1H 80h 08h 04h 0Dh 0Ah 02h 40h 00h 01h 75h 54h A0h 60h 00h 82h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h A0h 60h -1L
Note
1 1
2 2
Non-buffered/Non-Registered & redundant addressing +/- 10% voltage toleance, Burst Read Single bit Write precharge all, auto precharge 10ns 6ns 10ns 6ns 20ns 15ns 20ns 20ns 45ns 50ns 50ns 2Dh 20ns 0Fh 12ns 7ns A0h 60h
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time @CAS latency of 1 Minimum row precharge time (=tRP ) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD ) Minimum activate precharge time (=tRAS) Module Row density Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time
0Eh A0h 60h 00h 00h 14h 14h 14h 32ns 40h 32ns 14h C0h 70h 2 2 2 2
2 Rows of 256MB 1.5ns 0.8ns 1.5ns 2ns 1ns 2ns 2ns 1ns 2ns 15h 08h 15h
20h 10h 20h
20h 10h 20h
Rev. 0.0 Sept. 2001
M464S6453CKS
SERIAL PRESENCE DETECT INFORMATION
Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~12 126 127 128+ Function described Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & InterManufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Year) Manufacturing date (Week) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz Reserved Unused storage locations 7 A Function Supported -7A 0.8ns -1H 1ns Intel 1.2B Samsung Samsung Onyang Korea M 4 Blank 6 4 S 6 4 5 3 C K S "-" L/C 1 H Blank S C-die (4th Gen.) Undefined 100MHz Detailed PC100 Information Undefined 1 L -1L 1ns
PC133/PC100 SODIMM
Hex value -7A 08h -1H 10h 00h 12h D3h 3Ah CEh 00h 01h 4Dh 34h 20h 36h 34h 53h 36h 34h 35h 33h 43h 4Bh 53h 2Dh 4Ch/43h 37h 41h 31h 48h 20h 53h 43h 64h CDh 3 3 4 5 6 6 5 31h 4Ch 6Ah -1L 10h
Note
Note : 1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards.
Rev. 0.0 Sept. 2001

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