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21-S3-C9228/P9228-112002
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USER'S MANUAL
S3C9228/P9228
8-Bit CMOS Microcontroller Revision 1
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S3C9228/P9228
8-BIT CMOS MICROCONTROLLERS USER'S MANUAL
Revision 1
Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained www..com herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. S3C9228/P9228 8-Bit CMOS Microcontrollers User's Manual, Revision 1 Publication Number: 21-S3-C9228/P9228-112002 (c) 2002 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQI Certificate No 9330) All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung-Eup Yongin-City, Kyunggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(331)-209-1907 FAX: (82)-(331)-209-1889 Home-Page URL: Http://www.samsungsemi.com Printed in the Republic of Korea "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.
Preface
The S3C9228/P9228 Microcontrollers User's Manual is designed for application designers and programmers who are using the S3C9228/P9228 microcontrollers for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters:
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Chapter 1 Chapter 2 Chapter 3
Product Overview Address Spaces Addressing Modes
Chapter 4 Chapter 5 Chapter 6
Control Registers Interrupt Structure SAM88RCRI Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to the 100% with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," explains the 100% program and data memory, internal register file, and mapped control register, and explains how to address them. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in standard format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the 100% interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II. Chapter 6, "SAM88RCRI Instruction Set," describes the features and conventions of the instruction set used for all S3C9-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the SAM8 product family and are reading this manual for the first time, we recommend that you first read chapters 1-3 carefully. Then, briefly look over the detailed information in chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary. Part II "hardware Descriptions," has detailed information about specific hardware components of the S3C9228/P9228 microcontrollers. Also included in Part II are electrical, mechanical, OTP, and development tools data. It has 13 chapters: Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Clock Circuits RESET and Power-Down I/O Ports Basic Timer Timer 1 Watch Timer LCD Controller/Driver Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 10-bit ADC Serial I/O Interface Electrical Data Mechanical Data S3P9228 OTP Development Tools
Two order forms are included at the back of this manual to facilitate customer order for S3C9228/P9228 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
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Table of Contents
Part I -- Programming Model
Chapter 1
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Product Overview
Product Family ................................................................................................................... 1-1 S3C9228/P9228 Microcontroller .............................................................................................................. 1-1 OTP......................................................................................................................................................... 1-1 Features .................................................................................................................................................. 1-2 Block Diagram ......................................................................................................................................... 1-3 Pin Assignments ...................................................................................................................................... 1-4 Pin Descriptions....................................................................................................................................... 1-6 Pin Circuit Diagrams................................................................................................................................ 1-8
Chapter 2
Address Spaces
Overview ................................................................................................................................................. 2-1 Program Memory (ROM) ......................................................................................................................... 2-2 Register Architecture ............................................................................................................................... 2-3 Common Working Register Area (C0H-CFH) .......................................................................................... 2-4 System Stack .......................................................................................................................................... 2-5
Chapter 3
Addressing Modes
Overview ................................................................................................................................................. 3-1 Register Addressing Mode (R)......................................................................................................... 3-2 Indirect Register Addressing Mode (IR) ........................................................................................... 3-3 Indexed Addressing Mode (X).......................................................................................................... 3-7 Direct Address Mode (DA) ............................................................................................................... 3-10 Relative Address Mode (RA) ........................................................................................................... 3-12 Immediate Mode (IM) ...................................................................................................................... 3-12
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Table of Contents (Continued)
Chapter 4 Control Registers
Overview ................................................................................................................................................. 4-1
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Chapter 5
Interrupt Structure
Overview ................................................................................................................................................. 5-1 Interrupt Processing Control Points.................................................................................................. 5-1 Enable/Disable Interrupt Instructions (EI, DI) ................................................................................... 5-1 Interrupt Pending Function Types .................................................................................................... 5-2 Interrupt Priority............................................................................................................................... 5-2 Interrupt Source Service Sequence ................................................................................................. 5-3 Interrupt Service Routines ............................................................................................................... 5-3 Generating Interrupt Vector addresses............................................................................................. 5-3 S3C9228/P9228 Interrupt Structure ................................................................................................. 5-4
Chapter 6
SAM88RCRI Instruction Set
Overview ................................................................................................................................................. 6-1 Register Addressing......................................................................................................................... 6-1 Addressing Modes ........................................................................................................................... 6-1 Flags Register (FLAGS) .................................................................................................................. 6-4 Flag Descriptions............................................................................................................................. 6-4 Instruction Set Notation ................................................................................................................... 6-5 Condition Codes .............................................................................................................................. 6-9 Instruction Descriptions.................................................................................................................... 6-10
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Table of Contents (Continued)
Part II -- Hardware Descriptions
Chapter 7 Clock Circuit
www..com Overview ................................................................................................................................................. 7-1
System Clock Circuit ....................................................................................................................... 7-1 CPU Clock Notation ........................................................................................................................ 7-1 Main Oscillator Circuits.................................................................................................................... 7-2 Sub Oscillator Circuits ..................................................................................................................... 7-2 Clock Status During Power-Down Modes......................................................................................... 7-3 System Clock Control Register (CLKCON) ...................................................................................... 7-4 Oscillator Control Register (OSCCON) ............................................................................................ 7-5 Switching The CPU Clock................................................................................................................ 7-6 Stop Control Register (STPCON) .................................................................................................... 7-7
Chapter 8
RESET and Power-Down
System Reset .......................................................................................................................................... 8-1 Overview......................................................................................................................................... 8-1 Power-Down Modes................................................................................................................................. 8-2 Stop Mode....................................................................................................................................... 8-2 Idle Mode ........................................................................................................................................ 8-3 Hardware Reset Values ................................................................................................................... 8-4
Chapter 9
I/O Ports
Overview ................................................................................................................................................. 9-1 Port Data Registers ......................................................................................................................... 9-2 Port 0 .............................................................................................................................................. 9-3 Port 1 .............................................................................................................................................. 9-6 Port 2 .............................................................................................................................................. 9-9 Port 3 .............................................................................................................................................. 9-11 Port 4 .............................................................................................................................................. 9-14 Port 5 .............................................................................................................................................. 9-15 Port 6 .............................................................................................................................................. 9-16
Chapter 10
Basic Timer
Overview ................................................................................................................................................. 10-1 Basic Timer Control Register (BTCON) ........................................................................................... 10-2 Basic Timer Function Description .................................................................................................... 10-3
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Table of Contents (Continued)
Chapter 11 Timer 1
One 16-Bit Timer Mode (Timer 1) ............................................................................................................ 11-1 Overview ......................................................................................................................................... 11-1 Function Description........................................................................................................................ 11-1 Two 8-Bit Timers Mode (Timer A and B) .................................................................................................. 11-4 www..com Overview ......................................................................................................................................... 11-4 Function Description........................................................................................................................ 11-7
Chapter 12
Watch Timer
Overview ................................................................................................................................................. 12-1 Watch Timer Control Register (WTCON)......................................................................................... 12-2 Watch Timer Circuit Diagram................................................................................................................... 12-3
Chapter 13
LCD Controller/Driver
Overview ................................................................................................................................................. 13-1 LCD Circuit Diagram........................................................................................................................ 13-2 LCD RAM Address Area .................................................................................................................. 13-3 LCD Mode Control Register (LMOD)................................................................................................ 13-4 LCD Port Control Register ............................................................................................................... 13-5 LCD Voltage Dividing Resistors ....................................................................................................... 13-6 Common (COM) Signals.................................................................................................................. 13-6 Segment (SEG) Signals................................................................................................................... 13-6
Chapter 14
10-Bit A/D Converter
Overview ................................................................................................................................................. 14-1 Function Description ................................................................................................................................ 14-1 Conversion Timing .......................................................................................................................... 14-2 A/D Converter Control Register (ADCON) ....................................................................................... 14-2 Internal Reference Voltage Levels ................................................................................................... 14-3 Block Diagram ......................................................................................................................................... 14-3
Chapter 15
Serial I/O Interface
Overview ................................................................................................................................................. 15-1 Programming Procedure.................................................................................................................. 15-1 SIO Control Registers (SIOCON)..................................................................................................... 15-2 SIO Pre-Scaler Register (SIOPS) .................................................................................................... 15-3 SIO Block Diagram .................................................................................................................................. 15-3 Serial I/O Timing Diagram (SIO)...................................................................................................... 15-4
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Table of Contents (Concluded)
Chapter 16 Electrical Data
Overview ................................................................................................................................................. 16-1
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Chapter 17
Mechanical Data
Overview ................................................................................................................................................. 17-1
Chapter 18
S3P9228 OTP
Overview ................................................................................................................................................. 18-1 Operating Mode Characteristics....................................................................................................... 18-3
Chapter 19
Development Tools
Overview ................................................................................................................................................. 19-1 SHINE............................................................................................................................................. 19-1 SAMA Assembler ............................................................................................................................ 19-1 SASM86.......................................................................................................................................... 19-1 HEX2ROM ...................................................................................................................................... 19-1 Target Boards.................................................................................................................................. 19-1 TB9228 Target Board ...................................................................................................................... 19-3 Idle LED .......................................................................................................................................... 19-5 Stop LED......................................................................................................................................... 19-5
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List of Figures
Figure Number 1-1 1-2 1-3 1-4 www..com 1-5 1-7 1-8 1-9 1-10 1-11 1-12 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 4-1 Title Page Number
Block Diagram.................................................................................................................... 1-3 S3C9228 44-QFP Pin Assignments .................................................................................... 1-4 S3C9228 42-SDIP Pin Assignments ................................................................................... 1-5 Pin Circuit Type B .............................................................................................................. 1-8 Pin Circuit Type C .............................................................................................................. 1-8 Pin Circuit Type E-4 ........................................................................................................... 1-9 Pin Circuit Type F-16A ....................................................................................................... 1-9 Pin Circuit Type H-23 ......................................................................................................... 1-10 Pin Circuit Type H-32 ......................................................................................................... 1-11 Pin Circuit Type H-32A ....................................................................................................... 1-11 Pin Circuit Type H-32B ....................................................................................................... 1-12 S3C9228/P9228 Program Memory Address Space............................................................. 2-2 Internal Register File Organization ..................................................................................... 2-3 16-Bit Register Pairs........................................................................................................... 2-4 Stack Operations................................................................................................................ 2-5 Register Addressing ........................................................................................................... 3-2 Working Register Addressing ............................................................................................. 3-2 Indirect Register Addressing to Register File ...................................................................... 3-3 Indirect Register Addressing to Program Memory ............................................................... 3-4 Indirect Working Register Addressing to Register File ........................................................ 3-5 Indirect Working Register Addressing to Program or Data Memory..................................... 3-6 Indexed Addressing to Register File ................................................................................... 3-7 Indexed Addressing to Program or Data Memory with Short Offset..................................... 3-8 Indexed Addressing to Program or Data Memory with Long Offset ..................................... 3-9 Direct Addressing for Load Instructions............................................................................... 3-10 Direct Addressing for Call and Jump Instructions................................................................ 3-11 Relative Addressing............................................................................................................ 3-12 Immediate Addressing........................................................................................................ 3-12 Register Description Format ............................................................................................... 4-4
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List of Figures (Continued)
Figure Number 5-1 5-2 5-3
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Title
Page Number
S3C9-Series Interrupt Type ................................................................................................ 5-1 Interrupt Function Diagram ................................................................................................. 5-2 S3C9228/P9228 Interrupt Structure .................................................................................... 5-5 System Flags Register (FLAGS)......................................................................................... 6-4 Crystal/Ceramic Oscillator .................................................................................................. 7-2 External Oscillator .............................................................................................................. 7-2 RC Oscillator ...................................................................................................................... 7-2 Crystal/Ceramic Oscillator .................................................................................................. 7-2 External Oscillator .............................................................................................................. 7-2 System Clock Circuit Diagram ............................................................................................ 7-3 System Clock Control Register (CLKCON) ......................................................................... 7-4 Oscillator Control Register (OSCCON) ............................................................................... 7-5 STOP Control Register (STPCON) ..................................................................................... 7-7 S3C9228 I/O Port Data Register Format............................................................................. 9-2 Port 0 Control Register (P0CON) ........................................................................................ 9-4 Port 0 Interrupt Control Register (P0INT) ............................................................................ 9-4 Port 0 Interrupt Pending Bits (INTPND1.3-.0)...................................................................... 9-5 Port 0 Interrupt Edge Selection Register (P0EDGE)............................................................ 9-5 Port 0 Pull-up Control Register (P0PUR) ............................................................................ 9-5 Port 1 Control Register (P1CON) ........................................................................................ 9-6 Port 1 Interrupt Control Register (P1INT) ............................................................................ 9-7 Port 1 Interrupt Pending Bits (INTPND1.7-.4)...................................................................... 9-7 Port 1 Interrupt Edge Selection Register (P1EDGE)............................................................ 9-8 Port 1 Pull-up Control Register (P1PUR) ............................................................................ 9-8 Port 2 Control Register (P2CON) ........................................................................................ 9-9 Port 2 Pull-up Control Register (P2PUR) ............................................................................ 9-10 Port 3 Control Register (P3CON) ........................................................................................ 9-11 Port 3 Interrupt Control Register (P3INT) ............................................................................ 9-12 Port 3 Interrupt Pending Bits (INTPND2.5-.4)...................................................................... 9-12 Port 3 Interrupt Edge Selection Register (P3EDGE)............................................................ 9-13 Port 3 Pull-up Control Register (P3PUR) ............................................................................ 9-13 Port 4 High-Byte Control Register (P4CONH) ..................................................................... 9-14 Port 4 Low-Byte Control Register (P4CONL)....................................................................... 9-14 Port 5 High-Byte Control Register (P5CONH) ..................................................................... 9-15 Port 5 Low-Byte Control Register (P5CONL)....................................................................... 9-15 Port 6 Control Register (P6CON) ........................................................................................ 9-16
6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23
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List of Figures (Continued)
Figure Number 10-1 10-2 11-1 www..com 11-2 11-3 11-4 11-5 11-6 12-1 12-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 14-1 14-2 14-3 14-4 15-1 15-2 15-3 15-4 15-5 Title Page Number
Basic Timer Control Register (BTCON) .............................................................................. 10-2 Basic Timer Block Diagram ................................................................................................ 10-4 Timer 1 Control Register (TACON)..................................................................................... 11-2 Timer 1 Block Diagram (One 16-bit Mode) ......................................................................... 11-3 Timer A Control Register (TACON) .................................................................................... 11-5 Timer B Control Register (TBCON) .................................................................................... 11-6 Timer A Block Diagram (Two 8-bit Timers Mode) ............................................................... 11-8 Timer B Block Diagram (Two 8-bit Timers Mode) ............................................................... 11-9 Watch Timer Control Register (WTCON)............................................................................ 12-2 Watch Timer Circuit Diagram ............................................................................................. 12-3 LCD Function Diagram ....................................................................................................... 13-1 LCD Circuit Diagram .......................................................................................................... 13-2 LCD Display Data RAM Organization ................................................................................. 13-3 LCD Mode Control Register (LMOD) .................................................................................. 13-4 LCD Port Control Register .................................................................................................. 13-5 Internal Voltage Dividing Resistor Connection .................................................................... 13-6 LCD Signal Waveforms (1/8 Duty, 1/4 Bias) ....................................................................... 13-7 LCD Signal Waveforms (1/4 Duty, 1/3 Bias) ....................................................................... 13-8 LCD Signal Waveforms (1/3 Duty, 1/3 Bias) ....................................................................... 13-9 A/D Converter Control Register (ADCON) .......................................................................... 14-2 A/D Converter Data Register (ADDATAH/ADDATAL) ......................................................... 14-3 A/D Converter Functional Block Diagram ........................................................................... 14-3 Recommended A/D Converter Circuit for Highest Absolute Accuracy ................................. 14-4 Serial I/O Module Control Register (SIOCON) .................................................................... 15-2 SIO Prescaler Register (SIOPS)......................................................................................... 15-3 SIO Functional Block Diagram............................................................................................ 15-3 Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) ........................ 15-4 Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) ......................... 15-4
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List of Figures (Concluded)
Figure Number 16-1 16-2 16-3 16-4 www..com 16-5 16-6 16-7 16-8 17-1 17-2 18-1 18-2 18-3 19-1 19-2 19-3 19-4 19-5 Title Page Number
Stop Mode Release Timing When Initiated by an External Interrupt.................................... 16-5 Stop Mode Release Timing When Initiated by a RESET..................................................... 16-6 Input Timing for External Interrupts..................................................................................... 16-8 Input Timing for RESET...................................................................................................... 16-9 Serial Data Transfer Timing................................................................................................ 16-9 Clock Timing Measurement at XIN ..................................................................................... 16-11 Clock Timing Measurement at XTIN ................................................................................... 16-12 Operating Voltage Range ................................................................................................... 16-13 42-SDIP-600 Package Dimensions ..................................................................................... 17-1 44-QFP-1010B Package Dimensions.................................................................................. 17-2 S3P9228 44-QFP Pin Assignments .................................................................................... 18-1 S3P9228 42-SDIP Pin Assignments ................................................................................... 18-2 Standard Operating Voltage Range .................................................................................... 18-5 SMDS Product Configuration (SMDS2+) ............................................................................ 19-2 TB9228 Target Board Configuration ................................................................................... 19-3 Connectors (J101, J102) for TB9228 .................................................................................. 19-6 S3C9228 Probe Adapter for 42-SDIP Package ................................................................... 19-7 S3C9228 Probe Adapter for 44-QFP Package .................................................................... 19-7
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List of Tables
Table Number 1-1 6-1 6-2 www..com 6-3 6-4 6-5 6-6 8-1 9-1 9-2 13-1 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 18-1 18-2 18-3 18-4 19-1 19-2 19-3 Title Page Number
Pin Descriptions ................................................................................................................. 1-6 Instruction Group Summary................................................................................................ 6-2 Flag Notation Conventions ................................................................................................. 6-5 Instruction Set Symbols...................................................................................................... 6-5 Instruction Notation Conventions ........................................................................................ 6-6 Opcode Quick Reference ................................................................................................... 6-7 Condition Codes ................................................................................................................. 6-9 Register Values after RESET ............................................................................................. 8-4 S3C9228 Port Configuration Overview ............................................................................... 9-1 Port Data Register Summary.............................................................................................. 9-2 Common and Segment Pins per Duty Cycle ....................................................................... 13-3 Absolute Maximum Ratings ................................................................................................ 16-2 D.C. Electrical Characteristics ............................................................................................ 16-2 Data Retention Supply Voltage in Stop Mode ..................................................................... 16-5 Input/Output Capacitance ................................................................................................... 16-6 A.C. Electrical Characteristics ............................................................................................ 16-7 A/D Converter Electrical Characteristics ............................................................................. 16-8 Main Oscillation Characteristics.......................................................................................... 16-10 Sub Oscillation Characteristics ........................................................................................... 16-10 Main Oscillation Stabilization Time..................................................................................... 16-11 Sub Oscillation Stabilization Time ...................................................................................... 16-12 Descriptions of Pins Used to Read/Write the EPROM......................................................... 18-3 Comparison of S3P9228 and S3C9228 Features................................................................ 18-3 Operating Mode Selection Criteria...................................................................................... 18-3 D.C. Electrical Characteristics ............................................................................................ 18-4 Power Selection Settings for TB9228.................................................................................. 19-4 The SMDS2+ Tool Selection Setting .................................................................................. 19-5 Using Single Header Pins as the Input Path for External Trigger Sources........................... 19-5
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List of Programming Tips
Description Chapter 2: Address Spaces Addressing the Common Working Register Area ..................................................................................... 2-4 Standard Stack Operations Using PUSH and POP .................................................................................. 2-6 Page Number
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Chapter 5: Interrupt Structure How to clear an interrupt pending bit........................................................................................................ 5-6 Chapter 7: Clock Circuits Switching the CPU clock.......................................................................................................................... 7-6 How to Use Stop Instruction..................................................................................................................... 7-7
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List of Register Descriptions
Register Identifier ADCON BTCON CLKCON www..com FLAGS INTPND1 INTPND2 LMOD LPOT OSSCON P0CON P0INT P0PUR P0EDGE P1CON P1INT P1PUR P1EDGE P2CON P2PUR P3CON P3INT P3PUR P3EDGE P4CONH P4CONL P5CONH P5CONL P6CON SIOCON STPCON SYM TACON TBCON WTCON Full Register Name Page Number
A/D Converter Control Register.............................................................................. 4-5 Basic Timer Control Register ................................................................................. 4-6 System Clock Control Register............................................................................... 4-7 System Flags Register ........................................................................................... 4-8 Interrupt Pending Register 1................................................................................... 4-9 Interrupt Pending Register 2................................................................................... 4-10 LCD Mode Control Register ................................................................................... 4-11 LCD Port Control Register...................................................................................... 4-12 Oscillator Control Register ..................................................................................... 4-13 Port 0 Control Register........................................................................................... 4-14 Port 0 Interrupt Enable Register ............................................................................. 4-15 Port 0 Pull-up Resistors Enable Register................................................................ 4-16 Port 0 Interrupt Edge Selection Register ................................................................ 4-17 Port 1 Control Register........................................................................................... 4-18 Port 1 Interrupt Enable Register ............................................................................. 4-19 Port 1 Pull-up Resistors Enable Register................................................................ 4-20 Port 1 Interrupt Edge Selection Register ................................................................ 4-21 Port 2 Control Register........................................................................................... 4-22 Port 2 Pull-up Resistors Enable Register................................................................ 4-23 Port 3 Control Register........................................................................................... 4-24 Port 2 Interrupt Enable Register ............................................................................. 4-25 Port 3 Pull-up Resistors Enable Register................................................................ 4-26 Port 3 Interrupt Edge Selection Register ................................................................ 4-27 Port 4 Control Register........................................................................................... 4-28 Port 4 Control Register Low Byte ........................................................................... 4-29 Port 5 Control Register High Byte .......................................................................... 4-30 Port 5 Control Register Low Byte ........................................................................... 4-31 Port 6 Control Register........................................................................................... 4-32 SIO Control Register.............................................................................................. 4-33 Stop Control Register............................................................................................. 4-34 System Mode Register........................................................................................... 4-35 Timer 1/A Control Register..................................................................................... 4-36 Timer B Control Register........................................................................................ 4-37 Watch Timer Control Register................................................................................ 4-38
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List of Instruction Descriptions
Instruction Mnemonic ADC ADD AND www..com CALL CCF CLR COM CP DEC DI EI IDLE INC IRET JP JR LD LDC/LDE LDCD/LDED LDCI/LDEI NOP OR POP PUSH RCF RET RL RLC RR RRC SBC SCF SRA STOP SUB TCM TM XOR Full Instruction Name Page Number
Add With Carry ...................................................................................................... 6-11 Add ........................................................................................................................ 6-12 Logical AND........................................................................................................... 6-13 Call Procedure ....................................................................................................... 6-14 Complement Carry Flag......................................................................................... 6-15 Clear...................................................................................................................... 6-16 Complement .......................................................................................................... 6-17 Compare................................................................................................................ 6-18 Decrement ............................................................................................................. 6-19 Disable Interrupts................................................................................................... 6-20 Enable Interrupts.................................................................................................... 6-21 Idle Operation ........................................................................................................ 6-22 Increment............................................................................................................... 6-23 Interrupt Return...................................................................................................... 6-24 Jump...................................................................................................................... 6-25 Jump Relative........................................................................................................ 6-26 Load ...................................................................................................................... 6-27 Load Memory......................................................................................................... 6-29 Load Memory and Decrement ................................................................................ 6-31 Load Memory and Increment ................................................................................. 6-32 No Operation ......................................................................................................... 6-33 Logical OR............................................................................................................. 6-34 Pop From Stack ..................................................................................................... 6-35 Push To Stack ....................................................................................................... 6-36 Reset Carry Flag.................................................................................................... 6-37 Return.................................................................................................................... 6-38 Rotate Left ............................................................................................................. 6-39 Rotate Left Through Carry...................................................................................... 6-40 Rotate Right........................................................................................................... 6-41 Rotate Right Through Carry ................................................................................... 6-42 Subtract With Carry ............................................................................................... 6-43 Set Carry Flag........................................................................................................ 6-44 Shift Right Arithmetic ............................................................................................. 6-45 Stop Operation....................................................................................................... 6-46 Subtract ................................................................................................................. 6-47 Test Complement Under Mask............................................................................... 6-48 Test Under Mask.................................................................................................... 6-49 Logical Exclusive OR............................................................................................. 6-50
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S3C9228/P9228
PRODUCT OVERVIEW
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PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device. A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations.
S3C9228/P9228 MICROCONTROLLER
The S3C9228 can be used for dedicated control functions in a variety of applications, and is especially designed for application with FRS or etc. The S3C9228/P9228 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM88RCRI CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9228/P9228 has 8K-byte of program ROM, and 264-byte of RAM (including 16-byte of working register and 20-byte LCD display RAM). Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core: -- 7 configurable I/O ports including ports shared with segment/common drive outputs -- 10-bit programmable pins for external interrupts -- One 8-bit basic timer for oscillation stabilization and watch-dog functions -- Two 8-bit timer/counters with selectable operating modes -- Watch timer for real time -- 4 channel A/D converter -- 8-bit serial I/O interface
OTP
The S3C9228 microcontroller is also available in OTP (One Time Programmable) version. S3P9228 microcontroller has an on-chip 8K-byte one-time-programmable EPROM instead of masked ROM. The S3P9228 is comparable to S3C9228, both in function and in pin configuration.
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PRODUCT OVERVIEW
S3C9228/P9228
FEATURES
CPU * SAM88RCRI CPU core Memory 8192 x 8 bits program memory (ROM) 264 x 8 bits data memory (RAM) (Including LCD data memory) www..com Instruction Set * * 41 instructions Idle and Stop instructions added for power-down modes * * LCD Controller/Driver * * * 16 segments and 8 common terminals 3, 4, and 8 common selectable Internal resistor circuit for LCD bias
8-bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source
A/D Converter * * * 10-bit converter resolution 50us conversion speed at 1MHz fADC clock 4-channel
36 I/O Pins * * I/O: 34 pins (44-pin QFP, 42-pin SDIP) Output only: 2 pins (44-pin QFP)
Interrupts * * 14 interrupt source and 1 vector One interrupt level
Two Power-Down Modes * * Idle: only CPU clock stops Stop: system clock and CPU clock stop
8-Bit Basic Timer * * Watchdog timer function 3 kinds of clock source
Oscillation Sources * * * Crystal, ceramic, or RC for main clock Main clock frequency: 0.4 MHz - 8MHz 32.768 kHz crystal oscillation circuit for sub clock
Two 8-Bit Timer/Counters * * * The programmable 8-bit timer/counters External event counter function Configurable as one 16-bit timer/counters
Instruction Execution Times * 500nS at 8MHz fx(minimum)
Watch Timer * * * Interval time: 3.91mS, 0.25S, 0.5S, and 1S at 32.768 kHz 0.5/1/2/4 kHz Selectable buzzer output Clock source generation for LCD
Operating Voltage Range * * 2.0 V to 5.5 V at 0.4 - 4.2MHz 2.7 V to 5.5 V at 0.4 - 8MHz
Operating Temperature Range * -25 C to +85 C
Package Type * 44-pin QFP, 42-pin SDIP
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S3C9228/P9228
PRODUCT OVERVIEW
BLOCK DIAGRAM
TAOUT/ P0.0 T1CLK/ P0.1
8-Bit Timer/ CounterA 8-Bit Timer/ CounterB
RESET 16-Bit Timer/ Counter1
XIN XT IN
XOUT XTOUT
Watchdog Timer Basic Timer
P0.0/TAOUT/INT www..com P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P0.4 P0.5 P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT P2.0/SCK/SEG1 P2.1/SO/SEG0 P2.2/SI P2.3 P3.0/INTP/SEG3 P3.1/INTP/SEG2 P4.0-P4.7/ SEG4-SEG11 P5.0-P5.3/ SEG12-SEG15 P5.4-P5.7/ SEG16-SEG19/ COM7-COM4
I/O Port 0
Port I/O and Interrupt Control
Watch Timer
BUZ/P0.3
I/O Port 1 SAM88RCRI CPU
LCD Driver/ Controller
COM0-COM3/P6.3-P6.0 COM4-COM7/ SEG19-SEG16/P5.7-P5.4 SEG0-SEG1/P2.1-P2.0 SEG2-SEG3/P3.1-P3.0 SEG4-SEG11/P4.0-P4.7 SEG12-SEG15/P5.0-P5.3
I/O Port 2
I/O Port 3
8-Kbyte ROM
264-Byte Register File
SIO
P2.0/SCK/SEG1 P2.1/SO/SEG0 P2.2/SI P1.0-P1.3/AD0-AD3
I/O Port 4
A/D Converter
I/O Port 5
I/O Port 6
P6.0-P6.3/COM3-COM0
Figure 1-1. Block Diagram
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PRODUCT OVERVIEW
S3C9228/P9228
PIN ASSIGNMENTS
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P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT VDD VSS XOUT XIN TEST XTIN XTOUT
44 43 42 41 40 39 38 37 36 35 34
P0.5 P0.4 P0.3/BUZ/INT P0.2/INT P0.1/T1CLK/INT P0.0/TAOUT/INT COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7
1 2 3 4 5 6 7 8 9 10 11
S3C9228
(44-QFP)
33 32 31 30 29 28 27 26 25 24 23
COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4
Figure 1-2. S3C9228 44-QFP Pin Assignments
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RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.0/SCK SEG2/P3.1/INTP SEG3/P3.0/INTP SEG4/P4.0 SEG5/P4.1 SEG6/P4.2 SEG7/P4.3
12 13 14 15 16 17 18 19 20 21 22
S3C9228/P9228
PRODUCT OVERVIEW
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COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT VDD VSS XOUT XIN TEST XTIN XTOUT RESET P2.3 P2.2/SI SEG0/P2.1/SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4 SEG7/P4.3 SEG6/P4.2 SEG5/P4.1 SEG4/P4.0 SEG3/P3.0/INTP SEG2/P3.1/INTP SEG1/P2.0/SCK
S3C9228
Figure 1-3. S3C9228 42-SDIP Pin Assignments
(42-SDIP)
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PRODUCT OVERVIEW
S3C9228/P9228
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3
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Pin Type I/O
Pin Description 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable output port. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups.
Circuit Number E-4
Pin Numbers 39(3) 40(4) 41(5) 42(6) 43-44 1(7) 2(8) 3(9) 4(10) 16(22) 15(21) 14(20) 13(19) 18(24) 17(23) 19-26(25-32)
Share Pins TAOUT/INT T1CLK/INT INT BUZ/INT AD0/INT AD1/INT AD2/INT AD3/INT SCK/SEG1 SO/SEG0 SI - INTP/SEG3 INTP/SEG2 SEG4-SEG11
P0.4-P0.5 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P4.0-P4.7
O I/O
C F-16A
I/O I/O I/O
H-32A E-4 H-32B
I/O
H-32
P5.0-P5.3 P5.4-P5.7 P6.0-P6.3
I/O
H-32
27-30(33-36) 31-34(37-40)
SEG12-SEG15 SEG16-SEG19 /COM7-COM4 COM3-COM0
I/O
1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups.
H-32
35-38 (41-42,1-2)
NOTE: Parentheses indicate pin number for 42-SDIP-600 package.
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S3C9228/P9228
PRODUCT OVERVIEW
Table 1-1. Pin Descriptions (Continued) Pin Names VDD, VSS XOUT, XIN XTOUT, XTIN TEST
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Pin Type - - - - I I/O I/O I/O I/O I/O I/O I/O
Pin Description Power input pins for internal power block Main oscillator pins for main clock Sub oscillator pins for sub clock Chip test input pin Hold GND when the device is operating RESET signal input pin. Schmitt trigger input with internal pull-up resistor. External interrupts input. Key scan interrupts inputs. Timer 1/A external clock input. Timer 1/A clock output. Analog input pins for A/D converts module. Buzzer signal output. Serial clock, serial data output, serial data input LCD segment signal output
Circuit Number - - - - B E-4 F-16A H-32B E-4 E-4 F-16A E-4 H-32A E-4
Pin Numbers 5,6(11,12) 7,8(13,14) 11,10(17,16) 9(15) 12(18) 39-42(3-6) 1-4(7-10) 17-18(23-24) 40(4) 39(3) 1-4(7-10) 42(6) 16-15(22-21) 14(20) 15-16(21-22) 17-18(23-24) 19-34(25-40) 38-31 (2-1,42-37)
Share Pins -
- - - P0.0-P0.3 P1.0-P1.3 P3.1-P3.0 P0.1 P0.0 P1.0-P1.3 P0.3 P2.0-P2.1 P2.2 P2.1-P2.0 P3.1-P3.0 P4.0-P4.7 P5.0-P5.7 P6.3-P6.0 P5.7-P5.4
RESET INT INTP T1CLK TAOUT AD0-AD3 BUZ SCK SO SI SEG0-SEG1 SEG2-SEG3 SEG4-SEG19 COM0-COM7
I/O
H-32A H-32B H-32
I/O
LCD common signal output
H-32
NOTE: Parentheses indicate pin number for 42-SDIP-600 package.
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PRODUCT OVERVIEW
S3C9228/P9228
PIN CIRCUIT DIAGRAMS
VDD Pull-Up Resistor
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RESET
Noise Filter
Figure 1-4. Pin Circuit Type B
VDD
Data Output Output Disable VSS
Figure 1-5. Pin Circuit Type C
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S3C9228/P9228
PRODUCT OVERVIEW
VDD Pull-up Resistor Pull-up Enable
VDD Open-Drain
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Data Output Disable
I/O
External Interrupt Input
Figure 1-7. Pin Circuit Type E-4
VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data Output Disable
Circuit Type E
I/O
ADEN ADSELECT Data To ADC
Figure 1-8. Pin Circuit Type F-16A
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PRODUCT OVERVIEW
S3C9228/P9228
VLC1
VLC2
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VLC3
SEG/COM Output Disable
Out
VLC4
VLC5
VSS
Figure 1-9. Pin Circuit Type H-23
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S3C9228/P9228
PRODUCT OVERVIEW
VDD Pull-up Resistor Pull-up Enable
VDD Open-Drain EN
Data
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I/O
LCD Out EN
COM/SEG Output Disable
Circuit Type H-23
Figure 1-10. Pin Circuit Type H-32
VDD Pull-up Resistor Pull-up Enable
VDD Open-Drain EN
Data
I/O
LCD Out EN
COM/SEG Output Disable
Circuit Type H-23
Figure 1-11. Pin Circuit Type H-32A
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PRODUCT OVERVIEW
S3C9228/P9228
VDD Pull-up Resistor Pull-up Enable
VDD Open-Drain EN
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Data
I/O
LCD Out EN
Port Enable (LMOD.5)
COM/SEG Output Disable
Circuit Type H-23
Figure 1-12. Pin Circuit Type H-32B
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S3C9228/P9228
ADDRESS SPACES
2
OVERVIEW
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ADDRESS SPACES
The S3C9228/P9228 microcontroller has three kinds of address space: -- Program memory (ROM) -- Internal register file -- LCD display register file A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3C9228 has 8K bytes of mask-programmable program memory on-chip. The S3C9228/P9228 microcontroller has 244 bytes general-purpose registers in its internal register file and the 20 bytes for LCD display memory is implemented in the internal register file too. Fifty-six bytes in the register file are mapped for system and peripheral control functions.
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ADDRESS SPACES
S3C9228/P9228
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H-0001H) are an interrupt vector address. The program reset address in the ROM is 0100H.
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(Decimal) 8,192
(Hex) 1FFFH
8K bytes Internal Program Memory Area
256 2 1 0
Program Start
0100H 0002H
Interrupt Vector
0001H 0000H
Figure 2-1. S3C9228/P9228 Program Memory Address Space
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S3C9228/P9228
ADDRESS SPACES
REGISTER ARCHITECTURE
The upper 72 bytes of the S3C9228/P9228's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 184 bytes of internal register file (00H-B7H) is called the general purpose register space. For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00H-BFH). This register file expansion is implemented by page 1 in the S3C9228/P9228. The page 1 (20 x 8 bits) is for LCD display register and can be used as general-purpose registers.
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FFH Peripheral Control Registers E0H DFH D0H CFH C0H BFH B8H B7H
72 Bytes of Common Area
System Control Registers Working Registers Peripheral Control Registers
184 Bytes ~
General Purpose Register File and Stack Area 3FH General Purpose Register File LCD Display Registers 00H 00H
64 Bytes
13H
(Page 0)
(Page 1)
Figure 2-2. Internal Register File Organization
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ADDRESS SPACES
S3C9228/P9228
COMMON WORKING REGISTER AREA (C0H-CFH)
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. The Register (R) addressing mode can be used to access this area
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Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register.
MSB Rn
LSB Rn + 1
n = Even address
Figure 2-3. 16-Bit Register Pairs
+ PROGRAMMING TIP -- Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples: 1. LD LD 2. ADD 0C2H,40H R2,40H 0C3H,#45H ; Invalid addressing mode! ; R2 (C2H) the value in location 40H ; Invalid addressing mode! ; R3 (C3H) R3 + 45H
Use working register addressing instead:
Use working register addressing instead: ADD R3,#45H
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S3C9228/P9228
ADDRESS SPACES
SYSTEM STACK
S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file. STACK OPERATIONS Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents www..com of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-4.
High Address
PCL PCL Top of stack PCH PCH Top of stack Flags Stack contents after an interrupt
Stack contents after a call instruction
Low Address
Figure 2-4. Stack Operations
STACK POINTER (SP) Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C9228/P9228, the SP must be initialized to an 8bit value in the range 00H-B7H. NOTE In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area.
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ADDRESS SPACES
S3C9228/P9228
+ PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD
* * *
SP,#0B8H
; SP B8H (Normally, the SP is set to 0B8H by the ; initialization routine)
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PUSH PUSH PUSH PUSH
* * *
SYM WTCON 20H R3
; ; ; ;
Stack address 0B7H Stack address 0B6H Stack address 0B5H Stack address 0B4H
SYM WTCON 20H R3
POP POP POP POP
R3 20H WTCON SYM
; ; ; ;
R3 Stack address 0B4H 20H Stack address 0B5H WTCON Stack address 0B6H SYM Stack address 0B7H
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S3C9228/P9228
ADDRESSING MODES
3
OVERVIEW
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ADDRESSING MODES
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows: -- Register (R) -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Relative Address (RA) -- Immediate (IM)
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ADDRESSING MODES
S3C9228/P9228
REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2).
Program Memory
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Register File
8-bit Register File Address One-Operand Instruction (Example)
dst OPCODE
Point to One Rigister in Register File Value used in Instruction Execution
OPERAND
Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File CFH
Program Memory 4-Bit Working Register Two-Operand Instruction (Example) Sample Instruction: ADD R1, R2 ; 4 LSBs Point to the Woking Register (1 of 16)
. . . .
OPERAND C0H
dst
src
OPCODE
Where R1 = C1H and R2 = C2H
Figure 3-2. Working Register Addressing
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S3C9228/P9228
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location.
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Program Memory 8-Bit Register File Address One-Operand Instruction (Example)
Register File
dst OPCODE
Point to One Rigister in Register File Address of Operand used by Instruction
ADDRESS
Value used in Instruction Execution
OPERAND
Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-Bit register address
Figure 3-3. Indirect Register Addressing to Register File
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ADDRESSING MODES
S3C9228/P9228
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
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Program Memory Example Instruction References Program Memory REGISTER PAIR Points to Rigister Pair 16-Bit Address Points to Program Memory
dst OPCODE
Program Memory Sample Instructions: CALL JP @RR2 @RR2
Value used in Instruction
OPERAND
Figure 3-4. Indirect Register Addressing to Program Memory
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S3C9228/P9228
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File CFH
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Program Memory 4-Bit Working Register Address 4 LSBs Point to the Woking Register (1 of 16)
. . . .
OPERAND C0H
dst
src
OPCODE
Sample Instruction: OR R6, @R2
Value used in Instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing to Register File
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ADDRESSING MODES
S3C9228/P9228
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File CFH
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Program Memory 4-Bit Working Register Address dst src OPCODE Next 3 Bits Point to Working Register Pair (1 of 8) LSB Selects
. . . .
Register Pair C0H 16-Bit address points to program memory or data memory
Example Instruction References either Program Memory or Data Memory
Program Memory or Data Memory
Value used in Instruction
OPERAND
Sample Instructions: LCD LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
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S3C9228/P9228
ADDRESSING MODES
INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of -128 to +127. This applies to external memory accesses only (see Figure 3-8). For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address www..com (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented.
Register File
~
Value used in Instruction OPERAND
~
+
Program Memory Base Address dst src OPCODE 4 LSBs Point to One of the Woking Register (1 of 16)
~
INDEX
~
Two-Operand Instruction Example
Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
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ADDRESSING MODES
S3C9228/P9228
INDEXED ADDRESSING MODE (Continued)
Program Memory 4-Bit Working Register Address
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Register File NEXT 3 Bits Point to Working Register Pair (1 of 8) Register Pair 16-Bit address added to offset
XS (OFFSET) dst src OPCODE
LSB Selects
+
8-Bits 16-Bits Program Memory or Data Memory Value used in Instruction
16-Bits
OPERAND
Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
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S3C9228/P9228
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Program Memory XLH (OFFSET) XLL (OFFSET) dst src OPCODE
Register File
4-Bit Working www..comRegister Address
NEXT 3 Bits Point to Working Register Pair (1 of 8) LSB Selects
Register Pair 16-Bit address added to offset
+
8-Bits 16-Bits Program Memory or Data Memory
16-Bits Sample Instructions: LDC R4, #1000H[RR2] #1000H) LDE R4, #1000H[RR2]
OPERAND
Value used in Instruction
; The values in the program address (RR2 + are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
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ADDRESSING MODES
S3C9228/P9228
DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
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Program or Data Memory
Program Memory
Memory Address Used
Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory
Sample Instructions: LDC LDE R5,1234H R5,1234H ; ; The values in the program address (1234H) are loaded into register R5. Identical operation to LDC example, except that external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
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S3C9228/P9228
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
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Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE
Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
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ADDRESSING MODES
S3C9228/P9228
RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR.
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Program Memory
Next OPCODE Program Memory Address Used
Current Instruction
Displacement OPCODE
Current PC Value Signed Displacement Value
+
Sample Instructions: JR ULT,$ + OFFSET ; Where OFFSET is a value in the range + 127 to - 128
Figure 3-12. Relative Addressing IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH
Figure 3-13. Immediate Addressing
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S3C9228/P9228
CONTROL REGISTERS
4
OVERVIEW
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CONTROL REGISTERS
In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual.
4-1
CONTROL REGISTERS
S3C9228/P9228
Table 4-1. System and Peripheral Control Registers (Page 0) Register Name Port 0 Control Register Port 0 Pull-up Resistor Enable Register Port 0 Interrupt Control Register Port 0 Interrupt Edge Selection Register Port 1 Control www..com Register Port 1 Pull-up Resistor Enable Register Port 1 Interrupt Control Register Port 1 Interrupt Edge Selection Register Port 2 Control Register Port 2 Pull-up Resistor Enable Register Port 3 Control Register Port 3 Pull-up Resistor Enable Register Port 3 Interrupt Control Register Port 3 Interrupt Edge Selection Register Port 4 Control Register (High Byte) Port 4 Control Register (Low Byte) Port 5 Control Register (High Byte) Port 5 Control Register (Low Byte) Port 6 Control Register LCD Mode Register Mnemonic P0CON P0PUR P0INT P0EDGE P1CON P1PUR P1INT P1EDGE P2CON P2PUR P3CON P3PUR P3INT P3EDGE P4CONH P4CONL P5CONH P5CONL P6CON LMOD Address (Page 0) Decimal 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 Hex EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Location FFH is not mapped.
4-2
S3C9228/P9228
CONTROL REGISTERS
Table 4-1. System and Peripheral Control Registers (Page 0) Register Name Mnemonic Address (Page 0) Decimal Locations D8H-B9H are not mapped. Timer B Control Register Timer 1/A Control Register Timer B Data Register Timer A www..com Data Register Timer B Counter Timer A Counter A/D Converter Control Register A/D Converter Data Register (High Byte) A/D Converter Data Register (Low Byte) Oscillator Control Register System Clock Control Register System Flags Register Interrupt Pending Register 1 Interrupt Pending Register 2 LCD Port Control Register Stack Pointer Watch Timer Control Register Basic Timer Control Register Basic Timer Counter System Mode Register STOP Control Register SIO Control Register SIO Data Register SIO Prescaler Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register TBCON TACON TBDATA TADATA TBCNT TACNT ADCON ADDATAH ADDATAL OSCCON CLKCON FLAGS INTPND1 INTPND2 LPOT SP WTCON BTCON BTCNT SYM STPCON SIOCON SIODATA SIOPS P0 P1 P2 P3 P4 P5 P6 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 220 221 223 224 225 226 227 228 229 230 231 232 233 234 BAH BBH BCH BDH BEH BFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DCH DDH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Hex R/W
Location DBH is not mapped.
Location DEH is not mapped.
4-3
CONTROL REGISTERS
S3C9228/P9228
Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register bit or bit function Full Register name mnemonic
Register address (hexadecimal)
FLAGS - System Flags Register
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D5H .5 x R/W .4 x R/W .3 x R/W .2 x R/W .1 0 R/W .0 0 R/W
Bit Identifier RESET Value Read/Write
.7
.7 x R/W
.6 x R/W
Carry Flag (C) 0 1 Operation dose not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit7
.6
Zero Flag 0 1 Operation result is a non-zero value Operation result is zero
.5
Sign Flag 0 1 Operation generates positive number (MSB = "0") Operation generates negative number (MSB = "1")
R = Read-only W = Write-only R/W = Read/write ' - ' = Not used Addressing mode or modes you can use to modify register values
Description of the effect of specific bit settings
RESET value notation: '-' = Not used 'x' = Undetermind value '0' = Logic zero '1' = Logic one
Bit number: MSB = Bit 7 LSB = Bit 0
Figure 4-1. Register Description Format
4-4
S3C9228/P9228
CONTROL REGISTERS
ADCON -- A/D Converter Control Register
Bit Identifier RESET Value Read/Write .7-.6
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D0H
.4 0 R/W .3 0 R .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 0 R/W
Not used for the S3C9228/P9228 A/D Input Pin Selection Bits 0 0 1 1 0 1 0 1 AD0 (P1.0) AD1 (P1.1) AD2 (P1.2) AD3 (P1.3)
.5-.4
.3
End of Conversion Bit (Read-only) 0 1 Conversion not complete Conversion complete
.2-.1
Clock Source Selection Bits 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/4 fxx
.0
Start or Enable Bit 0 1 Disable operation Start operation (automatically disable operation after conversion complete)
4-5
CONTROL REGISTERS
S3C9228/P9228
BTCON -- Basic Timer Control Register
Bit Identifier RESET Value Read/Write .7-.4
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DCH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
Watchdog Timer Enable Bits 1 0 1 0 Disable watchdog function Enable watchdog function Any other value
.3-.2
Basic Timer Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/4096 fxx/1024 fxx/128 fxx/16
.1
Basic Timer Counter Clear Bit (1) 0 1 No effect Clear the basic timer counter value (BTCNT)
.0
Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters (2) 0 1 No effect Clear clock frequency dividers
NOTES 1. When "1" is written to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to "0". 2. When "1" is written to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0".
4-6
S3C9228/P9228
CONTROL REGISTERS
CLKCON -- System Clock Control Register
Bit Identifier RESET Value Read/Write .7
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D4H
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
Oscillator IRQ Wake-up Function Bit 0 1 Enable IRQ for main or sub oscillator wake-up in power down mode Disable IRQ for main or sub oscillator wake-up in power down mode
.6-.5
Bits 6-5 0 Always logic zero
.4-.3
CPU Clock (System Clock) Selection Bits 0 0 1 1 0 1 0 1 Divide by 16 (fxx/16) Divide by 8 (fxx /8) Divide by 2 (fxx /2) Non-divided clock (fxx)
.2-.0
Bits 2-0 0 Always logic zero
4-7
CONTROL REGISTERS
S3C9228/P9228
FLAGS -- System Flags Register
Bit Identifier RESET Value Read/Write .7
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D5H
.5 x R/W .4 x R/W .3 - - .2 - - .1 - - .0 - -
.7 x R/W
.6 x R/W
Carry Flag (C) 0 Operation does not generate a carry or borrow condition
.6
Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero
.5
Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1")
.4
Overflow Flag (V) 0 1 Operation result is +127 or -128 Operation result is +127 or -128
.3-.0
Not used for S3C9228/P9228
4-8
S3C9228/P9228
CONTROL REGISTERS
INTPND1 -- Interrupt Pending Register 1
Bit Identifier RESET Value Read/Write .7
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D6H
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
P1.3's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.6
P1.2's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.5
P1.1's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.4
P1.0's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.3
P0.3's Interrupt Pending Bit 0 No interrupt pending (when read), Clear pending bit (when write) 1 Interrupt is pending (when read)
.2
P0.2's Interrupt Pending Bit 0 No interrupt pending (when read), Clear pending bit (when write) 1 Interrupt is pending (when read)
.1
P0.1's Interrupt Pending Bit 0 No interrupt pending (when read), Clear pending bit (when write) 1 Interrupt is pending (when read)
.0
P0.0's Interrupt Pending Bit 0 No interrupt pending (when read), Clear pending bit (when write) 1 Interrupt is pending (when read)
NOTE: Refer to Page 5-6 to clear any pending bits.
4-9
CONTROL REGISTERS
S3C9228/P9228
INTPND2 -- Interrupt Pending Register 2
Bit Identifier RESET Value Read/Write .7-.6
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D7H
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 0 R/W
Not used for S3C9228/P9228 P3.1 (INTP) Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.5
.4
P3.0 (INTP) Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.3
Watch Timer Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read)
.2
SIO Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read)
.1
Timer B Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read)
.0
Timer 1/A Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read)
NOTE: Refer to Page 5-6 to clear any pending bits.
4-10
S3C9228/P9228
CONTROL REGISTERS
LMOD -- LCD Mode Control Register
Bit Identifier RESET Value Read/Write .7
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FEH
.5 0 .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 0 R/W
R/W
Not used for S3C9228/P9228 COM Pins High Impedance Control Bit 0 1 Normal COMs signal output COM pins are at high impedance
.6
.5
Port3 High Impedance Control Bit 0 1 Normal I/O High impedance input
.4
LCD Display Control Bit 0 1 Display off (cut off the LCD voltage dividing resistors) Normal display on
.3-.2
LCD Duty and Bias Selection Bits 0 0 1 1 0 1 0 1 1/3 duty, 1/3 bias; COM0-COM2/SEG0-SEG19 1/4 duty, 1/3 bias; COM0-COM3/SEG0-SEG19 1/8 duty, 1/4 bias; COM0-COM7/SEG0-SEG15 1/8 duty, 1/5 bias; COM0-COM7/SEG0-SEG15
.1-.0
LCD Clock Selection Bits 0 0 1 1 0 1 0 1 fw/27 (256 Hz when fw is 32.768 kHz) fw/26 (512 Hz when fw is 32.768 kHz) fw/25 (1,024 Hz when fw is 32.768 kHz) fw/24 (2,048 Hz when fw is 32.768 kHz)
4-11
CONTROL REGISTERS
S3C9228/P9228
LPOT -- LCD Port Control Register
Bit Identifier RESET Value Read/Write .7
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D8H
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 0 R/W
Not used for S3C9228/P9228 SEG4-SEG19 and COM0-COM3 Selection Bit SEG4-7 P4.0-P4.3 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 SEG Port Port Port Port Port SEG8-11 P4.4-P4.7 SEG SEG Port Port Port Port SEG12-15 P5.0-P5.3 SEG SEG SEG Port Port Port SEG16-19/ COM7-COM4 P5.4-P5.7 SEG/COM SEG/COM SEG/COM SEG/COM Port Port COM0-3 P6.0-P6.3 COM COM COM COM COM Port
.6-.4
.3
SEG3/P3.0 Selection Bit 0 1 SEG port Normal I/O port
.2
SEG2/P3.1 Selection Bit 0 1 SEG port Normal I/O port
.1
SEG1/P2.0 Selection Bit 0 1 SEG port Normal I/O port
.0
SEG0/P2.1 Selection Bit 0 1 SEG port Normal I/O port
NOTE: SEG16-SEG19 are shared with COM4-COM7.
4-12
S3C9228/P9228
CONTROL REGISTERS
OSCCON -- Oscillator Control Register
Bit Identifier RESET Value Read/Write .7-.4
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D3H
.4 - - .3 0 R/W .2 0 R/W .1 - - .0 0 R/W
.7 - -
.6 - -
.5 - -
Not used for S3C9228/P9228 Main Oscillator Control Bit 0 1 Main oscillator RUN Main oscillator STOP
.3
.2
Sub Oscillator Control Bit 0 1 Sub oscillator RUN Sub oscillator STOP
.1 .0
Not used for S3C9228/P9228 System Clock Selection Bit 0 1 Select main oscillator for system clock Select sub oscillator for system clock
4-13
CONTROL REGISTERS
S3C9228/P9228
P0CON - Port 0 Control Register
Bit Identifier RESET Value Read/Write .7-.6
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EBH
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
P0.3/BUZ/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (BUZ output)
.5-.4
P0.2/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Not available
.3-.2
P0.1/T1CLK/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (T1CLK input) Push-pull output N-channel open-drain output Not available
.1-.0
P0.0/TAOUT/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (TAOUT output)
4-14
S3C9228/P9228
CONTROL REGISTERS
P0INT -Port 0 Interrupt Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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EDH
.4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
Not used for S3C9228/P9228 P0.3's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.3
.2
P0.2's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.1
P0.1's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
P0.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
4-15
CONTROL REGISTERS
S3C9228/P9228
P0PUR -Port 0 Pull-up Resistors Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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ECH
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P0.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.3
.2
P0.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.1
P0.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.0
P0.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
4-16
S3C9228/P9228
CONTROL REGISTERS
P0EDGE -Port 0 Interrupt Edge Selection Register
Bit Identifier RESET Value Read/Write .7-.4
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EEH
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P0.3's Interrupt Edge Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.3
.2
P0.2's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.1
P0.1's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.0
P0.0's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
4-17
CONTROL REGISTERS
S3C9228/P9228
P1CON - Port 1 Control Register
Bit Identifier RESET Value Read/Write .7-.6
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EFH
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
P1.3/AD3/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode)
.5-.4
P1.2/AD2/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode)
.3-.2
P1.1/AD1/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode)
.1-.0
P1.0/AD0/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode)
4-18
S3C9228/P9228
CONTROL REGISTERS
P1INT -Port 1 Interrupt Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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F1H
.4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
Not used for S3C9228/P9228 P1.3's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.3
.2
P1.2's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.1
P1.1's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
P1.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
4-19
CONTROL REGISTERS
S3C9228/P9228
P1PUR -Port 1 Pull-up Resistors Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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F0H
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P1.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.3
.2
P1.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.1
P1.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.0
P1.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
4-20
S3C9228/P9228
CONTROL REGISTERS
P1EDGE -Port 1 Interrupt Edge Selection Register
Bit Identifier RESET Value Read/Write .7-.4
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F2H
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P1.3's Interrupt Edge Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.3
.2
P1.2's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.1
P1.1's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.0
P1.0's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
4-21
CONTROL REGISTERS
S3C9228/P9228
P2CON - Port 2 Control Register
Bit Identifier RESET Value Read/Write .7-.6
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F3H
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
P2.3 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Not available
.5-.4
P2.2/SI Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (SI) Push-pull output N-channel open-drain output Not available
.3-.2
P2.1/SO Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (SO out)
.1-.0
P2.0/SCK Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (SCK in) Push-pull output N-channel open-drain output Alternative function (SCK out)
4-22
S3C9228/P9228
CONTROL REGISTERS
P2PUR -Port 2 Pull-up Resistors Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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F4H
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P2.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.3
.2
P2.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.1
P2.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.0
P2.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
4-23
CONTROL REGISTERS
S3C9228/P9228
P3CON - Port 3 Control Register
Bit Identifier RESET Value Read/Write .7-.4
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F5H
.5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
Not used for S3C9228/P9228 P3.1/SEG2/INTP Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Not available
.3-.2
.1-.0
P3.0/SEG3/INTP Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Not available
4-24
S3C9228/P9228
CONTROL REGISTERS
P3INT -Port 3 Interrupt Enable Register
Bit Identifier RESET Value Read/Write .7-.2
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F7H
.4 - - .3 - - .2 - - .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
Not used for S3C9228/P9228 P3.1's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.1
.0
P3.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
4-25
CONTROL REGISTERS
S3C9228/P9228
P3PUR -Port 3 Pull-up Resistors Enable Register
Bit Identifier RESET Value Read/Write .7-.2
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F6H
.3 - - .2 - - .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P3.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.1
.0
P3.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
4-26
S3C9228/P9228
CONTROL REGISTERS
P3EDGE -Port 3 Interrupt Edge Selection Register
Bit Identifier RESET Value Read/Write .7-.4
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F8H
.3 - - .2 - - .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P3.1's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.1
.0
P3.0's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
4-27
CONTROL REGISTERS
S3C9228/P9228
P4CONH - Port 4 Control Register High Byte
Bit Identifier RESET Value Read/Write .7-.6
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F9H
.4 0 .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
R/W
P4.7/SEG11 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P4.6/SEG10 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P4.5/SEG9 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P4.4/SEG8 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
4-28
S3C9228/P9228
CONTROL REGISTERS
P4CONL-Port 4 Control Register Low Byte
Bit Identifier RESET Value Read/Write .7-.6
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FAH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
P4.3/SEG7 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P4.2/SEG6 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P4.1/SEG5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P4.0/SEG4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
4-29
CONTROL REGISTERS
S3C9228/P9228
P5CONH - Port 5 Control Register High Byte
Bit Identifier RESET Value Read/Write .7-.6
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FBH
.4 0 .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
R/W
P5.7/SEG19/COM4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P5.6/SEG18/COM5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P5.5/SEG17/COM6 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P5.4/SEG16/COM7 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
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S3C9228/P9228
CONTROL REGISTERS
P5CONL - Port 5 Control Register Low Byte
Bit Identifier RESET Value Read/Write .7-.6
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FCH
.4 0 .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
R/W
P5.3/SEG15 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P5.2/SEG14 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P5.1/SEG13 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P5.0/SEG12 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
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CONTROL REGISTERS
S3C9228/P9228
P6CON - Port 6 Control Register High Byte
Bit Identifier RESET Value Read/Write .7-.6
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FDH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
P6.3/COM0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P6.2/COM1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P6.1/COM2 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P6.0/COM3 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
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S3C9228/P9228
CONTROL REGISTERS
SIOCON -- SIO Control Register
Bit Identifier RESET Value Read/Write .7
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E1H
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 - -
.7 0 R/W
.6 0 R/W
SIO Shift Clock Selection Bit 0 1 Internal clock (P.S clock) External clock (SCK)
.6
Data Direction Control Bit 0 1 MSB-first mode LSB-first mode
.5
SIO Mode Selection Bit 0 1 Receive-only mode Transmit/receive mode
.4
Shift Clock Edge Selection Bit 0 1 Tx at falling edges, Rx at rising edges Tx at rising edges, Rx at falling edges
.3
SIO Counter Clear and Shift Start Bit 0 1 No action Clear 3-bit counter and start shifting
.2
SIO Shift Operation Enable Bit 0 1 Disable shifter and clock counter Enable shifter and clock counter
.1
SIO Interrupt Enable Bit 0 1 Disable SIO interrupt Enable SIO interrupt
.0
Not used for S3C9228/P9228
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CONTROL REGISTERS
S3C9228/P9228
STPCON - Stop Control Register
Bit Identifier RESET Value Read/Write .7
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E0H
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
Stop Control Bits 1 0 1 0 0 1 0 1 Enable Stop instruction Disable Stop instruction Other values
NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP instruction will not execute.
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S3C9228/P9228
CONTROL REGISTERS
SYM -- System Mode Register
Bit Identifier RESET Value Read/Write .7-.4
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DFH
.5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7
.6 - -
- -
Not used for S3C9228/P9228 Global Interrupt Enable Bit 0 1 Global interrupt processing disable (DI instruction) Global interrupt processing enable (EI instruction)
.3
.2-.0
Page Selection Bits 0 0 0 0 0 1 Page 0 Page 1 Not available
Other values
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CONTROL REGISTERS
S3C9228/P9228
TACON -- Timer 1/A Control Register
Bit Identifier RESET Value Read/Write .7
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BBH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 - -
.7 0 R/W
.6 0 R/W
.5 0 R/W
Timer 1 Mode Selection Bit 0 1 Two 8-bit timers mode (Timer A/B) One 16-bit timer mode (Timer 1)
.6-.4
Timer 1/A Clock Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/512 fxx/256 fxx/64 fxx/8 fxx (system clock) fxt (sub clock) T1CLK (external clock) Not available
.3
Timer 1/A Counter Clear Bit 0 1 No effect Clear the timer 1/A counter (when write)
.2
Timer 1/A Counter Enable Bit 0 1 Disable counting operation Enable counting operation
.1
Timer 1/A Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Bit 0 Not used for S3C9228/P9228
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S3C9228/P9228
CONTROL REGISTERS
TBCON -- Timer B Control Register
Bit Identifier RESET Value Read/Write .7
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BAH
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 - -
.7 - -
.6 0 R/W
Not used for S3C9228/P9228 Timer B Clock Selection Bits 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 fxx/512 fxx/256 fxx/64 fxx/8 fxx (system clock) fxt (sub clock)
.6-.4
.3
Timer B Counter Clear Bit 0 1 No effect Clear the timer B counter (when write)
.2
Timer B Counter Enable Bit 0 1 Disable counting operation Enable counting operation
.1
Timer B Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Not used for S3C9228/P9228
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CONTROL REGISTERS
S3C9228/P9228
WTCON -- Watch Timer Control Register
Bit Identifier RESET Value Read/Write .7
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DAH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 - -
.7 0 R/W
.6 0 R/W
.5 0 R/W
Watch Timer Clock Selection Bit 0 1 Select main clock divided by 27 (fx/128) Select sub clock (fxt)
.6
Watch Timer Interrupt Enable Bit 0 1 Disable watch timer interrupt Enable watch timer interrupt
.5-.4
Buzzer Signal Selection Bits 0 0 1 1 0 1 0 1 0.5 kHz 1 kHz 2 kHz 4 kHz
.3-.2
Watch Timer Speed Selection Bits 0 0 1 1 0 1 0 1 Set watch timer interrupt to 1s Set watch timer interrupt to 0.5s Set watch timer interrupt to 0.25s Set watch timer interrupt to 3.91ms
.1
Watch Timer Enable Bit 0 1 Disable watch timer; Clear frequency dividing circuits Enable watch timer
.0
Not used for S3C9228/P9228
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S3C9228/P9228
INTERRUPT STRUCTURE
5
OVERVIEW
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INTERRUPT STRUCTURE
The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H-0001H.
VECTOR
SOURCES S1
0000H 0001H
S2 S3 Sn
NOTES: 1. The SAM88RCRI interrupt has only one vector address (0000H-0001H). 2. The number of Sn value is expandable.
Figure 5-1. S3C9-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. The systemlevel control points in the interrupt structure are therefore: -- Global interrupt enable and disable (by EI and DI instructions) -- Interrupt source enable and disable settings in the corresponding peripheral control register(s) ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.3 is the enable and disable bit for global interrupt processing, which you can set by modifying SYM.3. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during normal operation, we recommend that you use the EI and DI instructions for this purpose.
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INTERRUPT STRUCTURE
S3C9228/P9228
INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine.
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"EI" Instruction Execution RESET Source Interrupts Source Interrupt Enable
S R
Q
Interrupt Pending Register
Interrpt priority is determind by software polling method Global Interrupt Control (EI, Di instruction)
Vector Interrupt Cycle
Figure 5-2. Interrupt Function Diagram
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S3C9228/P9228
INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source's pending flag is cleared to "0" by software. 4. Interrupt priority must be determined by software polling method.
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INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced, the following conditions must be met: -- Interrupt processing must be enabled (EI, SYM.3 = "1") -- Interrupt must be enabled at the interrupt's source (peripheral control register) If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0") to disable all subsequent interrupts. 2. Save the program counter and status flags to stack. 3. Branch to the interrupt vector to fetch the service routine's address. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.3 to "1"(EI), allowing the CPU to process the next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to stack. 2. Push the program counter's high-byte value to stack. 3. Push the FLAGS register values to stack. 4. Fetch the service routine's high-byte address from the vector address 0000H. 5. Fetch the service routine's low-byte address from the vector address 0001H. 6. Branch to the service routine specified by the 16-bit vector address.
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INTERRUPT STRUCTURE
S3C9228/P9228
S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: -- Timer 1/A interrupt -- Timer B interrupt -- SIO interrupt -- Watch Timer interrupt -- Four external interrupts for port 0
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interrupts for port 1
-- Two external interrupts for port 3
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S3C9228/P9228
INTERRUPT STRUCTURE
Vector
Enable/Disable P0INT.0
Pending INTPND1.0 INTPND1.1
Sources P0.0 External Interript P0.1 External Interript P0.2 External Interript P0.3 External Interript P1.0 External Interript P1.1 External Interript P1.2 External Interript P1.3 External Interrupt Timer 1/A Interrupt Timer B Interrupt SIO Interrupt Watch Timer Interrupt P3.0 Interrupt P3.1 Interrupt
P0INT.1 INTPND1.2 P0INT.2 INTPND1.3
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P0INT.3 INTPND1.4 P1INT.0 INTPND1.5 P1INT.1 INTPND1.6 P1INT.2 0000H 0001H SYM.3 (EI, DI) INTPND1.7 P1INT.3 INTPND2.0 TACON.1 INTPND2.1 TBCON.1 INTPND2.2 SIOCON.1 INTPND2.3 WTCON.1 INTPND2.4 P3INT.0 INTPND2.5 P3INT.1
Figure 5-3. S3C9228/P9228 Interrupt Structure
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INTERRUPT STRUCTURE
S3C9228/P9228
Programming Tip --
How to clear an interrupt pending bit
As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD
* * *
INTPND1, #11111011B
; Clear P0.2's interrupt pending bit
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IRET LD
* * *
2.
INTPND2, #11110111B
; Clear watch timer interrupt pending bit
IRET
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S3C9228/P9228
SAM88RCRI INSTRUCTION SET
6
OVERVIEW
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SAM88RCRI INSTRUCTION SET
The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces". ADDRESSING MODES There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and Immediate (IM). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes".
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SAM88RI INSTRUCTION SET
S3C9228/P9228
Table 6-1. Instruction Group Summary Mnemonic Operands Instruction
Load Instructions CLR LD LDC
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dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst src
Clear Load Load program memory Load external data memory Load program memory and decrement Load external data memory and decrement Load program memory and increment Load external data memory and increment Pop from stack Push to stack
LDCD LDED LDCI LDEI POP PUSH
Arithmetic Instructions ADC ADD CP DEC INC SBC SUB dst,src dst,src dst,src dst dst dst,src dst,src Add with carry Add Compare Decrement Increment Subtract with carry Subtract
Logic Instructions AND COM OR XOR dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR
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SAM88RCRI INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction
Program Control Instructions CALL IRET JP
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dst cc,dst dst cc,dst
Call procedure Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Return
JR RET
Bit Manipulation Instructions TCM TM dst,src dst,src Test complement under mask Test under mask
Rotate and Shift Instructions RL RLC RR RRC SRA dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic
CPU Control Instructions CCF DI EI IDLE NOP RCF SCF STOP Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set carry flag Enter Stop mode
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SAM88RI INSTRUCTION SET
S3C9228/P9228
FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 - FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result.
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System Flags Register (FLAGS) D5H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Carry flag (C) Zero flag (Z) Sign flag (S) Overflow flag (V)
Not mapped
Figure 6-1. System Flags Register (FLAGS) FLAG DESCRIPTIONS Overflow Flag (FLAGS.4, V) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than - 128. It is also cleared to "0" following logic operations. Sign Flag (FLAGS.5, S) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. Zero Flag (FLAGS.6, Z) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. Carry Flag (FLAGS.7, C) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.
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S3C9228/P9228
SAM88RCRI INSTRUCTION SET
INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag C Z S
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Description Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6-3. Instruction Set Symbols
V 0 1 * - x
Symbol dst src @ PC FLAGS # H D B opc Source operand
Description Destination operand Indirect register address prefix Program counter Flags register (D5H) Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode
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SAM88RI INSTRUCTION SET
S3C9228/P9228
Table 6-4. Instruction Notation Conventions Notation cc r rr R RR
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Description Condition code Working register only Working register pair Register or working register Register pair or working register pair Indirect working register only
Actual Operand Range See list of condition codes in Table 6-6. Rn (n = 0-15) RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0-255, n = 0-15) reg or RRp (reg = 0-254, even number only, where p = 0, 2, ..., 14) @Rn (n = 0-15)
Ir IR Irr IRR X XS xl da ra im
Indirect register or indirect working register @Rn or @reg (reg = 0-255, n = 0-15) Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode Indexed (long offset) addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode @RRp (p = 0, 2, ..., 14) @RRp or @reg (reg = 0-254, even only, where p = 0, 2, ..., 14) #reg[Rn] (reg = 0-255, n = 0-15) #addr[RRp] (addr = range -128 to +127, where p = 0, 2, ..., 14) #addr [RRp] (addr = range 0-8191, where p = 0, 2, ..., 14) addr (addr = range 0-8191) addr (addr = number in the range +127 to -128 that is an offset relative to the address of the next instruction) #data (data = 0-255)
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S3C9228/P9228
SAM88RCRI INSTRUCTION SET
Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) - U P
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0 DEC R1 RLC R1 INC R1 JP IRR1
1 DEC IR1 RLC IR1 INC IR1
2 ADD r1,r2 ADC r1,r2 SUB r1,r2 SBC r1,r2 OR r1,r2
3 ADD r1,Ir2 ADC r1,Ir2 SUB r1,Ir2 SBC r1,Ir2 OR r1,Ir2 AND r1,Ir2 TCM r1,Ir2 TM r1,Ir2
4 ADD R2,R1 ADC R2,R1 SUB R2,R1 SBC R2,R1 OR R2,R1 AND R2,R1 TCM R2,R1 TM R2,R1
5 ADD IR2,R1 ADC IR2,R1 SUB IR2,R1 SBC IR2,R1 OR IR2,R1 AND IR2,R1 TCM IR2,R1 TM IR2,R1
6 ADD R1,IM ADC R1,IM SUB R1,IM SBC R1,IM OR R1,IM AND R1,IM TCM R1,IM TM R1,IM
7
0 1 2 3 4 5
P E R
POP R1 COM R1 PUSH R2
POP IR1 COM IR1 PUSH IR2
AND r1,r2 TCM r1,r2 TM r1,r2
N I B B L E
6 7 8 9 A B C
LD r1, x, r2 RL R1 RL IR1 CP r1,r2 CLR R1 RRC R1 SRA R1 RR R1 CLR IR1 RRC IR1 SRA IR1 RR IR1 LDCD r1,Irr2 XOR r1,r2 CP r1,Ir2 XOR r1,Ir2 LDC r1,Irr2 LDC r2,Irr1 LDCI r1,Irr2 LD R2,R1 CALL IRR1 LD R2,IR1 LD IR2,R1 LD IR1,IM LD R1,IM CALL DA1 CP R2,R1 XOR R2,R1 CP IR2,R1 XOR IR2,R1 CP R1,IM XOR R1,IM LD r2, x, r1 LDC r1, Irr2, xL LDC r2, Irr2, xL LD r1, Ir2 LD Ir1, r2 LDC r1, Irr2, xs LDC r2, Irr1, xs
H E X
D E F
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SAM88RI INSTRUCTION SET
S3C9228/P9228
Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) - U P P E R N I B B L E H E X 0 1 2 3 4 5 6 7 8 9 A B C D E F LD r1,R2 LD r2,R1 JR cc,RA LD r1,IM JP cc,DA INC r1 IDLE STOP DI EI RET IRET RCF SCF CCF NOP 8 LD r1,R2 9 LD r2,R1 A B JR cc,RA C LD r1,IM D JP cc,DA E INC r1 F
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S3C9228/P9228
SAM88RCRI INSTRUCTION SET
CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes
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Binary 0000 1000 0111 0110 1110
(1)
Mnemonic F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Always true Carry No carry Zero Not zero Plus Minus Overflow
Description Always false - - C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0
Flags Set
1111 (1)
(1) (1)
1101 0101 0100 1100 0110 1110
(1) (1)
No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal
1001 0001 1010 0010 1111
(1)
(S XOR V) = 0 (S XOR V) = 1 (Z OR (S XOR V)) = 0 (Z OR (S XOR V)) = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1
0111 (1) 1011 0011
NOTES: 1. Indicate condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
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SAM88RI INSTRUCTION SET
S3C9228/P9228
INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Shorthand www..com notation of the instruction's operation -- Textual description of the instruction's effect -- Specific flag settings affected by the instruction -- Detailed description of the instruction's format, execution time, and addressing mode(s) -- Programming example(s) explaining how to use the instruction
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S3C9228/P9228
SAM88RCRI INSTRUCTION SET
ADC --
ADC Operation:
Add With Carry
dst,src dst dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 12 13 14 15 16 Addr Mode dst src r r R R R r lr R IR IM C: Z: S: V:
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Flags:
Format:
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H R1 = 14H, R2 = 03H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
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SAM88RI INSTRUCTION SET
S3C9228/P9228
ADD --
ADD Operation:
Add
dst,src dst dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
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Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if a carry from the low-order nibble occurred.
C: Z: S: V:
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 02 03 04 05 06 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.
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SAM88RCRI INSTRUCTION SET
AND --
AND Operation:
Logical AND
dst,src dst dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected.
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Flags:
C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 52 53 54 55 56 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
6-13
SAM88RI INSTRUCTION SET
S3C9228/P9228
CALL --
CALL Operation:
Call Procedure
dst SP @SP SP @SP PC SP - 1 PCL SP -1 PCH dst
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The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. No flags are affected.
Flags: Format:
Bytes opc opc dst dst 3 2
Cycles 14 12
Opcode (Hex) F6 F4
Addr Mode dst DA IRR
Examples:
Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H: CALL 1521H SP = 0B0H (Memory locations 00H = 1AH, 01H = 4AH, where 4AH is the address that follows the instruction.) SP = 0B0H (00H = 1AH, 01H = 49H)
CALL
@RR0
In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 01H (because the two-byte instruction format was used). The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed.
6-14
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
CCF --
CCF Operation:
Complement Carry Flag
C NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
Flags:
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C: Complemented. No other flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) EF
Example:
Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.
6-15
SAM88RI INSTRUCTION SET
S3C9228/P9228
CLR --
CLR Operation:
Clear
dst dst "0" The destination location is cleared to "0".
Flags: Format: www..com
No flags are affected.
Bytes opc dst 2
Cycles 4 4
Opcode (Hex) B0 B1
Addr Mode dst R IR
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H @01H Register 00H = 00H Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.
6-16
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
COM --
COM Operation:
Complement
dst dst NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa.
Flags:
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C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 60 61 Addr Mode dst R IR
Examples:
Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 R1 = 0F8H R1 = 07H, register 07H = 0EH
In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
6-17
SAM88RI INSTRUCTION SET
S3C9228/P9228
CP --
CP
Compare
dst,src dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.
Operation:
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Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) A2 A3 A4 A5 A6 Addr Mode dst src r r R R R r lr R IR IM
Examples:
1. Given: R1 = 02H and R2 = 03H: CP R1,R2 Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP JP INC LD R1,R2 UGE,SKIP R1 R3,R1
SKIP
In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3.
6-18
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
DEC --
DEC Operation:
Decrement
dst dst dst - 1 The contents of the destination operand are decremented by one.
Flags:
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Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is -128(80H) and result value is +127(7FH); cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 00 01 Addr Mode dst R IR
Examples:
Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 R1 = 02H Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.
6-19
SAM88RI INSTRUCTION SET
S3C9228/P9228
DI --
DI
Disable Interrupts
Operation:
SYM (2) 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
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No flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) 8F
Example:
Given: SYM = 04H: DI If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register and clears SYM.2 to "0", disabling interrupt processing.
6-20
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
EI --
EI
Enable Interrupts
Operation:
SYM (2) 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
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No flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) 9F
Example:
Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 04H, enabling all interrupts (SYM.2 is the enable bit for global interrupt processing).
6-21
SAM88RI INSTRUCTION SET
S3C9228/P9228
IDLE --
IDLE Operation:
Idle Operation
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.
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Flags:
No flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) 6F Addr Mode dst src - -
Example:
The instruction IDLE stops the CPU clock but not the system clock.
6-22
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
INC --
INC Operation:
Increment
dst dst dst + 1 The contents of the destination operand are incremented by one.
Flags:
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Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is -128(80H); cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes dst | opc 1 Cycles 4 Opcode (Hex) rE r = 0 to F opc dst 2 4 4 20 21 R IR Addr Mode dst r
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC INC INC R0 00H @R0 R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.
6-23
SAM88RI INSTRUCTION SET
S3C9228/P9228
IRET --
IRET Operation:
Interrupt Return
IRET FLAGS @SP SP SP + 1 PC @SP SP SP + 2 SYM(2) 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts.
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Flags: Format:
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
IRET (Normal) opc
Bytes 1
Cycles 6
Opcode (Hex) BF
6-24
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
JP --
JP JP
Jump
cc,dst dst (Conditional) (Unconditional)
Operation:
If cc is true, PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. No flags are affected.
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Flags: Format: (1)
Bytes
(2)
Cycles 8 (3)
Opcode (Hex) ccD cc = 0 to F
Addr Mode dst DA
cc | opc
dst
3
opc
dst
2
8
30
IRR
NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP JP C,LABEL_W @00H LABEL_W = 1000H, PC = 1000H PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
6-25
SAM88RI INSTRUCTION SET
S3C9228/P9228
JR --
JR
Jump Relative
cc,dst If cc is true, PC PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed (See list of condition codes).
Operation:
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The range of the relative address is +127, -128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: Format: Bytes
(1)
No flags are affected.
Cycles 6 (2)
Opcode (Hex) ccB cc = 0 to F
Addr Mode dst RA
cc | opc
dst
2
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.
6-26
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
LD --
LD
Load
dst,src dst src The contents of the source are loaded into the destination. The source's contents are unaffected.
Operation:
Flags: Format: www..com
No flags are affected.
Bytes dst | opc src 2
Cycles 4 4
Opcode (Hex) rC r8
Addr Mode dst src r r IM R
src | opc
dst
2
4
r9 r = 0 to F
R
r
opc
dst | src
2
4 4
C7 D7
r Ir
lr r
opc
src
dst
3
6 6
E4 E5
R R
R IR
opc
dst
src
3
6 6
E6 D6
R IR
IM IM
opc
src
dst
3
6
F5
IR
R
opc
dst | src
x
3
6
87
r
x [r]
opc
src | dst
x
3
6
97
x [r]
r
6-27
SAM88RI INSTRUCTION SET
S3C9228/P9228
LD --
LD
Load
(Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0,#LOOP[R1] #LOOP[R0],R1 R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 00H = 20H, register 01H = 20H Register 02H = 20H, register 00H = 01H Register 00H = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH
Examples:
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6-28
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
LDC/LDE --
LDC/LDE Operation: dst,src
Load Memory
dst src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data memory.
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Flags: Format:
No flags are affected.
Bytes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. opc opc opc opc opc opc opc opc opc opc
dst | src src | dst dst | src src | dst dst | src 2 2
Cycles
10 10 12 12 14
Opcode (Hex)
C3 D3 E7 F7 A7
Addr Mode dst src
r Irr r XS [rr] r Irr r XS [rr] r XL [rr]
XS XS XLL XLL DAL DAL DAL DAL XLH XLH DAH DAH DAH DAH
3 3 4
src | dst
4
14
B7
XL [rr]
r
dst | 0000
4
14
A7
r
DA
src | 0000
4
14
B7
DA
r
dst | 0001
4
14
A7
r
DA
src | 0001
4
14
B7
DA
r
NOTES: 1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0-1. 2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte. 3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
6-29
SAM88RI INSTRUCTION SET
S3C9228/P9228
LDC/LDE --
LDC/LDE Examples:
Load Memory
(Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC LDE LDC * R0,@RR2 R0,@RR2 @RR2,R0 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; R0 contents of program memory location 0104H R0 = 1AH, R2 = 01H, R3 = 04H R0 contents of external data memory location 0104H R0 = 2AH, R2 = 01H, R3 = 04H 11H (contents of R0) is loaded into program memory location 0104H (RR2), working registers R0, R2, R3 AE no change 11H (contents of R0) is loaded into external data memory location 0104H (RR2), working registers R0, R2, R3 AE no change R0 contents of program memory location 0061H (01H + RR4), R0 = AAH, R2 = 00H, R3 = 60H R0 contents of external data memory location 0061H (01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H 11H (contents of R0) is loaded into program memory location 0061H (01H + 0060H) 11H (contents of R0) is loaded into external data memory location 0061H (01H + 0060H) R0 contents of program memory location 1104H (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H R0 contents of external data memory location 1104H (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H R0 contents of program memory location 1104H, R0 = 88H R0 contents of external data memory location 1104H, R0 = 98H 11H (contents of R0) is loaded into program memory location 1105H, (1105H) 11H 11H (contents of R0) is loaded into external data memory location 1105H, (1105H) 11H
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LDE
@RR2,R0
LDC
R0,#01H[RR4]
LDE LDC (note) LDE LDC LDE LDC LDE LDC (note) LDE
R0,#01H[RR4] #01H[RR4],R0 #01H[RR4],R0 R0,#1000H[RR2] R0,#1000H[RR2] R0,1104H R0,1104H 1105H,R0 1105H,R0
NOTE: These instructions are not supported by masked ROM type devices.
6-30
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
LDCD/LDED --
LDCD/LDED Operation: dst,src dst src rr rr - 1
Load Memory and Decrement
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These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes `Irr' an even number for program memory and an odd number for data memory.
Flags: No flags are affected. Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E2 Addr Mode dst src r Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; ; ; ; ; ; 0CDH (contents of program memory location 1033H) is loaded into R8 and RR6 is decremented by one R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 - 1) 0DDH (contents of data memory location 1033H) is loaded into R8 and RR6 is decremented by one (RR6 RR6 - 1) R8 = 0DDH, R6 = 10H, R7 = 32H
LDED
R8,@RR6
6-31
SAM88RI INSTRUCTION SET
S3C9228/P9228
LDCI/LDEI --
LDCI/LDEI Operation: dst,src
Load Memory and Increment
dst src rr rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even for program memory and odd for data memory.
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Flags: Format:
No flags are affected.
Bytes opc dst | src 2
Cycles 10
Opcode (Hex) E3
Addr Mode dst src r Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; ; ; ; ; ; 0CDH (contents of program memory location 1033H) is loaded into R8 and RR6 is incremented by one (RR6 RR6 + 1) R8 = 0CDH, R6 = 10H, R7 = 34H 0DDH (contents of data memory location 1033H) is loaded into R8 and RR6 is incremented by one (RR6 RR6 + 1) R8 = 0DDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
6-32
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
NOP --
NOP Operation: Flags:
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No Operation
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. No flags are affected.
Format:
Bytes opc 1
Cycles 4
Opcode (Hex) FF
Example:
When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
6-33
SAM88RI INSTRUCTION SET
S3C9228/P9228
OR --
OR
Logical OR
dst,src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored.
Operation:
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Flags:
C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 42 43 44 45 46 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats.
6-34
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
POP --
POP Operation:
Pop From Stack
dst dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.
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Flags: No flags affected. Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) 50 51 Addr Mode dst R IR
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 0BCH Register 00H = 01H, register 01H = 55H, SP = 0BCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 0BBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.
6-35
SAM88RI INSTRUCTION SET
S3C9228/P9228
PUSH --
PUSH Operation:
Push To Stack
src SP SP - 1 @SP src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. No flags are affected.
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Flags: Format:
Bytes opc src 2
Cycles 8 8
Opcode (Hex) 70 71
Addr Mode dst R IR
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H: PUSH PUSH 40H @40H Register 40H = 4FH, stack register 0BFH = 4FH, SP = 0BFH Register 40H = 4FH, register 4FH = 0AAH, stack register 0BFH = 0AAH, SP = 0BFH
In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP points to location 0BFH.
6-36
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
RCF --
RCF Operation:
Reset Carry Flag
RCF C0 The carry flag is cleared to logic zero, regardless of its previous value.
Flags:
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C: Cleared to "0". No other flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) CF
Example:
Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
6-37
SAM88RI INSTRUCTION SET
S3C9228/P9228
RET --
RET Operation:
Return
PC @SP SP SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. No flags are affected.
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Flags: Format:
Bytes opc 1
Cycles 8
Opcode (Hex) AF
Example:
Given: SP = 0BCH, (SP) = 101AH, and PC = 1234: RET PC = 101AH, SP = 0BEH
The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 0BEH.
6-38
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
RL --
RL
Rotate Left
dst C dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
Operation:
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7 C
0
Flags:
Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 90 91 Addr Mode dst R IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.
6-39
SAM88RI INSTRUCTION SET
S3C9228/P9228
RLC --
RLC Operation:
Rotate Left Through Carry
dst dst (0) C C dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
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7 C
0
Flags:
C: Z: S: V:
Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 10 11 Addr Mode dst R IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
6-40
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
RR
RR
-- Rotate Right
dst C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Operation:
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7 C
0
Flags:
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) E0 E1 Addr Mode dst R IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
6-41
SAM88RI INSTRUCTION SET
S3C9228/P9228
RRC --
RRC Operation:
Rotate Right Through Carry
dst dst (7) C C dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB).
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7 C
0
Flags:
C: Z: S: V:
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) C0 C1 Addr Mode dst R IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".
6-42
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
SBC --
SBC Operation:
Subtract With Carry
dst,src dst dst - src - c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. C: Z: S: V: Set if a borrow occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign
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Flags:
f the result is the same as the sign of the source; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 32 33 34 35 36 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H,register 02H = 03H, register 03H = 0AH Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.
6-43
SAM88RI INSTRUCTION SET
S3C9228/P9228
SCF --
SCF Operation:
Set Carry Flag
C1 The carry flag (C) is set to logic one, regardless of its previous value.
Flags:
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C: Set to "1". No other flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) DF
Example:
The statement SCF sets the carry flag to logic one.
6-44
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
SRA --
SRA Operation:
Shift Right Arithmetic
dst dst (7) dst (7) C dst (0) dst (n) dst (n + 1), n = 0-6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6.
7 C 6 0
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Flags:
C: Z: S: V: D: H:
Set if the bit shifted from the LSB position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) D0 D1 Addr Mode dst R IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H Register 00H = 0CD, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H.
6-45
SAM88RI INSTRUCTION SET
S3C9228/P9228
STOP --
STOP Operation:
Stop Operation
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The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed.
Flags: No flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) 7F Addr Mode dst src - -
Example:
The statement STOP halts all microcontroller operations.
6-46
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
SUB --
SUB Operation:
Subtract
dst,src dst dst - src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
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Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow".
C: Z: S: V:
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 22 23 24 25 26 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB SUB SUB SUB SUB SUB R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H R1 = 0FH, R2 = 03H R1 = 08H, R2 = 03H Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H Register 01H = 91H; C, S, and V = "1" Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1.
6-47
SAM88RI INSTRUCTION SET
S3C9228/P9228
TCM --
TCM Operation:
Test Complement Under Mask
dst,src (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
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Flags:
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 62 63 64 65 66 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM TCM TCM TCM TCM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 R0 = 0C7H, R1 = 02H, Z = "1" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.
6-48
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
TM --
TM
Test Under Mask
dst,src dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.
Operation:
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Flags:
C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 72 73 74 75 76 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM TM TM TM TM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C7H, R1 = 02H, Z = "0" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "0" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.
6-49
SAM88RI INSTRUCTION SET
S3C9228/P9228
XOR -- Logical Exclusive OR
XOR Operation: dst,src dst dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored.
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C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) B2 B3 B4 B5 B6 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.
6-50
S3C9228/P9228
CLOCK CIRCUITS
7
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CLOCK CIRCUITS
OVERVIEW
The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency, is determined by CLKCON register settings.
SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: -- Crystal, ceramic resonator, RC oscillation source (main clock only), or an external clock -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) -- Clock circuit control register, CLKCON -- Oscillator control register, OSCCON CPU CLOCK NOTATION In this document, the following notation is used for descriptions of the CPU clock: fx main clock fxt sub clock fxx selected system clock
7-1
CLOCK CIRCUITS
S3C9228/P9228
MAIN OSCILLATOR CIRCUITS
SUB OSCILLATOR CIRCUITS
XIN
XTIN
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XOUT 32.768 kHz
XTOUT
Figure 7-1. Crystal/Ceramic Oscillator
Figure 7-4. Crystal/Ceramic Oscillator
XIN
XTIN
XOUT XTOUT
Figure 7-2. External Oscillator
Figure 7-5. External Oscillator
XIN R XOUT
Figure 7-3. RC Oscillator
7-2
S3C9228/P9228
CLOCK CIRCUITS
CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: -- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When the fx is selected as system clock). -- In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt structure, timer A/B, and watch timer. Idle mode is released by a reset or by an external or internal interrupts.
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Stop Release INT
Main-System Oscillator Circuit
fX
fXT
Sub-system Oscillator Circuit
Watch Timer LCD Controller
Selector 1 fXX Stop
OSCCON.3 OSCCON.0 STOP OSC inst. STPCON 1/1 1/8-1/4096 Frequency Dividing Circuit 1/2 1/8 1/16 Basic Timer Timer/Counters Watch Timer LCD Controller SIO A/D Converter Stop OSCCON.2
CLKCON.4-.3
Selector 2 CPU
Figure 7-6. System Clock Circuit Diagram
7-3
CLOCK CIRCUITS
S3C9228/P9228
SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following functions: -- Oscillator IRQ wake-up function enable/disable -- Oscillator frequency divide-by value CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release (This is called the "IRQ wake-up" function). The IRQ "wake-up" enable bit is CLKCON.7. www..com After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the fx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fx, fx/2, or fx/8 by setting the CLKCON, and you can change system clock from main clock to sub clock by setting the OSCCON.
System Clock Control Register (CLKCON) D4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Oscillator IRQ wake-up enable bit: 0 = Enable IRQ for main oscillator wake-up function in power down mode 1 = Disable IRQ for main oscillator wake-up function in power down mode
Not used for S3C92228 (must keep always "0") Divide-by selection bits for CPU clock frequency: 00 = fxx/16 01 = fxx/8 10 = fXx/2 11 = fxx
Not used for S3C9228 (must keep always "0")
Figure 7-7. System Clock Control Register (CLKCON)
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S3C9228/P9228
CLOCK CIRCUITS
OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions: -- System clock selection -- Main oscillator control -- Sub oscillator control
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OSCCON.0 register settings select Main clock or Sub clock as system clock. Main clock is selected for system clock because the reset value of OSCCON.0 is "0". The main oscillator can be stopped or run by setting OSCCON.3. The sub oscillator can be stopped or run by setting OSCCON.2.
Oscillator Control Register (OSCCON) D3H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
System clock selection bit: 0 = Main oscillator select 1 = Sub oscillator select Not used for S3C9228 Not used for S3C9228 Sub oscillator control bit: 0 = Sub oscillator RUN 1 = Sub oscillator STOP Main oscillator control bit: 0 = Main oscillator RUN 1 = Main oscillator STOP
Figure 7-8. Oscillator Control Register (OSCCON)
7-5
CLOCK CIRCUITS
S3C9228/P9228
SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the system clock. OSCCON .3 start or stop main clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4-.3 control the frequency divider circuit, and divide the selected fxx clock by 1, 2, 8, or 16.
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For example, you are using the default system clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set OSCCON.0 to "1", take a delay, and OSCCON.3 to "1" sequently. This switches the clock from fx to fxt and stops main clock oscillation. The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main clock by setting OSCCON.0 to "0".
+PROGRAMMING TIP -- Switching the CPU clock
1. This example shows how to change from the main clock to the sub clock: MA2SUB OR CALL OR RET OSCCON,#01H DLY16 OSCCON,#08H ; Switches to the sub clock ; Delay 16ms ; Stop the main clock oscillation
2. This example shows how to change from sub clock to main clock: SUB2MA AND CALL AND RET LD NOP DEC JR RET OSCCON,#0F7H DLY16 OSCCON,#0FEH R0,#20H R0 NZ,DEL ; Start the main clock oscillation ; Delay 16 ms ; Switch to the main clock
DLY16 DEL
7-6
S3C9228/P9228
CLOCK CIRCUITS
STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: -- Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B".
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Stop Control Register (STPCON) E0H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
STOP control bits: 10100101 = Enable STOP instruction Other values = Disable STOP instruction
Figure 7-9. STOP Control Register (STPCON)
+PROGRAMMING TIP -- How to Use Stop Instruction
This example shows how to go STOP mode when a main clock is selected as the system clock. LD STOP NOP NOP NOP LD STOPCON,#1010010B ; Enable STOP instruction ; Enter STOP mode
STOPCON,#00000000B
; Release STOP mode ; Disable STOP instruction
7-7
CLOCK CIRCUITS
S3C9228/P9228
NOTES
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7-8
S3C9228/P9228
RESET and POWER-DOWN
8
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RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C9228/P9228 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a reset operation is 1 millisecond. Whenever a reset occurs during normal operation (that is, when both VDD and RESET are High level), the RESET pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values (see Table 8-1). In summary, the following sequence of events occurs during a reset operation: -- All interrupts are disabled. -- The watchdog function (basic timer) is enabled. -- The P0.0-P0.3, P1, and P2.2-P2.3 are set to schmitt trigger input mode and all pull-up resistors are disabled for the I/O port pin circuits. -- Peripheral control and data registers are disabled and reset to their default hardware values. -- The program counter (PC) is loaded with the program reset address in the ROM, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed. NOTE To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON.
8-1
RESET and POWER-DOWN
S3C9228/P9228
POWER-DOWN MODES
STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But the watch timer and LCD controller will not halted in stop mode if the sub clock is selected as watch timer clock source. The data stored in the internal register file are retained in stop mode. Stop mode can be released in one of three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected as clock source of watch timer), or by an external interrupt.
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Example:
LD STOP NOP NOP NOP LD
STOPCON,#10100101B
STOPCON,#00000000B NOTES
1. Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage. 2. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. 3. To enable/disable STOP instruction, the STOPCON register should be written with 10100101B/other values before/after stop instruction. Using RESET to Release Stop Mode Stop mode is released when the RESET signal goes active (Low level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. When the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H. Using an External Interrupt to Release Stop Mode External interrupts can be used to release stop mode. For the S3C9228 microcontroller, we recommend using the INT interrupt, P0, P1, and P3.
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RESET and POWER-DOWN
Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release stop mode. That is, you had better use the idle instruction instead of stop one when sub clock is selected as the system clock. Please note the following conditions for Stop mode release: -- If you release stop mode using an internal or external interrupt, the current values in system and peripheral control registers are unchanged.
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-- If you use an internal or external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering stop mode. -- If you use an interrupt to release stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains unchanged and the currently selected clock value is used. -- The internal or external interrupt is serviced when the stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated stop mode is executed.
IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but the following peripherals, which remain active: -- Interrupt logic -- Basic timer -- Timer 1 (Timer A and B) -- Watch timer -- LCD controller I/O port pins retain the mode (input or output) they had at the time Idle mode was entered. Idle Mode Release You can release Idle mode in one of two ways: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the hardware reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the only way you can release Idle mode. 2. Activate any enabled interrupt -- internal or external. When you use an interrupt to release Idle mode, the 2-bit CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately following the one which initiated Idle mode is executed.
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RESET and POWER-DOWN
S3C9228/P9228
HARDWARE RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values: -- A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively. -- An 'x' means that the bit value is undefined following RESET.
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-- A dash ('-') means that the bit is either not used or not mapped.
Table 8-1. Register Values after RESET Register Name Mnemonic Address Dec Timer B Control Register Timer 1/A Control Register Timer B Data Register Timer A Data Register Timer B Counter Timer A Counter A/D Converter Control Register A/D Converter Data Register (high byte) A/D Converter Data Register (low byte) Oscillator Control Register System Clock Control Register System Flags Register Interrupt Pending Register 1 Interrupt Pending Register 2 LCD Port Control Register Stack Pointer Watch Timer Control Register Basic Timer Control Register Basic Timer Counter TBCON TACON TBDATA TADATA TBCNT TACNT ADCON ADDATAH ADDATAL OSCCON CLKCON FLAGS INTPND1 INTPND2 LOPT SP WTCON BTCON BTCNT 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 220 221 Hex BAH BBH BCH BDH BEH BFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DCH DDH 7 - 0 1 1 0 0 - X - - 0 X 0 - - X 0 0 0 6 0 0 1 1 0 0 - X - - 0 X 0 - 0 X 0 0 0 Bit Values after RESET 5 0 0 1 1 0 0 0 X - - 0 X 0 0 0 X 0 0 0 4 0 0 1 1 0 0 0 X - - 0 X 0 0 0 X 0 0 0 3 0 0 1 1 0 0 0 X - 0 0 - 0 0 0 X 0 0 0 2 0 0 1 1 0 0 0 X - 0 0 - 0 0 0 X 0 0 0 1 0 0 1 1 0 0 0 X X - 0 - 0 0 0 X 0 0 0 0 - - 1 1 0 0 0 X X 0 0 - 0 0 0 X - 0 0
Locations B8H-B9H are not mapped.
Locations DBH is not mapped.
Locations DEH is not mapped.
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RESET and POWER-DOWN
Table 8-1. Register Values after RESET (Continued) Register Name Mnemonic Address Dec System Mode Register STOP Control Register SIO Control Register SIO Data Register
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Bit Values after RESET 7 - 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 - - - 0 - - - - - 0 0 0 0 0 - 6 - 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 - - - 0 - - - - - 0 0 0 0 0 0 5 - 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 - - - 0 - - - - - 0 0 0 0 0 0 4 - 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 - - - 0 - - - - - 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Hex DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH
SYM STPCON SIOCON SIODATA SIOPS P0 P1 P2 P3 P4 P5 P6 P0CON P0PUR P0INT P0EDGE P1CON P1PUR P1INT P1EDGE P2CON P2PUR P3CON P3PUR P3INT P3EDGE P4CONH P4CONL P5CONH P5CONL P6CON LMOD
223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254
Register
Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 0 Control Register Port 0 Pull-up Resistors Enable Register Port 0 Interrupt Control Register Port 0 Interrupt Edge Selection Register Port 1 Control Register Port 1 Pull-up Resistors Enable Register Port 1 Interrupt Control Register Port 1 Interrupt Edge Selection Register Port 2 Control Register Port 2 Pull-up Resistors Enable Register Port 3 Control Register Port 3 Pull-up Resistors Enable Register Port 3 Interrupt Control Register Port 3 Interrupt Edge Selection Register Port 4 Control Register (High Byte) Port 4 Control Register (High Byte) Port 5 Control Register (High Byte) Port 5 Control Register (High Byte) Port 6 Control Register LCD Mode Register
Location FFH is not mapped.
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RESET and POWER-DOWN
S3C9228/P9228
NOTES
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I/O PORTS
9
OVERVIEW
Port 0
I/O PORTS
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microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the S3C9228/P9228 except P0.4 and P0.5 can be configured to input or output mode. All LCD signal pins are shared with normal I/O ports. Table 9-1 gives you a general overview of S3C9228 I/O port functions. Table 9-1. S3C9228 Port Configuration Overview Configuration Options 1-bit programmable I/O port except P0.4 and P0.5. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. The P0.4 and P0.5 are only push-pull output ports. Alternatively P0.0-P0.3 can be used as input for external interrupts INT and can be used as TAOUT, T1CLK, and BUZ. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P1 can be used as input for external interrupts INT and can be used as AD0-AD3. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P2.0 and P2.1 can be used as outputs for LCD segment signals and P2.0-P2.2 can be used as SCK, SO, and SI. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P3 can be used as input for external interrupts INTP and can be used as outputs for LCD segment signals. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P4 can be used as outputs for LCD segment signals. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P5.0-P5.3 can be used as outputs for LCD segment signals and P5.4-P5.7 can be used as outputs for LCD common or segment signals. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P6 can be used as outputs for LCD common signals.
1
2
3
4
5
6
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I/O PORTS
S3C9228/P9228
PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port 0 data register Port www..com 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Mnemonic P0 P1 P2 P3 P4 P5 P6 Decimal 228 229 230 231 232 233 234 Hex E4H E5H E6H E7H E8H E9H EAH R/W R/W R/W R/W R/W R/W R/W R/W
S3C9228 I/O Port Data Register Format (n = 0-6) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
Pn.1
Pn.0
Figure 9-1. S3C9228 I/O Port Data Register Format
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I/O PORTS
PORT 0 Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P0.0-P0.3): TAOUT,T1CLK, BUZ, INT -- High-nibble pins (P0.4-P0.5): push-pull output ports (only 44-QFP package) Port 0 Control register (P0CON)
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Port 0 has a 8-bit control register: P0CON for P0.0-P0.3. A reset clears the P0CON register to "00H", configuring pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 0 control register must also be enabled in the associated peripheral module. Port 0 Pull-up Resistor Control Register (P0PUR) Using the port 0 pull-up resistor control register, P0PUR (ECH, page 0), you can configure pull-up resistors to individual port 0 pins. Port 0 Interrupt Enable, Pending, and Edge Selection Registers (P0INT, INTPND1.3-.0, P0EDGE) To process external interrupts at the port 0 pins, three additional control registers are provided: the port 0 interrupt enable register P0INT (EDH, page 0), the port 0 interrupt pending bits INTPND1.3-.0 (D6H, page 0), and the port 0 interrupt edge selection register P0EDGE (EEH, page 0). The port 0 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND1.3-.0 register at regular intervals. When the interrupt enable bit of any port 0 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND1 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND1 bit.
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I/O PORTS
S3C9228/P9228
Port 0 Control Register (P0CON) EBH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P0.3/BUZ (INT)
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P0.2 (INT)
P0.1/T1CLK P0.0/TAOUT (INT) (INT)
P0CON bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (T1CLK) Push-pull output mode N-channel open-drain output mode Alternative function (TAOUT, BUZ)
Figure 9-2. Port 0 Control Register (P0CON)
Port 0 Interrupt Control Register (P0INT) EDH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT)
P0INT bit configuration settings: 0 1 Disable interrupt Enable interrupt
Figure 9-3. Port 0 Interrupt Control Register (P0INT)
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I/O PORTS
Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT)
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INTPND1 bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)
Port 0 Interrupt Edge Selection Register (P0EDGE) EEH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT)
P0EDGE bit configuration settings: 0 1 Falling edge detection Rising edge detection
Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)
Port 0 Pull-up Control Register (P0PUR) ECH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P0.3
P0.2
P0.1
P0.0
P0PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor
Figure 9-6. Port 0 Pull-up Control Register (P0PUR)
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I/O PORTS
S3C9228/P9228
PORT 1 Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0. P1.0-P1.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P1.0-P1.3): AD0-AD3, INT Port 1 Control Register (P1CON)
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Port 1 has a 8-bit control register: P1CON for P1.0-P1.3. A reset clears the P1CON register to "00H", configuring mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 1 control register must also be enabled in the associated peripheral module. Port 1 Pull-up Resistor Control Register (P1PUR) Using the port 1 pull-up resistor control register, P1PUR (F0H, page 0), you can configure pull-up resistors to individual port 1 pins. Port 1 Interrupt Enable, Pending, and Edge Selection Registers (P1INT, INTPND1.7-.4, P1EDGE) To process external interrupts at the port 1 pins, three additional control registers are provided: the port 1 interrupt enable register P1INT (F1H, page 0), the port 1 interrupt pending bits INTPND1.7-.4 (D6H, page 0), and the port 1 interrupt edge selection register P1EDGE (F2H, page 0). The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND1.7-.4 register at regular intervals. When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND1 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND1 bit.
Port 1 Control Register (P1CON) EFH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.3/AD3 (INT)
P1.2/AD2 (INT)
P1.1/AD1 (INT)
P1.0/AD0 (INT)
P1CON bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Alternative function (AD0,AD1, AD2, AD3)
Figure 9-7. Port 1 Control Register (P1CON)
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I/O PORTS
Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT)
P1INT bit configuration settings: 0 1 Disable interrupt Enable interrupt
Figure 9-8. Port 1 Interrupt Control Register (P1INT)
Port 1 Interrupt Pending Bits (INTPND1.7-.4) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND1 bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
Figure 9-9. Port 1 Interrupt Pending Bits (INTPND1.7-.4)
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S3C9228/P9228
Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT)
P1EDGE bit configuration settings: 0 1 Falling edge detection Rising edge detection
Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE)
Port 1 Pull-up Control Register (P1PUR) F0H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P1.3
P1.2
P1.1
P1.0
P1PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor
Figure 9-11. Port 1 Pull-up Control Register (P1PUR)
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I/O PORTS
PORT 2 Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0. P2.0-P2.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P2.0-P2.3): SCK, SO, SI, SEG0-SEG1 Port 2 Control Register (P2CON)
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Port 2 has a 8-bit control register: P2CON for P2.0-P2.3. A reset clears the P2CON register to "00H", configuring mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 2 control register must also be enabled in the associated peripheral module. Port 2 Pull-up Resistor Control Register (P2PUR) Using the port 2 pull-up resistor control register, P2PUR (F4H, page 0), you can configure pull-up resistors to individual port 2 pins.
Port 2 Control Register (P2CON) F3H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P2.3
P2.2/SI
P2.1/SO/SEG0 P2.0/SCK/SEG1
P2CON bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (SI,SCK) Push-pull output mode N-channel open-drain output mode Alternative function (SCK, SO)
Figure 9-12. Port 2 Control Register (P2CON)
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I/O PORTS
S3C9228/P9228
Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P2.3
P2.2
P2.1
P2.0
P2PUR bit configuration settings:
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0 1
Disable pull-up resistor Enable pull-up resistor
Figure 9-13. Port 2 Pull-up Control Register (P2PUR)
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S3C9228/P9228
I/O PORTS
PORT 3 Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0. P3.0-P3.1 can serve as inputs (with or without pullup, and high impedance input), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P3.0-P3.1): SEG2-SEG3, INTP Port 3 Control Register (P3CON)
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a 8-bit control register: P3CON for P3.0-P3.1. A reset clears the P3CON register to "00H", configuring pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain). Port 3 Pull-up Resistor Control Register (P3PUR) Using the port 3 pull-up resistor control register, P3PUR (F6H, page 0), you can configure pull-up resistors to individually port 3 pins. Port 3 Interrupt Enable, Pending, and Edge Selection Registers(P3INT, INTPND2.5-.4, P3EDGE) To process external interrupts at the port 3 pins, three additional control registers are provided: the port 3 interrupt enable register P3INT (F7H, page 0), the port 3 interrupt pending bits INTPND2.5-.4 (D7H, page 0), and the port 3 interrupt edge selection register P3EDGE (F8H, page 0). The port 3 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND2.5-.4 register at regular intervals. When the interrupt enable bit of any port 3 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND2 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND2 bit.
Port 3 Control Register (P3CON) F5H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P3.1/SEG2 (INTP)
P3.0/SEG3 (INTP)
P3CON bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Not available
Figure 9-14. Port 3 Control Register (P3CON)
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I/O PORTS
S3C9228/P9228
Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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P3.1 P3.0 (INTP) (INTP)
P3INT bit configuration settings: 0 1 Disable interrupt Enable interrupt
Figure 9-15. Port 3 Interrupt Control Register (P3INT)
Port 3 Interrupt Pending Bits (INTPND2.5-.4) D7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P3.0 (INTP)
SIO
Timer 1/A Timer B
P3.0 (INTP) Watch Timer INTPND2 bit configuration settings: 0 1
No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
Figure 9-16. Port 3 Interrupt Pending Bits (INTPND2.5-.4)
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I/O PORTS
Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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P3.1 P3.0 (INTP) (INTP)
P3EDGE bit configuration settings: 0 1 Falling edge detection Rising edge detection
Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE)
Port 3 Pull-up Control Register (P3PUR) F6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used P3PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor
P3.1
P3.0
Figure 9-18. Port 3 Pull-up Control Register (P3PUR)
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S3C9228/P9228
PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: -- Low-nibble pins (P4.0-P4.3): SEG4-SEG7 -- High-nibble pins (P4.4-P4.7): SEG8-SEG11 Port 4 Control Registers (P4CONH, P4CONL)
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Port 4 has two 8-bit control registers: P4CONH for P4.4-P4.7 and P4CONL for P4.0-P4.3. A reset clears the P4CONH and P4CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode.
Port 4 Control Register, High Byte (P4CONH) F9H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P4.7/SEG11 P4.6/SEG10 P4.5/SEG9
P4.4/SEG8
P4CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-19. Port 4 High-Byte Control Register (P4CONH)
Port 4 Control Register, Low Byte (P4CONL) FAH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P4.3/SEG7
P4.2/SEG6
P4.1/SEG5
P4.0/SEG4
P4CONL bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-20. Port 4 Low-Byte Control Register (P4CONL)
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S3C9228/P9228
I/O PORTS
PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: -- Low-nibble pins (P5.0-P5.3): SEG12-SEG15 -- High-nibble pins (P5.4-P5.7): SEG16-SEG19, COM4-COM7 Port 5 Control Registers (P5CONH, P5CONL)
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Port 5 has two 8-bit control registers: P5CONH for P5.4-P5.7 and P4CONL for P5.0-P5.3. A reset clears the P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode.
Port 5 Control Register, High Byte (P5CONH) FBH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P5.6/SEG18/COM5 P5.7/SEG19/COM4
P5.4/SEG16/COM7
P5.5/SEG17/COM6
P5CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-21. Port 5 High-Byte Control Register (P5CONH)
Port 5 Control Register, Low Byte (P5CONL) FCH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P5.3/SEG15 P5.2/SEG14 P5.1/SEG13 P5.0/SEG12 P5CONL bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-22. Port 5 Low-Byte Control Register (P5CONL)
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I/O PORTS
S3C9228/P9228
PORT 6 Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: -- Low-nibble pins (P6.0-P6.3): COM0-COM3 Port 6 Control Register (P6CON)
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Port 6 has a 8-bit control register: P6CONH for P6.0-P6.3. A reset clears the P6CON registers to "00H", all pins to input mode. You use control registers setting to select input or output mode.
Port 6 Control Register, Low Byte (P6CON) FDH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P6.3/COM0 P6.2/COM1 P6.1/COM2
P6.0/COM3
P6CON bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-23. Port 6 Control Register (P6CON)
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S3C9228/P9228 (Preliminary Spec)
BASIC TIMER
10
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BASIC TIMER
OVERVIEW
Basic timer (BT) can be used in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer
-- 8-bit basic timer counter, BTCNT (DDH, read-only) -- Basic timer control register, BTCON (DCH, read/write)
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BASIC TIMER
S3C9228/P9228 (Preliminary Spec)
BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addressable using Register addressing mode. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register control bits BTCON.7-BTCON.4.
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The 8-bit basic timer counter, BTCNT (page 0, DDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for the basic timer input clock and timer counters, you write a "1" to BTCON.0.
Basic TImer Control Register (BTCON) DCH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Watchdog function enable bits: 1010B = Disable watchdog timer Other Value = Enable watchdog timer
Divider clear bit for basic timer and timer counters: 0 = No effect 1 = Clear divider Basic timer counter clear bit: 0 = No effect 1 = Clear BTCNT
Basic timer input clock selection bits: 00 = fXX/4096 01 = fXX/1024 10 = fXX/128 11 = fXX/16
Figure 10-1. Basic Timer Control Register (BTCON)
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S3C9228/P9228 (Preliminary Spec)
BASIC TIMER
BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock. A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must www..com be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when stop mode is released: 1. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. 4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.
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BASIC TIMER
S3C9228/P9228 (Preliminary Spec)
RESET or STOP Bit 1 Bits 3, 2 Data Bus fXX/4096
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Basic Timer Control Register (Write '1010xxxxB' to Disable) Clear 8-Bit Up Counter (BTCNT, Read-Only) Start the CPU (note)
fXX/1024 DIV fXX/128 fXX/16 R MUX OVF RESET
fXX
Bit 0
NOTE:
During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
Figure 10-2. Basic Timer Block Diagram
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S3C9228/P9228
TIMER 1
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TIMER 1
ONE 16-BIT TIMER MODE (TIMER 1)
The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers. -- One 16-bit timer mode (Timer 1) -- Two 8-bit timers mode (Timer A and B) OVERVIEW The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate TACON setting. Timer 1 has the following functional components: -- Clock frequency divider (fxx divided by 512, 256, 64, 8, or 1, fxt, and T1CLK: External clock) with multiplexer -- 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA) -- Timer 1 match interrupt generation -- Timer 1 control register, TACON (page 0, BBH, read/write) FUNCTION DESCRIPTION Interval Timer Function The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT). The T1INT pending condition should be cleared by software when it has been serviced. Even though T1INT is disabled, the application's service routine can detect a pending condition of T1INT by the software and execute it's sub-routine. When this case is used, the T1INT pending bit must be cleared by the application sub-routine by writing a "0" to the INTPND2.0 pending bit. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer 1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt and clears the counter. If, for example, you write the value 32H and 10H to TADATA and TBDATA, respectively, and 8EH to TACON, the counter will increment until it reaches 3210H. At this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes.
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TIMER 1
S3C9228/P9228
Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to -- Enable the timer 1 operating (interval timer) -- Select the timer 1 input clock frequency -- Clear the timer 1 counter, TACNT and TBCNT -- Enable the timer 1 interrupt
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TACON is located in page 0, at address BBH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during normal operation by writing a "1" to TACON.3. To enable the timer 1 interrupt, you must write TACON.7, TACON.2, and TACON.1 to "1". To generate the exact time interval, you should write TACON.3 and INTPND2.0, which cleared counter and interrupt pending bit. To detect an interrupt pending condition when T1INT is disabled, the application program polls pending bit, INTPND.2.0. When a "1" is detected, a timer 1 interrupt is pending. When the T1INT subroutine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, INTPND2.0.
Timer A Control Register (TACON) BBH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
One 16-bit timer or Two 8-bit timers mode: 0 = Two 8-bit timers mode (Timer A/B) 1 = One 16-bit timer mode (Timer 1)
Not used Timer 1/A interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt
Timer 1/A clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = T1CLK (external clock) 111 = Not available
Timer 1/A counter enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer 1/A counter clear bit: 0 = No affect 1 = Clear the timer 1/A counter (when write)
Figure 11-1. Timer 1 Control Register (TACON)
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S3C9228/P9228
TIMER 1
BTCON.0
TACON.6-.4
R
1/512 1/256 TACON.2 Data Bus M U X 16-Bit Comparator LSB MSB TBDATA TADATA Buffer Buffer LSB TBCNT TACON.3 MSB TACNT R Match INTPND2.0 TAOUT T1INT Clear TACON.1
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(XIN or XTIN)
DIV
1/64 1/8 1/1
fxt T1CLK
Match Signal Counter clear signal TBDATA TADATA Data Bus
NOTE:
When one 16-bit timer mode (TACON.7 <- "1": Timer 1)
Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)
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TIMER 1
S3C9228/P9228
TWO 8-BIT TIMERS MODE (TIMER A and B)
OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively. Timer A and B have the following functional components: -- Clock frequency divider with multiplexer - fxx www..comdivided by 512, 256, 64, 8 or 1, fxt, and T1CLK (External clock) for timer A - fxx divided by 512, 256, 64, 8 or 1, and fxt for timer B -- 8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA) -- Timer A have I/O pin for match output (TAOUT) -- Timer A match interrupt generation -- Timer A control register, TACON (page 0, BBH, read/write) -- Timer B match interrupt generation -- Timer B control register, TBCON (page 0, BAH, read/write) Timer A and B Control Register (TACON, TBCON) You use the timer A and B control register, TACON and TBCON, to -- Enable the timer A (interval timer mode) and B operating (interval timer mode) -- Select the timer A and B input clock frequency -- Clear the timer A and B counter, TACNT and TBCNT -- Enable the timer A and B interrupt
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S3C9228/P9228
TIMER 1
TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer B counter at any time during normal operation by writing a "1" to TBCON.3.
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To enable the timer A interrupt (TAINT) and timer B interrupt (TBINT), you must write TACON.7 to "0", TACON.2 (TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should write TACON.3 (TBCON.3) and INTPND2.0 (INTPND2.1), which cleared counter and interrupt pending bit. To detect an interrupt pending condition when TAINT and TBINT is disabled, the application program polls pending bit, INTPND2.0 and INTPND2.1. When a "1" is detected, a timer A interrupt (TAINT) and timer B interrupt (TBINT) is pending. When the TAINT and TBINT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer A and B interrupt pending bit, INTPND2.0 and INTPND2.1.
Timer A Control Register (TACON) E4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
One 16-bit timer or Two 8-bit timers mode: 0 = Two 8-bit timers mode (Timer A/B) 1 = One 16-bit timer mode (Timer 1) Timer A clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = T1CLK (external clock) 111 = Not available
Not used Timer A interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer A counter enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer A counter clear bit: 0 = No affect 1 = Clear the timer A counter (when write)
Figure 11-3. Timer A Control Register (TACON)
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TIMER 1
S3C9228/P9228
Timer B Control Register (TBCON) BAH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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Not used
Timer B match interrupt enable bit: Timer B clock selection bits: 0 = Disable match interrupt 000 = fxx/512 1 = Enable match interrupt 001 = fxx/256 010 = fxx/64 011 = fxx/8 Timer B count enable bit: 100 = fxx (system clock) 0 = Disable counting operating 101 = fxt (sub clock) 1 = Enable counting operating 110 = Not available 111 = Not available Timer B counter clear bit: 0 = No effect 1 = Clear the timer B counter (when write)
Figure 11-4. Timer B Control Register (TBCON)
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S3C9228/P9228
TIMER 1
FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.0) and the timer B match interrupt pending condition (INTPND2.1) must be cleared by software in the application's interrupt service by means of writing a "0" to the INTPND2.0 and INTPND2.1 interrupt pending bit. Even though www..com TAINT and TBINT are disabled, the application's service routine can detect a pending condition of TAINT and TBINT by the software and execute it's sub-routine. When this case is used, the TAINT and TBINT pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit INTPND2.0 and INTPND2.1. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer A or timer B reference data registers, TADATA or TBDATA. The match signal generates corresponding match interrupt and clears the counter. If, for example, you write the value 20H to TADATA and 0EH to TACON, the counter will increment until it reaches 20H. At this point, the timer A interrupt request is generated, the counter value is cleared, and counting resumes and you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will increment until it reaches 10H. At this point, TB interrupt request is generated, the counter value is cleared and counting resumes.
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TIMER 1
S3C9228/P9228
BTCON.0
TACON.6-.4
R
1/512 1/256 TACON.2 Data Bus M U X 8-Bit Comparator LSB MSB LSB TACON.3 MSB Clear TACON.1 Match INTPND2.0 TAOUT TAINT
fxx
(XIN or XTIN)
DIV
1/64 1/8 1/1
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TACNT (8-Bit Up-Counter) R
fxt T1CLK/ P0.1
TADATA Buffer
Match Signal Counter Clear Signal TADATA Register Data Bus
NOTE:
When two 8-bit timers mode (TACON.7 <- "0": Timer A)
Figure 11-5. Timer A Block Diagram(Two 8-bit Timers Mode)
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S3C9228/P9228
TIMER 1
BTCON.0
TBCON.6-.4
R
1/512 1/256 Data Bus M U X 1/1 TBCON.2 LSB MSB TBCNT (8-Bit Up-Counter) R Clear TBCON.1 Match 8-Bit Comparator LSB MSB INTPND2.1 TBINT TBCON.3
(XIN or XTIN) fxx www..com
DIV
1/64 1/8
fxt
TBDATA Buffer
Match Signal Counter Clear Signal TBDATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B)
Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)
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TIMER 1
S3C9228/P9228
NOTES
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S3C9228/P9228
WATCH TIMER
12
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WATCH TIMER
OVERVIEW
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt, then set the WTCON.6 to "1". The watch timer overflow interrupt pending condition (INTPND2.3) must be cleared by software in the application's interrupt service routine by means of writing a "0" to the INTPND2.3 interrupt pending bit. After the watch timer starts and elapses a time, the watch timer interrupt pending bit (INTPND2.3) is automatically set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting Watch timer speed selection bits (WTCON.3 - .2). The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences. Also, you can select watch timer clock source by setting the WTCON.7 appropriately value. The watch timer supplies the clock frequency for the LCD controller (fLCD ). Therefore, if the watch timer is disabled, the LCD controller does not operate. Watch timer has the following functional components: -- Real Time and Watch-Time Measurement -- Using a Main or Sub Clock Source (Main clock divided by 27(fx/128) or Sub clock(fxt)) -- Clock Source Generation for LCD Controller (fLCD ) -- I/O pin for Buzzer Output Frequency Generator (P0.3, BUZ) -- Timing Tests in High-Speed Mode -- Watch timer overflow interrupt generation -- Watch timer control register, WTCON (page 0, DAH, read/write)
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WATCH TIMER
S3C9228/P9228
WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode. A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock. So, if you want to use the watch timer, you must write appropriate value to WTCON.
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Watch Timer Control Register (WTCON) DAH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Watch timer clock selection bit: 0 = Main clock divided by 27(fx/128) 1 = Sub clock (fxt) Watch timer INT Enable/Disable bit: 0 = Disable watch timer INT 1 = Enable watch timer INT
Not used
Watch timer Enable/Disable bit: 0 = Disable watch timer; clear frequency dividing circuits 1 = Enable watch timer Watch timer speed selection bits: 00 = Set watch timer interrupt to 1 s 01 = Set watch timer interrupt to 0.5 s 10 = Set watch timer interrupt to 0.25 s 11 = Set watch timer interrupt to 3.91 ms
Buzzer signal selection bits: 00 = 0.5 kHz 01 = 1 kHz 10 = 2 kHz 11 = 4 kHz
Figure 12-1. Watch Timer Control Register (WTCON)
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S3C9228/P9228
WATCH TIMER
WATCH TIMER CIRCUIT DIAGRAM
WTCON.7 WTCON.6 WTCON.5
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WT INT Enable WTCON.6 MUX fW/64 (0.5 kHz) fW/32 (1 kHz) fW/16 (2 kHz) fW/8 (4 kHz) Enable/Disable Selector Circuit
BUZ (P0.3)
8
WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0
WTINT
INTPND2.3
Clock Selector
fW 32.768 kHz
Frequency Dividing Circuit
fW/27 fW/213 fW/214 fW/215 (1 Hz) fLCD = 2048 Hz
fxt
fx/128 fX = Main clock (where fx = 4.19 MHz) fxt = Sub clock (32,768 Hz) fW = Watch timer frequency
Figure 12-2. Watch Timer Circuit Diagram
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WATCH TIMER
S3C9228/P9228
NOTES
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S3C9228/P9228
LCD CONTROLLER/DRIVER
13
OVERVIEW
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LCD CONTROLLER/DRIVER
The S3C9228/P9228 microcontroller can directly drive an up-to-128-dot (16segments x 8 commons) LCD panel. Its LCD block has the following components: -- LCD controller/driver -- Display RAM for storing display data -- 16 segment output pins (SEG0-SEG15) -- 8 common output pins (COM0-COM7) -- Internal resistor circuit for LCD bias To use the LCD controller, bit 2 in the watch mode register WMOD must be set to 1 because LCDCK is supplied by the watch timer. The LCD mode control register, LMOD, is used to turn the LCD display on or off, to select LCD clock frequency, to turn the COM signal output on or off, to select bias and duty, and to switch the port 3 high impedance or normal I/O port. Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control. The LCD port control register, LPOT, is used to determine the LCD signal pins used for display output. When a sub clock is selected as the LCD clock source, the LCD display is enabled even during main clock stop and idle modes.
COM0-COM3 4 LCD Controller/ Driver COM4/SEG19COM7/SEG16 SEG0/P2.1SEG15/P5.3 Data BUS
8
4
16
Figure 13-1. LCD Function Diagram
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LCD CONTROLLER/DRIVER
S3C9228/P9228
LCD CIRCUIT DIAGRAM
Port Latch
16
SEG15/P5.3
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Display RAM (Page1)
SEG Control 160 MUX 4 16 or Selector SEG0/P2.1
Data BUS
LPOT
fLCD COM Control or selector
COM7/SEG16/P5.4
Timing Controller
COM4/SEG19/P5.7
Port Latch
8
COM Control
COM3/P6.0 COM0/P6.3
LMOD
LCD Voltage Control P3.1/INTP/SEG2 P3.0/INTP/SEG3
Port Latch
2
Port 3 Control
Figure 13-2. LCD Circuit Diagram
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S3C9228/P9228
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0-SEG19 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use.
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SEG0 SEG1 SEG2 SEG3
SEG17 SEG18 SEG19
COM0 b0 COM1 b1 COM2 b2 COM3 b3 100H 101H 102H 103H COM4 b4 COM5 b5 COM6 b6 COM7 b7 111H 112H 113H
Figure 13-3. LCD Display Data RAM Organization
Table 13-1. Common and Segment Pins per Duty Cycle Duty 1/8 1/4 1/3 Common Pins COM0-COM7 COM0-COM3 COM0-COM2 Segment Pins 16 pins 20 pins 20 pins Dot Number 128 dots 80 dots 60 dots
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LCD CONTROLLER/DRIVER
S3C9228/P9228
LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode. It has the following control functions. -- LCD duty and bias selection -- LCD clock selection -- LCD display control -- COMs signal output control
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impedance control
The LMOD register is used to turn the LCD display on/off, to select duty and bias, to select LCD clock, to control port 3 high impedance/normal I/O port, and to turn the COM signal output on/off. Following a RESET, all LMOD values are cleared to "0". This turns off the LCD display, select 1/3 duty and 1/3 bias, and select 256Hz for LCD clock. The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch timer should be enabled when the LCD display is turned on.
LCD Mode Control Register (LMOD) FEH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used COM pins high impedance control bit: 0 = Normal COMs signal output 1 = High impendane COM pins Port 3 high impendance control bit 0 = Normal I/O 1 = High impendane input
LCD clock selection bits: 00 = fw/27 (256 Hz when fw is 32.768 kHz) 01 = fw/26 (512 Hz when fw is 32.768 kHz) 10 = fw/25 (1024 Hz when fw is 32.768 kHz) 11 = fw/24 (2048 Hz when fw is 32.768 kHz) LCD duty and bias selection bits: 00 = 1/3 duty, 1/3 bias (COM0-COM2, SEG0-SEG19) 01 = 1/4 duty, 1/3 bias (COM0-COM3, SEG0-SEG19) 10 = 1/8 duty, 1/4 bias (COM0-COM7, SEG0-SEG15) 11 = 1/8 duty, 1/5 bias (COM0-COM7, SEG0-SEG15)
LCD display control bit 0 = Display off 1 = Normal display on
Figure 13-4. LCD Mode Control Register (LMOD)
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S3C9228/P9228
LCD CONTROLLER/DRIVER
LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET, a LPOT values are cleared to "0".
LCD Port Control Register D8H, R/W
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MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
SEG4-SEG19 and COM0-COM3 selection bits: SEG1/P2.0 selection bit: 000 = P4.0-P6.3: LCD signal pins 0 = SEG port 001 = P4.0-P4.3: Normal I/O, P4.4-P6.3: LCD signal pins 1 = Normal I/O port 010 = P4.0-P4.7: Normal I/O, P5.0-P6.3: LCD signal pins 011 = P4.0-P5.3: Normal I/O, P5.4-P6.3: LCD signal pins SEG2/P3.1 selection bit: 100 = P4.0-P5.7: Normal I/O, P6.0-P6.3: LCD signal pins 0 = SEG port 101 = P4.0-P6.3: Normal I/O 1 = Normal I/O port 110 = Not available 111 = Not available SEG3/P3.0 selection bit: 0 = SEG port 1 = Normal I/O port
SEG0/P2.1 selection bit: 0 = SEG port 1 = Normal I/O port
Figure 13-5. LCD Port Control Register
13-5
LCD CONTROLLER/DRIVER
S3C9228/P9228
LCD VOLTAGE DIVIDING RESISTORS
1/5 Bias
1/4 Bias
1/3 Bias
S3C9228/P9228
S3C9228/P9228
S3C9228/P9228
VDD
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VDD LMOD.4 LMOD.4 VLC1 VLC1 R R R R R VLC2 VLC3 VLC4 VLC5 VSS
VDD
LMOD.4 VLC1 VLC2 VLC3 VLC4 VLC5 VSS R R R R R
VLC2 VLC3 VLC4 VLC5 VSS
R R R R R
Figure 13-6. Internal Voltage Dividing Resistor Connection COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. -- In 1/3 duty mode, COM0-COM2 pins are selected -- In 1/4 duty mode, COM0-COM3 pins are selected -- In 1/8 duty mode, COM0-COM7 pins are selected SEGMENT (SEG) SIGNALS The 19 LCD segment signal pins are connected to corresponding display RAM locations at page 1. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal to the corresponding segment pin.
13-6
S3C9228/P9228
LCD CONTROLLER/DRIVER
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
0123456701234567
FR 1 Frame
VDD VSS
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COM0
VDD VLC1 VLC2 (VLC3) VLC4 VSS
COM1
VDD VLC1 VLC2 (VLC3) VLC4 VSS
COM2
VDD VLC1 VLC2 (VLC3) VLC4 VSS
SEG0
VDD VLC1 VLC2 (VLC3) VLC4 VSS
+ VDD
SEG0-COM0
+ 1/4VLCD 0V - 1/4VLCD
-VLCD
Figure 13-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
13-7
LCD CONTROLLER/DRIVER
S3C9228/P9228
SEG0 SEG1 COM0 COM1 COM2
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3
0
1
2
0
1
2
3
VDD VSS
1 Frame VDD VLC1(VLC2) VLC3(VLC4) VSS
COM0
VDD COM1 VLC1(VLC2) VLC3(VLC4) VSS
COM2
VDD VLC1(VLC2) VLC3(VLC4) VSS
COM3
VDD VLC1(VLC2) VLC3(VLC4) VSS
SEG0
VDD VLC1(VLC2) VLC3(VLC4) VSS
SEG1
VDD VLC1(VLC2) VLC3(VLC4) VSS
+ VLCD + 1/3 VLCD 0V - 1/3 VLCD - VLCD
COM0-SEG0
Figure 13-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
13-8
S3C9228/P9228
LCD CONTROLLER/DRIVER
SEG2
SEG1
SEG0
0 1 1
2
0
2
COM0 1 Frame
VDD VSS
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COM1 COM0 COM2
VDD VLC1(VLC2) VLC3(VLC4) VSS
COM1
VDD VLC1(VLC2) VLC3(VLC4) VSS
COM2
VDD VLC1(VLC2) VLC3(VLC4) VSS
SEG0
VDD VLC1(VLC2) VLC3(VLC4) VSS
SEG1
VDD VLC1(VLC2) VLC3(VLC4) VSS
+ VLCD + 1/3 VLCD 0V - 1/3 VLCD - VLCD
COM0-SEG0
Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
13-9
LCD CONTROLLER/DRIVER
S3C9228/P9228
NOTES
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13-10
S3C9228/P9228
A/D CONVERTER
14
OVERVIEW
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10-BIT ANALOG-TO-DIGITAL CONVERTER
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register (ADCON) -- Four multiplexed analog data input pins (AD0-AD3) -- 10-bit A/D conversion data output register (ADDATAH/ADDATAL) -- 4-bit digital input port (Alternately, I/O port)
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at first you must set with alternative function for ADC input enable at port 1, the pin set with alternative function can be used for ADC analog input. And you write the channel selection data in the A/D converter control register ADCON.4-.5 to select one of the four analog input pins (AD0-3) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located in page 0, at address D0H. The pins which are not used for ADC can be used for normal I/O. During a normal conversion, ADC logic initially sets the successive approximation register to 800H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.5- 4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, ADCON.3, the end-of-conversion(EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH/ADDATAL register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/ADDATAL before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0-AD3 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished.
14-1
A/D CONVERTER
S3C9228/P9228
CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bit + set-up time = 50 clocks, 50 clock x 1.78 us = 89 us at 0.56 MHz (4.5 MHz/8) Note that A/D converter needs at least 25s for conversion time.
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A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address D0H in page 0. It has three functions: -- Analog input pin selection (bits 4 and 5) -- End-of-conversion status detection (bit 3) -- ADC clock selection (bits 2 and 1) -- A/D operation start or enable (bit 0 ) After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (AD0-AD3) can be selected dynamically by manipulating the ADCON.4-5 bits. And the pins not used for analog input can be used for normal I/O function.
A/D Converter Control Register (ADCON) D0H, Page0, R/W (EOC bit is read-only) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Always logic zero A/D input pin selection bits: 00 = AD0 01 = AD1 10 = AD2 11 = AD3 End-of-conversion bit 0 = Not complete Conversion 1 = complete Conversion
Start or enable bit 0 = Disable operation 1 = Start operation (Automatically disable the operation after conversion completes.) Clock Selection bits: 00 = fxx/16 01 = fxx/8 10 = fxx/4 11 = fxx/1
Figure 14-1. A/D Converter Control Register (ADCON)
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S3C9228/P9228
A/D CONVERTER
Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only MSB MSB .9 .8 .7 .6 .5 .4 .3 .1 .2 .0 LSB LSB (ADDATAH) (ADDATAL)
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Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL)
INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range VSS to VDD. Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 VDD.
BLOCK DIAGRAM
ADCON.2-.1 ADCON.4-5 (Select one input pin of the assigned pins)
Clock Selector
To ADCON.3 (EOC Flag)
ADCON.0 (AD/C Enable) M Input Pins AD0-AD3 (P1.0-P1.3) Analog Comparator Successive Approximation Logic & Register
. . .
U + X ADCON.0 (AD/C Enable)
P1CON (Assign Pins to ADC Input) 10-bit D/A Converter
VDD VSS
Conversion Result (ADDATAH/ADDATAL, D1H/D2H, Page 0)
Figure 14-3. A/D Converter Functional Block Diagram
14-3
A/D CONVERTER
S3C9228/P9228
VDD
Analog Input Pin (VSS ADC input VDD)
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AD0-AD3 C 101
S3C9228
Figure 14-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
14-4
S3C9228/P9228
SERIAL I/O INTERFACE
15
OVERVIEW
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SERIAL I/O INTERFACE
Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: -- 8-bit control register (SIOCON) -- Clock selector logic -- 8-bit data buffer (SIODATA) -- 8-bit prescaler (SIOPS) -- 3-bit serial clock counter -- Serial data I/O pins (SI, SO) -- Serial clock input/output pin (SCK) The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO module, follow these basic steps: 1. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P2CON register if necessary. 2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. 3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1". 4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts. 5. When the shift operation (transmit/receive) is completed, the SIO pending bit (INTPND2.2) are set to "1" and SIO interrupt request is generated.
15-1
SERIAL I/O INTERFACE
S3C9228/P9228
SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module. -- Clock source selection (internal or external) for shift clock -- Interrupt enable -- Edge selection for shift operation -- Clear 3-bit counter and start shift operation
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(transmit) enable
-- Mode selection (transmit/receive or receive-only) -- Data direction selection (MSB first or LSB first) A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first.
Serial I/O Module Control Register (SIOCON) E1H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
SIO shift clock selection bit: 0 = Internal clock (P.S Clock) 1 = External clock (SCK) Data direction control bit: 0 = MSB-first mode 1 = LSB-first mode SIO mode selection bit: 0 = Receive only mode 1 = Transmit/receive mode
Not used SIO interrupt enable bit: 0 = Disable SIO interrupt 1 = Enable SIO interrupt SIO shift operation enable bit: 0 = Disable shifter and clock counter 1 = Enable shifter and clock counter SIO counter clear and shift start bit: 0 = No action 1 = Clear 3-bit counter and start shifting
Shift clock edge selection bit: 0 = tX at falling edeges, rx at rising edges. 1 = tX at rising edeges, rx at falling edges.
Figure 15-1. Serial I/O Module Control Register (SIOCON)
15-2
S3C9228/P9228
SERIAL I/O INTERFACE
SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock.
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SIO Pre-scaler Register (SIOPS) E3H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Baud rate = (fXX/4)/(SIOPS + 1)
Figure 15-2. SIO Prescaler Register (SIOPS)
SIO BLOCK DIAGRAM
CLK
3-Bit Counter Clear
SIO INT INTPND2.2 Pending
SIOCON.3 SIOCON.7 SIOCON.4 (Edge Select) SCK SIOPS (E3H, page 0) fxx/2 8-bit P.S. 1/2 M U X CLK 8-Bit SIO Shift Buffer (SIODATA, E2H, page 0) SIOCON.2 (Shift Enable)
SIOCON.1 (Interrupt Enable)
SIOCON.5 (Mode Select) SO SIOCON.6 (LSB/MSB First Mode Select)
8 SI
Data Bus
Figure 15-3. SIO Functional Block Diagram
15-3
SERIAL I/O INTERFACE
S3C9228/P9228
SERIAL I/O TIMING DIAGRAM (SIO)
SCK
SI
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DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SIO INT Set SIOCON.3
Transmit Complete
Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SIO INT Set SIOCON.3
Transmit Complete
Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
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S3C9228/P9228
ELECTRICAL DATA
16
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ELECTRICAL DATA
OVERVIEW
In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by an external interrupt -- Stop mode release timing when initiated by a Reset -- I/O capacitance -- A.C. electrical characteristics -- A/D converter electrical characteristics -- Input timing for external interrupt -- Input timing for RESET -- Serial data transfer timing -- Oscillation characteristics -- Oscillation stabilization time -- Operating voltage range
16-1
ELECTRICAL DATA
S3C9228/P9228
Table 16-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Output voltage Output current High
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Symbol VDD VIN VO I OH I OL TA TSTG Ports 0-6
Conditions -
Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3
Unit V V V mA
- One I/O pin active All I/O pins active
- 0.3 to VDD + 0.3 - 15 - 60 + 30 + 100 - 25 to + 85 - 65 to + 150
Output current Low
One I/O pin active Total pin current for ports
mA
C C
Operating temperature Storage temperature
- -
Table 16-2. D.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Operating Voltage Input High voltage Symbol VDD VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage Output Low voltage Input High leakage current VOH VOL ILIH1 Conditions fx = 0.4-4MHz, fxt = 32.8kHz fx = 0.4-8MHz Ports 4-6 Ports 0-3, RESET XIN, XOUT and XTIN, XTOUT Ports 4-6 Ports 0-3, RESET XIN, XOUT, XTIN, XTOUT VDD = 4.5 to 5.5 V; All output ports; IOH = -1 mA VDD = 4.5 to 5.5 V; All output ports; IOL = 10 mA VI = VDD; All input pins except XIN, XOUT, XTIN, XTOUT VI = VDD; XIN, XOUT, XTIN, XTOUT VDD - 1.0 - - - - - Min 2.0 2.7 0.7 VDD 0.8 VDD VDD - 0.1 - - Typ - - - Max 5.5 5.5 VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 VDD 2.0 3 V V A V Unit V V
ILIH2
20
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S3C9228/P9228
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics (Continued) (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Input Low leakage current Symbol ILIL1 VI = 0 V; All input pins except RESET, XOUT, XTIN, XTOUT VI = 0 V; XIN, XOUT, XTIN, XTOUT VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5V, TA = 25C Ports 0-6 VDD = 3V, TA = 25C RL2 VI = 0 V; VDD = 5V, TA = 25C RESET VDD = 3V, TA = 25C Oscillator Feed back Resistors ROSC1 ROSC2 LCD Voltage Dividing Resistor VLCD-COMi Voltage Drop (i = 0-7) VLCD-SEGx Voltage Drop (x = 0-19) Middle Output Voltage VLC3 VLC4 VLC5
NOTE: Low leakage current is absolute value.
Conditions
Min -
Typ -
Max -3
Unit A
ILIL2
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-20 - - 25 50 150 300 300 1500 50 - - - 47 90 250 500 600 3000 70 - 3 -3 100 150 400 700 1500 4500 90 120 k mV k k
Output High leakage current Output Low leakage current Pull-Up Resistor
ILOH ILOL RL1
VDD = 5 V, TA = 25 C XIN = VDD, XOUT = 0V VDD = 5 V, TA = 25 C XTIN = VDD, XTOUT = 0 V TA = 25 C VDD = 2.7 V to 5.5 V - 15 A per common pin VDD = 2.7 V to 5.5 V - 15 A per common pin VDD = 2.7 V to 5.5 V, LCD clock = 0Hz, VLC1 = VDD
RLCD VDC
VDS
-
-
120
VLC2
0.8VDD-0.2 0.6VDD-0.2 0.4VDD-0.2 0.2VDD-0.2
0.8VDD 0.6VDD 0.4VDD 0.2VDD
0.8VDD+ 0.2 0.6VDD+ 0.2 0.4VDD+ 0.2 0.2VDD+ 0.2
V
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ELECTRICAL DATA
S3C9228/P9228
Table 16-2. D.C. Electrical Characteristics (Concluded) (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 Conditions Run mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF
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Min -
Typ 6.0 3.0 2.5 1.5 1.3 1.0 0.8 0.4 15 6 0.5
Max 12.0 6.0 5.0 3.0 3.0 2.0 1.6 0.8 30 15 3
Unit mA
8.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz
VDD = 3 V 10% IDD2 Idle mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% IDD3 IDD4 IDD5
8.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz
Run mode: VDD = 3 V 10%, 32 kHz crystal oscillator Idle mode: VDD = 3 V 10%, 32 kHz crystal oscillator TA = 25 C Stop mode; VDD = 5 V 10%, Stop mode; VDD = 3 V 10%, TA = 25 C
A
0.3
2
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 4. IDD5 is current when main system clock and subsystem clock oscillation stops.
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S3C9228/P9228
ELECTRICAL DATA
Table 16-3. Data Retention Supply Voltage in Stop Mode (TA = - 25 C to + 85 C) Parameter Data retention supply voltage Data retention supply current
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Symbol VDDDR IDDDR
Conditions - Stop mode, TA = 25 C VDDDR = 2.0 V
Min 2.0 -
Typ - -
Max 5.5 1
Unit V A
Idle Mode (Basic Timer Active)
~ ~ ~ ~
Stop Mode Data Retention Mode Normal Operating Mode
VDD
VDDDR Execution of STOP Instruction 0.8 VDD
tWAIT NOTE: tWAIT is the same as 16 x 1/BT clock.
Figure 16-1. Stop Mode Release Timing When Initiated by an External Interrupt
16-5
ELECTRICAL DATA
S3C9228/P9228
RESET Occurs
Oscillation Stabilization TIme Normal Operating Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
VDD
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VDDDR Execution of STOP Instrction 0.8 VDD 0.2 VDD tWAIT RESET
NOTE:
tWAIT is the same as 16 x 1/BT clock.
Figure 16-2. Stop Mode Release Timing When Initiated by a RESET
Table 16-4. Input/Output Capacitance (TA = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF
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S3C9228/P9228
ELECTRICAL DATA
Table 16-5. A.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter SCK cycle time Symbol tKCY tKH, tKL Conditions External SCK source Internal SCK source SCK high, low width
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Min 1,000 1,000 500 tKCY/2-50 250 250 400 400 -
Typ -
Max -
Unit ns
External SCK source Internal SCK source
SI setup time to SCK high SI hold time to SCK high
tSIK
External SCK source Internal SCK source
tKSI tKSO
External SCK source Internal SCK source
Output delay for SCK to SO Interrupt input, High, Low width RESET input Low width
External SCK source Internal SCK source
-
300 250
ns
tINTH, tINTL tRSL
All interrupt VDD = 3 V Input VDD = 3 V
500 10
700 -
- -
ns s
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ELECTRICAL DATA
S3C9228/P9228
Table 16-6. A/D Converter Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy Integral linearity error Differential linearity error
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Symbol
Conditions VDD = 5.12 V
Min - - - - - -
Typ 10 - - - 1 0.5 - - 1000 - 1 0.5 100
Max - 3 2 1 3 2 - VDD - 10 3 1.5 500
Unit bit LSB
ILE DLE EOT EOB TCON VIAN RAN IADIN IADC
fxx = 8 MHz f CON = fxx/4
of top
Offset error of bottom Conversion time (1) Analog input voltage Analog input impedance Analog input current
10-bit resolution 50 x fxx/4, fxx = 8MHz - - VDD = 5 V VDD = 5 V VDD = 3 V VDD = 5 V When power down mode
25 VSS 2 - -
S V M A mA
nA
NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during A/D conversion.
tINTL
tINTH
External Interrupt
0.8 VDD 0.2 VDD
NOTE:
The unit tCPU means one CPU clock period.
Figure 16-3. Input Timing for External Interrupts
16-8
S3C9228/P9228
ELECTRICAL DATA
tRSL
RESET 0.2 VDD
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Figure 16-4. Input Timing for RESET
tKCY tKL SCK 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI 0.2VDD tKSO tKH
SO
Output Data
Figure 16-5. Serial Data Transfer Timing
16-9
ELECTRICAL DATA
S3C9228/P9228
Table 16-7. Main Oscillation Characteristics (TA = - 25C to + 85C) Oscillator Crystal Clock Configuration
C1 XIN
Parameter Main oscillation frequency
Test Condition 2.7 V - 5.5 V
Min 0.4
Typ -
Max 8
Units MHz
XOUT
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2.0 V - 5.5 V
C1 XIN
0.4 0.4
- -
4 8
Ceramic Oscillator
Main oscillation frequency
2.7 V - 5.5 V
XOUT
2.0 V - 5.5 V External Clock XIN input frequency
XIN
0.4 0.4
- -
4 8
2.7 V - 5.5 V
XOUT
2.0 V - 5.5 V RC Oscillator
R XOUT
0.4 0.4
- -
4 2 MHz
Frequency
XIN
5.0 V
Frequency
3.0 V
0.4
-
1
Table 16-8. Sub Oscillation Characteristics (TA = - 25C to + 85C) Oscillator Crystal Clock Configuration
C1 XIN
Parameter Sub oscillation frequency
Test Condition 2.0 V - 5.5 V
Min 32
Typ 32.768
Max 35
Units kHz
XOUT
External clock
XIN
XTIN input frequency
2.0 V - 5.5 V
32
-
100
XOUT
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S3C9228/P9228
ELECTRICAL DATA
Table 16-9. Main Oscillation Stabilization Time (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Crystal Ceramic fx > 1 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage ranage. XIN input high and low width (tXH, tXL) Test Condition Min - - Typ - - Max 30 10 Unit ms ms
External clock
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62.5
-
1250
ns
1/fx tXL tX
XIN 0.1 V
VDD-0.1 V
Figure 16-6. Clock Timing Measurement at XIN
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ELECTRICAL DATA
S3C9228/P9228
Table 16-10. Sub Oscillation Stabilization Time (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Crystal External clock Test Condition - XTIN input high and low width (tXH, tXL) Min - 5 Typ - - Max 10 15 Unit s s
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1/fxt tXTL tXTH
XTIN VDD-0.1 V 0.1 V
Figure 16-7. Clock Timing Measurement at XTIN
16-12
S3C9228/P9228
ELECTRICAL DATA
Instruction Clock 2 MHz 1.0 MHz
fx (Main/Sub oscillation frequency) 8 MHz 4 MHz
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400 kHz
6.25 kHz (main)/8.2 kHz(sub) 1 2 2.7 Supply Voltage (V) 5.5 6
400 kHz (main)/32.8 kHz(sub)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 16-8. Operating Voltage Range
16-13
ELECTRICAL DATA
S3C9228/P9228
NOTES
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16-14
S3C9228/P9228
MECHANICAL DATA
17
OVERVIEW
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MECHANICAL DATA
The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package.
#42
#22
0-15
14.00 0.2
#1
#21
39.50 MAX 39.10 0.2
0.51 MIN
0.50 (1.77) 1.00
0.1 0.1
1.78
NOTE:
Dimensions are in millimeters.
Figure 17-1. 42-SDIP-600 Package Dimensions
3.30 0.3
5.08 MAX
3.50
0.2
0.2
5
+0 - 0 .1 .05
42-SDIP-600
15.24
17-1
MECHANICAL DATA
S3C9228/P9228
13.20 0.3 0-8 10.00 0.2 0.15
+ 0.10 - 0.05
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13.20 0.3
10.00 0.2
44-QFP-1010B
0.80 0.20 #1 0.80
+ 0.10
0.10 MAX
#44
0.35 - 0.05 (1.00)
0.05 MIN 2.05 0.10 2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 17-2. 44-QFP-1010B Package Dimensions
17-2
S3C9228/P9228
S3P9228 OTP
18
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S3P9228 OTP
OVERVIEW
The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9228 is fully compatible with the S3C9228, both in function and in pin configuration. Because of its simple programming requirements, the S3P9228 is ideal for use as an evaluation chip for the S3C9228.
P1.0/AD0/INT P1.1/AD1/INT SDAT/P1.2/AD2/INT SCLK/P1.3/AD3/INT VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
P0.5 P0.4 P0.3/BUZ/INT P0.2/INT P0.1/T1CLK/INT P0.0/TAOUT/INT COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7
S3C9228
(44-QFP)
COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4
Figure 18-1. S3P9228 44-QFP Pin Assignments
RESET/RESET RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.0/SCK SEG2/P3.1/INTP SEG3/P3.0/INTP SEG4/P4.0 SEG5/P4.1 SEG6/P4.2 SEG7/P4.3
12 13 14 15 16 17 18 19 20 21 22
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S3P9228 OTP
S3C9228/P9228
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COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT SDAT/P1.2/AD2/INT SCLK/P1.3/AD3/INT VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET /RESET P2.3 P2.2/SI SEG0/P2.1/SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4 SEG7/P4.3 SEG6/P4.2 SEG5/P4.1 SEG4/P4.0 SEG3/P3.0/INTP SEG2/P3.1/INTP SEG1/P2.0/SCK
S3C9228
Figure 18-2. S3P9228 42-SDIP Pin Assignments
(42-SDIP)
18-2
S3C9228/P9228
S3P9228 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P1.2 Pin Name SDAT Pin No. 3 (9) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to + 5 V during programming.
P1.3 TEST
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SCLK VPP(TEST)
4 (10) 9 (15)
I/O I
RESET VDD/VSS
RESET VDD/VSS
12 (18) 5/6 (11/12)
I I
NOTE: Parentheses indicate pin number for 42-SDIP package.
Table 18-2. Comparison of S3P9228 and S3C9228 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 8 Kbyte EPROM 2.0 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 44-QFP, 42-SDIP User Program 1 time 44-QFP, 42-SDIP Programmed at the factory S3P9228 S3C9228 8 Kbyte mask ROM 2.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P72C8, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below. Table 18-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: "0" means Low level; "1" means High level.
18-3
S3P9228 OTP
S3C9228/P9228
Table 18-4. D.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 Conditions Run mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF
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Min -
Typ 6.0 3.0 2.5 1.5 1.3 1.0 0.8 0.4 15 6 0.5
Max 12.0 6.0 5.0 3.0 3.0 2.0 1.6 0.8 30 15 3
Unit mA
8.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz
VDD = 3 V 10% IDD2 Idle mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% IDD3 IDD4 IDD5
8.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz
Run mode: VDD = 3 V 10%, 32 kHz crystal oscillator Idle mode: VDD = 3 V 10%, 32 kHz crystal oscillator TA = 25 C Stop mode; VDD = 5 V 10%, Stop mode; VDD = 3 V 10%, TA = 25 C
A
0.3
2
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 4. IDD5 is current when main system clock and subsystem clock oscillation stops.
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S3C9228/P9228
S3P9228 OTP
Instruction Clock 2 MHz 1.0 MHz
fx (Main/Sub oscillation frequency) 8 MHz 4 MHz
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400 kHz
6.25 kHz (main)/8.2 kHz(sub) 1 2 2.7 Supply Voltage (V) 5.5 6
400 kHz (main)/32.8 kHz(sub)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 18-3. Standard Operating Voltage Range
18-5
S3P9228 OTP
S3C9228/P9228
NOTES
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S3C9228/P9228
DEVELOPMENT TOOLS
19
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DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. SHINE Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM86 The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board.
19-1
DEVELOPMENT TOOLS
S3C9228/P9228
IBM-PC AT or Compatible
RS-232C
SMDS2+
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PROM/OTP Writer Unit
Target Application System
RAM Break/Display Unit Probe Adapter BUS Trace/Timer Unit
SAM8 Base Unit
POD
TB9228 Target Board EVA Chip
Power Supply Unit
Figure 19-1. SMDS Product Configuration (SMDS2+)
19-2
S3C9228/P9228
DEVELOPMENT TOOLS
TB9228 TARGET BOARD The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system.
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To User_VCC OFF RESET
C11
TB9228
IDLE STOP
+ +
R1 D1 C1 U2 R7 R8 Y1 T1T2 T3T4 C3 C4 C5 C6 R5 R4
REV.0 '2002.03.30
ON
C20
25
CB+ C7
20 C10 C9
J1 30 20 10 1 160
J101 42SDIP 1
T16 T15 T14 T13 T12 T11 T10 T9
42 40
J102 44QFP 1 44
CN1
10
50 60 70 80
150 140 130
5 35 10 30
5
GND 40 10 35 15 25 20 25 23 30 22 22 P2
90 1 51 76 26
100 110 120 C14
15
21
SMDS2
SMDS2+
SM1347A
Figure 19-2. TB9228 Target Board Configuration
VCC
19-3
DEVELOPMENT TOOLS
S3C9228/P9228
Table 19-1. Power Selection Settings for TB9228 "To User_VCC" Settings
To User_VCC Off On TB9228 VCC VSS
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Operating Mode
Comments The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system.
Target System
VCC SMDS2/SMDS2+
To User_VCC Off On TB9228 External VCC VSS VCC SMDS2/SMDS2+ Target System
The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
NOTE: The following symbol in the "To User_VCC" Setting column indicates the electrical short (off) configuration:
19-4
S3C9228/P9228
DEVELOPMENT TOOLS
SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 19-2. The SMDS2+ Tool Selection Setting "SW1" Setting
SMDS2
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Operating Mode
SMDS2+ R/W SMDS2+ R/W Target Board
Table 19-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part
External Triggers Ch1 Ch2
Comments
Connector from External Trigger Sources of the Application System
You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions.
IDLE LED The Green LED is ON when the evaluation chip (S3E9220) is in idle mode. STOP LED The Red LED is ON when the evaluation chip (S3E9220) is in stop mode.
19-5
DEVELOPMENT TOOLS
S3C9228/P9228
J101 42-SDIP
J102 44-QFP
P6.2 P6.3 P0.0 P0.1 P0.2 www..com P0.3 P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.1 NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47
P6.1 P6.0 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P3.0 P3.1 P2.0 NC NC NC NC
P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.1 P2.0 P3.1 P3.0 P4.0 P4.1 P4.2 P4.3 NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 45 46 47
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 50 49 48
P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P6.3 P6.2 P6.1 P6.0 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 NC NC NC
Figure 19-3. Connectors (J101, J102) for TB9228
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S3C9228/P9228
DEVELOPMENT TOOLS
Target Board J101 50-Pin DIP Connector 1 42 Target Cable for Connector Part Name: AP42SD Order Code: SM6538 21 22
Target System J101 1 42
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21
22
Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package
Target Board J102 1 44 Target Cable for 50-pin Connector Part Name: AP50D-A Order Code: SM6305 22 23 50-Pin Connector
Target System J102 1 44 50-Pin Connector
22
23
Figure 19-5. S3C9228 Probe Adapter for 44-QFP Package
19-7
DEVELOPMENT TOOLS
S3C9228/P9228
NOTES
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19-8
S3C9228/P9228
PRODUCT OVERVIEW
1
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PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device. A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations.
S3C9228/P9228 MICROCONTROLLER
The S3C9228 can be used for dedicated control functions in a variety of applications, and is especially designed for application with FRS or etc. The S3C9228/P9228 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM88RCRI CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9228/P9228 has 8K-byte of program ROM, and 264-byte of RAM (including 16-byte of working register and 20-byte LCD display RAM). Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core: -- 7 configurable I/O ports including ports shared with segment/common drive outputs -- 10-bit programmable pins for external interrupts -- One 8-bit basic timer for oscillation stabilization and watch-dog functions -- Two 8-bit timer/counters with selectable operating modes -- Watch timer for real time -- 4 channel A/D converter -- 8-bit serial I/O interface
OTP
The S3C9228 microcontroller is also available in OTP (One Time Programmable) version. S3P9228 microcontroller has an on-chip 8K-byte one-time-programmable EPROM instead of masked ROM. The S3P9228 is comparable to S3C9228, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9228/P9228
FEATURES
CPU * SAM88RCRI CPU core Memory 8192 x 8 bits program memory (ROM) 264 x 8 bits data memory (RAM) (Including LCD data memory) www..com Instruction Set * * 41 instructions Idle and Stop instructions added for power-down modes * * LCD Controller/Driver * * * 16 segments and 8 common terminals 3, 4, and 8 common selectable Internal resistor circuit for LCD bias
8-bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source
A/D Converter * * * 10-bit converter resolution 50us conversion speed at 1MHz fADC clock 4-channel
36 I/O Pins * * I/O: 34 pins (44-pin QFP, 42-pin SDIP) Output only: 2 pins (44-pin QFP)
Interrupts * * 14 interrupt source and 1 vector One interrupt level
Two Power-Down Modes * * Idle: only CPU clock stops Stop: system clock and CPU clock stop
8-Bit Basic Timer * * Watchdog timer function 3 kinds of clock source
Oscillation Sources * * * Crystal, ceramic, or RC for main clock Main clock frequency: 0.4 MHz - 8MHz 32.768 kHz crystal oscillation circuit for sub clock
Two 8-Bit Timer/Counters * * * The programmable 8-bit timer/counters External event counter function Configurable as one 16-bit timer/counters
Instruction Execution Times * 500nS at 8MHz fx(minimum)
Watch Timer * * * Interval time: 3.91mS, 0.25S, 0.5S, and 1S at 32.768 kHz 0.5/1/2/4 kHz Selectable buzzer output Clock source generation for LCD
Operating Voltage Range * * 2.0 V to 5.5 V at 0.4 - 4.2MHz 2.7 V to 5.5 V at 0.4 - 8MHz
Operating Temperature Range * -25 C to +85 C
Package Type * 44-pin QFP, 42-pin SDIP
1-2
S3C9228/P9228
PRODUCT OVERVIEW
BLOCK DIAGRAM
TAOUT/ P0.0 T1CLK/ P0.1
8-Bit Timer/ CounterA 8-Bit Timer/ CounterB
RESET 16-Bit Timer/ Counter1
XIN XT IN
XOUT XTOUT
Watchdog Timer Basic Timer
P0.0/TAOUT/INT www..com P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P0.4 P0.5 P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT P2.0/SCK/SEG1 P2.1/SO/SEG0 P2.2/SI P2.3 P3.0/INTP/SEG3 P3.1/INTP/SEG2 P4.0-P4.7/ SEG4-SEG11 P5.0-P5.3/ SEG12-SEG15 P5.4-P5.7/ SEG16-SEG19/ COM7-COM4
I/O Port 0
Port I/O and Interrupt Control
Watch Timer
BUZ/P0.3
I/O Port 1 SAM88RCRI CPU
LCD Driver/ Controller
COM0-COM3/P6.3-P6.0 COM4-COM7/ SEG19-SEG16/P5.7-P5.4 SEG0-SEG1/P2.1-P2.0 SEG2-SEG3/P3.1-P3.0 SEG4-SEG11/P4.0-P4.7 SEG12-SEG15/P5.0-P5.3
I/O Port 2
I/O Port 3
8-Kbyte ROM
264-Byte Register File
SIO
P2.0/SCK/SEG1 P2.1/SO/SEG0 P2.2/SI P1.0-P1.3/AD0-AD3
I/O Port 4
A/D Converter
I/O Port 5
I/O Port 6
P6.0-P6.3/COM3-COM0
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9228/P9228
PIN ASSIGNMENTS
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P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT VDD VSS XOUT XIN TEST XTIN XTOUT
44 43 42 41 40 39 38 37 36 35 34
P0.5 P0.4 P0.3/BUZ/INT P0.2/INT P0.1/T1CLK/INT P0.0/TAOUT/INT COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7
1 2 3 4 5 6 7 8 9 10 11
S3C9228
(44-QFP)
33 32 31 30 29 28 27 26 25 24 23
COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4
Figure 1-2. S3C9228 44-QFP Pin Assignments
1-4
RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.0/SCK SEG2/P3.1/INTP SEG3/P3.0/INTP SEG4/P4.0 SEG5/P4.1 SEG6/P4.2 SEG7/P4.3
12 13 14 15 16 17 18 19 20 21 22
S3C9228/P9228
PRODUCT OVERVIEW
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COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT VDD VSS XOUT XIN TEST XTIN XTOUT RESET P2.3 P2.2/SI SEG0/P2.1/SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4 SEG7/P4.3 SEG6/P4.2 SEG5/P4.1 SEG4/P4.0 SEG3/P3.0/INTP SEG2/P3.1/INTP SEG1/P2.0/SCK
S3C9228
Figure 1-3. S3C9228 42-SDIP Pin Assignments
(42-SDIP)
1-5
PRODUCT OVERVIEW
S3C9228/P9228
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3
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Pin Type I/O
Pin Description 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable output port. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups.
Circuit Number E-4
Pin Numbers 39(3) 40(4) 41(5) 42(6) 43-44 1(7) 2(8) 3(9) 4(10) 16(22) 15(21) 14(20) 13(19) 18(24) 17(23) 19-26(25-32)
Share Pins TAOUT/INT T1CLK/INT INT BUZ/INT AD0/INT AD1/INT AD2/INT AD3/INT SCK/SEG1 SO/SEG0 SI - INTP/SEG3 INTP/SEG2 SEG4-SEG11
P0.4-P0.5 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P4.0-P4.7
O I/O
C F-16A
I/O I/O I/O
H-32A E-4 H-32B
I/O
H-32
P5.0-P5.3 P5.4-P5.7 P6.0-P6.3
I/O
H-32
27-30(33-36) 31-34(37-40)
SEG12-SEG15 SEG16-SEG19 /COM7-COM4 COM3-COM0
I/O
1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups.
H-32
35-38 (41-42,1-2)
NOTE: Parentheses indicate pin number for 42-SDIP-600 package.
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S3C9228/P9228
PRODUCT OVERVIEW
Table 1-1. Pin Descriptions (Continued) Pin Names VDD, VSS XOUT, XIN XTOUT, XTIN TEST
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Pin Type - - - - I I/O I/O I/O I/O I/O I/O I/O
Pin Description Power input pins for internal power block Main oscillator pins for main clock Sub oscillator pins for sub clock Chip test input pin Hold GND when the device is operating RESET signal input pin. Schmitt trigger input with internal pull-up resistor. External interrupts input. Key scan interrupts inputs. Timer 1/A external clock input. Timer 1/A clock output. Analog input pins for A/D converts module. Buzzer signal output. Serial clock, serial data output, serial data input LCD segment signal output
Circuit Number - - - - B E-4 F-16A H-32B E-4 E-4 F-16A E-4 H-32A E-4
Pin Numbers 5,6(11,12) 7,8(13,14) 11,10(17,16) 9(15) 12(18) 39-42(3-6) 1-4(7-10) 17-18(23-24) 40(4) 39(3) 1-4(7-10) 42(6) 16-15(22-21) 14(20) 15-16(21-22) 17-18(23-24) 19-34(25-40) 38-31 (2-1,42-37)
Share Pins -
- - - P0.0-P0.3 P1.0-P1.3 P3.1-P3.0 P0.1 P0.0 P1.0-P1.3 P0.3 P2.0-P2.1 P2.2 P2.1-P2.0 P3.1-P3.0 P4.0-P4.7 P5.0-P5.7 P6.3-P6.0 P5.7-P5.4
RESET INT INTP T1CLK TAOUT AD0-AD3 BUZ SCK SO SI SEG0-SEG1 SEG2-SEG3 SEG4-SEG19 COM0-COM7
I/O
H-32A H-32B H-32
I/O
LCD common signal output
H-32
NOTE: Parentheses indicate pin number for 42-SDIP-600 package.
1-7
PRODUCT OVERVIEW
S3C9228/P9228
PIN CIRCUIT DIAGRAMS
VDD Pull-Up Resistor
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RESET
Noise Filter
Figure 1-4. Pin Circuit Type B
VDD
Data Output Output Disable VSS
Figure 1-5. Pin Circuit Type C
1-8
S3C9228/P9228
PRODUCT OVERVIEW
VDD Pull-up Resistor Pull-up Enable
VDD Open-Drain
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Data Output Disable
I/O
External Interrupt Input
Figure 1-7. Pin Circuit Type E-4
VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data Output Disable
Circuit Type E
I/O
ADEN ADSELECT Data To ADC
Figure 1-8. Pin Circuit Type F-16A
1-9
PRODUCT OVERVIEW
S3C9228/P9228
VLC1
VLC2
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VLC3
SEG/COM Output Disable
Out
VLC4
VLC5
VSS
Figure 1-9. Pin Circuit Type H-23
1-10
S3C9228/P9228
PRODUCT OVERVIEW
VDD Pull-up Resistor Pull-up Enable
VDD Open-Drain EN
Data
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I/O
LCD Out EN
COM/SEG Output Disable
Circuit Type H-23
Figure 1-10. Pin Circuit Type H-32
VDD Pull-up Resistor Pull-up Enable
VDD Open-Drain EN
Data
I/O
LCD Out EN
COM/SEG Output Disable
Circuit Type H-23
Figure 1-11. Pin Circuit Type H-32A
1-11
PRODUCT OVERVIEW
S3C9228/P9228
VDD Pull-up Resistor Pull-up Enable
VDD Open-Drain EN
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Data
I/O
LCD Out EN
Port Enable (LMOD.5)
COM/SEG Output Disable
Circuit Type H-23
Figure 1-12. Pin Circuit Type H-32B
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S3C9228/P9228
ADDRESS SPACES
2
OVERVIEW
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ADDRESS SPACES
The S3C9228/P9228 microcontroller has three kinds of address space: -- Program memory (ROM) -- Internal register file -- LCD display register file A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3C9228 has 8K bytes of mask-programmable program memory on-chip. The S3C9228/P9228 microcontroller has 244 bytes general-purpose registers in its internal register file and the 20 bytes for LCD display memory is implemented in the internal register file too. Fifty-six bytes in the register file are mapped for system and peripheral control functions.
2-1
ADDRESS SPACES
S3C9228/P9228
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H-0001H) are an interrupt vector address. The program reset address in the ROM is 0100H.
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(Decimal) 8,192
(Hex) 1FFFH
8K bytes Internal Program Memory Area
256 2 1 0
Program Start
0100H 0002H
Interrupt Vector
0001H 0000H
Figure 2-1. S3C9228/P9228 Program Memory Address Space
2-2
S3C9228/P9228
ADDRESS SPACES
REGISTER ARCHITECTURE
The upper 72 bytes of the S3C9228/P9228's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 184 bytes of internal register file (00H-B7H) is called the general purpose register space. For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00H-BFH). This register file expansion is implemented by page 1 in the S3C9228/P9228. The page 1 (20 x 8 bits) is for LCD display register and can be used as general-purpose registers.
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FFH Peripheral Control Registers E0H DFH D0H CFH C0H BFH B8H B7H
72 Bytes of Common Area
System Control Registers Working Registers Peripheral Control Registers
184 Bytes ~
General Purpose Register File and Stack Area 3FH General Purpose Register File LCD Display Registers 00H 00H
64 Bytes
13H
(Page 0)
(Page 1)
Figure 2-2. Internal Register File Organization
2-3
ADDRESS SPACES
S3C9228/P9228
COMMON WORKING REGISTER AREA (C0H-CFH)
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. The Register (R) addressing mode can be used to access this area
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Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register.
MSB Rn
LSB Rn + 1
n = Even address
Figure 2-3. 16-Bit Register Pairs
+ PROGRAMMING TIP -- Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples: 1. LD LD 2. ADD 0C2H,40H R2,40H 0C3H,#45H ; Invalid addressing mode! ; R2 (C2H) the value in location 40H ; Invalid addressing mode! ; R3 (C3H) R3 + 45H
Use working register addressing instead:
Use working register addressing instead: ADD R3,#45H
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S3C9228/P9228
ADDRESS SPACES
SYSTEM STACK
S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file. STACK OPERATIONS Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents www..com of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-4.
High Address
PCL PCL Top of stack PCH PCH Top of stack Flags Stack contents after an interrupt
Stack contents after a call instruction
Low Address
Figure 2-4. Stack Operations
STACK POINTER (SP) Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C9228/P9228, the SP must be initialized to an 8bit value in the range 00H-B7H. NOTE In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area.
2-5
ADDRESS SPACES
S3C9228/P9228
+ PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD
* * *
SP,#0B8H
; SP B8H (Normally, the SP is set to 0B8H by the ; initialization routine)
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PUSH PUSH PUSH PUSH
* * *
SYM WTCON 20H R3
; ; ; ;
Stack address 0B7H Stack address 0B6H Stack address 0B5H Stack address 0B4H
SYM WTCON 20H R3
POP POP POP POP
R3 20H WTCON SYM
; ; ; ;
R3 Stack address 0B4H 20H Stack address 0B5H WTCON Stack address 0B6H SYM Stack address 0B7H
2-6
S3C9228/P9228
ADDRESSING MODES
3
OVERVIEW
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ADDRESSING MODES
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows: -- Register (R) -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Relative Address (RA) -- Immediate (IM)
3-1
ADDRESSING MODES
S3C9228/P9228
REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2).
Program Memory
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Register File
8-bit Register File Address One-Operand Instruction (Example)
dst OPCODE
Point to One Rigister in Register File Value used in Instruction Execution
OPERAND
Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File CFH
Program Memory 4-Bit Working Register Two-Operand Instruction (Example) Sample Instruction: ADD R1, R2 ; 4 LSBs Point to the Woking Register (1 of 16)
. . . .
OPERAND C0H
dst
src
OPCODE
Where R1 = C1H and R2 = C2H
Figure 3-2. Working Register Addressing
3-2
S3C9228/P9228
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location.
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Program Memory 8-Bit Register File Address One-Operand Instruction (Example)
Register File
dst OPCODE
Point to One Rigister in Register File Address of Operand used by Instruction
ADDRESS
Value used in Instruction Execution
OPERAND
Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-Bit register address
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES
S3C9228/P9228
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
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Program Memory Example Instruction References Program Memory REGISTER PAIR Points to Rigister Pair 16-Bit Address Points to Program Memory
dst OPCODE
Program Memory Sample Instructions: CALL JP @RR2 @RR2
Value used in Instruction
OPERAND
Figure 3-4. Indirect Register Addressing to Program Memory
3-4
S3C9228/P9228
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File CFH
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Program Memory 4-Bit Working Register Address 4 LSBs Point to the Woking Register (1 of 16)
. . . .
OPERAND C0H
dst
src
OPCODE
Sample Instruction: OR R6, @R2
Value used in Instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES
S3C9228/P9228
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File CFH
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Program Memory 4-Bit Working Register Address dst src OPCODE Next 3 Bits Point to Working Register Pair (1 of 8) LSB Selects
. . . .
Register Pair C0H 16-Bit address points to program memory or data memory
Example Instruction References either Program Memory or Data Memory
Program Memory or Data Memory
Value used in Instruction
OPERAND
Sample Instructions: LCD LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
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S3C9228/P9228
ADDRESSING MODES
INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of -128 to +127. This applies to external memory accesses only (see Figure 3-8). For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address www..com (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented.
Register File
~
Value used in Instruction OPERAND
~
+
Program Memory Base Address dst src OPCODE 4 LSBs Point to One of the Woking Register (1 of 16)
~
INDEX
~
Two-Operand Instruction Example
Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES
S3C9228/P9228
INDEXED ADDRESSING MODE (Continued)
Program Memory 4-Bit Working Register Address
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Register File NEXT 3 Bits Point to Working Register Pair (1 of 8) Register Pair 16-Bit address added to offset
XS (OFFSET) dst src OPCODE
LSB Selects
+
8-Bits 16-Bits Program Memory or Data Memory Value used in Instruction
16-Bits
OPERAND
Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
S3C9228/P9228
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Program Memory XLH (OFFSET) XLL (OFFSET) dst src OPCODE
Register File
4-Bit Working www..comRegister Address
NEXT 3 Bits Point to Working Register Pair (1 of 8) LSB Selects
Register Pair 16-Bit address added to offset
+
8-Bits 16-Bits Program Memory or Data Memory
16-Bits Sample Instructions: LDC R4, #1000H[RR2] #1000H) LDE R4, #1000H[RR2]
OPERAND
Value used in Instruction
; The values in the program address (RR2 + are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
3-9
ADDRESSING MODES
S3C9228/P9228
DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
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Program or Data Memory
Program Memory
Memory Address Used
Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory
Sample Instructions: LDC LDE R5,1234H R5,1234H ; ; The values in the program address (1234H) are loaded into register R5. Identical operation to LDC example, except that external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
3-10
S3C9228/P9228
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
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Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE
Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES
S3C9228/P9228
RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR.
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Program Memory
Next OPCODE Program Memory Address Used
Current Instruction
Displacement OPCODE
Current PC Value Signed Displacement Value
+
Sample Instructions: JR ULT,$ + OFFSET ; Where OFFSET is a value in the range + 127 to - 128
Figure 3-12. Relative Addressing IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH
Figure 3-13. Immediate Addressing
3-12
S3C9228/P9228
CONTROL REGISTERS
4
OVERVIEW
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CONTROL REGISTERS
In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual.
4-1
CONTROL REGISTERS
S3C9228/P9228
Table 4-1. System and Peripheral Control Registers (Page 0) Register Name Port 0 Control Register Port 0 Pull-up Resistor Enable Register Port 0 Interrupt Control Register Port 0 Interrupt Edge Selection Register Port 1 Control www..com Register Port 1 Pull-up Resistor Enable Register Port 1 Interrupt Control Register Port 1 Interrupt Edge Selection Register Port 2 Control Register Port 2 Pull-up Resistor Enable Register Port 3 Control Register Port 3 Pull-up Resistor Enable Register Port 3 Interrupt Control Register Port 3 Interrupt Edge Selection Register Port 4 Control Register (High Byte) Port 4 Control Register (Low Byte) Port 5 Control Register (High Byte) Port 5 Control Register (Low Byte) Port 6 Control Register LCD Mode Register Mnemonic P0CON P0PUR P0INT P0EDGE P1CON P1PUR P1INT P1EDGE P2CON P2PUR P3CON P3PUR P3INT P3EDGE P4CONH P4CONL P5CONH P5CONL P6CON LMOD Address (Page 0) Decimal 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 Hex EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Location FFH is not mapped.
4-2
S3C9228/P9228
CONTROL REGISTERS
Table 4-1. System and Peripheral Control Registers (Page 0) Register Name Mnemonic Address (Page 0) Decimal Locations D8H-B9H are not mapped. Timer B Control Register Timer 1/A Control Register Timer B Data Register Timer A www..com Data Register Timer B Counter Timer A Counter A/D Converter Control Register A/D Converter Data Register (High Byte) A/D Converter Data Register (Low Byte) Oscillator Control Register System Clock Control Register System Flags Register Interrupt Pending Register 1 Interrupt Pending Register 2 LCD Port Control Register Stack Pointer Watch Timer Control Register Basic Timer Control Register Basic Timer Counter System Mode Register STOP Control Register SIO Control Register SIO Data Register SIO Prescaler Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register TBCON TACON TBDATA TADATA TBCNT TACNT ADCON ADDATAH ADDATAL OSCCON CLKCON FLAGS INTPND1 INTPND2 LPOT SP WTCON BTCON BTCNT SYM STPCON SIOCON SIODATA SIOPS P0 P1 P2 P3 P4 P5 P6 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 220 221 223 224 225 226 227 228 229 230 231 232 233 234 BAH BBH BCH BDH BEH BFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DCH DDH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Hex R/W
Location DBH is not mapped.
Location DEH is not mapped.
4-3
CONTROL REGISTERS
S3C9228/P9228
Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register bit or bit function Full Register name mnemonic
Register address (hexadecimal)
FLAGS - System Flags Register
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D5H .5 x R/W .4 x R/W .3 x R/W .2 x R/W .1 0 R/W .0 0 R/W
Bit Identifier RESET Value Read/Write
.7
.7 x R/W
.6 x R/W
Carry Flag (C) 0 1 Operation dose not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit7
.6
Zero Flag 0 1 Operation result is a non-zero value Operation result is zero
.5
Sign Flag 0 1 Operation generates positive number (MSB = "0") Operation generates negative number (MSB = "1")
R = Read-only W = Write-only R/W = Read/write ' - ' = Not used Addressing mode or modes you can use to modify register values
Description of the effect of specific bit settings
RESET value notation: '-' = Not used 'x' = Undetermind value '0' = Logic zero '1' = Logic one
Bit number: MSB = Bit 7 LSB = Bit 0
Figure 4-1. Register Description Format
4-4
S3C9228/P9228
CONTROL REGISTERS
ADCON -- A/D Converter Control Register
Bit Identifier RESET Value Read/Write .7-.6
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D0H
.4 0 R/W .3 0 R .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 0 R/W
Not used for the S3C9228/P9228 A/D Input Pin Selection Bits 0 0 1 1 0 1 0 1 AD0 (P1.0) AD1 (P1.1) AD2 (P1.2) AD3 (P1.3)
.5-.4
.3
End of Conversion Bit (Read-only) 0 1 Conversion not complete Conversion complete
.2-.1
Clock Source Selection Bits 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/4 fxx
.0
Start or Enable Bit 0 1 Disable operation Start operation (automatically disable operation after conversion complete)
4-5
CONTROL REGISTERS
S3C9228/P9228
BTCON -- Basic Timer Control Register
Bit Identifier RESET Value Read/Write .7-.4
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DCH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
Watchdog Timer Enable Bits 1 0 1 0 Disable watchdog function Enable watchdog function Any other value
.3-.2
Basic Timer Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/4096 fxx/1024 fxx/128 fxx/16
.1
Basic Timer Counter Clear Bit (1) 0 1 No effect Clear the basic timer counter value (BTCNT)
.0
Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters (2) 0 1 No effect Clear clock frequency dividers
NOTES 1. When "1" is written to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to "0". 2. When "1" is written to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0".
4-6
S3C9228/P9228
CONTROL REGISTERS
CLKCON -- System Clock Control Register
Bit Identifier RESET Value Read/Write .7
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D4H
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
Oscillator IRQ Wake-up Function Bit 0 1 Enable IRQ for main or sub oscillator wake-up in power down mode Disable IRQ for main or sub oscillator wake-up in power down mode
.6-.5
Bits 6-5 0 Always logic zero
.4-.3
CPU Clock (System Clock) Selection Bits 0 0 1 1 0 1 0 1 Divide by 16 (fxx/16) Divide by 8 (fxx /8) Divide by 2 (fxx /2) Non-divided clock (fxx)
.2-.0
Bits 2-0 0 Always logic zero
4-7
CONTROL REGISTERS
S3C9228/P9228
FLAGS -- System Flags Register
Bit Identifier RESET Value Read/Write .7
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D5H
.5 x R/W .4 x R/W .3 - - .2 - - .1 - - .0 - -
.7 x R/W
.6 x R/W
Carry Flag (C) 0 Operation does not generate a carry or borrow condition
.6
Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero
.5
Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1")
.4
Overflow Flag (V) 0 1 Operation result is +127 or -128 Operation result is +127 or -128
.3-.0
Not used for S3C9228/P9228
4-8
S3C9228/P9228
CONTROL REGISTERS
INTPND1 -- Interrupt Pending Register 1
Bit Identifier RESET Value Read/Write .7
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D6H
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
P1.3's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.6
P1.2's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.5
P1.1's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.4
P1.0's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.3
P0.3's Interrupt Pending Bit 0 No interrupt pending (when read), Clear pending bit (when write) 1 Interrupt is pending (when read)
.2
P0.2's Interrupt Pending Bit 0 No interrupt pending (when read), Clear pending bit (when write) 1 Interrupt is pending (when read)
.1
P0.1's Interrupt Pending Bit 0 No interrupt pending (when read), Clear pending bit (when write) 1 Interrupt is pending (when read)
.0
P0.0's Interrupt Pending Bit 0 No interrupt pending (when read), Clear pending bit (when write) 1 Interrupt is pending (when read)
NOTE: Refer to Page 5-6 to clear any pending bits.
4-9
CONTROL REGISTERS
S3C9228/P9228
INTPND2 -- Interrupt Pending Register 2
Bit Identifier RESET Value Read/Write .7-.6
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D7H
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 0 R/W
Not used for S3C9228/P9228 P3.1 (INTP) Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.5
.4
P3.0 (INTP) Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
.3
Watch Timer Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read)
.2
SIO Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read)
.1
Timer B Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read)
.0
Timer 1/A Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read)
NOTE: Refer to Page 5-6 to clear any pending bits.
4-10
S3C9228/P9228
CONTROL REGISTERS
LMOD -- LCD Mode Control Register
Bit Identifier RESET Value Read/Write .7
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FEH
.5 0 .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 0 R/W
R/W
Not used for S3C9228/P9228 COM Pins High Impedance Control Bit 0 1 Normal COMs signal output COM pins are at high impedance
.6
.5
Port3 High Impedance Control Bit 0 1 Normal I/O High impedance input
.4
LCD Display Control Bit 0 1 Display off (cut off the LCD voltage dividing resistors) Normal display on
.3-.2
LCD Duty and Bias Selection Bits 0 0 1 1 0 1 0 1 1/3 duty, 1/3 bias; COM0-COM2/SEG0-SEG19 1/4 duty, 1/3 bias; COM0-COM3/SEG0-SEG19 1/8 duty, 1/4 bias; COM0-COM7/SEG0-SEG15 1/8 duty, 1/5 bias; COM0-COM7/SEG0-SEG15
.1-.0
LCD Clock Selection Bits 0 0 1 1 0 1 0 1 fw/27 (256 Hz when fw is 32.768 kHz) fw/26 (512 Hz when fw is 32.768 kHz) fw/25 (1,024 Hz when fw is 32.768 kHz) fw/24 (2,048 Hz when fw is 32.768 kHz)
4-11
CONTROL REGISTERS
S3C9228/P9228
LPOT -- LCD Port Control Register
Bit Identifier RESET Value Read/Write .7
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D8H
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 0 R/W
Not used for S3C9228/P9228 SEG4-SEG19 and COM0-COM3 Selection Bit SEG4-7 P4.0-P4.3 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 SEG Port Port Port Port Port SEG8-11 P4.4-P4.7 SEG SEG Port Port Port Port SEG12-15 P5.0-P5.3 SEG SEG SEG Port Port Port SEG16-19/ COM7-COM4 P5.4-P5.7 SEG/COM SEG/COM SEG/COM SEG/COM Port Port COM0-3 P6.0-P6.3 COM COM COM COM COM Port
.6-.4
.3
SEG3/P3.0 Selection Bit 0 1 SEG port Normal I/O port
.2
SEG2/P3.1 Selection Bit 0 1 SEG port Normal I/O port
.1
SEG1/P2.0 Selection Bit 0 1 SEG port Normal I/O port
.0
SEG0/P2.1 Selection Bit 0 1 SEG port Normal I/O port
NOTE: SEG16-SEG19 are shared with COM4-COM7.
4-12
S3C9228/P9228
CONTROL REGISTERS
OSCCON -- Oscillator Control Register
Bit Identifier RESET Value Read/Write .7-.4
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D3H
.4 - - .3 0 R/W .2 0 R/W .1 - - .0 0 R/W
.7 - -
.6 - -
.5 - -
Not used for S3C9228/P9228 Main Oscillator Control Bit 0 1 Main oscillator RUN Main oscillator STOP
.3
.2
Sub Oscillator Control Bit 0 1 Sub oscillator RUN Sub oscillator STOP
.1 .0
Not used for S3C9228/P9228 System Clock Selection Bit 0 1 Select main oscillator for system clock Select sub oscillator for system clock
4-13
CONTROL REGISTERS
S3C9228/P9228
P0CON - Port 0 Control Register
Bit Identifier RESET Value Read/Write .7-.6
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EBH
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
P0.3/BUZ/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (BUZ output)
.5-.4
P0.2/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Not available
.3-.2
P0.1/T1CLK/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (T1CLK input) Push-pull output N-channel open-drain output Not available
.1-.0
P0.0/TAOUT/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (TAOUT output)
4-14
S3C9228/P9228
CONTROL REGISTERS
P0INT -Port 0 Interrupt Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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EDH
.4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
Not used for S3C9228/P9228 P0.3's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.3
.2
P0.2's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.1
P0.1's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
P0.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
4-15
CONTROL REGISTERS
S3C9228/P9228
P0PUR -Port 0 Pull-up Resistors Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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ECH
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P0.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.3
.2
P0.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.1
P0.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.0
P0.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
4-16
S3C9228/P9228
CONTROL REGISTERS
P0EDGE -Port 0 Interrupt Edge Selection Register
Bit Identifier RESET Value Read/Write .7-.4
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EEH
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P0.3's Interrupt Edge Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.3
.2
P0.2's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.1
P0.1's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.0
P0.0's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
4-17
CONTROL REGISTERS
S3C9228/P9228
P1CON - Port 1 Control Register
Bit Identifier RESET Value Read/Write .7-.6
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EFH
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
P1.3/AD3/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode)
.5-.4
P1.2/AD2/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode)
.3-.2
P1.1/AD1/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode)
.1-.0
P1.0/AD0/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode)
4-18
S3C9228/P9228
CONTROL REGISTERS
P1INT -Port 1 Interrupt Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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F1H
.4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
Not used for S3C9228/P9228 P1.3's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.3
.2
P1.2's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.1
P1.1's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
P1.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
4-19
CONTROL REGISTERS
S3C9228/P9228
P1PUR -Port 1 Pull-up Resistors Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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F0H
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P1.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.3
.2
P1.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.1
P1.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.0
P1.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
4-20
S3C9228/P9228
CONTROL REGISTERS
P1EDGE -Port 1 Interrupt Edge Selection Register
Bit Identifier RESET Value Read/Write .7-.4
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F2H
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P1.3's Interrupt Edge Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.3
.2
P1.2's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.1
P1.1's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.0
P1.0's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
4-21
CONTROL REGISTERS
S3C9228/P9228
P2CON - Port 2 Control Register
Bit Identifier RESET Value Read/Write .7-.6
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F3H
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
P2.3 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Not available
.5-.4
P2.2/SI Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (SI) Push-pull output N-channel open-drain output Not available
.3-.2
P2.1/SO Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (SO out)
.1-.0
P2.0/SCK Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (SCK in) Push-pull output N-channel open-drain output Alternative function (SCK out)
4-22
S3C9228/P9228
CONTROL REGISTERS
P2PUR -Port 2 Pull-up Resistors Enable Register
Bit Identifier RESET Value Read/Write .7-.4
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F4H
.3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P2.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.3
.2
P2.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.1
P2.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.0
P2.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
4-23
CONTROL REGISTERS
S3C9228/P9228
P3CON - Port 3 Control Register
Bit Identifier RESET Value Read/Write .7-.4
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F5H
.5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 - -
.6 - -
Not used for S3C9228/P9228 P3.1/SEG2/INTP Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Not available
.3-.2
.1-.0
P3.0/SEG3/INTP Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Not available
4-24
S3C9228/P9228
CONTROL REGISTERS
P3INT -Port 3 Interrupt Enable Register
Bit Identifier RESET Value Read/Write .7-.2
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F7H
.4 - - .3 - - .2 - - .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
Not used for S3C9228/P9228 P3.1's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.1
.0
P3.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
4-25
CONTROL REGISTERS
S3C9228/P9228
P3PUR -Port 3 Pull-up Resistors Enable Register
Bit Identifier RESET Value Read/Write .7-.2
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F6H
.3 - - .2 - - .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P3.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
.1
.0
P3.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor
4-26
S3C9228/P9228
CONTROL REGISTERS
P3EDGE -Port 3 Interrupt Edge Selection Register
Bit Identifier RESET Value Read/Write .7-.4
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F8H
.3 - - .2 - - .1 0 R/W .0 0 R/W
.7 - -
.6 - -
.5 - -
.4 - -
Not used for S3C9228/P9228 P3.1's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
.1
.0
P3.0's Interrupt State Setting Bit 0 1 Falling edge interrupt Rising edge interrupt
4-27
CONTROL REGISTERS
S3C9228/P9228
P4CONH - Port 4 Control Register High Byte
Bit Identifier RESET Value Read/Write .7-.6
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F9H
.4 0 .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
R/W
P4.7/SEG11 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P4.6/SEG10 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P4.5/SEG9 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P4.4/SEG8 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
4-28
S3C9228/P9228
CONTROL REGISTERS
P4CONL-Port 4 Control Register Low Byte
Bit Identifier RESET Value Read/Write .7-.6
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FAH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
P4.3/SEG7 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P4.2/SEG6 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P4.1/SEG5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P4.0/SEG4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
4-29
CONTROL REGISTERS
S3C9228/P9228
P5CONH - Port 5 Control Register High Byte
Bit Identifier RESET Value Read/Write .7-.6
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FBH
.4 0 .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
R/W
P5.7/SEG19/COM4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P5.6/SEG18/COM5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P5.5/SEG17/COM6 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P5.4/SEG16/COM7 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
4-30
S3C9228/P9228
CONTROL REGISTERS
P5CONL - Port 5 Control Register Low Byte
Bit Identifier RESET Value Read/Write .7-.6
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FCH
.4 0 .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
R/W
P5.3/SEG15 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P5.2/SEG14 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P5.1/SEG13 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P5.0/SEG12 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
4-31
CONTROL REGISTERS
S3C9228/P9228
P6CON - Port 6 Control Register High Byte
Bit Identifier RESET Value Read/Write .7-.6
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FDH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
.5 0 R/W
P6.3/COM0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.5-.4
P6.2/COM1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.3-.2
P6.1/COM2 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
.1-.0
P6.0/COM3 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode
4-32
S3C9228/P9228
CONTROL REGISTERS
SIOCON -- SIO Control Register
Bit Identifier RESET Value Read/Write .7
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E1H
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 - -
.7 0 R/W
.6 0 R/W
SIO Shift Clock Selection Bit 0 1 Internal clock (P.S clock) External clock (SCK)
.6
Data Direction Control Bit 0 1 MSB-first mode LSB-first mode
.5
SIO Mode Selection Bit 0 1 Receive-only mode Transmit/receive mode
.4
Shift Clock Edge Selection Bit 0 1 Tx at falling edges, Rx at rising edges Tx at rising edges, Rx at falling edges
.3
SIO Counter Clear and Shift Start Bit 0 1 No action Clear 3-bit counter and start shifting
.2
SIO Shift Operation Enable Bit 0 1 Disable shifter and clock counter Enable shifter and clock counter
.1
SIO Interrupt Enable Bit 0 1 Disable SIO interrupt Enable SIO interrupt
.0
Not used for S3C9228/P9228
4-33
CONTROL REGISTERS
S3C9228/P9228
STPCON - Stop Control Register
Bit Identifier RESET Value Read/Write .7
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E0H
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7 0 R/W
.6 0 R/W
Stop Control Bits 1 0 1 0 0 1 0 1 Enable Stop instruction Disable Stop instruction Other values
NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP instruction will not execute.
4-34
S3C9228/P9228
CONTROL REGISTERS
SYM -- System Mode Register
Bit Identifier RESET Value Read/Write .7-.4
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DFH
.5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W
.7
.6 - -
- -
Not used for S3C9228/P9228 Global Interrupt Enable Bit 0 1 Global interrupt processing disable (DI instruction) Global interrupt processing enable (EI instruction)
.3
.2-.0
Page Selection Bits 0 0 0 0 0 1 Page 0 Page 1 Not available
Other values
4-35
CONTROL REGISTERS
S3C9228/P9228
TACON -- Timer 1/A Control Register
Bit Identifier RESET Value Read/Write .7
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BBH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 - -
.7 0 R/W
.6 0 R/W
.5 0 R/W
Timer 1 Mode Selection Bit 0 1 Two 8-bit timers mode (Timer A/B) One 16-bit timer mode (Timer 1)
.6-.4
Timer 1/A Clock Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/512 fxx/256 fxx/64 fxx/8 fxx (system clock) fxt (sub clock) T1CLK (external clock) Not available
.3
Timer 1/A Counter Clear Bit 0 1 No effect Clear the timer 1/A counter (when write)
.2
Timer 1/A Counter Enable Bit 0 1 Disable counting operation Enable counting operation
.1
Timer 1/A Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Bit 0 Not used for S3C9228/P9228
4-36
S3C9228/P9228
CONTROL REGISTERS
TBCON -- Timer B Control Register
Bit Identifier RESET Value Read/Write .7
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BAH
.5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 - -
.7 - -
.6 0 R/W
Not used for S3C9228/P9228 Timer B Clock Selection Bits 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 fxx/512 fxx/256 fxx/64 fxx/8 fxx (system clock) fxt (sub clock)
.6-.4
.3
Timer B Counter Clear Bit 0 1 No effect Clear the timer B counter (when write)
.2
Timer B Counter Enable Bit 0 1 Disable counting operation Enable counting operation
.1
Timer B Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Not used for S3C9228/P9228
4-37
CONTROL REGISTERS
S3C9228/P9228
WTCON -- Watch Timer Control Register
Bit Identifier RESET Value Read/Write .7
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DAH
.4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 - -
.7 0 R/W
.6 0 R/W
.5 0 R/W
Watch Timer Clock Selection Bit 0 1 Select main clock divided by 27 (fx/128) Select sub clock (fxt)
.6
Watch Timer Interrupt Enable Bit 0 1 Disable watch timer interrupt Enable watch timer interrupt
.5-.4
Buzzer Signal Selection Bits 0 0 1 1 0 1 0 1 0.5 kHz 1 kHz 2 kHz 4 kHz
.3-.2
Watch Timer Speed Selection Bits 0 0 1 1 0 1 0 1 Set watch timer interrupt to 1s Set watch timer interrupt to 0.5s Set watch timer interrupt to 0.25s Set watch timer interrupt to 3.91ms
.1
Watch Timer Enable Bit 0 1 Disable watch timer; Clear frequency dividing circuits Enable watch timer
.0
Not used for S3C9228/P9228
4-38
S3C9228/P9228
INTERRUPT STRUCTURE
5
OVERVIEW
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INTERRUPT STRUCTURE
The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H-0001H.
VECTOR
SOURCES S1
0000H 0001H
S2 S3 Sn
NOTES: 1. The SAM88RCRI interrupt has only one vector address (0000H-0001H). 2. The number of Sn value is expandable.
Figure 5-1. S3C9-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. The systemlevel control points in the interrupt structure are therefore: -- Global interrupt enable and disable (by EI and DI instructions) -- Interrupt source enable and disable settings in the corresponding peripheral control register(s) ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.3 is the enable and disable bit for global interrupt processing, which you can set by modifying SYM.3. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during normal operation, we recommend that you use the EI and DI instructions for this purpose.
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INTERRUPT STRUCTURE
S3C9228/P9228
INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine.
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"EI" Instruction Execution RESET Source Interrupts Source Interrupt Enable
S R
Q
Interrupt Pending Register
Interrpt priority is determind by software polling method Global Interrupt Control (EI, Di instruction)
Vector Interrupt Cycle
Figure 5-2. Interrupt Function Diagram
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INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source's pending flag is cleared to "0" by software. 4. Interrupt priority must be determined by software polling method.
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INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced, the following conditions must be met: -- Interrupt processing must be enabled (EI, SYM.3 = "1") -- Interrupt must be enabled at the interrupt's source (peripheral control register) If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0") to disable all subsequent interrupts. 2. Save the program counter and status flags to stack. 3. Branch to the interrupt vector to fetch the service routine's address. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.3 to "1"(EI), allowing the CPU to process the next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to stack. 2. Push the program counter's high-byte value to stack. 3. Push the FLAGS register values to stack. 4. Fetch the service routine's high-byte address from the vector address 0000H. 5. Fetch the service routine's low-byte address from the vector address 0001H. 6. Branch to the service routine specified by the 16-bit vector address.
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INTERRUPT STRUCTURE
S3C9228/P9228
S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: -- Timer 1/A interrupt -- Timer B interrupt -- SIO interrupt -- Watch Timer interrupt -- Four external interrupts for port 0
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interrupts for port 1
-- Two external interrupts for port 3
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INTERRUPT STRUCTURE
Vector
Enable/Disable P0INT.0
Pending INTPND1.0 INTPND1.1
Sources P0.0 External Interript P0.1 External Interript P0.2 External Interript P0.3 External Interript P1.0 External Interript P1.1 External Interript P1.2 External Interript P1.3 External Interrupt Timer 1/A Interrupt Timer B Interrupt SIO Interrupt Watch Timer Interrupt P3.0 Interrupt P3.1 Interrupt
P0INT.1 INTPND1.2 P0INT.2 INTPND1.3
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P0INT.3 INTPND1.4 P1INT.0 INTPND1.5 P1INT.1 INTPND1.6 P1INT.2 0000H 0001H SYM.3 (EI, DI) INTPND1.7 P1INT.3 INTPND2.0 TACON.1 INTPND2.1 TBCON.1 INTPND2.2 SIOCON.1 INTPND2.3 WTCON.1 INTPND2.4 P3INT.0 INTPND2.5 P3INT.1
Figure 5-3. S3C9228/P9228 Interrupt Structure
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INTERRUPT STRUCTURE
S3C9228/P9228
Programming Tip --
How to clear an interrupt pending bit
As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD
* * *
INTPND1, #11111011B
; Clear P0.2's interrupt pending bit
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IRET LD
* * *
2.
INTPND2, #11110111B
; Clear watch timer interrupt pending bit
IRET
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SAM88RCRI INSTRUCTION SET
6
OVERVIEW
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SAM88RCRI INSTRUCTION SET
The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces". ADDRESSING MODES There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and Immediate (IM). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes".
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SAM88RI INSTRUCTION SET
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Table 6-1. Instruction Group Summary Mnemonic Operands Instruction
Load Instructions CLR LD LDC
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dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst src
Clear Load Load program memory Load external data memory Load program memory and decrement Load external data memory and decrement Load program memory and increment Load external data memory and increment Pop from stack Push to stack
LDCD LDED LDCI LDEI POP PUSH
Arithmetic Instructions ADC ADD CP DEC INC SBC SUB dst,src dst,src dst,src dst dst dst,src dst,src Add with carry Add Compare Decrement Increment Subtract with carry Subtract
Logic Instructions AND COM OR XOR dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR
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Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction
Program Control Instructions CALL IRET JP
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dst cc,dst dst cc,dst
Call procedure Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Return
JR RET
Bit Manipulation Instructions TCM TM dst,src dst,src Test complement under mask Test under mask
Rotate and Shift Instructions RL RLC RR RRC SRA dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic
CPU Control Instructions CCF DI EI IDLE NOP RCF SCF STOP Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set carry flag Enter Stop mode
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SAM88RI INSTRUCTION SET
S3C9228/P9228
FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 - FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result.
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System Flags Register (FLAGS) D5H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Carry flag (C) Zero flag (Z) Sign flag (S) Overflow flag (V)
Not mapped
Figure 6-1. System Flags Register (FLAGS) FLAG DESCRIPTIONS Overflow Flag (FLAGS.4, V) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than - 128. It is also cleared to "0" following logic operations. Sign Flag (FLAGS.5, S) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. Zero Flag (FLAGS.6, Z) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. Carry Flag (FLAGS.7, C) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.
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SAM88RCRI INSTRUCTION SET
INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag C Z S
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Description Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6-3. Instruction Set Symbols
V 0 1 * - x
Symbol dst src @ PC FLAGS # H D B opc Source operand
Description Destination operand Indirect register address prefix Program counter Flags register (D5H) Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode
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Table 6-4. Instruction Notation Conventions Notation cc r rr R RR
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Description Condition code Working register only Working register pair Register or working register Register pair or working register pair Indirect working register only
Actual Operand Range See list of condition codes in Table 6-6. Rn (n = 0-15) RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0-255, n = 0-15) reg or RRp (reg = 0-254, even number only, where p = 0, 2, ..., 14) @Rn (n = 0-15)
Ir IR Irr IRR X XS xl da ra im
Indirect register or indirect working register @Rn or @reg (reg = 0-255, n = 0-15) Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode Indexed (long offset) addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode @RRp (p = 0, 2, ..., 14) @RRp or @reg (reg = 0-254, even only, where p = 0, 2, ..., 14) #reg[Rn] (reg = 0-255, n = 0-15) #addr[RRp] (addr = range -128 to +127, where p = 0, 2, ..., 14) #addr [RRp] (addr = range 0-8191, where p = 0, 2, ..., 14) addr (addr = range 0-8191) addr (addr = number in the range +127 to -128 that is an offset relative to the address of the next instruction) #data (data = 0-255)
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SAM88RCRI INSTRUCTION SET
Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) - U P
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0 DEC R1 RLC R1 INC R1 JP IRR1
1 DEC IR1 RLC IR1 INC IR1
2 ADD r1,r2 ADC r1,r2 SUB r1,r2 SBC r1,r2 OR r1,r2
3 ADD r1,Ir2 ADC r1,Ir2 SUB r1,Ir2 SBC r1,Ir2 OR r1,Ir2 AND r1,Ir2 TCM r1,Ir2 TM r1,Ir2
4 ADD R2,R1 ADC R2,R1 SUB R2,R1 SBC R2,R1 OR R2,R1 AND R2,R1 TCM R2,R1 TM R2,R1
5 ADD IR2,R1 ADC IR2,R1 SUB IR2,R1 SBC IR2,R1 OR IR2,R1 AND IR2,R1 TCM IR2,R1 TM IR2,R1
6 ADD R1,IM ADC R1,IM SUB R1,IM SBC R1,IM OR R1,IM AND R1,IM TCM R1,IM TM R1,IM
7
0 1 2 3 4 5
P E R
POP R1 COM R1 PUSH R2
POP IR1 COM IR1 PUSH IR2
AND r1,r2 TCM r1,r2 TM r1,r2
N I B B L E
6 7 8 9 A B C
LD r1, x, r2 RL R1 RL IR1 CP r1,r2 CLR R1 RRC R1 SRA R1 RR R1 CLR IR1 RRC IR1 SRA IR1 RR IR1 LDCD r1,Irr2 XOR r1,r2 CP r1,Ir2 XOR r1,Ir2 LDC r1,Irr2 LDC r2,Irr1 LDCI r1,Irr2 LD R2,R1 CALL IRR1 LD R2,IR1 LD IR2,R1 LD IR1,IM LD R1,IM CALL DA1 CP R2,R1 XOR R2,R1 CP IR2,R1 XOR IR2,R1 CP R1,IM XOR R1,IM LD r2, x, r1 LDC r1, Irr2, xL LDC r2, Irr2, xL LD r1, Ir2 LD Ir1, r2 LDC r1, Irr2, xs LDC r2, Irr1, xs
H E X
D E F
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SAM88RI INSTRUCTION SET
S3C9228/P9228
Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) - U P P E R N I B B L E H E X 0 1 2 3 4 5 6 7 8 9 A B C D E F LD r1,R2 LD r2,R1 JR cc,RA LD r1,IM JP cc,DA INC r1 IDLE STOP DI EI RET IRET RCF SCF CCF NOP 8 LD r1,R2 9 LD r2,R1 A B JR cc,RA C LD r1,IM D JP cc,DA E INC r1 F
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SAM88RCRI INSTRUCTION SET
CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes
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Binary 0000 1000 0111 0110 1110
(1)
Mnemonic F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Always true Carry No carry Zero Not zero Plus Minus Overflow
Description Always false - - C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0
Flags Set
1111 (1)
(1) (1)
1101 0101 0100 1100 0110 1110
(1) (1)
No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal
1001 0001 1010 0010 1111
(1)
(S XOR V) = 0 (S XOR V) = 1 (Z OR (S XOR V)) = 0 (Z OR (S XOR V)) = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1
0111 (1) 1011 0011
NOTES: 1. Indicate condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
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INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Shorthand www..com notation of the instruction's operation -- Textual description of the instruction's effect -- Specific flag settings affected by the instruction -- Detailed description of the instruction's format, execution time, and addressing mode(s) -- Programming example(s) explaining how to use the instruction
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SAM88RCRI INSTRUCTION SET
ADC --
ADC Operation:
Add With Carry
dst,src dst dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 12 13 14 15 16 Addr Mode dst src r r R R R r lr R IR IM C: Z: S: V:
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Flags:
Format:
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H R1 = 14H, R2 = 03H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
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SAM88RI INSTRUCTION SET
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ADD --
ADD Operation:
Add
dst,src dst dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
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Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if a carry from the low-order nibble occurred.
C: Z: S: V:
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 02 03 04 05 06 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.
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SAM88RCRI INSTRUCTION SET
AND --
AND Operation:
Logical AND
dst,src dst dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected.
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Flags:
C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 52 53 54 55 56 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
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SAM88RI INSTRUCTION SET
S3C9228/P9228
CALL --
CALL Operation:
Call Procedure
dst SP @SP SP @SP PC SP - 1 PCL SP -1 PCH dst
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The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. No flags are affected.
Flags: Format:
Bytes opc opc dst dst 3 2
Cycles 14 12
Opcode (Hex) F6 F4
Addr Mode dst DA IRR
Examples:
Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H: CALL 1521H SP = 0B0H (Memory locations 00H = 1AH, 01H = 4AH, where 4AH is the address that follows the instruction.) SP = 0B0H (00H = 1AH, 01H = 49H)
CALL
@RR0
In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 01H (because the two-byte instruction format was used). The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed.
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SAM88RCRI INSTRUCTION SET
CCF --
CCF Operation:
Complement Carry Flag
C NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
Flags:
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C: Complemented. No other flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) EF
Example:
Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.
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S3C9228/P9228
CLR --
CLR Operation:
Clear
dst dst "0" The destination location is cleared to "0".
Flags: Format: www..com
No flags are affected.
Bytes opc dst 2
Cycles 4 4
Opcode (Hex) B0 B1
Addr Mode dst R IR
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H @01H Register 00H = 00H Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.
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SAM88RCRI INSTRUCTION SET
COM --
COM Operation:
Complement
dst dst NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa.
Flags:
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C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 60 61 Addr Mode dst R IR
Examples:
Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 R1 = 0F8H R1 = 07H, register 07H = 0EH
In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
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S3C9228/P9228
CP --
CP
Compare
dst,src dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.
Operation:
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Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) A2 A3 A4 A5 A6 Addr Mode dst src r r R R R r lr R IR IM
Examples:
1. Given: R1 = 02H and R2 = 03H: CP R1,R2 Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP JP INC LD R1,R2 UGE,SKIP R1 R3,R1
SKIP
In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3.
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SAM88RCRI INSTRUCTION SET
DEC --
DEC Operation:
Decrement
dst dst dst - 1 The contents of the destination operand are decremented by one.
Flags:
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Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is -128(80H) and result value is +127(7FH); cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 00 01 Addr Mode dst R IR
Examples:
Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 R1 = 02H Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.
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DI --
DI
Disable Interrupts
Operation:
SYM (2) 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
www..com Flags:
No flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) 8F
Example:
Given: SYM = 04H: DI If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register and clears SYM.2 to "0", disabling interrupt processing.
6-20
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
EI --
EI
Enable Interrupts
Operation:
SYM (2) 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
www..com Flags:
No flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) 9F
Example:
Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 04H, enabling all interrupts (SYM.2 is the enable bit for global interrupt processing).
6-21
SAM88RI INSTRUCTION SET
S3C9228/P9228
IDLE --
IDLE Operation:
Idle Operation
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.
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Flags:
No flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) 6F Addr Mode dst src - -
Example:
The instruction IDLE stops the CPU clock but not the system clock.
6-22
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
INC --
INC Operation:
Increment
dst dst dst + 1 The contents of the destination operand are incremented by one.
Flags:
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Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is -128(80H); cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes dst | opc 1 Cycles 4 Opcode (Hex) rE r = 0 to F opc dst 2 4 4 20 21 R IR Addr Mode dst r
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC INC INC R0 00H @R0 R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.
6-23
SAM88RI INSTRUCTION SET
S3C9228/P9228
IRET --
IRET Operation:
Interrupt Return
IRET FLAGS @SP SP SP + 1 PC @SP SP SP + 2 SYM(2) 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts.
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Flags: Format:
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
IRET (Normal) opc
Bytes 1
Cycles 6
Opcode (Hex) BF
6-24
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
JP --
JP JP
Jump
cc,dst dst (Conditional) (Unconditional)
Operation:
If cc is true, PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. No flags are affected.
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Flags: Format: (1)
Bytes
(2)
Cycles 8 (3)
Opcode (Hex) ccD cc = 0 to F
Addr Mode dst DA
cc | opc
dst
3
opc
dst
2
8
30
IRR
NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP JP C,LABEL_W @00H LABEL_W = 1000H, PC = 1000H PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
6-25
SAM88RI INSTRUCTION SET
S3C9228/P9228
JR --
JR
Jump Relative
cc,dst If cc is true, PC PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed (See list of condition codes).
Operation:
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The range of the relative address is +127, -128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: Format: Bytes
(1)
No flags are affected.
Cycles 6 (2)
Opcode (Hex) ccB cc = 0 to F
Addr Mode dst RA
cc | opc
dst
2
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.
6-26
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
LD --
LD
Load
dst,src dst src The contents of the source are loaded into the destination. The source's contents are unaffected.
Operation:
Flags: Format: www..com
No flags are affected.
Bytes dst | opc src 2
Cycles 4 4
Opcode (Hex) rC r8
Addr Mode dst src r r IM R
src | opc
dst
2
4
r9 r = 0 to F
R
r
opc
dst | src
2
4 4
C7 D7
r Ir
lr r
opc
src
dst
3
6 6
E4 E5
R R
R IR
opc
dst
src
3
6 6
E6 D6
R IR
IM IM
opc
src
dst
3
6
F5
IR
R
opc
dst | src
x
3
6
87
r
x [r]
opc
src | dst
x
3
6
97
x [r]
r
6-27
SAM88RI INSTRUCTION SET
S3C9228/P9228
LD --
LD
Load
(Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0,#LOOP[R1] #LOOP[R0],R1 R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 00H = 20H, register 01H = 20H Register 02H = 20H, register 00H = 01H Register 00H = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH
Examples:
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6-28
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
LDC/LDE --
LDC/LDE Operation: dst,src
Load Memory
dst src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data memory.
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Flags: Format:
No flags are affected.
Bytes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. opc opc opc opc opc opc opc opc opc opc
dst | src src | dst dst | src src | dst dst | src 2 2
Cycles
10 10 12 12 14
Opcode (Hex)
C3 D3 E7 F7 A7
Addr Mode dst src
r Irr r XS [rr] r Irr r XS [rr] r XL [rr]
XS XS XLL XLL DAL DAL DAL DAL XLH XLH DAH DAH DAH DAH
3 3 4
src | dst
4
14
B7
XL [rr]
r
dst | 0000
4
14
A7
r
DA
src | 0000
4
14
B7
DA
r
dst | 0001
4
14
A7
r
DA
src | 0001
4
14
B7
DA
r
NOTES: 1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0-1. 2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte. 3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
6-29
SAM88RI INSTRUCTION SET
S3C9228/P9228
LDC/LDE --
LDC/LDE Examples:
Load Memory
(Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC LDE LDC * R0,@RR2 R0,@RR2 @RR2,R0 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; R0 contents of program memory location 0104H R0 = 1AH, R2 = 01H, R3 = 04H R0 contents of external data memory location 0104H R0 = 2AH, R2 = 01H, R3 = 04H 11H (contents of R0) is loaded into program memory location 0104H (RR2), working registers R0, R2, R3 AE no change 11H (contents of R0) is loaded into external data memory location 0104H (RR2), working registers R0, R2, R3 AE no change R0 contents of program memory location 0061H (01H + RR4), R0 = AAH, R2 = 00H, R3 = 60H R0 contents of external data memory location 0061H (01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H 11H (contents of R0) is loaded into program memory location 0061H (01H + 0060H) 11H (contents of R0) is loaded into external data memory location 0061H (01H + 0060H) R0 contents of program memory location 1104H (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H R0 contents of external data memory location 1104H (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H R0 contents of program memory location 1104H, R0 = 88H R0 contents of external data memory location 1104H, R0 = 98H 11H (contents of R0) is loaded into program memory location 1105H, (1105H) 11H 11H (contents of R0) is loaded into external data memory location 1105H, (1105H) 11H
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LDE
@RR2,R0
LDC
R0,#01H[RR4]
LDE LDC (note) LDE LDC LDE LDC LDE LDC (note) LDE
R0,#01H[RR4] #01H[RR4],R0 #01H[RR4],R0 R0,#1000H[RR2] R0,#1000H[RR2] R0,1104H R0,1104H 1105H,R0 1105H,R0
NOTE: These instructions are not supported by masked ROM type devices.
6-30
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
LDCD/LDED --
LDCD/LDED Operation: dst,src dst src rr rr - 1
Load Memory and Decrement
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These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes `Irr' an even number for program memory and an odd number for data memory.
Flags: No flags are affected. Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E2 Addr Mode dst src r Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; ; ; ; ; ; 0CDH (contents of program memory location 1033H) is loaded into R8 and RR6 is decremented by one R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 - 1) 0DDH (contents of data memory location 1033H) is loaded into R8 and RR6 is decremented by one (RR6 RR6 - 1) R8 = 0DDH, R6 = 10H, R7 = 32H
LDED
R8,@RR6
6-31
SAM88RI INSTRUCTION SET
S3C9228/P9228
LDCI/LDEI --
LDCI/LDEI Operation: dst,src
Load Memory and Increment
dst src rr rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even for program memory and odd for data memory.
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Flags: Format:
No flags are affected.
Bytes opc dst | src 2
Cycles 10
Opcode (Hex) E3
Addr Mode dst src r Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; ; ; ; ; ; 0CDH (contents of program memory location 1033H) is loaded into R8 and RR6 is incremented by one (RR6 RR6 + 1) R8 = 0CDH, R6 = 10H, R7 = 34H 0DDH (contents of data memory location 1033H) is loaded into R8 and RR6 is incremented by one (RR6 RR6 + 1) R8 = 0DDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
6-32
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
NOP --
NOP Operation: Flags:
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No Operation
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. No flags are affected.
Format:
Bytes opc 1
Cycles 4
Opcode (Hex) FF
Example:
When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
6-33
SAM88RI INSTRUCTION SET
S3C9228/P9228
OR --
OR
Logical OR
dst,src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored.
Operation:
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Flags:
C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 42 43 44 45 46 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats.
6-34
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
POP --
POP Operation:
Pop From Stack
dst dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.
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Flags: No flags affected. Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) 50 51 Addr Mode dst R IR
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 0BCH Register 00H = 01H, register 01H = 55H, SP = 0BCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 0BBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.
6-35
SAM88RI INSTRUCTION SET
S3C9228/P9228
PUSH --
PUSH Operation:
Push To Stack
src SP SP - 1 @SP src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. No flags are affected.
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Flags: Format:
Bytes opc src 2
Cycles 8 8
Opcode (Hex) 70 71
Addr Mode dst R IR
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H: PUSH PUSH 40H @40H Register 40H = 4FH, stack register 0BFH = 4FH, SP = 0BFH Register 40H = 4FH, register 4FH = 0AAH, stack register 0BFH = 0AAH, SP = 0BFH
In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP points to location 0BFH.
6-36
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
RCF --
RCF Operation:
Reset Carry Flag
RCF C0 The carry flag is cleared to logic zero, regardless of its previous value.
Flags:
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C: Cleared to "0". No other flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) CF
Example:
Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
6-37
SAM88RI INSTRUCTION SET
S3C9228/P9228
RET --
RET Operation:
Return
PC @SP SP SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. No flags are affected.
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Flags: Format:
Bytes opc 1
Cycles 8
Opcode (Hex) AF
Example:
Given: SP = 0BCH, (SP) = 101AH, and PC = 1234: RET PC = 101AH, SP = 0BEH
The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 0BEH.
6-38
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
RL --
RL
Rotate Left
dst C dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
Operation:
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7 C
0
Flags:
Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 90 91 Addr Mode dst R IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.
6-39
SAM88RI INSTRUCTION SET
S3C9228/P9228
RLC --
RLC Operation:
Rotate Left Through Carry
dst dst (0) C C dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
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7 C
0
Flags:
C: Z: S: V:
Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 10 11 Addr Mode dst R IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
6-40
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
RR
RR
-- Rotate Right
dst C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Operation:
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7 C
0
Flags:
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
C: Z: S: V:
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) E0 E1 Addr Mode dst R IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
6-41
SAM88RI INSTRUCTION SET
S3C9228/P9228
RRC --
RRC Operation:
Rotate Right Through Carry
dst dst (7) C C dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB).
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7 C
0
Flags:
C: Z: S: V:
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) C0 C1 Addr Mode dst R IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".
6-42
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
SBC --
SBC Operation:
Subtract With Carry
dst,src dst dst - src - c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. C: Z: S: V: Set if a borrow occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign
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Flags:
f the result is the same as the sign of the source; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 32 33 34 35 36 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H,register 02H = 03H, register 03H = 0AH Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.
6-43
SAM88RI INSTRUCTION SET
S3C9228/P9228
SCF --
SCF Operation:
Set Carry Flag
C1 The carry flag (C) is set to logic one, regardless of its previous value.
Flags:
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C: Set to "1". No other flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) DF
Example:
The statement SCF sets the carry flag to logic one.
6-44
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
SRA --
SRA Operation:
Shift Right Arithmetic
dst dst (7) dst (7) C dst (0) dst (n) dst (n + 1), n = 0-6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6.
7 C 6 0
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Flags:
C: Z: S: V: D: H:
Set if the bit shifted from the LSB position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) D0 D1 Addr Mode dst R IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H Register 00H = 0CD, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H.
6-45
SAM88RI INSTRUCTION SET
S3C9228/P9228
STOP --
STOP Operation:
Stop Operation
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The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed.
Flags: No flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) 7F Addr Mode dst src - -
Example:
The statement STOP halts all microcontroller operations.
6-46
S3C9228/P9228
SAM88RCRI INSTRUCTION SET
SUB --
SUB Operation:
Subtract
dst,src dst dst - src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
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Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow".
C: Z: S: V:
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 22 23 24 25 26 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB SUB SUB SUB SUB SUB R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H R1 = 0FH, R2 = 03H R1 = 08H, R2 = 03H Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H Register 01H = 91H; C, S, and V = "1" Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1.
6-47
SAM88RI INSTRUCTION SET
S3C9228/P9228
TCM --
TCM Operation:
Test Complement Under Mask
dst,src (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
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Flags:
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 62 63 64 65 66 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM TCM TCM TCM TCM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 R0 = 0C7H, R1 = 02H, Z = "1" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.
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S3C9228/P9228
SAM88RCRI INSTRUCTION SET
TM --
TM
Test Under Mask
dst,src dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.
Operation:
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Flags:
C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 72 73 74 75 76 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM TM TM TM TM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C7H, R1 = 02H, Z = "0" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "0" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.
6-49
SAM88RI INSTRUCTION SET
S3C9228/P9228
XOR -- Logical Exclusive OR
XOR Operation: dst,src dst dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored.
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C: Z: S: V: D: H:
Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) B2 B3 B4 B5 B6 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.
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S3C9228/P9228
CLOCK CIRCUITS
7
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CLOCK CIRCUITS
OVERVIEW
The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency, is determined by CLKCON register settings.
SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: -- Crystal, ceramic resonator, RC oscillation source (main clock only), or an external clock -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) -- Clock circuit control register, CLKCON -- Oscillator control register, OSCCON CPU CLOCK NOTATION In this document, the following notation is used for descriptions of the CPU clock: fx main clock fxt sub clock fxx selected system clock
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CLOCK CIRCUITS
S3C9228/P9228
MAIN OSCILLATOR CIRCUITS
SUB OSCILLATOR CIRCUITS
XIN
XTIN
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XOUT 32.768 kHz
XTOUT
Figure 7-1. Crystal/Ceramic Oscillator
Figure 7-4. Crystal/Ceramic Oscillator
XIN
XTIN
XOUT XTOUT
Figure 7-2. External Oscillator
Figure 7-5. External Oscillator
XIN R XOUT
Figure 7-3. RC Oscillator
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S3C9228/P9228
CLOCK CIRCUITS
CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: -- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When the fx is selected as system clock). -- In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt structure, timer A/B, and watch timer. Idle mode is released by a reset or by an external or internal interrupts.
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Stop Release INT
Main-System Oscillator Circuit
fX
fXT
Sub-system Oscillator Circuit
Watch Timer LCD Controller
Selector 1 fXX Stop
OSCCON.3 OSCCON.0 STOP OSC inst. STPCON 1/1 1/8-1/4096 Frequency Dividing Circuit 1/2 1/8 1/16 Basic Timer Timer/Counters Watch Timer LCD Controller SIO A/D Converter Stop OSCCON.2
CLKCON.4-.3
Selector 2 CPU
Figure 7-6. System Clock Circuit Diagram
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CLOCK CIRCUITS
S3C9228/P9228
SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following functions: -- Oscillator IRQ wake-up function enable/disable -- Oscillator frequency divide-by value CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release (This is called the "IRQ wake-up" function). The IRQ "wake-up" enable bit is CLKCON.7. www..com After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the fx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fx, fx/2, or fx/8 by setting the CLKCON, and you can change system clock from main clock to sub clock by setting the OSCCON.
System Clock Control Register (CLKCON) D4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Oscillator IRQ wake-up enable bit: 0 = Enable IRQ for main oscillator wake-up function in power down mode 1 = Disable IRQ for main oscillator wake-up function in power down mode
Not used for S3C92228 (must keep always "0") Divide-by selection bits for CPU clock frequency: 00 = fxx/16 01 = fxx/8 10 = fXx/2 11 = fxx
Not used for S3C9228 (must keep always "0")
Figure 7-7. System Clock Control Register (CLKCON)
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S3C9228/P9228
CLOCK CIRCUITS
OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions: -- System clock selection -- Main oscillator control -- Sub oscillator control
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OSCCON.0 register settings select Main clock or Sub clock as system clock. Main clock is selected for system clock because the reset value of OSCCON.0 is "0". The main oscillator can be stopped or run by setting OSCCON.3. The sub oscillator can be stopped or run by setting OSCCON.2.
Oscillator Control Register (OSCCON) D3H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
System clock selection bit: 0 = Main oscillator select 1 = Sub oscillator select Not used for S3C9228 Not used for S3C9228 Sub oscillator control bit: 0 = Sub oscillator RUN 1 = Sub oscillator STOP Main oscillator control bit: 0 = Main oscillator RUN 1 = Main oscillator STOP
Figure 7-8. Oscillator Control Register (OSCCON)
7-5
CLOCK CIRCUITS
S3C9228/P9228
SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the system clock. OSCCON .3 start or stop main clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4-.3 control the frequency divider circuit, and divide the selected fxx clock by 1, 2, 8, or 16.
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For example, you are using the default system clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set OSCCON.0 to "1", take a delay, and OSCCON.3 to "1" sequently. This switches the clock from fx to fxt and stops main clock oscillation. The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main clock by setting OSCCON.0 to "0".
+PROGRAMMING TIP -- Switching the CPU clock
1. This example shows how to change from the main clock to the sub clock: MA2SUB OR CALL OR RET OSCCON,#01H DLY16 OSCCON,#08H ; Switches to the sub clock ; Delay 16ms ; Stop the main clock oscillation
2. This example shows how to change from sub clock to main clock: SUB2MA AND CALL AND RET LD NOP DEC JR RET OSCCON,#0F7H DLY16 OSCCON,#0FEH R0,#20H R0 NZ,DEL ; Start the main clock oscillation ; Delay 16 ms ; Switch to the main clock
DLY16 DEL
7-6
S3C9228/P9228
CLOCK CIRCUITS
STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: -- Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B".
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Stop Control Register (STPCON) E0H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
STOP control bits: 10100101 = Enable STOP instruction Other values = Disable STOP instruction
Figure 7-9. STOP Control Register (STPCON)
+PROGRAMMING TIP -- How to Use Stop Instruction
This example shows how to go STOP mode when a main clock is selected as the system clock. LD STOP NOP NOP NOP LD STOPCON,#1010010B ; Enable STOP instruction ; Enter STOP mode
STOPCON,#00000000B
; Release STOP mode ; Disable STOP instruction
7-7
CLOCK CIRCUITS
S3C9228/P9228
NOTES
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7-8
S3C9228/P9228
RESET and POWER-DOWN
8
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RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C9228/P9228 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a reset operation is 1 millisecond. Whenever a reset occurs during normal operation (that is, when both VDD and RESET are High level), the RESET pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values (see Table 8-1). In summary, the following sequence of events occurs during a reset operation: -- All interrupts are disabled. -- The watchdog function (basic timer) is enabled. -- The P0.0-P0.3, P1, and P2.2-P2.3 are set to schmitt trigger input mode and all pull-up resistors are disabled for the I/O port pin circuits. -- Peripheral control and data registers are disabled and reset to their default hardware values. -- The program counter (PC) is loaded with the program reset address in the ROM, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed. NOTE To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON.
8-1
RESET and POWER-DOWN
S3C9228/P9228
POWER-DOWN MODES
STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But the watch timer and LCD controller will not halted in stop mode if the sub clock is selected as watch timer clock source. The data stored in the internal register file are retained in stop mode. Stop mode can be released in one of three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected as clock source of watch timer), or by an external interrupt.
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Example:
LD STOP NOP NOP NOP LD
STOPCON,#10100101B
STOPCON,#00000000B NOTES
1. Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage. 2. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. 3. To enable/disable STOP instruction, the STOPCON register should be written with 10100101B/other values before/after stop instruction. Using RESET to Release Stop Mode Stop mode is released when the RESET signal goes active (Low level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. When the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H. Using an External Interrupt to Release Stop Mode External interrupts can be used to release stop mode. For the S3C9228 microcontroller, we recommend using the INT interrupt, P0, P1, and P3.
8-2
S3C9228/P9228
RESET and POWER-DOWN
Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release stop mode. That is, you had better use the idle instruction instead of stop one when sub clock is selected as the system clock. Please note the following conditions for Stop mode release: -- If you release stop mode using an internal or external interrupt, the current values in system and peripheral control registers are unchanged.
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-- If you use an internal or external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering stop mode. -- If you use an interrupt to release stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains unchanged and the currently selected clock value is used. -- The internal or external interrupt is serviced when the stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated stop mode is executed.
IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but the following peripherals, which remain active: -- Interrupt logic -- Basic timer -- Timer 1 (Timer A and B) -- Watch timer -- LCD controller I/O port pins retain the mode (input or output) they had at the time Idle mode was entered. Idle Mode Release You can release Idle mode in one of two ways: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the hardware reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the only way you can release Idle mode. 2. Activate any enabled interrupt -- internal or external. When you use an interrupt to release Idle mode, the 2-bit CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately following the one which initiated Idle mode is executed.
8-3
RESET and POWER-DOWN
S3C9228/P9228
HARDWARE RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values: -- A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively. -- An 'x' means that the bit value is undefined following RESET.
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-- A dash ('-') means that the bit is either not used or not mapped.
Table 8-1. Register Values after RESET Register Name Mnemonic Address Dec Timer B Control Register Timer 1/A Control Register Timer B Data Register Timer A Data Register Timer B Counter Timer A Counter A/D Converter Control Register A/D Converter Data Register (high byte) A/D Converter Data Register (low byte) Oscillator Control Register System Clock Control Register System Flags Register Interrupt Pending Register 1 Interrupt Pending Register 2 LCD Port Control Register Stack Pointer Watch Timer Control Register Basic Timer Control Register Basic Timer Counter TBCON TACON TBDATA TADATA TBCNT TACNT ADCON ADDATAH ADDATAL OSCCON CLKCON FLAGS INTPND1 INTPND2 LOPT SP WTCON BTCON BTCNT 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 220 221 Hex BAH BBH BCH BDH BEH BFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DCH DDH 7 - 0 1 1 0 0 - X - - 0 X 0 - - X 0 0 0 6 0 0 1 1 0 0 - X - - 0 X 0 - 0 X 0 0 0 Bit Values after RESET 5 0 0 1 1 0 0 0 X - - 0 X 0 0 0 X 0 0 0 4 0 0 1 1 0 0 0 X - - 0 X 0 0 0 X 0 0 0 3 0 0 1 1 0 0 0 X - 0 0 - 0 0 0 X 0 0 0 2 0 0 1 1 0 0 0 X - 0 0 - 0 0 0 X 0 0 0 1 0 0 1 1 0 0 0 X X - 0 - 0 0 0 X 0 0 0 0 - - 1 1 0 0 0 X X 0 0 - 0 0 0 X - 0 0
Locations B8H-B9H are not mapped.
Locations DBH is not mapped.
Locations DEH is not mapped.
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S3C9228/P9228
RESET and POWER-DOWN
Table 8-1. Register Values after RESET (Continued) Register Name Mnemonic Address Dec System Mode Register STOP Control Register SIO Control Register SIO Data Register
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Bit Values after RESET 7 - 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 - - - 0 - - - - - 0 0 0 0 0 - 6 - 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 - - - 0 - - - - - 0 0 0 0 0 0 5 - 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 - - - 0 - - - - - 0 0 0 0 0 0 4 - 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 - - - 0 - - - - - 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Hex DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH
SYM STPCON SIOCON SIODATA SIOPS P0 P1 P2 P3 P4 P5 P6 P0CON P0PUR P0INT P0EDGE P1CON P1PUR P1INT P1EDGE P2CON P2PUR P3CON P3PUR P3INT P3EDGE P4CONH P4CONL P5CONH P5CONL P6CON LMOD
223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254
Register
Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 0 Control Register Port 0 Pull-up Resistors Enable Register Port 0 Interrupt Control Register Port 0 Interrupt Edge Selection Register Port 1 Control Register Port 1 Pull-up Resistors Enable Register Port 1 Interrupt Control Register Port 1 Interrupt Edge Selection Register Port 2 Control Register Port 2 Pull-up Resistors Enable Register Port 3 Control Register Port 3 Pull-up Resistors Enable Register Port 3 Interrupt Control Register Port 3 Interrupt Edge Selection Register Port 4 Control Register (High Byte) Port 4 Control Register (High Byte) Port 5 Control Register (High Byte) Port 5 Control Register (High Byte) Port 6 Control Register LCD Mode Register
Location FFH is not mapped.
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RESET and POWER-DOWN
S3C9228/P9228
NOTES
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S3C9228/P9228
I/O PORTS
9
OVERVIEW
Port 0
I/O PORTS
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microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the S3C9228/P9228 except P0.4 and P0.5 can be configured to input or output mode. All LCD signal pins are shared with normal I/O ports. Table 9-1 gives you a general overview of S3C9228 I/O port functions. Table 9-1. S3C9228 Port Configuration Overview Configuration Options 1-bit programmable I/O port except P0.4 and P0.5. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. The P0.4 and P0.5 are only push-pull output ports. Alternatively P0.0-P0.3 can be used as input for external interrupts INT and can be used as TAOUT, T1CLK, and BUZ. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P1 can be used as input for external interrupts INT and can be used as AD0-AD3. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P2.0 and P2.1 can be used as outputs for LCD segment signals and P2.0-P2.2 can be used as SCK, SO, and SI. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P3 can be used as input for external interrupts INTP and can be used as outputs for LCD segment signals. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P4 can be used as outputs for LCD segment signals. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P5.0-P5.3 can be used as outputs for LCD segment signals and P5.4-P5.7 can be used as outputs for LCD common or segment signals. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P6 can be used as outputs for LCD common signals.
1
2
3
4
5
6
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I/O PORTS
S3C9228/P9228
PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port 0 data register Port www..com 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Mnemonic P0 P1 P2 P3 P4 P5 P6 Decimal 228 229 230 231 232 233 234 Hex E4H E5H E6H E7H E8H E9H EAH R/W R/W R/W R/W R/W R/W R/W R/W
S3C9228 I/O Port Data Register Format (n = 0-6) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
Pn.1
Pn.0
Figure 9-1. S3C9228 I/O Port Data Register Format
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S3C9228/P9228
I/O PORTS
PORT 0 Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P0.0-P0.3): TAOUT,T1CLK, BUZ, INT -- High-nibble pins (P0.4-P0.5): push-pull output ports (only 44-QFP package) Port 0 Control register (P0CON)
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Port 0 has a 8-bit control register: P0CON for P0.0-P0.3. A reset clears the P0CON register to "00H", configuring pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 0 control register must also be enabled in the associated peripheral module. Port 0 Pull-up Resistor Control Register (P0PUR) Using the port 0 pull-up resistor control register, P0PUR (ECH, page 0), you can configure pull-up resistors to individual port 0 pins. Port 0 Interrupt Enable, Pending, and Edge Selection Registers (P0INT, INTPND1.3-.0, P0EDGE) To process external interrupts at the port 0 pins, three additional control registers are provided: the port 0 interrupt enable register P0INT (EDH, page 0), the port 0 interrupt pending bits INTPND1.3-.0 (D6H, page 0), and the port 0 interrupt edge selection register P0EDGE (EEH, page 0). The port 0 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND1.3-.0 register at regular intervals. When the interrupt enable bit of any port 0 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND1 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND1 bit.
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I/O PORTS
S3C9228/P9228
Port 0 Control Register (P0CON) EBH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P0.3/BUZ (INT)
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P0.2 (INT)
P0.1/T1CLK P0.0/TAOUT (INT) (INT)
P0CON bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (T1CLK) Push-pull output mode N-channel open-drain output mode Alternative function (TAOUT, BUZ)
Figure 9-2. Port 0 Control Register (P0CON)
Port 0 Interrupt Control Register (P0INT) EDH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT)
P0INT bit configuration settings: 0 1 Disable interrupt Enable interrupt
Figure 9-3. Port 0 Interrupt Control Register (P0INT)
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S3C9228/P9228
I/O PORTS
Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT)
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INTPND1 bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)
Port 0 Interrupt Edge Selection Register (P0EDGE) EEH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT)
P0EDGE bit configuration settings: 0 1 Falling edge detection Rising edge detection
Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)
Port 0 Pull-up Control Register (P0PUR) ECH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P0.3
P0.2
P0.1
P0.0
P0PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor
Figure 9-6. Port 0 Pull-up Control Register (P0PUR)
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I/O PORTS
S3C9228/P9228
PORT 1 Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0. P1.0-P1.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P1.0-P1.3): AD0-AD3, INT Port 1 Control Register (P1CON)
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Port 1 has a 8-bit control register: P1CON for P1.0-P1.3. A reset clears the P1CON register to "00H", configuring mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 1 control register must also be enabled in the associated peripheral module. Port 1 Pull-up Resistor Control Register (P1PUR) Using the port 1 pull-up resistor control register, P1PUR (F0H, page 0), you can configure pull-up resistors to individual port 1 pins. Port 1 Interrupt Enable, Pending, and Edge Selection Registers (P1INT, INTPND1.7-.4, P1EDGE) To process external interrupts at the port 1 pins, three additional control registers are provided: the port 1 interrupt enable register P1INT (F1H, page 0), the port 1 interrupt pending bits INTPND1.7-.4 (D6H, page 0), and the port 1 interrupt edge selection register P1EDGE (F2H, page 0). The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND1.7-.4 register at regular intervals. When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND1 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND1 bit.
Port 1 Control Register (P1CON) EFH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.3/AD3 (INT)
P1.2/AD2 (INT)
P1.1/AD1 (INT)
P1.0/AD0 (INT)
P1CON bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Alternative function (AD0,AD1, AD2, AD3)
Figure 9-7. Port 1 Control Register (P1CON)
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I/O PORTS
Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT)
P1INT bit configuration settings: 0 1 Disable interrupt Enable interrupt
Figure 9-8. Port 1 Interrupt Control Register (P1INT)
Port 1 Interrupt Pending Bits (INTPND1.7-.4) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND1 bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
Figure 9-9. Port 1 Interrupt Pending Bits (INTPND1.7-.4)
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I/O PORTS
S3C9228/P9228
Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT)
P1EDGE bit configuration settings: 0 1 Falling edge detection Rising edge detection
Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE)
Port 1 Pull-up Control Register (P1PUR) F0H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P1.3
P1.2
P1.1
P1.0
P1PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor
Figure 9-11. Port 1 Pull-up Control Register (P1PUR)
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S3C9228/P9228
I/O PORTS
PORT 2 Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0. P2.0-P2.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P2.0-P2.3): SCK, SO, SI, SEG0-SEG1 Port 2 Control Register (P2CON)
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Port 2 has a 8-bit control register: P2CON for P2.0-P2.3. A reset clears the P2CON register to "00H", configuring mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 2 control register must also be enabled in the associated peripheral module. Port 2 Pull-up Resistor Control Register (P2PUR) Using the port 2 pull-up resistor control register, P2PUR (F4H, page 0), you can configure pull-up resistors to individual port 2 pins.
Port 2 Control Register (P2CON) F3H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P2.3
P2.2/SI
P2.1/SO/SEG0 P2.0/SCK/SEG1
P2CON bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (SI,SCK) Push-pull output mode N-channel open-drain output mode Alternative function (SCK, SO)
Figure 9-12. Port 2 Control Register (P2CON)
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I/O PORTS
S3C9228/P9228
Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P2.3
P2.2
P2.1
P2.0
P2PUR bit configuration settings:
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0 1
Disable pull-up resistor Enable pull-up resistor
Figure 9-13. Port 2 Pull-up Control Register (P2PUR)
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S3C9228/P9228
I/O PORTS
PORT 3 Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0. P3.0-P3.1 can serve as inputs (with or without pullup, and high impedance input), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P3.0-P3.1): SEG2-SEG3, INTP Port 3 Control Register (P3CON)
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a 8-bit control register: P3CON for P3.0-P3.1. A reset clears the P3CON register to "00H", configuring pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain). Port 3 Pull-up Resistor Control Register (P3PUR) Using the port 3 pull-up resistor control register, P3PUR (F6H, page 0), you can configure pull-up resistors to individually port 3 pins. Port 3 Interrupt Enable, Pending, and Edge Selection Registers(P3INT, INTPND2.5-.4, P3EDGE) To process external interrupts at the port 3 pins, three additional control registers are provided: the port 3 interrupt enable register P3INT (F7H, page 0), the port 3 interrupt pending bits INTPND2.5-.4 (D7H, page 0), and the port 3 interrupt edge selection register P3EDGE (F8H, page 0). The port 3 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND2.5-.4 register at regular intervals. When the interrupt enable bit of any port 3 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND2 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND2 bit.
Port 3 Control Register (P3CON) F5H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P3.1/SEG2 (INTP)
P3.0/SEG3 (INTP)
P3CON bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Not available
Figure 9-14. Port 3 Control Register (P3CON)
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I/O PORTS
S3C9228/P9228
Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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P3.1 P3.0 (INTP) (INTP)
P3INT bit configuration settings: 0 1 Disable interrupt Enable interrupt
Figure 9-15. Port 3 Interrupt Control Register (P3INT)
Port 3 Interrupt Pending Bits (INTPND2.5-.4) D7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P3.0 (INTP)
SIO
Timer 1/A Timer B
P3.0 (INTP) Watch Timer INTPND2 bit configuration settings: 0 1
No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read)
Figure 9-16. Port 3 Interrupt Pending Bits (INTPND2.5-.4)
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I/O PORTS
Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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P3.1 P3.0 (INTP) (INTP)
P3EDGE bit configuration settings: 0 1 Falling edge detection Rising edge detection
Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE)
Port 3 Pull-up Control Register (P3PUR) F6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used P3PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor
P3.1
P3.0
Figure 9-18. Port 3 Pull-up Control Register (P3PUR)
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I/O PORTS
S3C9228/P9228
PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: -- Low-nibble pins (P4.0-P4.3): SEG4-SEG7 -- High-nibble pins (P4.4-P4.7): SEG8-SEG11 Port 4 Control Registers (P4CONH, P4CONL)
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Port 4 has two 8-bit control registers: P4CONH for P4.4-P4.7 and P4CONL for P4.0-P4.3. A reset clears the P4CONH and P4CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode.
Port 4 Control Register, High Byte (P4CONH) F9H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P4.7/SEG11 P4.6/SEG10 P4.5/SEG9
P4.4/SEG8
P4CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-19. Port 4 High-Byte Control Register (P4CONH)
Port 4 Control Register, Low Byte (P4CONL) FAH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P4.3/SEG7
P4.2/SEG6
P4.1/SEG5
P4.0/SEG4
P4CONL bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-20. Port 4 Low-Byte Control Register (P4CONL)
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I/O PORTS
PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: -- Low-nibble pins (P5.0-P5.3): SEG12-SEG15 -- High-nibble pins (P5.4-P5.7): SEG16-SEG19, COM4-COM7 Port 5 Control Registers (P5CONH, P5CONL)
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Port 5 has two 8-bit control registers: P5CONH for P5.4-P5.7 and P4CONL for P5.0-P5.3. A reset clears the P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode.
Port 5 Control Register, High Byte (P5CONH) FBH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P5.6/SEG18/COM5 P5.7/SEG19/COM4
P5.4/SEG16/COM7
P5.5/SEG17/COM6
P5CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-21. Port 5 High-Byte Control Register (P5CONH)
Port 5 Control Register, Low Byte (P5CONL) FCH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P5.3/SEG15 P5.2/SEG14 P5.1/SEG13 P5.0/SEG12 P5CONL bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-22. Port 5 Low-Byte Control Register (P5CONL)
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I/O PORTS
S3C9228/P9228
PORT 6 Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: -- Low-nibble pins (P6.0-P6.3): COM0-COM3 Port 6 Control Register (P6CON)
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Port 6 has a 8-bit control register: P6CONH for P6.0-P6.3. A reset clears the P6CON registers to "00H", all pins to input mode. You use control registers setting to select input or output mode.
Port 6 Control Register, Low Byte (P6CON) FDH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P6.3/COM0 P6.2/COM1 P6.1/COM2
P6.0/COM3
P6CON bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up
Figure 9-23. Port 6 Control Register (P6CON)
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S3C9228/P9228 (Preliminary Spec)
BASIC TIMER
10
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BASIC TIMER
OVERVIEW
Basic timer (BT) can be used in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer
-- 8-bit basic timer counter, BTCNT (DDH, read-only) -- Basic timer control register, BTCON (DCH, read/write)
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BASIC TIMER
S3C9228/P9228 (Preliminary Spec)
BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addressable using Register addressing mode. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register control bits BTCON.7-BTCON.4.
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The 8-bit basic timer counter, BTCNT (page 0, DDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for the basic timer input clock and timer counters, you write a "1" to BTCON.0.
Basic TImer Control Register (BTCON) DCH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Watchdog function enable bits: 1010B = Disable watchdog timer Other Value = Enable watchdog timer
Divider clear bit for basic timer and timer counters: 0 = No effect 1 = Clear divider Basic timer counter clear bit: 0 = No effect 1 = Clear BTCNT
Basic timer input clock selection bits: 00 = fXX/4096 01 = fXX/1024 10 = fXX/128 11 = fXX/16
Figure 10-1. Basic Timer Control Register (BTCON)
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S3C9228/P9228 (Preliminary Spec)
BASIC TIMER
BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock. A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must www..com be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when stop mode is released: 1. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. 4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.
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BASIC TIMER
S3C9228/P9228 (Preliminary Spec)
RESET or STOP Bit 1 Bits 3, 2 Data Bus fXX/4096
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Basic Timer Control Register (Write '1010xxxxB' to Disable) Clear 8-Bit Up Counter (BTCNT, Read-Only) Start the CPU (note)
fXX/1024 DIV fXX/128 fXX/16 R MUX OVF RESET
fXX
Bit 0
NOTE:
During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
Figure 10-2. Basic Timer Block Diagram
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TIMER 1
11
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TIMER 1
ONE 16-BIT TIMER MODE (TIMER 1)
The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers. -- One 16-bit timer mode (Timer 1) -- Two 8-bit timers mode (Timer A and B) OVERVIEW The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate TACON setting. Timer 1 has the following functional components: -- Clock frequency divider (fxx divided by 512, 256, 64, 8, or 1, fxt, and T1CLK: External clock) with multiplexer -- 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA) -- Timer 1 match interrupt generation -- Timer 1 control register, TACON (page 0, BBH, read/write) FUNCTION DESCRIPTION Interval Timer Function The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT). The T1INT pending condition should be cleared by software when it has been serviced. Even though T1INT is disabled, the application's service routine can detect a pending condition of T1INT by the software and execute it's sub-routine. When this case is used, the T1INT pending bit must be cleared by the application sub-routine by writing a "0" to the INTPND2.0 pending bit. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer 1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt and clears the counter. If, for example, you write the value 32H and 10H to TADATA and TBDATA, respectively, and 8EH to TACON, the counter will increment until it reaches 3210H. At this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes.
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TIMER 1
S3C9228/P9228
Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to -- Enable the timer 1 operating (interval timer) -- Select the timer 1 input clock frequency -- Clear the timer 1 counter, TACNT and TBCNT -- Enable the timer 1 interrupt
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TACON is located in page 0, at address BBH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during normal operation by writing a "1" to TACON.3. To enable the timer 1 interrupt, you must write TACON.7, TACON.2, and TACON.1 to "1". To generate the exact time interval, you should write TACON.3 and INTPND2.0, which cleared counter and interrupt pending bit. To detect an interrupt pending condition when T1INT is disabled, the application program polls pending bit, INTPND.2.0. When a "1" is detected, a timer 1 interrupt is pending. When the T1INT subroutine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, INTPND2.0.
Timer A Control Register (TACON) BBH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
One 16-bit timer or Two 8-bit timers mode: 0 = Two 8-bit timers mode (Timer A/B) 1 = One 16-bit timer mode (Timer 1)
Not used Timer 1/A interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt
Timer 1/A clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = T1CLK (external clock) 111 = Not available
Timer 1/A counter enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer 1/A counter clear bit: 0 = No affect 1 = Clear the timer 1/A counter (when write)
Figure 11-1. Timer 1 Control Register (TACON)
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S3C9228/P9228
TIMER 1
BTCON.0
TACON.6-.4
R
1/512 1/256 TACON.2 Data Bus M U X 16-Bit Comparator LSB MSB TBDATA TADATA Buffer Buffer LSB TBCNT TACON.3 MSB TACNT R Match INTPND2.0 TAOUT T1INT Clear TACON.1
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(XIN or XTIN)
DIV
1/64 1/8 1/1
fxt T1CLK
Match Signal Counter clear signal TBDATA TADATA Data Bus
NOTE:
When one 16-bit timer mode (TACON.7 <- "1": Timer 1)
Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)
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TIMER 1
S3C9228/P9228
TWO 8-BIT TIMERS MODE (TIMER A and B)
OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively. Timer A and B have the following functional components: -- Clock frequency divider with multiplexer - fxx www..comdivided by 512, 256, 64, 8 or 1, fxt, and T1CLK (External clock) for timer A - fxx divided by 512, 256, 64, 8 or 1, and fxt for timer B -- 8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA) -- Timer A have I/O pin for match output (TAOUT) -- Timer A match interrupt generation -- Timer A control register, TACON (page 0, BBH, read/write) -- Timer B match interrupt generation -- Timer B control register, TBCON (page 0, BAH, read/write) Timer A and B Control Register (TACON, TBCON) You use the timer A and B control register, TACON and TBCON, to -- Enable the timer A (interval timer mode) and B operating (interval timer mode) -- Select the timer A and B input clock frequency -- Clear the timer A and B counter, TACNT and TBCNT -- Enable the timer A and B interrupt
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S3C9228/P9228
TIMER 1
TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer B counter at any time during normal operation by writing a "1" to TBCON.3.
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To enable the timer A interrupt (TAINT) and timer B interrupt (TBINT), you must write TACON.7 to "0", TACON.2 (TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should write TACON.3 (TBCON.3) and INTPND2.0 (INTPND2.1), which cleared counter and interrupt pending bit. To detect an interrupt pending condition when TAINT and TBINT is disabled, the application program polls pending bit, INTPND2.0 and INTPND2.1. When a "1" is detected, a timer A interrupt (TAINT) and timer B interrupt (TBINT) is pending. When the TAINT and TBINT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer A and B interrupt pending bit, INTPND2.0 and INTPND2.1.
Timer A Control Register (TACON) E4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
One 16-bit timer or Two 8-bit timers mode: 0 = Two 8-bit timers mode (Timer A/B) 1 = One 16-bit timer mode (Timer 1) Timer A clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = fxt (sub clock) 110 = T1CLK (external clock) 111 = Not available
Not used Timer A interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer A counter enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer A counter clear bit: 0 = No affect 1 = Clear the timer A counter (when write)
Figure 11-3. Timer A Control Register (TACON)
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TIMER 1
S3C9228/P9228
Timer B Control Register (TBCON) BAH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
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Not used
Timer B match interrupt enable bit: Timer B clock selection bits: 0 = Disable match interrupt 000 = fxx/512 1 = Enable match interrupt 001 = fxx/256 010 = fxx/64 011 = fxx/8 Timer B count enable bit: 100 = fxx (system clock) 0 = Disable counting operating 101 = fxt (sub clock) 1 = Enable counting operating 110 = Not available 111 = Not available Timer B counter clear bit: 0 = No effect 1 = Clear the timer B counter (when write)
Figure 11-4. Timer B Control Register (TBCON)
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S3C9228/P9228
TIMER 1
FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.0) and the timer B match interrupt pending condition (INTPND2.1) must be cleared by software in the application's interrupt service by means of writing a "0" to the INTPND2.0 and INTPND2.1 interrupt pending bit. Even though www..com TAINT and TBINT are disabled, the application's service routine can detect a pending condition of TAINT and TBINT by the software and execute it's sub-routine. When this case is used, the TAINT and TBINT pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit INTPND2.0 and INTPND2.1. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer A or timer B reference data registers, TADATA or TBDATA. The match signal generates corresponding match interrupt and clears the counter. If, for example, you write the value 20H to TADATA and 0EH to TACON, the counter will increment until it reaches 20H. At this point, the timer A interrupt request is generated, the counter value is cleared, and counting resumes and you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will increment until it reaches 10H. At this point, TB interrupt request is generated, the counter value is cleared and counting resumes.
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TIMER 1
S3C9228/P9228
BTCON.0
TACON.6-.4
R
1/512 1/256 TACON.2 Data Bus M U X 8-Bit Comparator LSB MSB LSB TACON.3 MSB Clear TACON.1 Match INTPND2.0 TAOUT TAINT
fxx
(XIN or XTIN)
DIV
1/64 1/8 1/1
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TACNT (8-Bit Up-Counter) R
fxt T1CLK/ P0.1
TADATA Buffer
Match Signal Counter Clear Signal TADATA Register Data Bus
NOTE:
When two 8-bit timers mode (TACON.7 <- "0": Timer A)
Figure 11-5. Timer A Block Diagram(Two 8-bit Timers Mode)
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S3C9228/P9228
TIMER 1
BTCON.0
TBCON.6-.4
R
1/512 1/256 Data Bus M U X 1/1 TBCON.2 LSB MSB TBCNT (8-Bit Up-Counter) R Clear TBCON.1 Match 8-Bit Comparator LSB MSB INTPND2.1 TBINT TBCON.3
(XIN or XTIN) fxx www..com
DIV
1/64 1/8
fxt
TBDATA Buffer
Match Signal Counter Clear Signal TBDATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B)
Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)
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TIMER 1
S3C9228/P9228
NOTES
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S3C9228/P9228
WATCH TIMER
12
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WATCH TIMER
OVERVIEW
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt, then set the WTCON.6 to "1". The watch timer overflow interrupt pending condition (INTPND2.3) must be cleared by software in the application's interrupt service routine by means of writing a "0" to the INTPND2.3 interrupt pending bit. After the watch timer starts and elapses a time, the watch timer interrupt pending bit (INTPND2.3) is automatically set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting Watch timer speed selection bits (WTCON.3 - .2). The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences. Also, you can select watch timer clock source by setting the WTCON.7 appropriately value. The watch timer supplies the clock frequency for the LCD controller (fLCD ). Therefore, if the watch timer is disabled, the LCD controller does not operate. Watch timer has the following functional components: -- Real Time and Watch-Time Measurement -- Using a Main or Sub Clock Source (Main clock divided by 27(fx/128) or Sub clock(fxt)) -- Clock Source Generation for LCD Controller (fLCD ) -- I/O pin for Buzzer Output Frequency Generator (P0.3, BUZ) -- Timing Tests in High-Speed Mode -- Watch timer overflow interrupt generation -- Watch timer control register, WTCON (page 0, DAH, read/write)
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WATCH TIMER
S3C9228/P9228
WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode. A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock. So, if you want to use the watch timer, you must write appropriate value to WTCON.
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Watch Timer Control Register (WTCON) DAH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Watch timer clock selection bit: 0 = Main clock divided by 27(fx/128) 1 = Sub clock (fxt) Watch timer INT Enable/Disable bit: 0 = Disable watch timer INT 1 = Enable watch timer INT
Not used
Watch timer Enable/Disable bit: 0 = Disable watch timer; clear frequency dividing circuits 1 = Enable watch timer Watch timer speed selection bits: 00 = Set watch timer interrupt to 1 s 01 = Set watch timer interrupt to 0.5 s 10 = Set watch timer interrupt to 0.25 s 11 = Set watch timer interrupt to 3.91 ms
Buzzer signal selection bits: 00 = 0.5 kHz 01 = 1 kHz 10 = 2 kHz 11 = 4 kHz
Figure 12-1. Watch Timer Control Register (WTCON)
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S3C9228/P9228
WATCH TIMER
WATCH TIMER CIRCUIT DIAGRAM
WTCON.7 WTCON.6 WTCON.5
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WT INT Enable WTCON.6 MUX fW/64 (0.5 kHz) fW/32 (1 kHz) fW/16 (2 kHz) fW/8 (4 kHz) Enable/Disable Selector Circuit
BUZ (P0.3)
8
WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0
WTINT
INTPND2.3
Clock Selector
fW 32.768 kHz
Frequency Dividing Circuit
fW/27 fW/213 fW/214 fW/215 (1 Hz) fLCD = 2048 Hz
fxt
fx/128 fX = Main clock (where fx = 4.19 MHz) fxt = Sub clock (32,768 Hz) fW = Watch timer frequency
Figure 12-2. Watch Timer Circuit Diagram
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WATCH TIMER
S3C9228/P9228
NOTES
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S3C9228/P9228
LCD CONTROLLER/DRIVER
13
OVERVIEW
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LCD CONTROLLER/DRIVER
The S3C9228/P9228 microcontroller can directly drive an up-to-128-dot (16segments x 8 commons) LCD panel. Its LCD block has the following components: -- LCD controller/driver -- Display RAM for storing display data -- 16 segment output pins (SEG0-SEG15) -- 8 common output pins (COM0-COM7) -- Internal resistor circuit for LCD bias To use the LCD controller, bit 2 in the watch mode register WMOD must be set to 1 because LCDCK is supplied by the watch timer. The LCD mode control register, LMOD, is used to turn the LCD display on or off, to select LCD clock frequency, to turn the COM signal output on or off, to select bias and duty, and to switch the port 3 high impedance or normal I/O port. Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control. The LCD port control register, LPOT, is used to determine the LCD signal pins used for display output. When a sub clock is selected as the LCD clock source, the LCD display is enabled even during main clock stop and idle modes.
COM0-COM3 4 LCD Controller/ Driver COM4/SEG19COM7/SEG16 SEG0/P2.1SEG15/P5.3 Data BUS
8
4
16
Figure 13-1. LCD Function Diagram
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LCD CONTROLLER/DRIVER
S3C9228/P9228
LCD CIRCUIT DIAGRAM
Port Latch
16
SEG15/P5.3
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Display RAM (Page1)
SEG Control 160 MUX 4 16 or Selector SEG0/P2.1
Data BUS
LPOT
fLCD COM Control or selector
COM7/SEG16/P5.4
Timing Controller
COM4/SEG19/P5.7
Port Latch
8
COM Control
COM3/P6.0 COM0/P6.3
LMOD
LCD Voltage Control P3.1/INTP/SEG2 P3.0/INTP/SEG3
Port Latch
2
Port 3 Control
Figure 13-2. LCD Circuit Diagram
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S3C9228/P9228
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0-SEG19 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use.
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SEG0 SEG1 SEG2 SEG3
SEG17 SEG18 SEG19
COM0 b0 COM1 b1 COM2 b2 COM3 b3 100H 101H 102H 103H COM4 b4 COM5 b5 COM6 b6 COM7 b7 111H 112H 113H
Figure 13-3. LCD Display Data RAM Organization
Table 13-1. Common and Segment Pins per Duty Cycle Duty 1/8 1/4 1/3 Common Pins COM0-COM7 COM0-COM3 COM0-COM2 Segment Pins 16 pins 20 pins 20 pins Dot Number 128 dots 80 dots 60 dots
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LCD CONTROLLER/DRIVER
S3C9228/P9228
LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode. It has the following control functions. -- LCD duty and bias selection -- LCD clock selection -- LCD display control -- COMs signal output control
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impedance control
The LMOD register is used to turn the LCD display on/off, to select duty and bias, to select LCD clock, to control port 3 high impedance/normal I/O port, and to turn the COM signal output on/off. Following a RESET, all LMOD values are cleared to "0". This turns off the LCD display, select 1/3 duty and 1/3 bias, and select 256Hz for LCD clock. The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch timer should be enabled when the LCD display is turned on.
LCD Mode Control Register (LMOD) FEH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used COM pins high impedance control bit: 0 = Normal COMs signal output 1 = High impendane COM pins Port 3 high impendance control bit 0 = Normal I/O 1 = High impendane input
LCD clock selection bits: 00 = fw/27 (256 Hz when fw is 32.768 kHz) 01 = fw/26 (512 Hz when fw is 32.768 kHz) 10 = fw/25 (1024 Hz when fw is 32.768 kHz) 11 = fw/24 (2048 Hz when fw is 32.768 kHz) LCD duty and bias selection bits: 00 = 1/3 duty, 1/3 bias (COM0-COM2, SEG0-SEG19) 01 = 1/4 duty, 1/3 bias (COM0-COM3, SEG0-SEG19) 10 = 1/8 duty, 1/4 bias (COM0-COM7, SEG0-SEG15) 11 = 1/8 duty, 1/5 bias (COM0-COM7, SEG0-SEG15)
LCD display control bit 0 = Display off 1 = Normal display on
Figure 13-4. LCD Mode Control Register (LMOD)
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S3C9228/P9228
LCD CONTROLLER/DRIVER
LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET, a LPOT values are cleared to "0".
LCD Port Control Register D8H, R/W
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MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
SEG4-SEG19 and COM0-COM3 selection bits: SEG1/P2.0 selection bit: 000 = P4.0-P6.3: LCD signal pins 0 = SEG port 001 = P4.0-P4.3: Normal I/O, P4.4-P6.3: LCD signal pins 1 = Normal I/O port 010 = P4.0-P4.7: Normal I/O, P5.0-P6.3: LCD signal pins 011 = P4.0-P5.3: Normal I/O, P5.4-P6.3: LCD signal pins SEG2/P3.1 selection bit: 100 = P4.0-P5.7: Normal I/O, P6.0-P6.3: LCD signal pins 0 = SEG port 101 = P4.0-P6.3: Normal I/O 1 = Normal I/O port 110 = Not available 111 = Not available SEG3/P3.0 selection bit: 0 = SEG port 1 = Normal I/O port
SEG0/P2.1 selection bit: 0 = SEG port 1 = Normal I/O port
Figure 13-5. LCD Port Control Register
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LCD CONTROLLER/DRIVER
S3C9228/P9228
LCD VOLTAGE DIVIDING RESISTORS
1/5 Bias
1/4 Bias
1/3 Bias
S3C9228/P9228
S3C9228/P9228
S3C9228/P9228
VDD
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VDD LMOD.4 LMOD.4 VLC1 VLC1 R R R R R VLC2 VLC3 VLC4 VLC5 VSS
VDD
LMOD.4 VLC1 VLC2 VLC3 VLC4 VLC5 VSS R R R R R
VLC2 VLC3 VLC4 VLC5 VSS
R R R R R
Figure 13-6. Internal Voltage Dividing Resistor Connection COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. -- In 1/3 duty mode, COM0-COM2 pins are selected -- In 1/4 duty mode, COM0-COM3 pins are selected -- In 1/8 duty mode, COM0-COM7 pins are selected SEGMENT (SEG) SIGNALS The 19 LCD segment signal pins are connected to corresponding display RAM locations at page 1. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal to the corresponding segment pin.
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S3C9228/P9228
LCD CONTROLLER/DRIVER
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
0123456701234567
FR 1 Frame
VDD VSS
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COM0
VDD VLC1 VLC2 (VLC3) VLC4 VSS
COM1
VDD VLC1 VLC2 (VLC3) VLC4 VSS
COM2
VDD VLC1 VLC2 (VLC3) VLC4 VSS
SEG0
VDD VLC1 VLC2 (VLC3) VLC4 VSS
+ VDD
SEG0-COM0
+ 1/4VLCD 0V - 1/4VLCD
-VLCD
Figure 13-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
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LCD CONTROLLER/DRIVER
S3C9228/P9228
SEG0 SEG1 COM0 COM1 COM2
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3
0
1
2
0
1
2
3
VDD VSS
1 Frame VDD VLC1(VLC2) VLC3(VLC4) VSS
COM0
VDD COM1 VLC1(VLC2) VLC3(VLC4) VSS
COM2
VDD VLC1(VLC2) VLC3(VLC4) VSS
COM3
VDD VLC1(VLC2) VLC3(VLC4) VSS
SEG0
VDD VLC1(VLC2) VLC3(VLC4) VSS
SEG1
VDD VLC1(VLC2) VLC3(VLC4) VSS
+ VLCD + 1/3 VLCD 0V - 1/3 VLCD - VLCD
COM0-SEG0
Figure 13-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
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S3C9228/P9228
LCD CONTROLLER/DRIVER
SEG2
SEG1
SEG0
0 1 1
2
0
2
COM0 1 Frame
VDD VSS
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COM1 COM0 COM2
VDD VLC1(VLC2) VLC3(VLC4) VSS
COM1
VDD VLC1(VLC2) VLC3(VLC4) VSS
COM2
VDD VLC1(VLC2) VLC3(VLC4) VSS
SEG0
VDD VLC1(VLC2) VLC3(VLC4) VSS
SEG1
VDD VLC1(VLC2) VLC3(VLC4) VSS
+ VLCD + 1/3 VLCD 0V - 1/3 VLCD - VLCD
COM0-SEG0
Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
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LCD CONTROLLER/DRIVER
S3C9228/P9228
NOTES
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S3C9228/P9228
A/D CONVERTER
14
OVERVIEW
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10-BIT ANALOG-TO-DIGITAL CONVERTER
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register (ADCON) -- Four multiplexed analog data input pins (AD0-AD3) -- 10-bit A/D conversion data output register (ADDATAH/ADDATAL) -- 4-bit digital input port (Alternately, I/O port)
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at first you must set with alternative function for ADC input enable at port 1, the pin set with alternative function can be used for ADC analog input. And you write the channel selection data in the A/D converter control register ADCON.4-.5 to select one of the four analog input pins (AD0-3) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located in page 0, at address D0H. The pins which are not used for ADC can be used for normal I/O. During a normal conversion, ADC logic initially sets the successive approximation register to 800H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.5- 4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, ADCON.3, the end-of-conversion(EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH/ADDATAL register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/ADDATAL before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0-AD3 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished.
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A/D CONVERTER
S3C9228/P9228
CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bit + set-up time = 50 clocks, 50 clock x 1.78 us = 89 us at 0.56 MHz (4.5 MHz/8) Note that A/D converter needs at least 25s for conversion time.
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A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address D0H in page 0. It has three functions: -- Analog input pin selection (bits 4 and 5) -- End-of-conversion status detection (bit 3) -- ADC clock selection (bits 2 and 1) -- A/D operation start or enable (bit 0 ) After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (AD0-AD3) can be selected dynamically by manipulating the ADCON.4-5 bits. And the pins not used for analog input can be used for normal I/O function.
A/D Converter Control Register (ADCON) D0H, Page0, R/W (EOC bit is read-only) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Always logic zero A/D input pin selection bits: 00 = AD0 01 = AD1 10 = AD2 11 = AD3 End-of-conversion bit 0 = Not complete Conversion 1 = complete Conversion
Start or enable bit 0 = Disable operation 1 = Start operation (Automatically disable the operation after conversion completes.) Clock Selection bits: 00 = fxx/16 01 = fxx/8 10 = fxx/4 11 = fxx/1
Figure 14-1. A/D Converter Control Register (ADCON)
14-2
S3C9228/P9228
A/D CONVERTER
Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only MSB MSB .9 .8 .7 .6 .5 .4 .3 .1 .2 .0 LSB LSB (ADDATAH) (ADDATAL)
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Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL)
INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range VSS to VDD. Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 VDD.
BLOCK DIAGRAM
ADCON.2-.1 ADCON.4-5 (Select one input pin of the assigned pins)
Clock Selector
To ADCON.3 (EOC Flag)
ADCON.0 (AD/C Enable) M Input Pins AD0-AD3 (P1.0-P1.3) Analog Comparator Successive Approximation Logic & Register
. . .
U + X ADCON.0 (AD/C Enable)
P1CON (Assign Pins to ADC Input) 10-bit D/A Converter
VDD VSS
Conversion Result (ADDATAH/ADDATAL, D1H/D2H, Page 0)
Figure 14-3. A/D Converter Functional Block Diagram
14-3
A/D CONVERTER
S3C9228/P9228
VDD
Analog Input Pin (VSS ADC input VDD)
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AD0-AD3 C 101
S3C9228
Figure 14-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
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S3C9228/P9228
SERIAL I/O INTERFACE
15
OVERVIEW
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SERIAL I/O INTERFACE
Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: -- 8-bit control register (SIOCON) -- Clock selector logic -- 8-bit data buffer (SIODATA) -- 8-bit prescaler (SIOPS) -- 3-bit serial clock counter -- Serial data I/O pins (SI, SO) -- Serial clock input/output pin (SCK) The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO module, follow these basic steps: 1. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P2CON register if necessary. 2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. 3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1". 4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts. 5. When the shift operation (transmit/receive) is completed, the SIO pending bit (INTPND2.2) are set to "1" and SIO interrupt request is generated.
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SERIAL I/O INTERFACE
S3C9228/P9228
SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module. -- Clock source selection (internal or external) for shift clock -- Interrupt enable -- Edge selection for shift operation -- Clear 3-bit counter and start shift operation
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(transmit) enable
-- Mode selection (transmit/receive or receive-only) -- Data direction selection (MSB first or LSB first) A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first.
Serial I/O Module Control Register (SIOCON) E1H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
SIO shift clock selection bit: 0 = Internal clock (P.S Clock) 1 = External clock (SCK) Data direction control bit: 0 = MSB-first mode 1 = LSB-first mode SIO mode selection bit: 0 = Receive only mode 1 = Transmit/receive mode
Not used SIO interrupt enable bit: 0 = Disable SIO interrupt 1 = Enable SIO interrupt SIO shift operation enable bit: 0 = Disable shifter and clock counter 1 = Enable shifter and clock counter SIO counter clear and shift start bit: 0 = No action 1 = Clear 3-bit counter and start shifting
Shift clock edge selection bit: 0 = tX at falling edeges, rx at rising edges. 1 = tX at rising edeges, rx at falling edges.
Figure 15-1. Serial I/O Module Control Register (SIOCON)
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S3C9228/P9228
SERIAL I/O INTERFACE
SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock.
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SIO Pre-scaler Register (SIOPS) E3H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Baud rate = (fXX/4)/(SIOPS + 1)
Figure 15-2. SIO Prescaler Register (SIOPS)
SIO BLOCK DIAGRAM
CLK
3-Bit Counter Clear
SIO INT INTPND2.2 Pending
SIOCON.3 SIOCON.7 SIOCON.4 (Edge Select) SCK SIOPS (E3H, page 0) fxx/2 8-bit P.S. 1/2 M U X CLK 8-Bit SIO Shift Buffer (SIODATA, E2H, page 0) SIOCON.2 (Shift Enable)
SIOCON.1 (Interrupt Enable)
SIOCON.5 (Mode Select) SO SIOCON.6 (LSB/MSB First Mode Select)
8 SI
Data Bus
Figure 15-3. SIO Functional Block Diagram
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SERIAL I/O INTERFACE
S3C9228/P9228
SERIAL I/O TIMING DIAGRAM (SIO)
SCK
SI
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DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SIO INT Set SIOCON.3
Transmit Complete
Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SIO INT Set SIOCON.3
Transmit Complete
Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
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S3C9228/P9228
ELECTRICAL DATA
16
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ELECTRICAL DATA
OVERVIEW
In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by an external interrupt -- Stop mode release timing when initiated by a Reset -- I/O capacitance -- A.C. electrical characteristics -- A/D converter electrical characteristics -- Input timing for external interrupt -- Input timing for RESET -- Serial data transfer timing -- Oscillation characteristics -- Oscillation stabilization time -- Operating voltage range
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ELECTRICAL DATA
S3C9228/P9228
Table 16-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Output voltage Output current High
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Symbol VDD VIN VO I OH I OL TA TSTG Ports 0-6
Conditions -
Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3
Unit V V V mA
- One I/O pin active All I/O pins active
- 0.3 to VDD + 0.3 - 15 - 60 + 30 + 100 - 25 to + 85 - 65 to + 150
Output current Low
One I/O pin active Total pin current for ports
mA
C C
Operating temperature Storage temperature
- -
Table 16-2. D.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Operating Voltage Input High voltage Symbol VDD VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage Output Low voltage Input High leakage current VOH VOL ILIH1 Conditions fx = 0.4-4MHz, fxt = 32.8kHz fx = 0.4-8MHz Ports 4-6 Ports 0-3, RESET XIN, XOUT and XTIN, XTOUT Ports 4-6 Ports 0-3, RESET XIN, XOUT, XTIN, XTOUT VDD = 4.5 to 5.5 V; All output ports; IOH = -1 mA VDD = 4.5 to 5.5 V; All output ports; IOL = 10 mA VI = VDD; All input pins except XIN, XOUT, XTIN, XTOUT VI = VDD; XIN, XOUT, XTIN, XTOUT VDD - 1.0 - - - - - Min 2.0 2.7 0.7 VDD 0.8 VDD VDD - 0.1 - - Typ - - - Max 5.5 5.5 VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 VDD 2.0 3 V V A V Unit V V
ILIH2
20
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S3C9228/P9228
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics (Continued) (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Input Low leakage current Symbol ILIL1 VI = 0 V; All input pins except RESET, XOUT, XTIN, XTOUT VI = 0 V; XIN, XOUT, XTIN, XTOUT VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5V, TA = 25C Ports 0-6 VDD = 3V, TA = 25C RL2 VI = 0 V; VDD = 5V, TA = 25C RESET VDD = 3V, TA = 25C Oscillator Feed back Resistors ROSC1 ROSC2 LCD Voltage Dividing Resistor VLCD-COMi Voltage Drop (i = 0-7) VLCD-SEGx Voltage Drop (x = 0-19) Middle Output Voltage VLC3 VLC4 VLC5
NOTE: Low leakage current is absolute value.
Conditions
Min -
Typ -
Max -3
Unit A
ILIL2
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-20 - - 25 50 150 300 300 1500 50 - - - 47 90 250 500 600 3000 70 - 3 -3 100 150 400 700 1500 4500 90 120 k mV k k
Output High leakage current Output Low leakage current Pull-Up Resistor
ILOH ILOL RL1
VDD = 5 V, TA = 25 C XIN = VDD, XOUT = 0V VDD = 5 V, TA = 25 C XTIN = VDD, XTOUT = 0 V TA = 25 C VDD = 2.7 V to 5.5 V - 15 A per common pin VDD = 2.7 V to 5.5 V - 15 A per common pin VDD = 2.7 V to 5.5 V, LCD clock = 0Hz, VLC1 = VDD
RLCD VDC
VDS
-
-
120
VLC2
0.8VDD-0.2 0.6VDD-0.2 0.4VDD-0.2 0.2VDD-0.2
0.8VDD 0.6VDD 0.4VDD 0.2VDD
0.8VDD+ 0.2 0.6VDD+ 0.2 0.4VDD+ 0.2 0.2VDD+ 0.2
V
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ELECTRICAL DATA
S3C9228/P9228
Table 16-2. D.C. Electrical Characteristics (Concluded) (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 Conditions Run mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF
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Min -
Typ 6.0 3.0 2.5 1.5 1.3 1.0 0.8 0.4 15 6 0.5
Max 12.0 6.0 5.0 3.0 3.0 2.0 1.6 0.8 30 15 3
Unit mA
8.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz
VDD = 3 V 10% IDD2 Idle mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% IDD3 IDD4 IDD5
8.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz
Run mode: VDD = 3 V 10%, 32 kHz crystal oscillator Idle mode: VDD = 3 V 10%, 32 kHz crystal oscillator TA = 25 C Stop mode; VDD = 5 V 10%, Stop mode; VDD = 3 V 10%, TA = 25 C
A
0.3
2
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 4. IDD5 is current when main system clock and subsystem clock oscillation stops.
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S3C9228/P9228
ELECTRICAL DATA
Table 16-3. Data Retention Supply Voltage in Stop Mode (TA = - 25 C to + 85 C) Parameter Data retention supply voltage Data retention supply current
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Symbol VDDDR IDDDR
Conditions - Stop mode, TA = 25 C VDDDR = 2.0 V
Min 2.0 -
Typ - -
Max 5.5 1
Unit V A
Idle Mode (Basic Timer Active)
~ ~ ~ ~
Stop Mode Data Retention Mode Normal Operating Mode
VDD
VDDDR Execution of STOP Instruction 0.8 VDD
tWAIT NOTE: tWAIT is the same as 16 x 1/BT clock.
Figure 16-1. Stop Mode Release Timing When Initiated by an External Interrupt
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ELECTRICAL DATA
S3C9228/P9228
RESET Occurs
Oscillation Stabilization TIme Normal Operating Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
VDD
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VDDDR Execution of STOP Instrction 0.8 VDD 0.2 VDD tWAIT RESET
NOTE:
tWAIT is the same as 16 x 1/BT clock.
Figure 16-2. Stop Mode Release Timing When Initiated by a RESET
Table 16-4. Input/Output Capacitance (TA = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF
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S3C9228/P9228
ELECTRICAL DATA
Table 16-5. A.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter SCK cycle time Symbol tKCY tKH, tKL Conditions External SCK source Internal SCK source SCK high, low width
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Min 1,000 1,000 500 tKCY/2-50 250 250 400 400 -
Typ -
Max -
Unit ns
External SCK source Internal SCK source
SI setup time to SCK high SI hold time to SCK high
tSIK
External SCK source Internal SCK source
tKSI tKSO
External SCK source Internal SCK source
Output delay for SCK to SO Interrupt input, High, Low width RESET input Low width
External SCK source Internal SCK source
-
300 250
ns
tINTH, tINTL tRSL
All interrupt VDD = 3 V Input VDD = 3 V
500 10
700 -
- -
ns s
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ELECTRICAL DATA
S3C9228/P9228
Table 16-6. A/D Converter Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy Integral linearity error Differential linearity error
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Symbol
Conditions VDD = 5.12 V
Min - - - - - -
Typ 10 - - - 1 0.5 - - 1000 - 1 0.5 100
Max - 3 2 1 3 2 - VDD - 10 3 1.5 500
Unit bit LSB
ILE DLE EOT EOB TCON VIAN RAN IADIN IADC
fxx = 8 MHz f CON = fxx/4
of top
Offset error of bottom Conversion time (1) Analog input voltage Analog input impedance Analog input current
10-bit resolution 50 x fxx/4, fxx = 8MHz - - VDD = 5 V VDD = 5 V VDD = 3 V VDD = 5 V When power down mode
25 VSS 2 - -
S V M A mA
nA
NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during A/D conversion.
tINTL
tINTH
External Interrupt
0.8 VDD 0.2 VDD
NOTE:
The unit tCPU means one CPU clock period.
Figure 16-3. Input Timing for External Interrupts
16-8
S3C9228/P9228
ELECTRICAL DATA
tRSL
RESET 0.2 VDD
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Figure 16-4. Input Timing for RESET
tKCY tKL SCK 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI 0.2VDD tKSO tKH
SO
Output Data
Figure 16-5. Serial Data Transfer Timing
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ELECTRICAL DATA
S3C9228/P9228
Table 16-7. Main Oscillation Characteristics (TA = - 25C to + 85C) Oscillator Crystal Clock Configuration
C1 XIN
Parameter Main oscillation frequency
Test Condition 2.7 V - 5.5 V
Min 0.4
Typ -
Max 8
Units MHz
XOUT
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2.0 V - 5.5 V
C1 XIN
0.4 0.4
- -
4 8
Ceramic Oscillator
Main oscillation frequency
2.7 V - 5.5 V
XOUT
2.0 V - 5.5 V External Clock XIN input frequency
XIN
0.4 0.4
- -
4 8
2.7 V - 5.5 V
XOUT
2.0 V - 5.5 V RC Oscillator
R XOUT
0.4 0.4
- -
4 2 MHz
Frequency
XIN
5.0 V
Frequency
3.0 V
0.4
-
1
Table 16-8. Sub Oscillation Characteristics (TA = - 25C to + 85C) Oscillator Crystal Clock Configuration
C1 XIN
Parameter Sub oscillation frequency
Test Condition 2.0 V - 5.5 V
Min 32
Typ 32.768
Max 35
Units kHz
XOUT
External clock
XIN
XTIN input frequency
2.0 V - 5.5 V
32
-
100
XOUT
16-10
S3C9228/P9228
ELECTRICAL DATA
Table 16-9. Main Oscillation Stabilization Time (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Crystal Ceramic fx > 1 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage ranage. XIN input high and low width (tXH, tXL) Test Condition Min - - Typ - - Max 30 10 Unit ms ms
External clock
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62.5
-
1250
ns
1/fx tXL tX
XIN 0.1 V
VDD-0.1 V
Figure 16-6. Clock Timing Measurement at XIN
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ELECTRICAL DATA
S3C9228/P9228
Table 16-10. Sub Oscillation Stabilization Time (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Crystal External clock Test Condition - XTIN input high and low width (tXH, tXL) Min - 5 Typ - - Max 10 15 Unit s s
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1/fxt tXTL tXTH
XTIN VDD-0.1 V 0.1 V
Figure 16-7. Clock Timing Measurement at XTIN
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S3C9228/P9228
ELECTRICAL DATA
Instruction Clock 2 MHz 1.0 MHz
fx (Main/Sub oscillation frequency) 8 MHz 4 MHz
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400 kHz
6.25 kHz (main)/8.2 kHz(sub) 1 2 2.7 Supply Voltage (V) 5.5 6
400 kHz (main)/32.8 kHz(sub)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 16-8. Operating Voltage Range
16-13
ELECTRICAL DATA
S3C9228/P9228
NOTES
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16-14
S3C9228/P9228
MECHANICAL DATA
17
OVERVIEW
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MECHANICAL DATA
The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package.
#42
#22
0-15
14.00 0.2
#1
#21
39.50 MAX 39.10 0.2
0.51 MIN
0.50 (1.77) 1.00
0.1 0.1
1.78
NOTE:
Dimensions are in millimeters.
Figure 17-1. 42-SDIP-600 Package Dimensions
3.30 0.3
5.08 MAX
3.50
0.2
0.2
5
+0 - 0 .1 .05
42-SDIP-600
15.24
17-1
MECHANICAL DATA
S3C9228/P9228
13.20 0.3 0-8 10.00 0.2 0.15
+ 0.10 - 0.05
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13.20 0.3
10.00 0.2
44-QFP-1010B
0.80 0.20 #1 0.80
+ 0.10
0.10 MAX
#44
0.35 - 0.05 (1.00)
0.05 MIN 2.05 0.10 2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 17-2. 44-QFP-1010B Package Dimensions
17-2
S3C9228/P9228
S3P9228 OTP
18
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S3P9228 OTP
OVERVIEW
The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9228 is fully compatible with the S3C9228, both in function and in pin configuration. Because of its simple programming requirements, the S3P9228 is ideal for use as an evaluation chip for the S3C9228.
P1.0/AD0/INT P1.1/AD1/INT SDAT/P1.2/AD2/INT SCLK/P1.3/AD3/INT VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
P0.5 P0.4 P0.3/BUZ/INT P0.2/INT P0.1/T1CLK/INT P0.0/TAOUT/INT COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7
S3C9228
(44-QFP)
COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4
Figure 18-1. S3P9228 44-QFP Pin Assignments
RESET/RESET RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.0/SCK SEG2/P3.1/INTP SEG3/P3.0/INTP SEG4/P4.0 SEG5/P4.1 SEG6/P4.2 SEG7/P4.3
12 13 14 15 16 17 18 19 20 21 22
18-1
S3P9228 OTP
S3C9228/P9228
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COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT SDAT/P1.2/AD2/INT SCLK/P1.3/AD3/INT VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET /RESET P2.3 P2.2/SI SEG0/P2.1/SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4 SEG7/P4.3 SEG6/P4.2 SEG5/P4.1 SEG4/P4.0 SEG3/P3.0/INTP SEG2/P3.1/INTP SEG1/P2.0/SCK
S3C9228
Figure 18-2. S3P9228 42-SDIP Pin Assignments
(42-SDIP)
18-2
S3C9228/P9228
S3P9228 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P1.2 Pin Name SDAT Pin No. 3 (9) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to + 5 V during programming.
P1.3 TEST
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SCLK VPP(TEST)
4 (10) 9 (15)
I/O I
RESET VDD/VSS
RESET VDD/VSS
12 (18) 5/6 (11/12)
I I
NOTE: Parentheses indicate pin number for 42-SDIP package.
Table 18-2. Comparison of S3P9228 and S3C9228 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 8 Kbyte EPROM 2.0 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 44-QFP, 42-SDIP User Program 1 time 44-QFP, 42-SDIP Programmed at the factory S3P9228 S3C9228 8 Kbyte mask ROM 2.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P72C8, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below. Table 18-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: "0" means Low level; "1" means High level.
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S3P9228 OTP
S3C9228/P9228
Table 18-4. D.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 Conditions Run mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF
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Min -
Typ 6.0 3.0 2.5 1.5 1.3 1.0 0.8 0.4 15 6 0.5
Max 12.0 6.0 5.0 3.0 3.0 2.0 1.6 0.8 30 15 3
Unit mA
8.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz
VDD = 3 V 10% IDD2 Idle mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% IDD3 IDD4 IDD5
8.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz
Run mode: VDD = 3 V 10%, 32 kHz crystal oscillator Idle mode: VDD = 3 V 10%, 32 kHz crystal oscillator TA = 25 C Stop mode; VDD = 5 V 10%, Stop mode; VDD = 3 V 10%, TA = 25 C
A
0.3
2
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 4. IDD5 is current when main system clock and subsystem clock oscillation stops.
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S3C9228/P9228
S3P9228 OTP
Instruction Clock 2 MHz 1.0 MHz
fx (Main/Sub oscillation frequency) 8 MHz 4 MHz
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400 kHz
6.25 kHz (main)/8.2 kHz(sub) 1 2 2.7 Supply Voltage (V) 5.5 6
400 kHz (main)/32.8 kHz(sub)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 18-3. Standard Operating Voltage Range
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S3P9228 OTP
S3C9228/P9228
NOTES
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S3C9228/P9228
DEVELOPMENT TOOLS
19
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DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. SHINE Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM86 The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board.
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DEVELOPMENT TOOLS
S3C9228/P9228
IBM-PC AT or Compatible
RS-232C
SMDS2+
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PROM/OTP Writer Unit
Target Application System
RAM Break/Display Unit Probe Adapter BUS Trace/Timer Unit
SAM8 Base Unit
POD
TB9228 Target Board EVA Chip
Power Supply Unit
Figure 19-1. SMDS Product Configuration (SMDS2+)
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S3C9228/P9228
DEVELOPMENT TOOLS
TB9228 TARGET BOARD The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system.
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To User_VCC OFF RESET
C11
TB9228
IDLE STOP
+ +
R1 D1 C1 U2 R7 R8 Y1 T1T2 T3T4 C3 C4 C5 C6 R5 R4
REV.0 '2002.03.30
ON
C20
25
CB+ C7
20 C10 C9
J1 30 20 10 1 160
J101 42SDIP 1
T16 T15 T14 T13 T12 T11 T10 T9
42 40
J102 44QFP 1 44
CN1
10
50 60 70 80
150 140 130
5 35 10 30
5
GND 40 10 35 15 25 20 25 23 30 22 22 P2
90 1 51 76 26
100 110 120 C14
15
21
SMDS2
SMDS2+
SM1347A
Figure 19-2. TB9228 Target Board Configuration
VCC
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DEVELOPMENT TOOLS
S3C9228/P9228
Table 19-1. Power Selection Settings for TB9228 "To User_VCC" Settings
To User_VCC Off On TB9228 VCC VSS
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Operating Mode
Comments The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system.
Target System
VCC SMDS2/SMDS2+
To User_VCC Off On TB9228 External VCC VSS VCC SMDS2/SMDS2+ Target System
The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
NOTE: The following symbol in the "To User_VCC" Setting column indicates the electrical short (off) configuration:
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S3C9228/P9228
DEVELOPMENT TOOLS
SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 19-2. The SMDS2+ Tool Selection Setting "SW1" Setting
SMDS2
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Operating Mode
SMDS2+ R/W SMDS2+ R/W Target Board
Table 19-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part
External Triggers Ch1 Ch2
Comments
Connector from External Trigger Sources of the Application System
You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions.
IDLE LED The Green LED is ON when the evaluation chip (S3E9220) is in idle mode. STOP LED The Red LED is ON when the evaluation chip (S3E9220) is in stop mode.
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DEVELOPMENT TOOLS
S3C9228/P9228
J101 42-SDIP
J102 44-QFP
P6.2 P6.3 P0.0 P0.1 P0.2 www..com P0.3 P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.1 NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47
P6.1 P6.0 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P3.0 P3.1 P2.0 NC NC NC NC
P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.1 P2.0 P3.1 P3.0 P4.0 P4.1 P4.2 P4.3 NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 45 46 47
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 50 49 48
P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P6.3 P6.2 P6.1 P6.0 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 NC NC NC
Figure 19-3. Connectors (J101, J102) for TB9228
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S3C9228/P9228
DEVELOPMENT TOOLS
Target Board J101 50-Pin DIP Connector 1 42 Target Cable for Connector Part Name: AP42SD Order Code: SM6538 21 22
Target System J101 1 42
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21
22
Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package
Target Board J102 1 44 Target Cable for 50-pin Connector Part Name: AP50D-A Order Code: SM6305 22 23 50-Pin Connector
Target System J102 1 44 50-Pin Connector
22
23
Figure 19-5. S3C9228 Probe Adapter for 44-QFP Package
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DEVELOPMENT TOOLS
S3C9228/P9228
NOTES
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19-8

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