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Cologne Chip
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Copyright 1994-2001 Cologne Chip AG All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the information presented may be protected by patent or other rights. Cologne Chip products are not designed, intended, or authorized for use in any application intended to support or sustain life, or for any other application in which the failure of the Cologne Chip product could create a situation where personal injury or death may occur.
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Revision History
Date Jan. 2001 Remarks Information added to section: TRM register bit description, GCI/IOM2 timing. Changes made on: ISDN PCI card for 3.3V power supply (no D3cold support) part list and ISDN PCI card for 3.3V power supply with D3cold support part list: RG3, RG4 renamed to RG1, RG2 to match with the schematics. Changes made in section: Sample circuitries: ISDN PCI card for 3.3 and 5V power supply (auto detect) with D3cold support: connectors for alternative footprint removed. Information added to section: S/T module part numbers, Sample circuitries. Section added: Register list. Information added to section: GCI frame structure, sample circuitries. Errors corrected in section: configuring test loops (register addresses corrected), register bit description (STATES register address corrected), Auxiliary port write access (data out is valid until the next write access is initiated). Sections added: Power management support of HFC-S PCI A, configuring test loops. Information added in section: STATES register bit description, S/T interface activation / deactivation layer 1 for finite state matrix for NT. Auxiliary port access timing diagrams added. Changes made on: S/T module part numbers and manufacturers.
Oct. 2000
May 2000 Jan. 2000
Aug. 1999
Apr. 1999 Mar. 1999
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Cologne Chip AG Eintrachtstrasse 113 D-50668 Koln Germany Tel.: +49 (0) 221 / 91 24-0 Fax: +49 (0) 221 / 91 24-100 http://www.CologneChip.com http://www.CologneChip.de info@CologneChip.com
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Contents
Features........................................................................................................................................................ 6 1 General description............................................................................................................................ 6 1.1 Applications ..................................................................................................................................... 7 2 Pin description.................................................................................................................................... 8 2.1 PCI bus interface.............................................................................................................................. 8 2.2 Auxiliary port................................................................................................................................. 10 2.3 S/T interface transmit signals ........................................................................................................ 10 2.4 S/T interface receive signals.......................................................................................................... 10 2.5 Oscillator........................................................................................................................................ 11 2.6 GCI/IOM2 bus interface ................................................................................................................ 11 2.7 GCI/IOM2 Timeslot enable signals ............................................................................................... 11 2.8 EEPROM interface ........................................................................................................................ 11 2.9 Power supply.................................................................................................................................. 12 2.10 RESET characteristics............................................................................................................... 12 3 Functional description ..................................................................................................................... 13 3.1 PCI-interface .................................................................................................................................. 13 3.1.1 PCI access types used by HFC-S PCI A ............................................................................... 13 3.1.2 PCI modes supported ............................................................................................................ 13 3.1.3 PCI buffer signaling and power supply environment............................................................ 13 3.1.4 PCI configuration registers ................................................................................................... 14 3.2 Internal HFC-S PCI A register description.................................................................................... 17 3.2.1 Registers of the S/T section .................................................................................................. 18 3.2.2 Registers of the GCI/IOM2 bus section ................................................................................ 19 3.2.3 Interrupt and status registers ................................................................................................. 20 3.2.4 Register list ........................................................................................................................... 21 3.3 Power Management Support of HFC-S PCI A .............................................................................. 22 3.3.1 PME events ........................................................................................................................... 22 3.3.2 Special considerations for support of D3cold ......................................................................... 22 3.4 Timer.............................................................................................................................................. 24 3.5 FIFOs ............................................................................................................................................. 25 3.5.1 FIFO counters location in Memory Window ........................................................................ 26 3.5.2 FIFO data location in Memory Window ............................................................................... 27 3.5.3 FIFO channel operation......................................................................................................... 28 3.5.3.1 Send channels (B1, B2 and D transmit)............................................................................ 28 3.5.3.2 Automatically D-channel frame repetition ....................................................................... 29 3.5.3.3 FIFO full condition in send channels................................................................................ 29 3.5.3.4 Receive Channels (B1, B2 and D receive) ....................................................................... 29 3.5.3.5 FIFO full condition in receive channels ........................................................................... 31 3.5.3.6 FIFO initialisation............................................................................................................. 31 3.5.4 Transparent mode of HFC-S PCI A ...................................................................................... 32 3.6 Configuring test loops.................................................................................................................... 33 4 Register bit description.................................................................................................................... 34 4.1 Register bit description of S/T section .......................................................................................... 34 4.2 Register bit description of GCI/IOM2 bus section ........................................................................ 37 4.3 Register bit description of CONNECT register............................................................................. 40
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4.4 5
Register bit description of auxiliary and cross data registers ........................................................ 41 Electrical characteristics ................................................................................................................. 46
6 Timing characteristics ..................................................................................................................... 50 6.1 PCI bus timing ............................................................................................................................... 50 6.2 GCI/IOM2 bus clock and data alignment for Mitel STTM bus....................................................... 50 6.3 GCI/IOM2 timing .......................................................................................................................... 51 6.3.1 Master mode.......................................................................................................................... 51 6.3.2 Slave mode ............................................................................................................................ 52 6.4 EEPROM access ............................................................................................................................ 53 6.5 Auxiliary port access ..................................................................................................................... 54 6.5.1 Write access .......................................................................................................................... 54 6.5.2 Read access ........................................................................................................................... 55 7 S/T interface circuitry...................................................................................................................... 56 7.1 External receiver circuitry ............................................................................................................. 56 7.2 External transmitter circuitry......................................................................................................... 57 7.3 Oscillator circuitry ......................................................................................................................... 60 7.4 EEPROM circuitry......................................................................................................................... 60 7.5 PME pin circuitry........................................................................................................................... 61 8 State matrices for NT and TE ......................................................................................................... 62 8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT .................................. 62 8.2 Activation/deactivation layer 1 for finite state matrix for TE ....................................................... 63 9 Binary organisation of the frames .................................................................................................. 64 9.1 S/T frame structure ........................................................................................................................ 64 9.2 GCI frame structure ....................................................................................................................... 65 10 Clock synchronisation...................................................................................................................... 66 10.1 Clock synchronisation in NT-mode........................................................................................... 66 10.2 Clock synchronisation in TE-mode ........................................................................................... 67 11 HFC-S PCI A package dimensions................................................................................................. 68
12 ISDN PCI card sample circuitries with HFC-S PCI A................................................................. 69 12.1 ISDN PCI card for 5V power supply (no D3cold support).......................................................... 69 12.2 ISDN PCI card for 5V power supply with D3cold support ......................................................... 72 12.3 ISDN PCI card for 3.3V power supply (no D3cold support)....................................................... 75 12.4 ISDN PCI card for 3.3V power supply with D3cold support ...................................................... 78 12.5 ISDN PCI card for 3.3 and 5V power supply (auto detect) with D3cold support ....................... 81
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Figures
Figure 1: HFC-S PCI A block diagram......................................................................................................... 7 Figure 2: Pin Connection .............................................................................................................................. 8 Figure 3: HFC-S PCI A in I/O address mapped mode................................................................................ 17 Figure 4: HFC-S PCI A in memory address mapped mode ........................................................................ 17 Figure 5: Masking RST# for D3cold Support ............................................................................................... 23 Figure 6: FIFO Organisation (shown for B-channel, similar for D-channel) ............................................. 28 Figure 7: FIFO Data Organisation .............................................................................................................. 30 Figure 8: Function of the CONNECT register bits..................................................................................... 40 Figure 9: GCI/IOM2 bus clock and data alignment.................................................................................... 50 Figure 10: External receiver circuitry......................................................................................................... 56 Figure 11: External transmitter circuitry .................................................................................................... 57 Figure 12: Oscillator Circuitry.................................................................................................................... 60 Figure 13: EEPROM circuitry .................................................................................................................... 60 Figure 14: PME pin circuitry ...................................................................................................................... 61 Figure 15: Frame structure at reference point S and T ............................................................................... 64 Figure 16: Single channel GCI format........................................................................................................ 65 Figure 17: Clock synchronisation in NT-mode .......................................................................................... 66 Figure 18: Clock synchronisation in TE-mode........................................................................................... 67 Figure 19: HFC-S PCI A package dimensions ........................................................................................... 68
Tables
Table 1: PCI command types ...................................................................................................................... 13 Table 2: PCI configuration registers' initial values..................................................................................... 17 Table 3: Register list by address ................................................................................................................. 21 Table 4: Register list by name .................................................................................................................... 21 Table 5: S/T module part numbers and manufacturer ................................................................................ 59 Table 6: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 62 Table 7: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 63
Timing Diagrams
Timing diagram 1: GCI/IOM2 timing......................................................................................................... 51 Timing diagram 2: EEPROM access .......................................................................................................... 53 Timing diagram 3: Auxiliary port write access .......................................................................................... 54 Timing diagram 4: Auxiliary port read access............................................................................................ 55
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Features

Single chip ISDN-S-controller with B- and D-channel HDLC support Independent Read and Write HDLC-Channels for 2 ISDN B-channels and one ISDN D-channel B1- and B2-channel transparent mode independently selectable FIFO-Memory-Window: 4x 7.5 KByte (B-channel) and 2x 512 Byte (D-channel) max. 31 HDLC frames (B-channel) and 15 HDLC frames (D-channel) per channel and direction in FIFO 56 kbit/s restricted mode for U.S. ISDN lines selectable full I.430 ITU S/T ISDN support in TE and NT mode B1+B2 HDLC mode PCM30 interface configurable to interface MITEL STTM bus (MVIPTM), Siemens IOM2TM or GCITM for interface to U-chip or external codecs integrated PCI Spec. 2.2 bus interface (power management included, ACPI ready) for 3.3V and 5V bus signal environment direct access to PCM30 interface for tone synthetisation 3.3V and 5V supply voltage rectangular QFP 100 case
1
General description
The HFC-S PCI A is an ISDN S/T HDLC basic rate controller for so called passive" ISDN PC cards with integrated S/T interface and PCM30 highway interface. It is the first all in one solution for a PCI ISDN PC-card world wide with power management and Windows 98 support. A 32Kbyte memory window of the PC is used for the deep FIFOs. Also an industrial standard serial interface for telecom peripheral ICs is implemented. Codecs are normally connected to this interface.
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1.1
Applications ISDN PCI PC card
Figure 1: HFC-S PCI A block diagram
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2
Pin description
Figure 2: Pin Connection
2.1
PCI bus interface
For further information please refer to the PCI Local Bus Specification. Pin No. Pin Name Input Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function PCI address bus Address bit 0 Address bit 1 Address bit 2 Address bit 3 Address bit 4 Address bit 5 Address bit 6 Address bit 7 Address bit 8 Address bit 9 Address bit 10 Address bit 11 Address bit 12 Address bit 13 Address bit 14 Address bit 15
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47 46 45 44 43 42 41 40 37 36 35 34 33 32 31 30
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AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
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Input Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I I/O O I I/O O O O Function Address bit 16 Address bit 17 Address bit 18 Address bit 19 Address bit 20 Address bit 21 Address bit 22 Address bit 23 Address bit 24 Address bit 25 Address bit 26 Address bit 27 Address bit 28 Address bit 29 Address bit 30 Address bit 31 Parity bit Bus command and byte enable 0 Bus command and byte enable 1 Bus command and byte enable 2 Bus command and byte enable 3 PCI clock Reset Cycle frame Initiator ready Target ready Stop Initialisation device select Device select Request Grant Parity error System error Power management event (high active) see also: Figure 14 on page 61 Interrupt A
Pin No. 16 15 14 13 12 11 10 9 4 3 2 1 100 99 98 97 26 38 27 18 5 93 92 19 20 21 23 6 22 95 94 24 25 53 91
Pin Name AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PAR C/BE0# C/BE1# C/BE2# C/BE3# CLK RST# FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# REQ# GNT# PERR# SERR# PME INTA#
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2.2
Auxiliary port Pin Name DAUX0 DAUX1 DAUX2 DAUX3 DAUX4 DAUX5 DAUX6 DAUX7 /AUX_WR /AUX_RD /ADR_WR Input Output I/O I/O I/O I/O I/O I/O I/O I/O O O I/O d) Function AUX data bit 0 AUX data bit 1 AUX data bit 2 AUX data bit 3 AUX data bit 4 AUX data bit 5 AUX data bit 6 AUX data bit 7 AUX write AUX read AUX address write
Pin No. 75 74 73 72 71 70 69 68 67 66 65
d)
internal pull down
2.3 88 87 86 85 84
S/T interface transmit signals TX2_HI /TX1_LO /TX_EN /TX2_LO TX1_HI O O O O O Transmit output 2 GND driver for transmitter 1 Transmit enable GND driver for transmitter 2 Transmit output 1
See also: 7.2 External transmitter circuitry.
2.4 82 81 80 79 78
S/T interface receive signals R2 LEV_R2 LEV_R1 R1 ADJ_LEV I I I I O Receive data 2 Level detect for R2 Level detect for R1 Receive data 1 Levelgenerator
See also: 7.1 External receiver circuitry.
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2.5
Oscillator Pin Name OSC_IN OSC_OUT Input Output I O Function Oscillator input or quarz connection 12.288 MHz Oscillator output or quarz connection
Pin No. 51 50
2.6 54
GCI/IOM2 bus interface C4IO I/O u) I/O u) 4.096 MHz clock GCI/IOM2 bus clock master: output GCI/IOM2 bus clock slave: input (reset default) Frame synchronisation, 8kHz pulse for GCI/IOM2 bus frame synchronisation GCI/IOM2 bus master: output GCI/IOM2 bus slave: input (reset default) GCI/IOM2 bus databus I Slotwise programmable as input or output GCI/IOM2 bus databus II Slotwise programmable as input or output
55
F0IO
56 57
STIO1 STIO2
I/O u) I/O u)
u)
internal pull up
2.7 GCI/IOM2 Timeslot enable signals (e. g. for PCM codecs) 58 59 F1_A F1_B O O enable signal for external CODEC A Programmable as positive (reset default) or negative pulse. enable signal for external CODEC B Programmable as positive (reset default) or negative pulse.
2.8
EEPROM interface
The external EEPROM is optional. EE_SCL/EN must be connected to GND if no external EEPROM is available. 63 62
u)
EE_SDA EE_SCL/EN
I/O u) I/O u)
Serial data of external EEPROM Clock of external EEPROM / EEPROM enable
internal pull up
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2.9
Power supply Pin Name VDD GND Function VDD (+3.3V or +5V) GND
Pin No. 7, 28, 48, 60, 76, 89 8, 17, 29, 39, 49, 52, 61, 64, 77, 83, 90, 96
* important!
All power supply pins VDD must be directly connected to each other. Also all pins GND must be directly connected to each other. To keep VDD and GND bounce to a minimum a bypass capacitor (10 nF to 100 nF) should be placed between each pair of VDD/GND pins.
2.10
RESET characteristics
The reset signal (hardware reset or software reset) must be active for at least 4 clock cycles. The GCI/IOM2 bus lines STIO1, STIO2 and the interrupt lines are in tristate mode after a reset. The HFC-S PCI A is in slave mode after reset. C4IO and F0IO are inputs. The S/T state machine is stuck to '0' after reset. This means the HFC-S PCI A does not react to any signal on the S/T interface before the S/T state machine is initialised. The registers' initial values are described in the Register bit description (section 4 of this data sheet). During initialisation phase the HFC-S PCI A must not be accessed. Bit 1 of the STATUS register is cleared to '0' to indicate that the initialisation phase has been finished.
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3
3.1 3.1.1
Functional description
PCI-interface PCI access types used by HFC-S PCI A C/BE2# 0 0 1 1 1 1 1 0 0 C/BE1# 1 1 1 0 1 1 1 1 1 C/BE0# 0 1 0 0 0 1 1 0 1 Command Type I/O Read I/O Write Memory Read Memory Read Multiple Memory Read Line Memory Write Memory Write and Invalidate Configuration Read Configuration Write HFC-S PCI A mode target mode target mode target mode and master mode target mode target mode target mode and master mode target mode target mode target mode
C/BE3# 0 0 0 1 1 0 1 1 1
Table 1: PCI command types Memory Read Line and Memory Read Multiple commands are aliased to Memory Read. Memory Write and Invalidate is aliased to Memory Write.
3.1.2
PCI modes supported
The HFC-S PCI A supports both target mode and master mode. Before the HFC-S PCI A can operate in master mode the 32K Memory Window Base Address register (MWBA) must be configured. Afterwards all FIFO data accesses are done by the HFC-S PCI A automatically by PCI master accesses. Only control and configuration register accesses must be done by PCI target accesses by the host CPU.
3.1.3 PCI buffer signaling and power supply environment The HFC-S PCI A supports 5V and 3.3V PCI bus environments. The environment mode is set during RESET (RST# low) by the input value of /ADR_WR. PCI bus power and signaling environment 3.3V 5V
*)
/ADR_WR during RST# low high *) low
Warning! /ADR_WR is an output after reset. So do not connect it directly to GND or VDD.
external pull-up resistor required (10k)
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3.1.4
PCI configuration registers
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The external EEPROM is optional. If no EEPROM is available, EE_SCL/EN must be connected to GND. Without EEPROM the PCI configuration registers will be loaded with the default values shown in Table 2. All registers which can be read from EEPROM can also be written by configuration write accesses. The addresses for configuration write are shown in the table below. Register Name Vendor ID Device ID Command Register Default Value 1397h 2BD0h Remarks Value can be read from EEPROM. Base address for configuration write is C0h. Value can be read from EEPROM. Base address for configuration write is C0h. Bits Function 0 Enables/disables I/O space accesses. 1 Enables/disables memory space accesses. 2 Enables/disables master accesses. 5..3 fixed to '0' 6 PERR# enable/disable 7 fixed to '0' 8 SERR# enable/disable 15..9 fixed to '0' Bits[7:0] can be read from EEPROM. Base address for configuration write is C4h. Bits Function 3..0 reserved 4 fixed to '1' 5 66MHz capable 6 User definable features supported 7 fast Back-to-Back capable 8 data parity error detected 10..9 fixed to '01': timing of DEVSEL# is medium 11 signaled target abort (fixed to '0') 12 received target abort 13 received master abort 14 signaled system error (Addr. parity error) 15 detected partity error HFC-S PCI A Value can be read from EEPROM. Base address for configuration write is C8h. Set to 16 clocks, value is fixed. Header Type 0 No build in self test supported. Bits[31:3] are r/w by configuration accesses Bits[31:8] are r/w by configuration accesses Value can be read from EEPROM. Base address for configuration write is ECh. Value can be read from EEPROM. Base address for configuration write is ECh. Offset to Power Management register block.
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0210h
Revision ID Class Code Latency Timer Header Type BIST I/O Base Address Memory Base Address Subsystem Vendor ID Subsystem ID Cap_Ptr
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02h 02 80 00h 10h 00h 00h
1397h 2BD0h 40h
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Default Value FFh 01h 00h 10h 01h 00h 7E21h Remarks This register must be configured by configuration write. INTA supported Value can be read from EEPROM. Base address for configuration write is FCh. Value can be read from EEPROM. Base address for configuration write is FCh. Capability ID. 01h identifies the linked list item as PCI Power Management registers. There are no next items in the linked list. Power Management Capabilities. See also PCI Bus Power Management Interface Specification. This register's value can be read from EEPROM. Base address for configuration write is E0h. PME# can be asserted from D0, D1, D2 and D3hot. Device specific initialisation is required. The HFC-S PCI A does not require PCI-clock to generate PME# (if S/T change state is selected). This function complies with the PCI Power Management Spec. Version 1.0. Power Management Control/Status Bits Function 15 PME_Status - This bit is set when the function would normally assert the PME# signal independent of the state of the PME_En bit. Writing a '1' to this bit will clear it and cause the function to stop asserting a PME# (if enabled). Writing a '0' has no effect. 14..9 fixed to '0' 8 PME_En - A '1' enables the function to assert PME#. When '0', PME# assertion is disabled. 7..2 fixed to '0' 1..0 PowerState - This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. 00b - D0 01b - D1 10b - D2 11b - D3hot All States except D0 disable HFC-S PCI A master accesses.
Register Name Interrupt Line Interrupt Pin Min_Gnt Max_Lat Cap_ID Next Ptr PMC
PMCSR
0000h
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Default Value 0000h Remarks Bits[31:15] are r/w by configuration accesses. The 32K Memory Window is for HFC-S PCI A internal use and for the B- and D-channel FIFOs. This register must be written by a "DWORD Config Write" to enable the HFC-S PCI A to operate in master mode.
Register Name 32K Memory Window Base Address (MWBA)
Table 2: PCI configuration registers' initial values Unimplemented registers return all 0's when read.
3.2
Internal HFC-S PCI A register description
If the HFC-S PCI A is used in memory mapped mode all register can directly be accessed by adding their CIP address to the configured Memory Base Address. In I/O address mapped mode the HFC-S PCI A occupies 8 bytes in the I/O address space. Byte 0 is for data read/write, byte 4 for register selection. The AUX-port address is selected by byte 3, AUX-port data is read/written by byte 1.
Figure 3: HFC-S PCI A in I/O address mapped mode
Figure 4: HFC-S PCI A in memory address mapped mode
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3.2.1
Registers of the S/T section Name STATES SCTRL SCTRL_E SCTRL_R SQ_REC SQ_SEND CLKDEL r/w r/w w w w r w w Function State of the TE/NT state machine S/T control register S/T control register (extended) receive enable for B-channels receive register for S/Q bits send register for S/Q bits setup of the delay time between receive and send direction (TE) receive data sample time (NT) B1-channel receive register B1-channel transmit register B2-channel receive register B2-channel transmit register D-channel receive register D-channel transmit register E-channel receive register
CIP / I/O-address 1100 0000 1100 0100 1100 1000 1100 1100 1101 0000 C0h C4h C8h CCh D0h
1101 1100
DCh
1111 0000
F0h
B1_REC*) B1_SEND*) B2_REC*) B2_SEND*) D_REC*) D_SEND*) E_REC*)
r w r w r w r
1111 0100
F4h
1111 1000
F8h
1111 1100
FCh
*)
These registers are read/written automatically by the HDLC FIFO controller (HFC) or GCI/IOM2 bus controller and need not be accessed by the user. To read/write data the FIFOs in the Memory Window should be used.
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3.2.2
Registers of the GCI/IOM2 bus section
GCI/IOM2 bus timeslot selection registers CIP / I/O-address 0000 1000 0000 1100 0010 1000 0010 1100 08h 0Ch 28h 2Ch Name C/I TRxR MON1_D MON2_D r/w r/w r r/w r/w Function C/I command/indication register Monitor Tx ready handshake first monitor byte second monitor byte
GCI/IOM2 bus timeslot selection registers CIP / I/O-address 1000 0000 1000 0100 1000 1000 1000 1100 1001 0000 1001 0100 1001 1000 1001 1100 80h 84h 88h 8Ch 90h 94h 98h 9Ch Name B1_SSL B2_SSL AUX1_SSL AUX2_SSL B1_RSL B2_RSL AUX1_RSL AUX2_RSL r/w w w w w w w w w Function B1-channel transmit slot (0..31) B2-channel transmit slot (0..31) AUX1-channel transmit slot (0..31) AUX2-channel transmit slot (0..31) B1-channel receive slot (0..31) B2-channel receive slot (0..31) AUX1-channel receive slot (0..31) AUX2-channel receive slot (0..31)
GCI/IOM2 bus data registers CIP / I/O-address 1010 0000 1010 0100 1010 1000 1010 1100 A0h A4h A8h ACh Name B1_D*) B2_D*) AUX1_D AUX2_D r/w r/w r/w r/w r/w Function GCI/IOM2 bus B1-channel data register GCI/IOM2 bus B2-channel data register AUX1-channel data register AUX2-channel data register
*)
These registers are read/written automatically by the HDLC FIFO controller (HFC) or by the S/T controller and need not be accessed by the user.
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GCI/IOM2 bus configuration registers CIP / I/O-address 1011 0100 1011 1000 1011 1100 B4h B8h BCh Name r/w Function extended mode register for GCI/IOM2 bus mode register for GCI/IOM2 bus connect functions for S/T, HFC, GCI/IOM2
MST_EMOD w MST_MODE w CONNECT w
3.2.3
Interrupt and status registers Name FIFO_EN TRM B_MODE CHIP_ID CIRM CTMT r/w w w w r w w Function FIFO enable/disable transparent mode interrupt mode register mode of B-channels register for chip identification interrupt selection and softreset register transparent mode and timer control register
CIP / I/O address 0100 0100 0100 1000 0100 1100 0101 1000 0110 0000 0110 0100 44h 48h 4Ch 58h 60h 64h
0110 1000 0110 1100
68h 6Ch
INT_M1 INT_M2
w w
interrupt mask register 1 interrupt mask register 2
0111 1000 0111 1100
78h 7Ch
INT_S1 INT_S2
r r
interrupt status register 1 interrupt status register 2
0111 0000
70h
STATUS
r
common status register
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3.2.4
Register list
Registers by Address Name C/I TRxR MON1_D MON2_D FIFO_EN TRM B_MODE CHIP_ID CIRM CTMT INT_M1 INT_M2 STATUS INT_S1 INT_S2 B1_SSL B2_SSL AUX1_SSL AUX2_SSL B1_RSL B2_RSL AUX1_RSL AUX2_RSL B1_D B2_D AUX1_D AUX2_D MST_EMOD MST_MODE CONNECT STATES SCTRL SCTRL_E SCTRL_R SQ_REC SQ_SEND CLKDEL B1_REC B1_SEND B2_REC B2_SEND D_REC D_SEND E_REC Registers by Name Name AUX1_D AUX1_RSL AUX1_SSL AUX2_D AUX2_RSL AUX2_SSL B_MODE B1_D B1_REC B1_RSL B1_SEND B1_SSL B2_D B2_REC B2_RSL B2_SEND B2_SSL C/I CHIP_ID CIRM CLKDEL CONNECT CTMT D_REC D_SEND E_REC FIFO_EN INT_M1 INT_M2 INT_S1 INT_S2 MON1_D MON2_D MST_EMOD MST_MODE SCTRL SCTRL_E SCTRL_R SQ_REC SQ_SEND STATES STATUS TRM TRxR
Address 08h 0Ch 28h 2Ch 44h 48h 4Ch 58h 60h 64h 68h 6Ch 70h 78h 7Ch 80h 80h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B4h B8h BCh C0h C4h C8h CCh D0h D0h DCh F0h F0h F4h F4h F8h F8h FCh
Page 39 39 19 19 41 43 42 42 41 42 43 43 45 44 44 37 37 37 37 37 37 37 37 37 37 37 37 39 38 40 34 35 35 36 36 36 36 18 18 18 18 18 18 18
Address A8h 98h 88h ACh 9Ch 8Ch 4Ch A0h F0h 90h F0h 80h A4h F4h 94h F4h 80h 08h 58h 60h DCh BCh 64h F8h F8h FCh 44h 68h 6Ch 78h 7Ch 28h 2Ch B4h B8h C4h C8h CCh D0h D0h C0h 70h 48h 0Ch
Page 37 37 37 37 37 37 42 37 18 37 18 37 37 18 37 18 37 39 42 41 36 40 42 18 18 18 41 43 43 44 44 19 19 39 38 35 35 36 36 36 34 45 43 39
Table 3: Register list by address
Table 4: Register list by name
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3.3
Power Management Support of HFC-S PCI A
Because of the very low power dissipitation of HFC-S PCI A device there is no need of reducing power in standby mode. Furthermore the main source of power dissipation is the 33MHz PCI clock. So the biggest reduction in power dissipation of the device can be achieved by stopping the PCI clock which can only be done by the PCI bridge generating the PCI clock for the PCI slot concerned. So the lowest power is needed in bus states B2 and B3. Another minor reduction of power dissipation can be achieved by stopping the 12.288 MHz clock for the ISDN part of the HFC-S PCI A. If no awake (restart of oscillation) from S/T bus activity is selected the power dissipation can be reduced to less then 3mW if PCI clock is also stopped. None of the settings above are accomplished by changing the power states from D0 to D1, D2 or D3hot. The register settings are only implemented to be compatible to PCI Power Management Specification. So no reduction of power is achieved by purely changing the power states. In the following paragraph the awake scenarios for asserting PME# from different power states are described.
3.3.1
PME events
Generally the source for PME# generation can be selected from: 1. D-channel receive frame interrupt This is only possible in power state D0 and bus state B0 because D-channel data is put into the memory window (MW) of the HFC-S PCI A which is located in the memory space of the host PC. 2. S/T state change normally generated due to S/T interface activation from outside This is the normal source of the PME# event. In this case the PME# pin can be asserted in any power state (D0 - D3hot).
3.3.2
Special considerations for support of D3cold
The HFC-S PCI A was not specially designed to support D3cold. However it is possible to use the device even in D3cold applications if an external power supply or the Vaux3.3 is available. The device should be powered in a way that if the main supply is switched off the device is automatically feed by the auxiliary power supply. Because PME context (PME_Status and PME_En) bits in PCMCSR register is not maintained when the device is reset (RST# asserted) the device must be prevented from being reset if main power is off. This unwanted reset is normally done due to dropping of all PCI input signals to GND when power is switched off.
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With the additional device in Figure 5 the ability to react on RST# asserted can be switched off and on by masking the RST# pin. Because of a power on reset circuitry connected to the auxiliary power source the RST# masking is switched off when power is first time switched on. In the preparation process for D3cold e.g. when the context of the chip must be saved before power is switched off the device driver must set the RES# mask bit to prevent an unwanted reset when the PC is switched off. After getting power again and the reinitialisation of the chip is initiated the RST# mask bit is reset again by the device driver.
3. 3 V aux V i/ o pc i 3. 3V / 5V Q1 3 B C 560C 1 2 R1 10k D1 B C 560C 1 R2 10k 3 2 Q2
For universal PCI board power supply can be 3.3V or 5V. For 3.3V PCI board power supply must be 3.3V. For 5V PCI board power supply must be 5V.
1N 4148 VD D H F C R3 CB 1M C1 1u GN D all V c c P ins / A U X_W R D A U X0 14 6 16 4 18 3 20 19 2
U3 VC C 2C LR 1C LR 2P R E 1P R E 2C LK 2Q 1C LK 1Q 2D 1D 2Q 1Q 12 9 13 8
H F C -S P C I A D2
R S T#
The receiver and transmitter circuitry must be selected correspondingly.
74H C 74/ LC C
1N 4148 R4 10k
R S T# (P C I s lot )
Figure 5: Masking RST# for D3cold Support
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For 3.3V PCI boards Vcc must be 3.3V and the 3.3V receiver/transmitter circuitry must be used which can be found in the HFC-S PCI A datasheet. For 5V PCI boards Vcc must be 5V and the 5V receiver/transmitter circuitry must be used which can be found in the HFC-S PCI A datasheet. For the universal PCI board with auto power detection Vcc can be either 3.3V or 5V and the receiver/transmitter circuitry for the universal PCI board must be used which can be found in the universal PCI board sample circuitry for 3.3V and 5V power supply (see 12.5).
Literature Further information about PCI Power Management can be found in the following specifications: - PCI Local Bus Specification, Revision 2.2, December 18, 1998 - PCI Bus Power Management Interface Specification, Revision 1.1, December 18, 1998
3.4
Timer
The HFC-S PCI A includes a timer with interrupt capability. The timer counts F0IO pulses. So the timer counter is incremented every 125s. It can be reset by bit 7 of of the CTMT register. Furthermore the timer is reset at every HFC-S PCI A access when bit 5 of the CTMT register is set. Seven different timer values can be selected.
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3.5
FIFOs
All FIFOs are located in the 32K Memory Window (MW) in host PC's memory. There are 6 FIFOs with 6 HDLC-Controllers handled by the HFC-S PCI A. The HDLC circuits are located on the S/T device side of the HFC-S PCI A. So always plain data is stored in the FIFO. Zero insertion and deletion is done in HDLC mode: - if the data goes to the S/T or GCI/IOM device in send FIFOs and - when the HDLC data comes from the S/T device or GCI/IOM2 bus in receive operation. There are a send and a receive FIFO for each of the two B-channels and for the D-channel. The FIFOs are realized as ring buffers in the 32K Memory Window in host PC's memory. To control them there are some counters. B-channel 13 Bit 13 Bit D-channel 9 Bit 9 Bit
Z1: FIFO input counter Z2: FIFO output counter
Each counter points to a byte position in the Memory Window. This is an offset to the 32K Memory Window Base Address in the configuration space. On a FIFO input operation Z1 is incremented. On an output operation Z2 is incremented. After every pulse on the F0IO signal two HDLC-bytes are written into the S/T interface (FIFOs No. 0 and 2) and two HDLC-bytes are read from the S/T interface (FIFOs No. 1 and 3). D-channel data is handled in a similar way but only 2 bits are processed.
* important!
Instead of the S/T interface also GCI/IOM2 bus is selectable for each B-channel (see CONNECT register). If Z1 = Z2 the FIFO is empty. Additionally there are two counters F1 and F2 for every FIFO channel (5Bit for B-channel, 4Bit for Dchannel). They count the HDLC-frames in the FIFOs and form a ring buffer as Z1 and Z2 do, too. F1 is incremented when a complete frame has been received and stored in the FIFO. F2 is incremented when a complete frame has been read from the FIFO. If F1 = F2 there is no complete frame in the FIFO. When the RESET line is active or software reset is active Z1, Z2, F1 and F2 are all initialized to all 1s. All Zx and Fx counters are also stored in the Memory Window. So it is easy to read and write the counters by simple host memory accesses.
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Because the HFC-S PCI A is limited to the 32K Memory Window data in different regions of the host PC can not be overwritten even if counter and pointer values are handled in a wrong way.
* important!
The counter state 0200h of the Z-counters follows counter state 1FFFh in the B-channel FIFOs. The counter state 000h of the Z-counters follows counter state 1FFh in the D-channel FIFOs. The counter state 00h of the F-counters follows counter state 1Fh in the B-channel FIFOs. The counter state 10h of the F-counters follows counter state 1Fh in the D-channel FIFOs.
3.5.1
FIFO counters location in Memory Window
For each FIFO one F1 and one F2 counter is available. The counters are located at the following offsets to the Memory Window Base Address (MWBA) in the Memory Window (MW). FIFO B1-transmit B1-receive B2-transmit B2-receive D-transmit D-receive Counter F1 F2*) F1*) F2 F1 F2*) F1*) F2 F1 F2*) F1*) F2 Offset to Memory Window Base Address 2080h 2081h 6080h 6081h 2180h 2181h 6180h 6181h 20A0h 20A1h 60A0h 60A1h Counter Size in Bytes 1 1 1 1 1 1 1 1 1 1 1 1
*)
These counters are handled by the HFC-S PCI A automatically and must not be written by software.
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For each FIFO an array of Z1 and Z2 counters is available. The offset of the counters to the Memory Window Base Address (MWBA) can be calculated as shown in the following table. FIFO B1-transmit B1-receive B2-transmit B2-receive D-transmit D-receive Counter Z1 Z2*) Z1*) Z2 Z1 Z2*) Z1*) Z2 Z1 Z2*) Z1*) Z2 Offset to Memory Window Base Address 2000h + (Fx * 4) 2000h + (Fx * 4) + 2 6000h + (Fx * 4) 6000h + (Fx * 4) + 2 2100h + (Fx * 4) 2100h + (Fx * 4) + 2 6100h + (Fx * 4) 6100h + (Fx * 4) + 2 2080h + (Fx * 4) 2080h + (Fx * 4) + 2 6080h + (Fx * 4) 6080h + (Fx * 4) + 2 Counter Size in Bytes 2 2 2 2 2 2 2 2 2 2 2 2
*)
These counters are handled by the HFC-S PCI A automatically and must not be written by software.
Fx is either F1 or F2. F1 is used for input data in transmit FIFOs, F2 is used for output data in receive FIFOs.
3.5.2 FIFO
FIFO data location in Memory Window Starting at Offset 0200h 4200h 2200h 6200h 0000h 4000h Ending at Offset 1FFFh 5FFFh 3FFFh 7FFFh 01FFh 41FFh Offset to add to Z-counters value 0000h 4000h 2000h 6000h 0000h 4000h
B1-transmit B1-receive B2-transmit B2-receive D-transmit D-receive
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3.5.3
FIFO channel operation
J3_e^dUbc dQR\U Y^ =U]_bi GY^T_g
Fx = 00h F2 F2 = 02h
Z 1 00 Z 1 02
Z 2 00 Z 2 02
e nd of fra m e
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o u tp u t fra m e 0 2 fra m e 0 3
F1
F1 = 07h
Z 1 06 Z 1 07
e nd o f fra m e
fra m e 0 6 in p ut fra m e 0 7
Fx = 1Fh
Figure 6: FIFO Organisation (shown for B-channel, similar for D-channel)
3.5.3.1 Send channels (B1, B2 and D transmit) The send channels send data from the host bus interface to the FIFO and the HFC-S PCI A converts the data into HDLC code and tranfers it from the FIFO into the S/T or/and the GCI/IOM2 bus interface write registers. The HFC-S PCI A checks Z1 and Z2. If Z1=Z2 (FIFO empty) the HFC-S PCI A generates a HDLC-Flag (01111110) and sends it to the S/T device. In this case Z2 is not incremented. If also F1=F2 only HDLC flags are sent to the S/T interface and all counters remain unchanged. If the frame counters are unequal F2 is incremented and the HFC-S PCI A tries to send the next frame to the output device. After the end of a frame (Z2 reaches Z1) it automatically generates the 16 bit CRC checksum and adds the ending flag. If there is another frame in the FIFO (F1F2) the F2 counter is incremented. With every byte being sent from the host bus side to the FIFO Z1 is incremented automatically. If a complete frame has been sent F1 must be incremented to send the next frame. If the frame counter F1 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 6). Z1(F1) is used for the frame which is just written from the PC-bus side. Z2(F2) is used for the frame which is just beeing transmitted to the S/T device side of the HFC-S PCI A. Z1(F2) is the end of frame pointer of the current output frame.
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In the send channels F1 is only changed from the PC interface side if the software driver wants to say end of send frame". Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start address of the next frame. Z1(F2) and Z2(F2) can not be accessed.
3.5.3.2 Automatically D-channel frame repetition The D-channel send FIFO has a special feature. If the S/T interface signals a D-channel contention before the CRC is sent the Z2 counter is set to the starting address of the current frame and the HFCS PCI A tries to repeat the frame automatically.
* important!
The HFC-S PCI A begins to transmit bytes from a FIFO at the moment Z1 Z2. So if the Z1 pointer is updated by software after writing the transmit data into the FIFO space of the Memory Window the transmission starts.
3.5.3.3 FIFO full condition in send channels FIFO full condition can easily be calculated from the Z1/Z2 table in the Memory Window. Remember that an increment of Z-value 1FFFh is 0200h in the B-channels! There are two different FIFO full conditions. The first one is met when the FIFO contents comes up to 31 frames (B-channel) or 15 frames (D-channel). There is no possibility for the HFC-S PCI A to manage more frames even if the frames are very small. The second limitation is the size of the FIFO which is 512 byte for the D-channel and 7.5 KByte for the B-channels.
3.5.3.4 Receive Channels (B1, B2 and D receive) The receive channels receive data from the S/T or GCI/IOM2 bus interface read registers. The data is converted from HDLC into plain data and sent to the FIFO. The data can then be read via the host bus interface. The HFC-S PCI A checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does not generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is converted by the HFC-S PCI A into plain data. After the ending flag of a frame the HFC-S PCI A checks the HDLC CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the FIFO named STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct CRC field at the end of the frame.
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Figure 7: FIFO Data Organisation The ending flag of a HDLC-frame can also be the starting flag of the next frame. After a frame is received completely F1 is incremented by the HFC-S PCI A automatically and the next frame can be received. After reading a frame via the host bus interface F2 must be incremented. If the frame counter F2 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 6). Z1(F1) is used for the frame which is just received from the S/T device side of the HFC. Z2(F2) is used for the frame which is just beeing transmitted to the host bus interface. Z1(F2) is the end of frame pointer of the current output frame. To calculate the length of the current receive frame the software has to evaluate Z1-Z2+1. In the receive channels F2 must be incremented to point to the next Z1/Z2 pair. If Z1 = Z2 and F1 = F2 the FIFO is totally empty.
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3.5.3.5 FIFO full condition in receive channels Because the ISDN-B-channels and the ISDN-D-channels have no hardware based flow control there is no possibility to stop input data if a receive FIFO is full. So there is no FIFO full condition implemented in the HFC-S PCI A. The HFC-S PCI A assumes that the FIFOs are so deep that the host processor hard- and software is able to avoid any overflow of the receive FIFOs. Overflow conditions are again more than 31 input frames (15 frames for D-channel) or a real overflow of the FIFO because of excessive data. Because HDLC procedures only know a window size of 7 frames no more than 7 frames are sent without software intervention. Due to the great size of the FIFOs of the HFC-S PCI A it is easy to poll counters in the Memory Window even in large time intervalls without having to fear a FIFO overflow condition. However to avoid any undetected FIFO overflows the software driver should check the number of frames in the FIFO which is F1-F2. An overflow exists if the number (F1-F2) is less than the number in the last reading even if there was no reading of a frame in between. After a detected FIFO overflow condition this FIFO must be reset.
3.5.3.6 FIFO initialisation All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET. Then the result is Z1 = Z2 = 1FFFh and F1 = F2 = 1Fh for the B-channels and Z1 = Z2 = 1FFh and F1 = F2 = 1Fh for the D-channel. This information is written in the Memory Window for initialisation. Please mask bit 4 of D-channel from counter F1, F2. The same initialisation is done if the bit 3 in the CIRM register is set (soft reset). During initialisation phase the HFC-S PCI A must not be accessed. Bit 1 of the STATUS register is cleared to '0' to indicate that the initialisation phase has been finished.
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3.5.4
Transparent mode of HFC-S PCI A
You can switch off HDLC operation for each B-channel independently. There is one bit for each Bchannel in the CTMT control register. If this bit is set data in the FIFO is sent directly to the S/T or GCI/IOM2 bus interface and data from the S/T or GCI/IOM2 bus interface is sent directly to the FIFO. Be sure to switch into transparent mode only if F1=F2. Being in transparent mode the Fx counters remain unchanged. Z1 and Z2 are the input and output pointers respectively. Because F1=F2 both Z-counters are always accessable and have valid data. If a send FIFO channel changes to FIFO empty condition no CRC is generated and the last data byte written into the FIFO is repeated until there is new data. In receive channels there is no check on flags or correct CRCs and no status byte is added. The byte bounderies are not arbitrary like in HDLC mode where byte synchronisation is achieved with HDLC-flags. The data is just the same as it comes from the S/T or GCI/IOM2 bus interface or is sent to this. Send and receive transparent data can be handled in two ways. The usual way is transmitting B-channel data with the LSB first as it is usual in HDLC mode. The second way is sending the bytes in reverse bit order as it is usual for PWM data. So the first bit is the MSB. The bit order can be reversed by setting the corresponding bits in the CIRM register.
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3.6
Configuring test loops
For electrical tests of layer 1 it is useful to create a S/T test loop for the B1/B2 channel. The test loop described here transmits the data that has been received on the B1 or B2 channel to the same channel on the S/T interface. The 32K Memory Window Base Address (MWBA) PCI configuration register must be written first to enable PCI master accesses of the HFC-S PCI A. To configure the test loop the following must be done: - write 0Fh to register CLKDEL (DCh) // Adjust the phase offset between receive and // transmit direction (the value depends on the external // circuitry). // 03h is to enable B1, B2 at the S/T interface for // transmission // 40h is for TX_LO setup (capacitive line mode) // Release S/T state machine for activation over the // S/T interface by incoming INFO 2 or INFO 4. // Configure S/T B1 and B2 channel to normal // receive operation. // Configure CONNECT register for B1/B2 channel // test loop. // Enable transmit channel for GCI/IOM2 bus, pin // STIO1 is used as output, use time slot #0. // Enable receive channel for GCI/IOM2 bus, pin // STIO1 is used as input, use time slot #0. // Enable transmit channel for GCI/IOM2 bus, pin // STIO1 is used as output, use transmission slot #1. // Enable receive channel for GCI/IOM2 bus, pin // STIO1 is used as input, use time slot #1. // Configure HFC-S PCI A as GCI/IOM2 bus master.
- write 43h to register SCTRL (C4h)
- write 00h to register STATES (C0h)
- write 03h to register SCTRL_R (CCh)
- write 36h to register CONNECT (BCh)
- write 80h to register B1_SSL (80h)
- write C0h to register B1_RSL (90h)
- write 81h to register B2_SSL (84h)
- write C1h to register B2_RSL (94h)
- write 01h to register MST_MODE (B8h)
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4
4.1
Register bit description
Register bit description of S/T section Addr. C0h Bits 3..0 4 5 r/w r r r Function binary value of actual state (NT: Gx, TE: Fx) Frame-Sync ('1'=synchronized) '1' timer T2 expired (NT mode only, see also 8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT on page 62) '1' receiving INFO0 '0' no operation '1' in NT mode allows transition from G2 to G3. This bit is automatically cleared after the transition. binary value of new state (NT: Gx, TE: Fx) (bit 4 must also be set to load the state). '1' loads the prepared state (bit 3..0) and stops the state machine.This bit needs to be set for a minimum period of 5.21Ps and must be cleared by software. (reset default) '0' enables the state machine (bits 3..0 are ignored). After writing an invalid state the state machine goes to deactivated state (G1, F2) '00' no operation '01' no operation '10' start deactivation '11' start activation The bits are automatically cleared after activation/deactivation. '0' no operation '1' in NT mode allows transition from G2 to G3. This bit is automatically cleared after the transition.
Name STATES (read)
6 7
r r
STATES (write)
C0h
3..0 4
w w
6..5
w
7
w
* important!
The state machine is stuck to '0' after a reset. Writing a '0' to bit 4 of the STATES register restarts the state machine. In this state the HFC-S PCI A sends no signal on the S/T-line and it is not possible to activate it by incoming INFOx. NT mode: The NT state machine does not change automatically from G2 to G3 if the TE side sends INFO3 frames. This transition must be activated each time by bit 7 of the STATES register. Fix the NT state machine to state G3 when activated (by writing 13h into STATES register). This prevents deactivation of NT mode S/T interface due to sporadically errors on NT input data.
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Name SCTRL
Addr. C4h
Bits 0
1
2
3
4
5 6
7
SCTRL_E
C8h
0
1 2
3
6..4 7
r/w Function B-channel enable w '0' B1 send data disabled (permanent 1 sent in activated states, reset default) '1' B1 data enabled w '0' B2 send data disabled (permanent 1 sent in activated states, reset default) '1' B2 data enabled w S/T interface mode '0' TE mode (reset default) '1' NT mode w D-channel priority '0' high priority 8/9 (reset default) '1' low priority 10/11 w S/Q bit transmission '0' S/Q bit disable (reset default) '1' S/Q bit and multiframe enable w '0' normal operation (reset default) '1' send 96kHz transmit test signal (alternating zeros) w TX_LO line setup This bit must be configured depending on the used S/T module and circuitry to match the 400 pulse mask test. '0' capacitive line mode (reset default) '1' non capacitive line mode w Power down '0' power up, oscillator active (reset default) '1' power down, oscillator stopped w Power down mode bit '0' S/T awake disable (reset default) Power up can only be programmed by register access (SCTRL bit 7). '1' S/T awake enable. Oscillator starts on every non INFO0 S/T signal. w must be '0' w D reset '0' normal operation (reset default) '1' D bits are forced to '1' w D_U enable '0' normal operation (reset default) '1' D channel is always send enabled regardless of E receive bit w must be '0' w '0' normal operation (reset default) '1' B1/B2 are exchanged in the S/T interface
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Name SCTRL_R
Addr. CCh
Bits 0 1
SQ_REC
D0h
7..2 3..0
4 6..5 7 SQ_SEND D0h 3..0
CLKDEL
DCh
7..4 3..0
6..4
7
r/w Function w B1-channel receive enable w B2-channel receive enable '0' B-receive bits are forced to '1' '1' normal operation w unused r TE mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4) NT mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3, bit 0 = Q4) r '1' a complete S or Q multiframe has been received Reading SQ_REC clears this bit. r not defined r '1' ready to send a new S or Q multiframe Writing to SQ_SEND clears this bit. w TE mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3, bit 0 = Q4) NT mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4) w not defined w TE: 4 bit delay value to adjust the 2 bit delay time between receive and transmit direction. The delay of the external S/T-interface circuit can be compensated. The lower the value the smaller the delay between receive and transmit direction (see also Figure 15) NT: Data sample point. The lower the value the earlier the input data is sampled. The steps are 163ns. w NT mode only early edge input data shaping Low pass characteristic of extended bus configurations can be compensated. The lower the value the earlier input data pulse is sampled. No compensation means a value of 6 (110b). Step size is the same as for bits 3-0. w unused
* note!
The register is not initialized with a '0' after reset. The register should be initialized as follows before activating the TE/NT state machine: TE mode: 0Dh .. 0Fh NT mode: 6Ch
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4.2
Register bit description of GCI/IOM2 bus section
Timeslots for transmit direction Name B1_SSL B2_SSL AUX1_SSL AUX2_SSL Addr. 80h 84h 88h 8Ch Bits 4..0 5 6 r/w w w w Function select GCI/IOM2 bus transmission slot (0..31) unused select GCI/IOM2 bus data lines '0' STIO1 output '1' STIO2 output transmit channel enable for GCI/IOM2 bus '0' disable (reset default) '1' enable
7
w
* important!
Enabling more than one channel on the same slot causes undefined output data.
Timeslots for receive direction Name B1_RSL B2_RSL AUX1_RSL AUX2_RSL Addr. 90h 94h 98h 9Ch Bits 4..0 5 6 r/w w w w Function select GCI/IOM2 bus receive slot (0..31) unused select GCI/IOM2 bus data lines '0' STIO2 is input '1' STIO1 is input receive channel enable for GCI/IOM2 bus '0' disable (reset default) '1' enable
7
w
Data registers Name B1_D B2_D AUX1_D AUX2_D Addr. A0h A4h A8h ACh Bits 0..7 r/w Function r/w read/write data registers for selected timeslot data
* note!
If the data registers AUX1_D and AUX2_D are not overwritten, the transmisson slots AUX1_SSL and AUX2_SSL mirror the data received in AUX1_RSL and AUX2_RSL slots. This is useful for an internal connection between two CODECs. This mirroring is disabled by setting bit 1 in MST_EMOD register
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Name MST_MODE
Addr. B8h
Bits 0
1
2
3
5, 4
7, 6
r/w Function w GCI/IOM2 bus mode '0' slave (reset default) (C4IO and F0IO are inputs) '1' master (C4IO and F0IO are outputs) w polarity of C4- and C2O-clock '0' F0IO is sampled on negative clock transition '1' F0IO is sampled on positive clock transition w polarity of F0-signal '0' F0 positive pulse '1' F0 negative pulse w duration of F0-signal '0' F0 active for one C4-clock (244ns) (reset default) '1' F0 active for two C4-clocks (488ns) w time slot for codec-A signal F1_A '00' B1 receive slot '01' B2 receive slot '10' AUX1 receive slot '11' signal C2O pin F1_A (C2O is 2048 kHz clock) w time slot for codec-B signal F1_B '00' B1 receive slot '01' B2 receive slot '10' AUX1 receive slot '11' AUX2 receive slot
The pulse shape and polarity of the codec signals F1_A and F1_B is the same as the pulseshape of the F0IO signal. The polarity of C2O can be changed by bit 1. RESET sets register MST_MODE to all '0's.
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Name MST_EMOD
Addr. B4h
Bits 0
1
2 5..3
6 7
C/I
08h
3..0 7..4 0 1 5..2 6 7
TRxR
0Ch
r/w Function w slow down C4IO clock adjustment (see Figure 18) '0' C4IO clock is adjusted in the 31th time slot twice for one half clock cycle (reset default) '1' C4IO clock is adjusted in the 31th time slot once for one half clock cycle w enable/disable AUX channel mirroring '0' normal opration (reset default) '1' disable AUX channel data mirroring w unused w select D-channel data flow (see also: CONNECT register) destination source bit 3: '0' D-HFC D-S/T '1' D-HFC D-GCI/IOM2 bit 4: '0' D-S/T D-HFC '1' D-S/T D-GCI/IOM2 bit 5: '0' D-GCI/IOM2 D-HFC '1' D-GCI/IOM2 D-S/T w unused w enable GCI/IOM2 write slots '0' disable GCI/IOM2 write slots; slot #2 and slot #3 may be used for normal data '1' enables slot #2 and slot #3 as master, D- and C/I-channel r/w on read: indication on write: command unused r '1' monitor receive ready (2 bytes received) This bit is reset after read of second monitor byte (MON2_D) r '1' Monitor transmitter ready Writing on MON2_D starts transmisssion and resets this bit. r reserved r STIO2 in r STIO1 in
RESET sets register MST_EMOD to all '0's.
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4.3
Register bit description of CONNECT register Addr. BCh Bits 2..0 r/w Function w select B1-channel data flow destination bit 0: '0' B1-HFC '1' B1-HFC bit 1: '0' B1-S/T '1' B1-S/T bit 2: '0' B1-GCI/IOM2 '1' B1-GCI/IOM2 w select B2-channel data flow destination bit 3: '0' B2-HFC '1' B2-HFC bit 4: '0' B2-S/T '1' B2-S/T bit 5: '0' B2-GCI/IOM2 '1' B2-GCI/IOM2 w unused
Name CONNECT

source B1-S/T B1-GCI/IOM2 B1-HFC B1-GCI/IOM2 B1-HFC B1-S/T source B2-S/T B2-GCI/IOM2 B2-HFC B2-GCI/IOM2 B2-HFC B2-S/T
5..3
7..6
RESET sets CONNECT register to all '0's. The following figure shows the different options for switching the B-channels with the CONNECT register.
Figure 8: Function of the CONNECT register bits
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4.4 Name CIRM
Register bit description of auxiliary and cross data registers Addr. 60h Bits 2..0 r/w Function w defines the length of the auxiliary port access: Value Cycle time (AUX_WR or AUX_RD low) 000b 1 PCI-Clock 001b 3 PCI-Clocks 010b 5 PCI-Clocks 011b 7 PCI-Clocks 100b 9 PCI-Clocks 101b 11 PCI-Clocks 110b 13 PCI-Clocks 111b 15 PCI-Clocks w soft reset, similar as hardware reset; the registers CIP, CIRM and CTMT are not changed. The PCI interface is not reset. The reset is active until the bit is cleared. '0' deactivate reset (reset default) '1' activate reset w must be '0' w select bit order for B1 channel '0' normal read/write data operation '1' reverse bit order read/write data operation w select bit order for B2 channel '0' normal read/write data operation '1' reverse bit order read/write data operation w FIFO enable/disable ('1' = enable (reset default)) Bit FIFO 0 B1-transmit 1 B1-receive 2 B2-transmit 3 B2-receive 4 D-transmit 5 D-receive The enable/disable change becomes valid between 0 and 250s after the bit has been written. All PCI bus accesses and FIFO activities are disabled for the selected FIFOs. To avoid unnecessary PCI transfers all unused FIFOs should be disabled. At least one FIFO (usually D-receive) must be enabled. w unused, should be '0'
3
5..4 6
7
FIFO_EN
44h
5..0
7..6
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Name CTMT
Addr. 64h
Bits 0
1
4..2
5
6 7
CHIP_ID
58h
0
3..1 7..4 B_MODE 4Ch 1..0 2 3 4
5
6 7
r/w Function w HDLC/transparent mode for B1-channel '0' HDLC mode (reset default) '1' transparent mode w HDLC/transparent mode for B2-channel '0' HDLC mode (reset default) '1' transparent mode w select timer (bit 4 = MSB) timer '000' off '001' 3.125ms '010' 6.25ms '011' 12.5ms '100' 25ms '101' 50ms '110' 400ms '111' 800ms w timer reset mode '0' reset timer by CTMT bit 7 (reset default) '1' automatically reset timer at each access to HFC-S PCI A w ignored w reset timer '1' reset timer This bit is automatically cleared. r power supply '0' 5V PCI signaling environment '1' 3.3V PCI signaling environment r reserved r Chip identification 0011b HFC-S PCI A w unused w in 64 kbit/s mode: bit is ignored in 56 kbit/s mode: value of the LSB in 7-bit mode w unused w 56 kbit/s mode selection bit for B1-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode w 56 kbit/s mode selection bit for B2-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode w '0' Data not inverted for B1-channel (reset default) '1' Data inverted for B1-channel w '0' Data not inverted for B2-channel (reset default) '1' Data inverted for B2-channel
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Name INT_M1
Addr. 68h
Bits 0 1 2 3 4 5 6 7
r/w w w w w w w w w
Function interrupt mask for channel B1 in transmit direction interrupt mask for channel B2 in transmit direction interrupt mask for channel D in transmit direction interrupt mask for channel B1 in receive direction interrupt mask for channel B2 in receive direction interrupt mask for channel D in receive direction interrupt mask for state change of TE/NT state machine interrupt mask for timer
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'. Name INT_M2 Addr. 6Ch Bits 0 1 2 3 6..4 7 r/w w w w w w w Function interrupt mask for processing/non processing phase transition interrupt mask for GCI I-change interrupt mask for GCI monitor receive enable for interrupt output ('1' = enable) unused PMESEL '0' PME triggered on D-channel receive int '1' PME triggered on S/T interface state change
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'. Name TRM Addr. 48h Bits 1..0 r/w Function w interrupt in transparent mode is generated if Z1 in receive FIFOs or Z2 in transmit FIFOs change from: 00: x xxxx x011 1111 x xxxx x100 0000 01: x xxxx 0111 1111 x xxxx 1000 0000 10: x xxx0 1111 1111 x xxx1 0000 0000 11: x 0111 1111 1111 x 1000 0000 0000 w must be '0' w E B2 receive channel When set the E receive channel of the S/T interface is connected to the B2 receive channel. w B1+B2 mode '0' normal operation (reset default) '1' B1+B2 are combined to one HDLC or transparent channel. All settings for data shape and connect are derived from B1. Both B1 and B2 channel FIFOs must be enabled to use B1+B2 mode. w IOM test loop When set MST output data is looped to the MST input.
4..2 5
6
7
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Name INT_S1
Addr. 78h
Bits 0 1
2
3 4
5
6 7 INT_S2 7Ch 0
1 2 6..3 7
r/w Function r B1-channel interrupt status in transmit direction r B2-channel interrupt status in transmit direction in HDLC mode: '1' a complete frame has been transmitted, the frame counter F2 has been incremented in transparent mode: '1' interrupt as selected in TRM register bits 1..0 r D-channel interrupt status in transmit direction '1' a complete frame was transmitted, the frame counter F2 was incremented r B1-channel interrupt status in receive direction r B2-channel interrupt status in receive direction in HDLC mode: '1' a complete frame has been transmitted, the frame counter F1 has been incremented in transparent mode: '1' interrupt as selected in TRM register bits 1..0 r D-channel interrupt status in receive direction '1' a complete frame was received, the frame counter F1 was incremented r TE/NT state machine interrupt status '1' state of state machine changed r timer interrupt status '1' timer is elapsed r processing/non processing transition interrupt status '1' The HFC-S PCI A has changed from processing to non processing state. r GCI I-change interrupt '1' a different I-value on GCI was detected r receiver ready (RxR) of monitor channel '1' 2 monitor bytes have been received r unused, '0' r '1' fatal error: synchronisation lost. PCI performance too low for HFC-S PCI A. Only soft reset recovers from this situation.
* important!
Reading the INT_S1 or INT_S2 register resets all active read interrupts in the INT_S1 or INT_S2 register. New interrupts may occur during read. These interrupts are reported at the next read of INT_S1 or INT_S2. All interrupt bits are reported regardless of the mask registers settings (INT_M1 and INT_M2). The mask register settings only influence the interrupt output condition. The interrupt output goes inactive during the read of INT_S1 or INT_S2. If interrupts occur during this read the interrupt line goes active immediately after the read is finished. So processors with level or transition triggered interrupt inputs can be connected.
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Name STATUS
Addr. 70h
Bits 0 1
2
3 4
5 6 7
r/w Function r always '0' r processing/non processing status '1' the HFC-S PCI A is in processing phase (every 125s) '0' the HFC-S PCI A is not in processing phase r processing/non processing transition interrupt status '1' The HFC-S PCI A has finished internal processing phase (every 125s) r always '0' r timer status '0' timer not elapsed '1' timer elapsed r TE/NT state machine interrupt state '1' state of state machine has changed r FRAME interrupt has occured (any data channel interrupt) all masked D-channel and B-channel interrupts are "ored" r ANY interrupt all masked interrupts are "ored"
Reading the STATUS register clears no bit.
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5
Electrical characteristics
Symbol VDD VI VO Topr Tstg Rating -0.3V to +7.0V -0.3V to VDD + 0.3V -0.3V to VDD + 0.3V -10C to +85C -40C to +125C
Absolute maximum ratings Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature
Recommended operating conditions Parameter Supply voltage Operating temperature Symbol VDD Topr Condition VDD=5V VDD=3.3V MIN. 4.75V 3.15V 0C TYP. 5.0V 3.3V MAX. 5.25V 3.45V +70C
Electrical characteristics for 5V power supply
VDD = 4.75V to 5.25V, Topr = 0C to +70C
Parameter Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage Output leakage current Pull-up resistor input current
Symbol VIL VIH VOL VOH | IOZ | | IIL |
Condition
High Z VI = VSS
TTL level MIN. TYP. MAX. 0.8V 2.0V 0.4V 4.3V 10A 50A
CMOS level MIN. TYP. MAX. 1.0V 3.5V 0.4V 4.3V 10A 50A
Electrical characteristics for 3.3V power supply
VDD = 3.15V to 3.45V, Topr = 0C to +70C
Parameter Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage
Symbol VIL VIH VOL VOH
Condition MIN. 2.0V
TTL level TYP. MAX. 0.8V 0.4V
2.4V
CMOS level MIN. TYP. MAX. 1.0V 2.3V 0.4V 2.4V
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DC current consumption of HFC-S PCI A
25C ambient temperature, 5 V operating voltage, 33 MHz PCI clock
Condition PCI master, PCM master (full operational) power down, no S/T awake (12.288 MHz OSC off) All pins GND (except power supply)
MIN.
TYP. 24,5 mA 15 mA
MAX.
1 mA
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I/O Characteristics Input AD0-31 PAR C/BE0-3 RST# FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# GNT# PERR# DAUX0-7 C4IO F0IO STIO1-2 EE_SDA EE_SCL/EN Interface Level PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI TTL TTL, internal pull-up resistor TTL, internal pull-up resistor TTL, internal pull-up resistor TTL, internal pull-up resistor TTL, internal pull-up resistor
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Driver Capability Low Output AD0-31 PAR
*) *) *) *)
High 0.6V VDD - 0.4V 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 1mA 3mA 2mA 1mA 1mA 4mA 3mA 3mA 2mA 3mA 3mA 0.5mA 4mA 4mA 4mA 3mA 0.5mA 0.5mA
0.4V 6mA 6mA 6mA 6mA 6mA 6mA 6mA
C/BE0-3 IRDY# STOP# REQ#
FRAME#
*) *)
TRDY#
*) *)
DEVSEL#
*) *) *)
6mA 6mA 6mA 6mA 2mA 6mA 4mA 2mA 2mA 8mA 6mA 6mA 4mA 6mA 6mA 1mA 8mA 8mA 8mA 6mA 1mA
PERR# SERR# PME INTA#
*)
DAUX0-7 /AUX_WR /AUX_RD /ADR_WR TX2_HI /TX1_LO /TX_EN /TX2_LO TX1_HI ADJ_LEV C4IO F0IO STIO1-2 F1_A-B EE_SDA
*)
EE_SCL/EN 1mA PCI buffer is PCI Spec. 2.2 compliant.
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6
6.1
Timing characteristics
PCI bus timing
The timing characteristics of the HFC-S PCI As integrated PCI bus interface is compliant with version 2.1 of the PCI Local Bus specification.
6.2
GCI/IOM2 bus clock and data alignment for Mitel STTM bus
Figure 9: GCI/IOM2 bus clock and data alignment
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6.3
GCI/IOM2 timing
Timing diagram 1: GCI/IOM2 timing
*)
F0IO starts one C4IO clock earlier if bit 3 in MST_MODE register is set. If this bit is set F0IO is also awaited one C4IO clock cycle earlier.
6.3.1
Master mode
To configure the HFC-S PCI A as GCI/IOM2 bus master bit 0 of the MST_MODE register must be set. In this case C4IO and F0IO are outputs. SYMBOL tC4P tC4H tC4L tC2P tC2H tC2L CHARACTERISTICS Clock C4IO period (4.096 MHz) Clock C4IO High Width Clock C4IO Low Width Clock C2O Period Clock C2O High Width Clock C2O Low Width MIN. 180 ns *) 78 ns *) 78 ns *) 360 ns 180 ns 180 ns TYP. 244.14 ns*) 122 ns *) 122 ns *) 488.28 ns 244.14 ns 244.14 ns MAX. 308 ns*) 166 ns*) 166 ns *) 616 ns 308 ns 308 ns
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CHARACTERISTICS F0IO Width Short F0IO Long F0IO MIN. 230 ns 460 ns TYP. 244 ns 488 ns 10 ns MAX. 260 ns 520 ns 25 ns
SYMBOL tF0iW
tSToD tF0iCYCLE
STIO1/2 Delay fom C4IO Level 1 Output F0IO Cycle Time 1 half clock adjust 2 half clocks adjust
124.955 us 125.000 us 125.045 us 124.910 us 125.000 us 125.090 us
All specifications are for 2.048 Mb/s Streams and fCLK = 12.288 Mhz.
*)
Time depends on accuracy of OSC_IN frequency. Because of clock adjustment in the 31st time slot these are the worst case timings when C4IO is adjusted.
6.3.2
Slave mode
To configure the HFC-S PCI A as GCI/IOM2 bus slave bit 0 of the MST_MODE register must be cleared (reset default). In this case C4IO and F0IO are inputs. SYMBOL tC4P tC4H tC4L tC2P tC2H tC2L tF0iS tF0iH tF0iW tSTiS tSTiH CHARACTERISTICS Clock C4IO period (4.096 MHz) Clock C4IO High Width Clock C4IO Low Width Clock C2O Period Clock C2O High Width Clock C2O Low Width F0IO Setup Time to C4IO F0IO Hold Time after C4IO F0IO Width STIO2 Setup Time STIO2 Hold Time 25 ns 25 ns 20 ns 20 ns 40 ns 20 ns 20 ns 20 ns 20 ns 488.28 ns*) MIN. TYP. 244.14 ns*) MAX.
All specifications are for 2.048 Mb/s Streams and fCLK = 12.288 Mhz.
*)
If the S/T interface is synchronized from C4IO (NT mode) the frequency must be stable to 10 -4.
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6.4
EEPROM access
Timing diagram 2: EEPROM access
SYMBOL fSCL tSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU tDH
*)
CHARACTERISTICS Serial Clock Frequency Serial Clock Period Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Output Data Change after Clock Data In Setup Time Data In Hold Time
TYP. 32.2 KHz *) 1 / fSCL
3/4 tSCL 1/2 tSCL 1/2 tSCL 3/4 tSCL
10 ns 100 ns 100 ns
with 33 MHz PCI clock
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6.5 6.5.1
Auxiliary port access Write access
tC L K
P C IC L K
D A U X 0-7
tS ET U P
ADR OUT tA D W L O W tD tH O L D tO U T SE T U P tD
D ATA O U T
** )
/A D R _W R /A U X _W R
tA X W R LO W
Timing diagram 3: Auxiliary port write access
SYMBOL tCLK tSETUP tADWLOW tHOLD tOUTSETUP tAXWLOW tD
*) **)
CHARACTERISTICS PCI Clock Period (33 MHz) Address Setup Time before /ADR_WR /ADR_WR Low Time Address Hold Time after /ADR_WR Data Out Setup Time before /AUX_WR /AUX_WR Low Time Delay Time between PCICLK and /ADR_WR or /AUX_WR
TYP. 30 ns tCLK tCLK tCLK tCLK 3 x tCLK *) 10 ns
configurable (see also: CIRM register bit description) data out is valid until the next auxiliary port write access is initiated
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6.5.2
Read access
tCL K
P C IC L K
tT R I
D A U X 0 -7
tS ET U P
ADR OUT tA D W L O W tD tH O L D tA X R D L O W
D ATA IN t IN S E T U P t IN H O L D
/A D R _ W R /A U X _ R D
tD
Timing diagram 4: Auxiliary port read access
SYMBOL tCLK tSETUP tADWLOW tHOLD tINSETUP tAXRDLOW tINHOLD tD tTRI
*)
CHARACTERISTICS PCI Clock Period (33 MHz) Address Setup Time before /ADR_WR /ADR_WR Low Time Address Hold Time after /ADR_WR Minimum Data In Setup Time before /AUX_RD /AUX_RD Low Time Data In Hold Time after /AUX_RD Delay Time between PCICLK and /ADR_WR or /AUX_RD Time Data Floating after PCICLK
TYP. 30 ns tCLK tCLK tCLK 20 ns 3 x tCLK *) 0 ns 10 ns 20 ns
configurable (see also: CIRM register bit description)
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7
S/T interface circuitry
In order to comply to the physical requirements of ITU-T recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the HFC-S PCI A needs some additional circuitry, which are shown in the following figures.
7.1
External receiver circuitry
VDD R1 C3 R2 R7 R3
LEV_R1
R1 R5 D1 R1 R5 LEV_R2 GND D3 D4 D2 VDD R6 12 14 RX R6 10 11 S/T module 5 RX + 16 S/T side
R2 R2 C3
R4 ADJ_LEV C1 GND
Figure 10: External receiver circuitry
Part list VDD R1, R1' R2, R2' R3 R4 R5, R5' R6, R6' R7 5V 33 k: 100 k: 1 M: 680k: 3.9 k: 4.7 k: 4.7 k: 1.8 M: 1.2M: 3.3V C1 C3, C3' D1, D2 D3, D4 S/T module 47 nF 22pF 1N4148 or LL4148 1N4148 or LL4148 see Table 5 on page 59.
C3, C3' are for reduction of high frequency input noise and should be located as close as possible to the HFC-S PCI A.
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7.2
External transmitter circuitry
VDD R6 C3
R4
R5 T3 TX_EN
TX1_HI R1
TX2_HI
R1
T1
R7
T1
R2 T2 TX2_LO R3 T2 R3
R2
R8
TX1_LO GND
9 D2 GND D4 D5 7 ZD1 D3 8
S/T module
1 3 18
TX +
S/T side
TX -
Figure 11: External transmitter circuitry Part List VDD R1 R2 R3, R3' *) R4 R5 R6 R7 R8
*)
5V 2.2 k: 1% 3.0 k: 1% 18 : 100 : 5.6 k: 3.3 k: 3.3 k: 2.2 k:
3.3V 560 : 1% 3.9 k: 1% 18 :
0 :
C3 D2, D3 D4, D5 ZD1 T1, T1' T2, T2' T3 S/T module
3.3 k: 2.2 k: 1.8 k: 2.2 k:
470 pF 1N4148 or LL4148 1N4148 or LL4148 Z-Diode 2.7 V (e. g. BZV 55C 2V7) BC550C, BC850C or similar BC550C, BC850C or similar BC560C, BC860C or similar see Table 5 on page 59.
value is depending on the used S/T module
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S/T module part number APC 56624-1 APC 40495S (SMD)
manufacturer Advanced Power Components United Kingdom Phone: +44 1634-290588 +44 1634-290591 S-Hybrid modules with receiver and transmitter Fax: http://www.apcisdn.com circuitry included: APC 5568-3V APC 5568-5V APC 5568DS-3V APC 5568DS-5V FE 8131-55Z FEE GmbH Singapore Phone: +65 741-5277 Fax: +65 741-3013 Bangkok Phone: +662 718-0726-30 Fax: +662 718-0712 Germany Phone: +49 6106-82980 Fax: +49 6106-829898 transformers: Pulse Engineering, Inc. United States PE-64995 Phone: +1-619-674-8100 PE-64999 Fax: +1-619-674-8262 PE-65795 (SMD) http://www.pulseeng.com PE-65799 (SMD) PE-68995 PE-68999 T5006 (SMD) T5007 (SMD) S0-modules: T5012 T5034 T5038 transformers: Sun Myung Korea SM TC-9001 Phone: +82-348-943-8525 SM ST-9002 Fax: +82-348-943-8527 SM ST-16311F http://www.sunmyung.com S0-modules: SM TC-16311 SM TC-16311A transformers UMEC GmbH Germany UT21023 Phone: +49 7131-7617-0 S0-modules: Fax: +49 7131-7617-20 UT 20795 (SMD) Taiwan UT 21624 Phone: +886-4-359-009-6 UT 28624 A Fax: +886-4-359-012-9 United States Phone: +1-310-326-707-2 Fax: +1-310-326-705-8 http://www.umec.de
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manufacturer VAC GmbH Germany Phone: +49 6181/ 38-0 Fax: +49 6181/ 38-2645 http://www.vacuumschmelze.de
S/T module part number T 6040... transformers: 3-L4021-X066 3-L4025-X095 3-L5024-X028 3-L4096-X005 3-L5032-X040 S0-modules: 7-L5026-X010 (SMD) 7-L5051-X014 7-M5051-X032 7-L5052-X102 (SMD) 7-M5052-X110 7-M5052-X114 transformers: ST5069 S0-modules: PT5135 ST5201 ST5202
543 76 009 00 503 740 010 0 (SMD)
Valor Electronics, Inc. Asia Phone: +852 2333-0127 Fax: +852 2363-6206 North America Phone: +1 800 31VALOR Fax: +1 619 537-2525 Europe Phone: +44 1727-824-875 Fax: +44 1727-824-898 http://www.valorinc.com Vogt electronic AG Germany Phone: +49 8591/ 17-0 Fax: +49 8591/ 17-240 http://www.vogt-electronic.com
Table 5: S/T module part numbers and manufacturer
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7.3
Oscillator circuitry
Part list:
OSC_IN C1
Q1 R1 R2 C1, C2
12.288 MHz quartz 0..50 : 1 M: 47 pF
Q1
R2
OSC_OUT C2 R1
Figure 12: Oscillator Circuitry
The values of C1, C2 and R1 depend on the used quartz. For a load-free check of the oscillator frequency the C4O clock of the GCI/IOM2 bus should be measured (HFC-S PCI A as master, S/T interface deactivated, 4.096 MHz frequency intented on the C4IO).
7.4
EEPROM circuitry
Figure 13: EEPROM circuitry
& _V (#
:Q^eQbi " !
863C @39 1
Cologne Chip
7.5
PME pin circuitry
The PME pin (pin 53) on the HFC-S PCI A is high active. To connect it to the low active PME# pin on the PCI bus, the following circuitry is neccessary.
Figure 14: PME pin circuitry
:Q^eQbi " !
&! _V (#
863C @39 1
Cologne Chip
8
8.1
State matrices for NT and TE
S/T interface activation/deactivation layer 1 for finite state matrix for NT
Pending activation G2 Pending deactivation G4
State name State number INFO sent
Reset G0
Deactive G1
Active G3
Event
INFO 0
INFO 0
INFO 2
INFO 4
INFO 0
State machine release (Note 3) Activate request Deactivate request Expiry T2 (Note 2) Receiving INFO 0 Receiving INFO 1 Receiving INFO 3
G2 G2 (Note 1)
| G2 (Note 1) |
| | Start timer T2 G4
| | Start timer T2 G4
| G2 (Note 1) | G1 G1
] ] ] ] ]
] ]
G2 (Note 1) /
] ] ]
G3 (Note 1)
]
G2 /
]
] ]
Table 6: Activation/deactivation layer 1 for finite state matrix for NT
/ |
No state change Impossible by the definition of peer-to-peer physical layer procedures or system internal reasons Impossible by the definition of the physical layer service
Note 1: Timer 1 (T1) is not implemented in the HFC-S PCI A and must be implemented in software. Note 2: Timer 2 (T2) prevents unintentional reactivation. Its value is 32ms (256 x 125s). This implies that a TE has to recognize INFO 0 and to react on it within this time. Note 3: After reset the state machine is fixed to G0.
* hint!
Fix the NT state machine to state G3 when activated (by writing 13h into STATES register). This prevents deactivation of NT mode S/T interface due to sporadically errors on NT input data.
&" _V (#
:Q^eQbi " !
863C @39 1
Cologne Chip
8.2
Activation/deactivation layer 1 for finite state matrix for TE
State name State number Info sent
Reset F0 INFO 0 F2
Sensing F2 INFO 0 / | | /
Deactivated F3 INFO 0 / F5 F4
Awaiting signal F4 INFO 1 / | |
Identifying input F5 INFO 0 / | |
Synchronized F6 INFO 3 /
Activated F7 INFO 3 / | |
Lost framing F8 INFO 0 /
Event
State machine release (Note 1) Activate Receiving any signal Request Receiving INFO 0 Expiry T3 (Note 5) Receiving INFO 0 Receiving any signal (Note 2) Receiving INFO 2 (Note 3) Receiving INFO 4 (Note 3) Lost framing (Note 4)
] ] ] ] ] ] ] ]
]
F3
] ] ]
] ]
F3 F3 /
]
F3
F5 F6 F7 /
] ]
F3
]
F3 / F6
] ] ]
F3
F6 F7 /
F6 F7 /
F6 F7 /
]
F7 F8
]
F6 F7
]
F8
]
Table 7: Activation/deactivation layer 1 for finite state matrix for TE
| /
No change, no action Impossible by the definition of the layer 1 service Impossible situation
Notes Note 1: After reset the state machine is fixed to F0. Note 2: This event reflects the case where a signal is received and the TE has not (yet) determined wether it is INFO 2 or INFO 4. Note 3: Bit- and frame-synchronisation achieved. Note 4: Loss of Bit- or frame-synchronisation. Note 5: Timer 3 (T3) is not implemented in the HFC-S PCI A and must be implemented in software.
:Q^eQbi " !
&# _V (#
863C @39 1
Cologne Chip
9
9.1
Binary organisation of the frames
S/T frame structure
The frame structures are different for each direction of transmission. Both structures are illustrated in Figure 15.
Figure 15: Frame structure at reference point S and T
F L D E FA M
Framing bit D.C. balancing bit D-channel bit D-echo-channel bit Auxiliary framing bit Multiframing bit
N B1 B2 A S
Bit set to a binary value N = F A (NT to TE) Bit within B-channel 1 Bit within B-channel 2 Bit used for activation S-channel bit
* note! Lines demarcate those parts of the frame that are independently d.c.-balanced. The FA bit in the direction TE to NT is used as Q bit in every fifth frame if S/Q bit transmission is enabled (see SCTRL register). The nominal 2-bit offset is as seen from the TE. The offset can be adjusted with the CLKDEL register in TE mode. The corresponding offset at the NT may be greater due to delay in the interface cable and varies by configuration. HDLC-B-channel data start with the LSB, PCM-B-channel data start with the MSB.
&$ _V (#
:Q^eQbi " !
863C @39 1
Cologne Chip
9.2
GCI frame structure
The binary organistation of a single GCI channel frame is described below. C4IO clock frequency is 4.096MHz.
C 4 IO F 0 IO b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b1 b2 b4 b3 b2 b1 D IN
D O UT B1 B2 M D C /I MM RX B1 B1
T im e S lo t 0
T im e S lo t 1 G C I F ra m e
T im e S lo t 2
T im e S lo t 3
T im e S lo t 4
T im e S lo t 3 2
Figure 16: Single channel GCI format
B1 B2 M D C/I MR MX
B-channel 1 data B-channel 2 data Monitor channel data D-channel data Command/indication bits for controlling activation/deactivation and for additional control functions Handshake bit for monitor channel Handshake bit for monitor channel
:Q^eQbi " !
&% _V (#
863C @39 1
Cologne Chip
10 Clock synchronisation
10.1 Clock synchronisation in NT-mode
Figure 17: Clock synchronisation in NT-mode
&& _V (#
:Q^eQbi " !
863C @39 1
Cologne Chip
10.2
Clock synchronisation in TE-mode
Figure 18: Clock synchronisation in TE-mode
The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus twice for one half clock cycle. This can be reduced to one adjustment of a half clock cycle. This is useful if another HFC-S, HFC-S+, HFCSP or HFC-S PCI A is connected as slave in NT mode to the GCI/IOM2 bus.
:Q^eQbi " !
&' _V (#
863C @39 1
Cologne Chip
11 HFC-S PCI A package dimensions
Figure 19: HFC-S PCI A package dimensions
&( _V (#
:Q^eQbi " !
Cologne Chip
12 ISDN PCI card sample circuitries with HFC-S PCI A
Please see chapter 3.3 for details on power management support of HFC-S PCI A and special considerations for support of power management state D3cold.
3. 3Vaux
P CI_S T 1D P M E# IN T D# IN T C# IN T B# IN TA # P RS N T 2# P RS N T 1# GND GND GND U2 GND P M E_S PM E INTA # RS T # CLK GNT# RE Q # SE R R # PE R R # O S C _O U T O S C_IN JP2 T R S T# TMS T CK T DI T DO P CI_S T 1C S D O NE SBO# P CIS P E C R S T# C LK G N T# REQ# S E R R# P E R R# LO C K# ID S EL D EV S E L# S TO P # IR D Y# T R D Y# FR A M E# M 66EN
P28/29
P48/49
P60/61
P76/77
P89/90
74HC74
JP1
B11 B9 A1 A3 B2 A4 B4 A40 A41 A15 B16 A17 B18 B42 B40 B39 A26 B37 A38 B35 A36 A34 B49 53 50 51
R3 R ST #
C LK GN T# REQ # S ERR# P ERR# ID S E L D E V S E L# S TO P # IR D Y # TRDY# FRAM E #
24C04
JP2
4
24C04
IN TA
P7/8
+
NC
74HC374
74HC374
P CI_S T 1B PC IIN T C 29 C30
A19 B8 A7 B7 A6
PM E _S +12V -12V +5V +3.3V 3.3Vaux Vi/o NC NC
P CIP O W
Vi/ o
Vi/o
+5V
V DD _HF C
Vi/o
+5V
+ C1
10
C2
C3
C4
C5
C6
C7
C8
C9
C 10
C 11
C 12
C16
GND
V DD _H FC
GND
R1
ISDN PCI card for 5V power supply (no D3cold support)
Q1
91 92 93 94 95 25 24 6 22 23 20 21 19
IDS E L DE V S EL# STO P # IRD Y # TR D Y # FR A M E#
G ND
+5V V D D _H F C Q2 R5 R6 U3 C 14 C15 Q3 G ND
optional
20
/A D R _W R
VC C
1 11
PA R C /B E 3# C /B E 2# C /B E 1# C /B E 0# A D 31 A D 30 A D 29 A D 28 A D 27 A D 26 A D 25 A D 24 A D 23 A D 22 A D 21 A D 20 A D 19 A D 18 A D 17 A D 16 A D 15 A D 14 A D 13 A D 12 A D 11 A D 10 A D 09 A D 08 A D 07 A D 06 A D 05 A D 04 A D 03 A D 02 A D 01 A D0 P CI_S T 1A P CIA D R
A43
PA R C /B E 3# C /B E 2# C /B E 1# C /B E 0# A D31 A D30 A D29 A D28 A D27 A D26 A D25 A D24 A D23 A D22 A D21 A D20 A D19 A D18 A D17 A D16 A D15 A D14 A D13 A D12 A D 11 A D10 A D09 A D08 A D07 A D06 A D05 A D04 A D03 A D02 A D01 A D00
G ND
26 5 18 27 38 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47
EN C1
PAR GND C/B E 3# C/B E 2# C/B E 1# C/B E 0# AD 31 AD 30 AD 29 AD 28 AD 27 AD 26 AD 25 AD 24 AD 23 AD 22 AD 21 AD 20 AD 19 AD 18 AD 17 AD 16 AD 15 AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 GND V DD _H FC A D J_LE V LE V _R 1 R1 R2 LE V _R 2 T X 1_H I /T X 2_LO /T X_E N /T X 1_LO T X 2_H I S TIO 2 S TIO 1 C4IO F0IO F1_A F1_B E E _S C L/EN E E __SD A /AD R _W R /A U X _R D /A U X _W R D AU X 7 D AU X 6 D AU X 5 D AU X 4 D AU X 3 D AU X 2 D AU X 1 D AU X 0
D AUX0 D AUX1 D AUX2 D AUX3 D AUX7 D AUX6 D AUX5 D AUX4
B26 B33 B44 A52 B20 A20 B21 A22 B23 A23 B24 A25 B27 A28 B29 A29 B30 A31 B32 A32 A44 B45 A46 B47 A47 B48 A49 B52 B53 A54 B55 A55 B56 A57 B58 A58
V DD _H FC
G ND
78 80 79 82 81 84 85 86 87 88 57 56 54 55 58 59 62 63 65 66 67 68 69 70 71 72 73 74 75 89
VD D _HF C GND
/A D R _ W R /A U X _R D /A U X _W R DA UX7 DA UX6 DA UX5 DA UX4 DA UX3 DA UX2 DA UX1 DA UX0 S T IO 2 S T IO 1 C 4 IO F 0 IO F 1 _A F 1 _B
A D J_LE V LE V_R 1 R1 R2 LE V_R 2 T X 1_H I /T X 2_LO /T X _E N /T X 1_LO T X 2_H I
JP 1 P CM
optional
3 4 7 8 13 14 17 18 1 3 5 7
F1 _A F1 _B
1D
2 5 6 9 12 15 16 19 2 4 6 8
C 4IO F 0IO S T IO 1 S T IO 2
A0 A1 A2 A3 A7 A6 A5 A4
74H C 374 +5V Vi/o JP 2
S T IO [1 :2],C 4 IO ,F 0IO ,F 1_ A ,F 1_ B
VD D _HF C
optional
VD D _HF C
DAU X0 DAU X2 DAU X4 DAU X6 A0 A2 A4 A6 /A U X _W R /A D R _ W R
R 11
R 12
U4
863C @39 1
5 6 8
J P 10 J P 11
SDA A2 SCL A1 VCC A0 TE S T
3 2 1 7
1 3 5 7 9 11 13 15 17 19 21 23 25
IO G ND
2 4 6 8 10 12 14 16 18 20 22 24 26
DAUX 1 DAUX 3 DAUX 5 DAUX 7 A1 A3 A5 A7 /A U X _ R D
24C04
G ND GND
D A U X [0 :7 ],/A U X _W R ,/A U X _R D ,/A D R _ W R
A [0 :7 ]
Title
8
IS D N P C I C a rd fo r 5 V w ith o ut D 3 co ld S u pp o rt
(c) 20 0 0 b y C o log ne C hip A G
all VDD_HFC Pins 7/28/48/60/76/89
H F C -S P C I A
GND
all GND Pins 8/17/29/39 49/52/61/64/77/83/90/96
S ize A4 D ate:
D ocum ent Num ber
R ev 2.0
Thursday, O ctober 19, 2000
Sheet
1
of
2
:Q^eQbi " !
GND
12.1
&) _V (#
VD D_H FC R13 AD J_LEV C18 R A1 VDD _H FC R B1 D3 R 15 R B2 LEV_R 2 R A2 D4 RC 2 RD 2 C 22 R2 C20 GND TR 1A GND LEV_R 1 R1 RC 1 RD 1 + C 19 R 14
GND
+5V C 23 C24 R 17 GND R EC C21
R16
ISD N _ST1 GND
R 18 /TX_EN Q6
R EC 1 R EC 2
TRAN S1 TRAN S2
R E1 TX1_HI Q7 Q8
R E2
TX2_H I TR 1B Q 10 Q9
/TX2_LO RG 1
/TX1_LO RG 2 R F1 R 19 R F2 C 25
GND
GND
TR AN S
C26
D6
GND R 22 D7
863C @39 1
GND GND
D8 Title
IS D N P C I C a rd fo r 5 V w ith o u t D 3 c o ld S u p p o rt
(c) 2 0 0 0 b y C o lo g n e C h ip A G
Size A4 D ate:
Docum ent N um ber Thursday, O ctober 19, 2000 Sheet 2
R ev 2.0
of
2
' _V (#
:Q^eQbi " !
Cologne Chip
863C @39 1
Cologne Chip
ISDN PCI Card for 5 V without D3cold support
Capacitors C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C14 C15 C16 C18 C19 C20 C21 C22 C23 C24 C25 C26 C29 C30 C31 C32 33 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 47p 47p 33 22p 33 22p 0 0 47n 470p 0 0 33n 33n 0R 0
Resistors R01 R03 R05 R06 R11 R12 R13 R14 R15 R16 R17 R18 R19 R22 RA1 RA2 RB1 RB2 RC1 RC2 RD1 RD2 RE1 RE2 RF1 RF2 RG1 RG2 10k 1M 330 10k 10k 10k 3k9 680k 1M2 3k3 100 5k6 3k3 2k2 100k 100k 33k 33k 4k7 4k7 4k7 4k7 2k2 2k2 15 15 3k 3k
IC's U2 U3 U4 HFC-S PCI A Cologne Chip AG optional 74HC374 24C04
nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby JP1 optiona l nearby JP2 optional nearby U1 nearby U4 nearby U3 optional depends on crystal depends on crystal nearby U2 nearby U2
Connectors JP1 JP2 JP10 JP11
PCM IO
optional optional
EEPROM options optional EEPROM options optional
Transistors / Crystals Q1 Q2 Q3 Q6 Q7 Q8 Q9 Q10
1% 1%
optional optional
BC850C 12.288M BC860C BC860C BC850C BC850C BC850C BC850C
CMPT5088 or similar CMPT5087 or similar CMPT5087 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar
optional optional nearby JP2 optional
nearby JP2 optional
Resistor or connect to GND
Diodes D3 D4 D6 D7 D8 BAV99 BAV99 BAV99 2V7 BAV99
can also be 2*4148 can also be 2*4148 can also be 2*4148 can also be 2*4148
1% 1%
optional
:Q^eQbi " !
'! _V (#
3. 3Vaux
P CI_S T1D Vi/ o Vi/o +5V +5V PME# INTD # INTC # IN TB # IN TA# P RSN T2# P RSN T1# GND G ND G ND U2 PM E _S R1 R ST_S RS T_P GND JP2 G ND TR ST # TM S TC K TDI TD O PCI_ST 1C S DO NE PCIS PE C S BO # R ST # CLK G NT # REQ # S ER R# P ER R# LO CK # IDSE L DE VS EL# STO P# IRDY # T RDY # FR AM E # M 66EN
C LK GNT# REQ# SERR# PERR#
VDD _HF C
PC I_S T1B P CIINT 74HC74 C 29 74HC374 24C04
4 10
P28/29
P48/49
P60/61
P76/77
P89/90
74HC74
NC
JP1
B11 B9 A1 A3 B2 A4 B4 A40 A41 A15 B16 A17 B18 B42 B40 B39 A26 B37 A38 B35 A36 A34 B49 91 92 93 94 95 25 24
INTA# RS T# CLK G NT # RE Q # SE RR# PE RR# O SC _O U T O SC_IN R3 PM E
JP2
74HC374
A19 B8 A7 B7 A6
PM E _S +12V -12V +5V +3.3V 3.3Vaux Vi/o NC NC
7
P CIPO W
VDD _H FC
C30
+ C1
C2 P7/8
C3
C4
C5
C6
C7
C8
C9
C 10
C 11 24C04
C12
U1A
IN TA
4 3 2 1
S VCC C1 5 1D 6 R 74HC74
14
G ND VD D_HFC Q1 R2
V DD _HF C
RS T_P
53 50 51
JP 3
G ND
U1B +5V
/A U X _ W R DA UX 0
ID S E L D EVSE L# S TO P # IR D Y # TRD Y# FRA ME#
6 22 23 20 21 19
IDSE L DE VS EL# STO P # IRDY # TR DY # FR AM E # C 14
Q2
R5 R6
V DD_HF C + U3 C 15 G ND Q3
optional
10 11 12 13
C13
S VCC C1 9 1D 8 R 7 4H C 74
20 1 11
/A D R _ W R
14
D1
R4
VCC EN C1
G ND GND VD D_HF C
DAUX0 DAUX1 DAUX2 DAUX3 DAUX7 DAUX6 DAUX5 DAUX4
RST _S GND
PAR C /B E3# C /B E2# C /B E1# C /B E0# A D31 A D30 A D29 A D28 A D27 A D26 A D25 A D24 A D23 A D22 A D21 A D20 A D19 A D18 A D17 A D16 A D15 A D14 A D13 A D12 A D11 A D10 A D09 A D08 A D07 A D06 A D05 A D04 A D03 A D02 A D01 AD 0 PC I_S T1A PCIA DR VDD _H FC
A43
PA R
GND
26
PAR C/BE 3# C/BE 2# C/BE 1# C/BE 0# AD 31 AD 30 AD 29 AD 28 AD 27 AD 26 AD 25 AD 24 AD 23 AD 22 AD 21 AD 20 AD 19 AD 18 AD 17 AD 16 AD 15 AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0
B26 B33 B44 A52
C /B E 3 # C /B E 2 # C /B E 1 # C /B E 0 # AD 31 AD 30 AD 29 AD 28 AD 27 AD 26 AD 25 AD 24 AD 23 AD 22 AD 21 AD 20 AD 19 AD 18 AD 17 AD 16 AD 15 AD 14 AD 13 AD 12 A D 11 AD 10 AD 09 AD 08 AD 07 AD 06 AD 05 AD 04 AD 03 AD 02 AD 01 AD 00
5 18 27 38 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 89
863C @39 1
D A U X [0 :7 ],/A U X _ W R ,/A U X _ R D ,/A D R _ W R
Title VD D_HFC all VDD_HFC Pins 7/28/48/60/76/89 GND
8
IS D N P C I C a rd for 5 V w ith D 3 co ld S upp ort
(c) 2 00 0 by C olog ne C hip A G
H F C -S P C I A
G ND
all GND Pins 8/17/29/39 49/52/61/64/77/83/90/96
Size A4 Date:
Docum ent Num ber Thursday, O ctober 19, 2000
Rev 2.0
S heet
1
of
2
'" _V (#
B20 A20 B21 A22 B23 A23 B24 A25 B27 A28 B29 A29 B30 A31 B32 A32 A44 B45 A46 B47 A47 B48 A49 B52 B53 A54 B55 A55 B56 A57 B58 A58
G ND
AD J_LE V LEV _R 1 R1 R2 LEV _R 2 T X1_HI /T X2_LO /TX _E N /T X1_LO T X2_HI STIO 2 STIO 1 C4IO F0IO F 1_A F 1_B E E_S CL/EN EE __SD A /AD R_W R /AU X_R D /AU X_W R DA UX 7 DA UX 6 DA UX 5 DA UX 4 DA UX 3 DA UX 2 DA UX 1 DA UX 0
78 80 79 82 81 84 85 86 87 88 57 56 54 55 58 59 62 63 65 66 67 68 69 70 71 72 73 74 75
/A D R _ W R /A U X _ R D /A U X _ W R D AUX 7 D AUX 6 D AUX 5 D AUX 4 D AUX 3 D AUX 2 D AUX 1 D AUX 0 S T IO 2 S T IO 1 C 4 IO F0 IO F1 _ A F1 _ B
ADJ_LEV LEV _R 1 R1 R2 LEV _R 2 TX1_H I /T X2_LO /T X_EN /T X1_LO TX2_H I
JP 1 P CM
optional
3 4 7 8 13 14 17 18 1 3 5 7
F1_A F1_B
1D
2 5 6 9 12 15 16 19 2 4 6 8
C 4 IO F0 IO S T IO 1 S T IO 2
A0 A1 A2 A3 A7 A6 A5 A4
R_Sens optional
D9
R 30 R _S ens
Power Management
74HC374 +5V Vi/o JP2
S T IO [1 :2 ],C 4 IO ,F 0 IO ,F1 _ A ,F1 _ B
Vi/o VDD _H FC
optional
3.3Vaux
VD D_HFC
DAUX0 DAUX2 DAUX4 DAUX6 A0 A2 A4 A6 /A U X _ W R /A D R _ W R
R11
R 12
U4
5 6 8
J P10 J P11
SD A A 2 SC L A 1 VC C A 0 T ES T
3 2 1 7
1 3 5 7 9 11 13 15 17 19 21 23 25
IO GND
2 4 6 8 10 12 14 16 18 20 22 24 26
Q4
DA UX 1 DA UX 3 DA UX 5 DA UX 7 A1 A3 A5 A7 /A U X _ R D
Q5
R9
D2
R 10
JP 4
JP5
G ND
G ND
+ GND
C16
C 17
24C04
G ND GND
A [0 :7 ]
VDD _HF C
G ND
G ND
The R_Sens part is optional. It is used to decrease the receiver sensitivity for wake-up signals to avoid a wake-up caused by disturbance on the ISDN line. 12.2 Please see chapter 3.3 for details on power management support of HFC-S PCI A and special considerations for support of power management state D3cold. ISDN PCI card for 5V power supply with D3cold support
:Q^eQbi " !
Cologne Chip
Cologne Chip
V D D _H FC R 13 A D J_ LE V C 18 R A1 VD D_HFC RB1 D3 R 15 RB2 LE V _ R 2 R A2 D4 R _S en s C 20 RC2 RD2 C22 + 5V C 23 C 24 R17 GND R18 /TX _E N Q6 G ND REC1 REC2 REC C 21 R2 G ND TR 1A G ND LE V _ R 1 R1 RC1 RD1 + C 19 R14
GND
R 16
IS D N _S T1
TR A N S 1 TR A N S 2 R E2 Q7 Q8
RE1 TX 1 _ H I
T X 2_ H I TR 1B Q10
/T X 2 _L O RG 1
Q9
/TX 1 _LO RG 2 R F1 R 19 RF2 C 25
G ND
G ND
TR A N S
C 26
D6
GND R22 D7
863C @39 1
G ND G ND
D8 Title
IS D N P C I C a rd fo r 5 V w ith D 3 co ld S u p p o rt
(c ) 2 0 0 0 b y C o lo g n e C h ip A G
S ize A4 D ate:
D oc um en t N um b er Thu rsd ay, O cto be r 19 , 2 00 0 S he et 2 of
Rev 2 .0
2
:Q^eQbi " !
'# _V (#
863C @39 1
Cologne Chip
ISDN PCI Card for 5 V with D3cold support
Capacitors C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C29 C30 C31 C32 33 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 1 47p 47p 33 33n 22p 33 22p 0 0 47n 470p 0 0 33n 33n 0R 0
Resistors R01 R02 R03 R04 R05 R06 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R22 R30 RA1 RA2 RB1 RB2 RC1 RC2 RD1 RD2 RE1 RE2 RF1 RF2 RG1 RG2 10k 1M 1M 10k 330 10k 10k 10k 10k 10k 3k9 680k 1M2 3k3 100 5k6 3k3 2k2 680k * 100k 100k 33k 33k 4k7 4k7 4k7 4k7 2k2 2k2 15 15 3k 3k
IC's U1 U2 U3 U4 74HC74 HFC-S PCI A Cologne Chip AG optional 74HC374 24C04
nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby JP1 optiona l nearby JP2 optional nearby U1 nearby U4 nearby U3 optional depends on crystal depends on crystal
Connectors JP1 JP2 JP3 JP4 JP5 JP10 JP11
PCM IO Reset options Power options Power options EEPROM options optional EEPROM options optional
optional optional
nearby U2 nearby U2
optional optional
Transistors / Crystals Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 BC850C 12.288M BC860C BC860C BC860C BC860C BC850C BC850C BC850C BC850C
CMPT5088 or similar CMPT5087 or similar CMPT5087 or similar CMPT5087 or similar CMPT5087 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar
optional optional nearby JP2 optional
nearby JP2 optional
Resistor or connect to GND
1% 1%
optional
1% 1%
Diodes D1 D2 D3 D4 D6 D7 D8 D9 LL4148 LL4148 BAV99 BAV99 BAV99 2V7 BAV99 LL4148 *
or similar or similar can also be 2*4148 can also be 2*4148 can also be 2*4148 can also be 2*4148 or similar
* optional, not on PCB Layout V 2.0
'$ _V (#
:Q^eQbi " !
Cologne Chip
Please see chapter 3.3 for details on power management support of HFC-S PCI A and special considerations for support of power management state D3cold.
3.3Vaux
P C I_ S T 1D PME# IN TD # IN TC # IN TB # IN TA # P R S N T2# P R S N T1# G ND GND GND U2 P M E _S PME IN TA # R S T# C LK G N T# REQ# SER R# PER R# O S C _O U T O S C _ IN R3 R1 G ND JP2 GND TR S T # TM S TC K TD I TD O P C I_ S T1 C S D O N E P C IS P E C SBO # R ST# C LK G NT# R EQ# SERR# PERR# LO C K # ID S E L D E V S E L# S TO P # IR D Y # TR D Y # FR A M E # M 6 6E N
P28/29
P48/49
P60/61
P76/77
P89/90
74HC74
JP1
B 11 B9 A1 A3 B2 A4 B4 A 40 A 41 A 15 B 16 A 17 B 18 B 42 B 40 B 39 A 26 B 37 A 38 B 35 A 36 A 34 B 49 53 50 51
GND
R S T# C LK GNT# REQ# S E R R# P E R R# ID S E L D E V S E L# S TO P # IR DY # T RD Y # F RA M E #
24C04
JP2
4
24C04
INTA
P7/8
+
NC
74HC374
74HC374
P C I_S T1 B P C IIN T C 29
10
A 19 B8 A7 B7 A6
P M E _S + 12V -12V +5V + 3.3V 3.3Va ux V i/o C 30 NC NC
P C IP O W
V i/ o
V i/o
+ 5V
V D D _H F C
V i/o
+5 V
+ C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C 11
C 12
C 16
V D D _H F C JP 12 M 66E N Q1 C 31 GND +5V V D D _H F C
GND
ISDN PCI card for 3.3V power supply (no D3cold support)
91 92 93 94 95 25 24 6 22 23 20 21 19
ID S E L D E V S E L# S TO P # IR D Y # TR D Y # FR A M E # C 14 M 66E N Q2 R5
R6 U3 C15 G ND Q3
optional
20
/A D R_W R
VCC
1 11
GND GND V D D _H FC
D A UX 0 D A UX 1 D A UX 2 D A UX 3 D A UX 7 D A UX 6 D A UX 5 D A UX 4
PA R C /B E 3# C /B E 2# C /B E 1# C /B E 0# A D 31 A D 30 A D 29 A D 28 A D 27 A D 26 A D 25 A D 24 A D 23 A D 22 A D 21 A D 20 A D 19 A D 18 A D 17 A D 16 A D 15 A D 14 A D 13 A D 12 A D 11 A D 10 A D 09 A D 08 A D 07 A D 06 A D 05 A D 04 A D 03 A D 02 A D 01 AD0 P C I_S T1 A P C IA D R V D D _H F C
A 43
PA R
26
PA R C /B E 3 # C /B E 2 # C /B E 1 # C /B E 0 # A D 31 A D 30 A D 29 A D 28 A D 27 A D 26 A D 25 A D 24 A D 23 A D 22 A D 21 A D 20 A D 19 A D 18 A D 17 A D 16 A D 15 A D 14 A D 13 A D 12 A D 11 A D 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0
EN C1
3 4 7 8 13 14 17 18
B 26 B 33 B 44 A 52
C /B E 3# C /B E 2# C /B E 1# C /B E 0# A D 31 A D 30 A D 29 A D 28 A D 27 A D 26 A D 25 A D 24 A D 23 A D 22 A D 21 A D 20 A D 19 A D 18 A D 17 A D 16 A D 15 A D 14 A D 13 A D 12 A D 11 A D 10 A D 09 A D 08 A D 07 A D 06 A D 05 A D 04 A D 03 A D 02 A D 01 A D 00
5 18 27 38 97 98 99 10 0 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 89
1D
78 80 79 82 81
A D J_ LE V L E V _R 1 R1 R2 L E V _R 2 TX 1 _H I /T X 2 _LO /TX _ E N /T X 1 _LO TX 2 _H I S TIO 2 S TIO 1 C 4 IO F0 IO F1 _A F1 _B E E _S C L /E N E E __S D A /A D R _ W R /A U X _ R D /A U X _ W R DAU X7 DAU X6 DAU X5 DAU X4 DAU X3 DAU X2 DAU X1 DAU X0
863C @39 1
GND GND
D A UX [0:7],/A UX _W R,/A U X _R D,/A D R_W R
A [0:7]
Title V D D _H FC all VDD_HFC Pins 7/28/48/60/76/89 G ND
8
IS D N P C I C a rd fo r 3 .3 V w ith o u t D 3 co ld S u p p o rt
(c) 2 0 0 0 b y C o lo g n e C h ip A G
H FC -S P C I A
GND
all GND Pins 8/17/29/39 49/52/61/64/77/83/90/96
S ize A4 D ate:
D oc um e nt N um ber
Rev 2.0
T hursday, O cto ber 19, 200 0
S h eet
1
of
2
:Q^eQbi " !
B 20 A 20 B 21 A 22 B 23 A 23 B 24 A 25 B 27 A 28 B 29 A 29 B 30 A 31 B 32 A 32 A 44 B 45 A 46 B 47 A 47 B 48 A 49 B 52 B 53 A 54 B 55 A 55 B 56 A 57 B 58 A 58
G ND
A D J_ LE V LE V _ R 1 R1 R2 LE V _ R 2
JP 1 PC M
optional
2 5 6 9 12 15 16 19 84 85 86 87 88 57 56 54 55 58 59 62 63 65 66 67 68 69 70 71 72 73 74 75
/AD R _W R /AU X _RD /AU X _W R DA U X 7 DA U X 6 DA U X 5 DA U X 4 DA U X 3 DA U X 2 DA U X 1 DA U X 0 S TIO 2 S TIO 1 C4IO F0IO F1_A F1_B
A0 A1 A2 A3 A7 A6 A5 A4
TX 1_ H I /TX 2_ LO /TX _E N /TX 1_ LO TX 2_ H I
F 1_A F 1_B
1 3 5 7
2 4 6 8
C 4IO F 0IO S T IO 1 S T IO 2
74 H C 3 74 +5V Vi/o JP 2
S TIO [1:2],C4IO ,F0IO ,F 1_A ,F1_B
V D D _ H FC
optional
V D D _H F C
D AU X 0 D AU X 2 D AU X 4 D AU X 6 A0 A2 A4 A6 /A UX _W R /A DR _W R
R 11
R12
U4
5 6 8
J P 10 J P 11
SD A A2 SC L A1 VC C A0 TE S T
3 2 1 7
1 3 5 7 9 11 13 15 17 19 21 23 25
IO GND
2 4 6 8 10 12 14 16 18 20 22 24 26
D A UX 1 D A UX 3 D A UX 5 D A UX 7 A1 A3 A5 A7 /A U X _R D
GND
24C 04
12.3
'% _V (#
V D D _H FC R 13 AD J_LE V C 18 R A1 VD D _H FC R B1 D3 R15 R B2 LEV _R 2 R A2 D4 RC2 RD2 R2 C 20 G ND TR 1A GND LEV _R 1 R1 RC1 RD1 + C 19 R 14
C22
G ND
+5V C 23 C 24 R 17 G ND REC C 21
R 16
ISD N _S T1 G ND
R 18 /T X_E N Q6
REC1 REC2
TR AN S1 TR AN S2
R E1 TX1 _H I Q7 Q8
RE2
T X2_H I TR 1B Q 10 Q9
/T X2 _LO RG1
/TX 1_L O RG 2 R F1 R 19 RF2 C 25
G ND
G ND
TR AN S
C 26
D6
G ND R 22 D7
863C @39 1
GND G ND
D8 Title
IS D N P C I C a rd fo r 3 .3 V w ith o u t D 3 co ld S u p po rt
(c) 2 0 0 0 by C o lo gn e C h ip A G
S iz e A4 D ate:
D o cum ent N um ber Thursday, O ctob er 19, 2 000 S heet 2
Rev 2.0
of
2
'& _V (#
:Q^eQbi " !
Cologne Chip
863C @39 1
Cologne Chip
ISDN PCI Card for 3.3 V without D3cold support
Capacitors C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C14 C15 C16 C18 C19 C20 C21 C22 C23 C24 C25 C26 C29 C30 C31 33 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 47p 47p 33 22p 33 22p 0 0 47n 470p 0 0 33n 33n 10n
Resistors R01 R03 R05 R06 R11 R12 R13 R14 R15 R16 R17 R18 R19 R22 RA1 RA2 RB1 RB2 RC1 RC2 RD1 RD2 RE1 RE2 RF1 RF2 RG1 RG2 10k 1M 330 10k 10k 10k 3k9 680k 1M2 3k3 100 5k6 3k3 2k2 100k 100k 33k 33k 4k7 4k7 4k7 4k7 430 430 15 15 3k9 3k9
IC's U2 U3 U4 HFC-S PCI A Cologne Chip AG optional 74HC374 24C04
nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby JP1 optiona l nearby JP2 optional nearby U1 nearby U4 nearby U3 optional depends on crystal depends on crystal nearby U2 nearby U2
Connectors JP1 JP2 JP10 JP11 JP12
PCM IO
optional optional
EEPROM options optional EEPROM options optional 33/66 MHz
optional
Transistors / Crystals Q1 Q2 Q3 Q6 Q7 Q8 Q9 Q10
1% 1%
optional optional
BC850C 12.288M BC860C BC860C BC850C BC850C BC850C BC850C
CMPT5088 or similar CMPT5087 or similar CMPT5087 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar
optional optional nearby JP2 optional
nearby JP2 optional optional
Diodes D3 D4 D6 D7 D8 BAV99 BAV99 BAV99 2V7 BAV99
can also be 2*4148 can also be 2*4148 can also be 2*4148 can also be 2*4148
1% 1%
:Q^eQbi " !
'' _V (#
3. 3Vaux
P CI_S T1D Vi/ o +5V Vi/o +5V PME# INTD # INTC # IN TB # IN TA# P RSN T2# P RSN T1# GND G ND G ND U2 PM E _S R1 R ST_S RS T_P GND JP2 G ND TR ST # TM S TC K TDI TD O PCI_ST 1C S DO NE PCIS PE C S BO # R ST # CLK G NT # REQ # S ER R# P ER R# LO CK # IDSE L DE VS EL# STO P# IRDY # T RDY # FR AM E # M 66EN
C LK GNT# REQ# SERR# PERR#
VDD _HF C
P28/29
P48/49
P60/61
P76/77
P89/90
74HC74
NC 24C04
4
74HC374
JP1
B11 B9 A1 A3 B2 A4 B4 A40 A41 A15 B16 A17 B18 B42 B40 B39 A26 B37 A38 B35 A36 A34 B49 91 92 93 94 95 25 24
INTA# RS T# CLK G NT # RE Q # SE RR# PE RR# O SC _O U T O SC_IN R3 PM E
JP2
74HC374
PC I_S T1B P CIINT 74HC74 C 29
10
A19 B8 A7 B7 A6
PM E _S +12V -12V +5V +3.3V 3.3Vaux Vi/o
7
P CIPO W NC NC C30
VDD _H FC
+ C1
C2 P7/8
C3
C4
C5
C6
C7
C8
C9
C 10
C 11 24C04
C12
U1A
4 3 2 1
S VCC C1 5 1D 6 R 74HC74
14
G ND JP12 M 66E N Q1 C 31 G ND G ND +5V
/A U X _ W R DA UX 0
ISDN PCI card for 3.3V power supply with D3cold support
VD D_HFC
V DD _HF C
RS T_P
53 50 51
JP 3 R2 U1B
ID S E L D EVSE L# S TO P # IR D Y # TRD Y# FRA ME#
6 22 23 20 21 19
IDSE L DE VS EL# STO P # IRDY # TR DY # FR AM E # C 14 M 66E N
Q2
R5 R6
V DD_HF C + U3 C 15 G ND Q3
optional
10 11 12 13
C13
S VCC C1 9 1D 8 R 7 4H C 74
20 1 11
/A D R _ W R
14
D1
R4
VCC EN C1
G ND GND VD D_HF C
DAUX0 DAUX1 DAUX2 DAUX3 DAUX7 DAUX6 DAUX5 DAUX4
RST _S GND
PAR C /B E3# C /B E2# C /B E1# C /B E0# A D31 A D30 A D29 A D28 A D27 A D26 A D25 A D24 A D23 A D22 A D21 A D20 A D19 A D18 A D17 A D16 A D15 A D14 A D13 A D12 A D11 A D10 A D09 A D08 A D07 A D06 A D05 A D04 A D03 A D02 A D01 AD 0 PC I_S T1A PCIA DR VDD _H FC
A43
PA R
26
PAR C/BE 3# C/BE 2# C/BE 1# C/BE 0# AD 31 AD 30 AD 29 AD 28 AD 27 AD 26 AD 25 AD 24 AD 23 AD 22 AD 21 AD 20 AD 19 AD 18 AD 17 AD 16 AD 15 AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0
B26 B33 B44 A52
C /B E 3 # C /B E 2 # C /B E 1 # C /B E 0 # AD 31 AD 30 AD 29 AD 28 AD 27 AD 26 AD 25 AD 24 AD 23 AD 22 AD 21 AD 20 AD 19 AD 18 AD 17 AD 16 AD 15 AD 14 AD 13 AD 12 A D 11 AD 10 AD 09 AD 08 AD 07 AD 06 AD 05 AD 04 AD 03 AD 02 AD 01 AD 00
5 18 27 38 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 89
863C @39 1
D A U X [0 :7 ],/A U X _ W R ,/A U X _ R D ,/A D R _ W R
Title VD D_HFC all VDD_HFC Pins 7/28/48/60/76/89 GND
8
IS D N P C I C a rd for 3 .3 V w ith D 3 co ld S upp ort
(c) 200 0 by C olog ne C hip A G
H F C -S P C I A
G ND
all GND Pins 8/17/29/39 49/52/61/64/77/83/90/96
Size A4 Date:
Docum ent Num ber Thursday, O ctober 19, 2000
Rev 2.0
S heet
1
of
2
'( _V (#
B20 A20 B21 A22 B23 A23 B24 A25 B27 A28 B29 A29 B30 A31 B32 A32 A44 B45 A46 B47 A47 B48 A49 B52 B53 A54 B55 A55 B56 A57 B58 A58
G ND
AD J_LE V LEV _R 1 R1 R2 LEV _R 2 T X1_HI /T X2_LO /TX _E N /T X1_LO T X2_HI STIO 2 STIO 1 C4IO F0IO F 1_A F 1_B E E_S CL/EN EE __SD A /AD R_W R /AU X_R D /AU X_W R DA UX 7 DA UX 6 DA UX 5 DA UX 4 DA UX 3 DA UX 2 DA UX 1 DA UX 0
78 80 79 82 81 84 85 86 87 88 57 56 54 55 58 59 62 63 65 66 67 68 69 70 71 72 73 74 75
/A D R _ W R /A U X _ R D /A U X _ W R D AUX 7 D AUX 6 D AUX 5 D AUX 4 D AUX 3 D AUX 2 D AUX 1 D AUX 0 S T IO 2 S T IO 1 C 4 IO F0 IO F1 _ A F1 _ B
ADJ_LEV LEV _R 1 R1 R2 LEV _R 2 TX1_H I /T X2_LO /T X_EN /T X1_LO TX2_H I
JP 1 P CM
optional
3 4 7 8 13 14 17 18 1 3 5 7
F1_A F1_B
1D
2 5 6 9 12 15 16 19 2 4 6 8
C 4 IO F0 IO S T IO 1 S T IO 2
A0 A1 A2 A3 A7 A6 A5 A4
R_Sens (optional)
D9
R 30 R _S ens
Power Management
74HC374 +5V Vi/o JP2
S T IO [1 :2 ],C 4 IO ,F 0 IO ,F1 _ A ,F1 _ B
Vi/o VDD _H FC
optional
3.3Vaux
VD D_HFC
DAUX0 DAUX2 DAUX4 DAUX6 A0 A2 A4 A6 /A U X _ W R /A D R _ W R
R11
R 12
U4
5 6 8
J P 10 J P 11
SD A A 2 SC L A 1 VC C A 0 T ES T
3 2 1 7
1 3 5 7 9 11 13 15 17 19 21 23 25
IO GND
2 4 6 8 10 12 14 16 18 20 22 24 26
Q4
DA UX 1 DA UX 3 DA UX 5 DA UX 7 A1 A3 A5 A7 /A U X _ R D
Q5
R9
D2
R 10
JP 4
JP5
G ND
G ND
+ GND
C16
C 17
24C04
G ND GND
A [0 :7 ]
VDD _HF C
G ND
G ND
The R_Sens part is optional. It is used to decrease the receiver sensitivity for wake-up signals to avoid a wake-up caused by disturbance on the ISDN line. Please see chapter 3.3 for details on power management support of HFC-S PCI A and special considerations for support of power management state D3cold. 12.4
IN TA
:Q^eQbi " !
Cologne Chip
Cologne Chip
VD D _H FC R 13 AD J_LEV C 18 R A1 VD D _H FC R B1 D3 R 15 R B2 LEV_ R 2 R A2 D4 R _Sens C 20 RC2 RD2 R2 GND TR 1A G ND LEV_ R 1 R1 RC1 RD1 + C 19 R 14
C 22 +5V C 23 R 16 C 24 R 17 GND R 18 /TX_E N Q6 GND REC C 21
GND
ISD N _ST1
R EC 1 R EC 2
TR AN S1 TR AN S2 R E2 Q7 Q8
R E1 TX1_H I
TX2_H I TR 1B Q 10
/TX2_LO RG1
Q9
/TX1 _LO RG 2 R F1 R 19 RF2 C 25
GND
GND
TR A N S
C 26
D6
GND R 22 D7
863C @39 1
G ND GND
D8 Title
IS D N P C I C a rd fo r 3 .3 V w ith D 3 cold S up p ort
(c) 20 0 0 b y C o lo gn e C h ip A G
S ize A4 D a te:
D ocum ent N um ber Thursday, O ctober 19, 2000 She et 2
R ev 2.0
of
2
:Q^eQbi " !
') _V (#
863C @39 1
Cologne Chip
ISDN PCI Card for 3.3 V with D3cold support
Capacitors C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C29 C30 C31 33 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 1 47p 47p 33 33n 22p 33 22p 0 0 47n 470p 0 0 33n 33n 10n
Resistors R01 R02 R03 R04 R05 R06 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R22 R30 RA1 RA2 RB1 RB2 RC1 RC2 RD1 RD2 RE1 RE2 RF1 RF2 RG1 RG2 10k 1M 1M 10k 330 10k 10k 10k 10k 10k 3k9 680k 1M2 3k3 100 5k6 3k3 2k2 680k * 100k 100k 33k 33k 4k7 4k7 4k7 4k7 430 430 15 15 3k9 3k9
IC's U1 U2 U3 U4 74HC74 HFC-S PCI A Cologne Chip AG optional 74HC374 24C04
nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby JP1 optiona l nearby JP2 optional nearby U1 nearby U4 nearby U3 optional depends on crystal depends on crystal
Connectors JP1 JP2 JP3 JP4 JP5 JP10 JP11 JP12
PCM IO Reset options Power options Power options EEPROM options optional EEPROM options optional 33/66 MHz
optional optional
nearby U2 nearby U2
optional
optional optional
Transistors / Crystals Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 BC850C 12.288M BC860C BC860C BC860C BC860C BC850C BC850C BC850C BC850C
CMPT5088 or similar CMPT5087 or similar CMPT5087 or similar CMPT5087 or similar CMPT5087 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar
optional optional nearby JP2 optional nearby JP2 optional
optional
1% 1%
1% 1%
Diodes D1 D2 D3 D4 D6 D7 D8 D9 LL4148 LL4148 BAV99 BAV99 BAV99 2V7 BAV99 LL4148 *
or similar or similar can also be 2*4148 can also be 2*4148 can also be 2*4148 can also be 2*4148 or similar
* optional, not on PCB Layout V 2.0
( _V (#
:Q^eQbi " !
Cologne Chip
3. 3Vaux
P CI_S T1D Vi/ o +5V Vi/o +5V PME# INTD # INTC # IN TB # IN TA# P RSN T2# P RSN T1# GND G ND G ND U2 PM E _S R1 R ST_S RS T_P GND JP2 G ND TR ST # TM S TC K TDI TD O PCI_ST 1C S DO NE PCIS PE C S BO # R ST # CLK G NT # REQ # S ER R# P ER R# LO CK # IDSE L DE VS EL# STO P# IRDY # T RDY # FR AM E # M 66EN
C LK GNT# REQ# SERR# PERR#
VDD _HF C
P28/29
P48/49
P60/61
P76/77
P89/90
74HC74
NC 24C04
4
74HC374
JP1
B11 B9 A1 A3 B2 A4 B4 A40 A41 A15 B16 A17 B18 B42 B40 B39 A26 B37 A38 B35 A36 A34 B49 91 92 93 94 95 25 24
INTA# RS T# CLK G NT # RE Q # SE RR# PE RR# O SC _O U T O SC_IN R3 PM E
JP2
74HC374
PC I_S T1B P CIINT 74HC74 C 29
10
A19 B8 A7 B7 A6
PM E _S +12V -12V +5V +3.3V 3.3Vaux Vi/o
7
P CIPO W NC NC C30
VDD _H FC
+ C1
C2 P7/8
C3
C4
C5
C6
C7
C8
C9
C 10
C 11 24C04
C12
U1A
IN TA
4 3 2 1
S VCC C1 5 1D 6 R 74HC74
14
G ND JP12 M 66E N Q1 C 31 G ND G ND +5V
/A U X _ W R DA UX 0
VD D_HFC
V DD _HF C
RS T_P
53 50 51
JP 3 R2 U1B
ID S E L D EVSE L# S TO P # IR D Y # TRD Y# FRA ME#
6 22 23 20 21 19
IDSE L DE VS EL# STO P # IRDY # TR DY # FR AM E # M 66EN
Q2
R5 R6
V DD_HF C + U3
optional
10 11 12 13
C13
S VCC C1 9 1D 8 R 7 4H C 74
C 14 C 15 G ND Q3
14
D1
R4
20 1 11
/A D R _ W R
VCC EN C1
G ND GND VD D_HF C
DAUX0 DAUX1 DAUX2 DAUX3 DAUX7 DAUX6 DAUX5 DAUX4
RST _S GND
PAR PAR C/BE 3# C/BE 2# C/BE 1# C/BE 0# AD 31 AD 30 AD 29 AD 28 AD 27 AD 26 AD 25 AD 24 AD 23 AD 22 AD 21 AD 20 AD 19 AD 18 AD 17 AD 16 AD 15 AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 PC I_S T1A PCIA DR VDD _H FC C /B E3# C /B E2# C /B E1# C /B E0# A D31 A D30 A D29 A D28 A D27 A D26 A D25 A D24 A D23 A D22 A D21 A D20 A D19 A D18 A D17 A D16 A D15 A D14 A D13 A D12 A D11 A D10 A D09 A D08 A D07 A D06 A D05 A D04 A D03 A D02 A D01 AD 0
A43
PA R C /B E 3 # C /B E 2 # C /B E 1 # C /B E 0 # AD 31 AD 30 AD 29 AD 28 AD 27 AD 26 AD 25 AD 24 AD 23 AD 22 AD 21 AD 20 AD 19 AD 18 AD 17 AD 16 AD 15 AD 14 AD 13 AD 12 A D 11 AD 10 AD 09 AD 08 AD 07 AD 06 AD 05 AD 04 AD 03 AD 02 AD 01 AD 00
26 5 18 27 38 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 89
B26 B33 B44 A52 B20 A20 B21 A22 B23 A23 B24 A25 B27 A28 B29 A29 B30 A31 B32 A32 A44 B45 A46 B47 A47 B48 A49 B52 B53 A54 B55 A55 B56 A57 B58 A58
G ND
AD J_LE V LEV _R 1 R1 R2 LEV _R 2 T X1_HI /T X2_LO /TX _E N /T X1_LO T X2_HI STIO 2 STIO 1 C4IO F0IO F 1_A F 1_B E E_S CL/EN EE __SD A /AD R_W R /AU X_R D /AU X_W R DA UX 7 DA UX 6 DA UX 5 DA UX 4 DA UX 3 DA UX 2 DA UX 1 DA UX 0 VD D_HFC GND
78 80 79 82 81 84 85 86 87 88 57 56 54 55 58 59 62 63 65 66 67 68 69 70 71 72 73 74 75 8
/A D R _ W R /A U X _ R D /A U X _ W R D AUX 7 D AUX 6 D AUX 5 D AUX 4 D AUX 3 D AUX 2 D AUX 1 D AUX 0 S T IO 2 S T IO 1 C 4 IO F0 IO F1 _ A F1 _ B
ADJ_LEV LEV _R 1 R1 R2 LEV _R 2 TX1_H I /T X2_LO /T X_EN /T X1_LO TX2_H I
JP 1 P CM
optional
3 4 7 8 13 14 17 18 1 3 5 7
F1_A F1_B
1D
2 5 6 9 12 15 16 19 2 4 6 8
C 4 IO F0 IO S T IO 1 S T IO 2
A0 A1 A2 A3 A7 A6 A5 A4
R_Sens (optional)
D9
R 30 R _S ens
Power Management
74HC374 +5V Vi/o JP2
S T IO [1 :2 ],C 4 IO ,F 0 IO ,F1 _ A ,F1 _ B
Vi/o VDD _H FC
optional
3.3Vaux
VD D_HFC
DAUX0 DAUX2 DAUX4 DAUX6 A0 A2 A4 A6 /A U X _ W R /A D R _ W R
R11
R 12
U4
863C @39 1
5 6 8
J P10 J P11
SD A A 2 SC L A 1 VC C A 0 T ES T
3 2 1 7
1 3 5 7 9 11 13 15 17 19 21 23 25
IO GND
2 4 6 8 10 12 14 16 18 20 22 24 26
Q4
DA UX 1 DA UX 3 DA UX 5 DA UX 7 A1 A3 A5 A7 /A U X _ R D
Q5
R9
D2
R 10
JP 4
JP5
G ND
G ND
+ GND
C16
C 17
The R_Sens part is optional. It is used to decrease the receiver sensitivity for wake-up signals to avoid a wake-up caused by disturbance on the ISDN line. Please see chapter 3.3 for details on power management support of HFC-S PCI A and special considerations for support of power management state D3cold. ISDN PCI card for 3.3 and 5V power supply (auto detect) with D3cold support
24C04
G ND GND
D A U X [0 :7 ],/A U X _ W R ,/A U X _ R D ,/A D R _ W R A [0 :7 ]
VDD _HF C
G ND
G ND
Title Size A4 all VDD_HFC Pins 7/28/48/60/76/89 Docum ent Num ber
IS DN P CI Card for 3.3/5 V or universal Power w ith D 3cold S upport all GND Pins 8/17/29/39 49/52/61/64/77/83/90/96
H F C -S P C I A
Rev 2.0 G ND Date: Tuesday, O ctober 17, 2000
S heet
1
of
2
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12.5
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VD D _H FC R 13 AD J_LEV C 18 R A1 VD D _H FC R B1 D3 R 15 R B2 LEV_ R 2 R A2 D4 R _Sens C 20 RC2 RD2 R2 GND TR 1A G ND LEV_ R 1 R1 RC1 RD1 + C 19 R 14
C 22 GND +5V C 23 R 16 C 24 R 17 GND R 18 /TX_E N Q6 JP6 R E1
5V/uni
REC
C 21
ISD N _ST1 GND
R EC 1 R EC 2
TR AN S1 TR AN S2 R E2 Q7 Q8
5V/uni
JP7 1
3V3
1 TX1_H I
3V3
TX2_H I TR 1B R E4 Q 10 1 JP9
R E3 1 JP8 RG1
5V 3V3
/TX2_LO
Q9
/TX 1_LO
C 25 R F1 R 19 R F2 RG 2
5V 3V3
GND
RG3 D5
RG 4
GND
TR A N S
C 26
Vi/o
+5V U5
D6
GND
863C @39 1
1 4
R 21 C 27 R 23 Q 11 G ND
VIN VO U T VO U T AD J VO U T VO U T
2 3 6 7
R 22 D7 R 20 D8 + R 24 S ize A4 GND D a te: Thursday, O ctober 19, 2000 She et 2 C 28 C 32 G ND GND Title D ocum ent N um ber
ISD N PC I C ard for 3.3/5 V or universal Pow er w ith D 3cold Support
R ev 2.0
of
2
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Cologne Chip
863C @39 1
Cologne Chip
ISDN PCI Card for 3.3/5 V or Universal Power with D3cold Support
Capacitors C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 Diodes D1 D2 D3 D4 D5 D6 D7 D8 D9 LL4148 LL4148 BAV99 BAV99 BAV70 BAV99 2V7 BAV99 LL4148 **
or similar or similar can also be 2*4148 * can also be 2*4148 * can also be 2*4148 * can also be 2*4148 * can also be 2*4148 * or similar
Resistors R01 R02 R03 R04 R05 R06 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R30 RA1 RA2 RB1 RB2 RC1 RC2 RD1 RD2 RE1 RE2 RE3 RE4 RF1 RF2 RG1 RG2 RG3 RG4 10k 1M 1M 10k 330 10k 10k 10k 10k 10k 3k9 680k 1M2 3k3 100 5k6 3k3 180 1k 2k2 2k7 150 680k ** 100k 100k 33k 33k 4k7 4k7 4k7 4k7 2k2 2k2 430 430 15 15 3k 3k 3k9 3k9
IC's U1 U2 U3 U4 U5 74HC74 HFC-S PCI A Cologne Chip AG optional 74HC374 24C04 LM317L/SO
33 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 33n 1 47p 47p 22 33n 22p 33 22p 0 0 47n 470p 0 0 33n 1 33n 33n 10n 0
nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby U2 nearby JP1 optiona l nearby JP2 optional nearby U1 nearby U4 nearby U3 optional depends on crystal depends on crystal
Connectors JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP11 JP12
PCM IO Reset options Power options Power options Power options Power options Power options Power options EEPROM options EEPROM options 66 MHz options only for 3.3V systems
optional optional
nearby U2 nearby U2
optional optional
optional optional
Transistors / Crystals Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 BC850C 12.288M BC860C BC860C BC860C BC860C BC850C BC850C BC850C BC850C BC860C
CMPT5088 or similar CMPT5087 or similar CMPT5087 or similar CMPT5087 or similar CMPT5087 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar CMPT5088 or similar CMPT5087 or similar
nearby JP2 optional nearby JP2 optional
only for 3.3V systems optional
1% 1% 1% 1%
1% 1% 1% 1%
* alternative footprint required ** optional, not on PCB Layout V 2.0
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