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NEOTEC SEMICONDUCTOR LTD.
NT7086
www..com
NT7086
80 CH SEGMENT / COMMON DRIVER FOR DOT MATRIX LCD
Copyright: NEOTEC (C) 2002
http://www.neotec.com.tw
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of NEOTEC
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NEOTEC SEMICONDUCTOR LTD. INTRODUCTION
NT7086
The NT7086 is a LCD driver LSI that is fabricated by low power CMOS high voltage process technology. In segment drive mode, it can be interfaced in 1-bit serial or 4-bit parallel method by the controller. In common drive mode, dual type mode is applicable. And in segment mode application, the power down function reduces power consumption.
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FEATURES
Power supply voltage:+5 V10%, + 3V10% Supply voltage for display: 6 to 28 V (VDD-VEE) 4-bit parallel/1-bit serial data processing (in segment mode).. Single mode operation / dual mode operation (in common mode). Power down function (in segment mode). Applicable LCD duty:1/64 ~ 1/256 Interface DRIVERS COM(cascade) NT7086 SEG(cascade) NT7086
High voltage CMOS process. Available PKG type : bare chip, 100-LQFP, 100-TQFP Order Number Package NT7086 chip on tray NT7086Q LQFP NT7086TQ TQFP
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NEOTEC SEMICONDUCTOR LTD.
SC2 SC1 ELB CL1 AMS CL2 D1_SID D2_DL D3_DM D4_DR VSS SHL VDD DISPOFFB M CS V0 V12 V43 V5 VEE ERB SC80 SC79 SC78
NT7086
NT7086 100 LQFP PACKAGE
SC3 SC4 www..comSC5 SC6 SC7 SC8 SC9 SC10 SC11 SC12 SC13 SC14 SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 SC27
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
NT7086
SC77 SC76 SC75 SC74 SC73 SC72 SC71 SC70 SC69 SC68 SC67 SC66 SC65 SC64 SC63 SC62 SC61 SC60 SC59 SC58 SC57 SC56 SC55 SC54 SC53
PKG TYPE PKG THICKNESS PKG SIZE PAD PITCH PAD WIDTH PAD LENGTH
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SC28 SC29 SC30 SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50 SC51 SC52
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
= = = = = =
100-LQFP 1.40 ( 0.05) mm 14.00 ( 0.10) X 14.00 ( 0.10) mm 0.5 mm 0.20 ( +0.07,-0.03) mm 1.0 (+-0.1) mm
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NEOTEC SEMICONDUCTOR LTD.
NT7086 100 TQFP PACKAGE
NT7086
76 SC3 77 SC4 78 SC5 www..com 79 SC6 80 SC7 81 SC8 82 SC9 SC10 83 SC11 84 SC12 85 SC13 86 SC14 87 SC15 88 SC16 89 SC17 90 SC18 91 SC19 92 SC20 93 SC21 94 SC22 95 SC23 96 SC24 97 SC25 98 SC26 99 SC27 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
SC2 SC1 ELB CL1 AMS CL2 D1_SID D2_DL D3_DM D4_DR VSS SHL VDD DISPOFFB M CS V0 V12 V43 V5 VEE ERB SC80 SC79 SC78
NT7086
SC77 SC76 SC75 SC74 SC73 SC72 SC71 SC70 SC69 SC68 SC67 SC66 SC65 SC64 SC63 SC62 SC61 SC60 SC59 SC58 SC57 SC56 SC55 SC54 SC53
PKG TYPE PKG THICKNESS PKG SIZE PAD PITCH PAD WIDTH PAD LENGTH
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SC28 SC29 SC30 SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50 SC51 SC52
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
= = = = = =
100-TQFP 1.00 ( 0.05) mm 14.00 ( 0.10) X 14.00 ( 0.10) mm 0.5 mm 0.20 ( 0.03) mm 1.0 ( 0.1) mm
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NEOTEC SEMICONDUCTOR LTD. PAD DIAGRAM Note: Please connects the substrate to VDD or Floating
SC50 100
2 3 4 5
NT7086
SC52 SC53 SC54 SC55
SC29 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 SC18 SC17 SC16
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SC51
1
SC49
SC48
SC47
SC46
SC45
SC44
SC43
SC42
SC41
SC40
SC39
SC38
SC37
SC36
SC35
SC34
SC33
SC32
SC31
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7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SC57 SC58 SC59 SC60 SC61 SC62 SC63 SC64 SC65 SC66 SC67 SC68 SC69 SC70 SC71 SC72 SC73 SC74 SC75 SC76 DISPOFFB SC77 SC78 ERB VEE CS V5 V0 M SC79 SC80 V43 V12
(0,0)
SC30 ELB
50
SC15 SC14 SC13 SC12
NT7086
CHIP SIZE: 3340X3760 um2 PAD SIZE: 100X100 um2 MIN PITCH: 125 um
SC11 SC10 SC9 SC8 SC7 SC6 SC5 SC4 D3_DM D1_SID D4_DR D2_DL SC3 AMS CL2 CL1 SC2 SC1
VDD
SHL
41
31
32
33
34
35
36
37
38
39
40
42
VSS
43
44
45
46
47
48
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NEOTEC SEMICONDUCTOR LTD. PAD LOCATION
Pad No.
1 2 3 4 5 6 7 www..com 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NT7086
Pad name
SC51 SC52 SC53 SC54 SC55 SC56 SC57 SC58 SC59 SC60 SC61 SC62 SC63 SC64 SC65 SC66 SC67 SC68 SC69 SC70 SC71 SC72 SC73 SC74 SC75 SC76 SC77 SC78 SC79 SC80 ERB VEE V5 V43 V12 V0 CS M DISPOFFB VDD SHL VSS D4_DR D3_DM D2_DL D1_SID CL2 AMS CL1 ELB
X
-1313.50 -1544.00
Y
1746.00 1746.00 1621.00 1496.00 1371.00 1246.00 1121.00 996.00 871.00 746.00 621.00 496.00 371.00 246.00 121.00 -4.00 -129.00 -254.00 -379.00 -504.00 -629.00 -754.00 -879.00 -1004.00 -1129.00 -1254.00 -1379.00 -1504.00 -1629.00 -1754.00
Pad No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pad name
SC1 SC2 SC3 SC4 SC5 SC6 SC7 SC8 SC9 SC10 SC11 SC12 SC13 SC14 SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 SC27 SC28 SC29 SC30 SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50
X
1542.00
Y
-1754.00 -1629.00 -1504.00 -1379.00 -1254.00 -1129.00 -1004.00 -879.00 -754.00 -629.00 -504.00 -379.00 -254.00 -129.00 -4.00 121.00 246.00 371.00 496.00 621.00 746.00 871.00 996.00 1121.00 1246.00 1371.00 1496.00 1621.00 1746.00
-1218.40 -1048.70 -923.70 -798.70 -673.70 -548.70 -380.00 -255.00 -130.00 -5.00 120.10 245.10 370.10 495.10 620.10 745.10 870.10 995.10 1120.10 1245.10
1311.50 1186.50 1061.50 936.50 811.50 686.50 561.50 436.50 311.50 186.50 61.50 -63.50 -188.50 -313.50 -438.50 -563.50 -688.50 -813.50 -938.50 -1063.50 -1188.50
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NEOTEC SEMICONDUCTOR LTD.
BL O C K DI AG R AM
SC1 SC2 SC3 SC78 SC79 SC80
NT7086
......
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V0 V12 V43 V5 VEE
80-bit 4-level driver .............. 80-bit level driver .............. 80 bit data latch / common data bidirectional shift register .............. SCK 20 X 4-bits segment data bidirectional shift register / D1_SID D2_DL D3_DM D4_DR
M DISPOFFB
Output level selector LCK
CL1 CL2 Clock control
Data latch control
CS AMS
Power down function
ERB VDD VSS
ELB
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NEOTEC SEMICONDUCTOR LTD. BLOCK DESCRIPTION
NAME FUNCTION Generates latch clock (LCK), shift clock (SCK) and control clock timing according to the input of CL1, CL2 and control inputs (CS, AMS). In common driver application mode, this block generates the shift clock (LCK) for the common data Bi-directional shift register. Determines the direction of segment data shift, and input data of each Data latch Bi-directional shift register. In 4-bit segment data parallel transfer mode, data is shifted by a 4-bit unit. In common driver application mode, data is transferred to the common data shift register directly, which disables this block. Controls the clock enable state of the current driver according to the input value of enable pin (ELB or ERB). If enable input value is "Low", every clock of the current driver is enabled and the clock control block works. But if enable input is "High", current driver is disabled and the input data value has no effect on the output level. So power consumption can be lowered. Controls the output voltage level according to the input control pin (M and DISPOFFB) (refer to PIN DESCRIPTION). Stores output data value by shifting the input values. In 1-bit serial interface mode application, all 80 shift clocks (SCK) are needed to store all the display data. But in 4-bit parallel transfer mode application, only 20 clocks are needed. In common driver application mode, this block does not work. In segment driver application mode, the data from the 20x4-bit segment data shift register are latched for segment driver output. In single-type common driver application, 1-bit input data (from DL or DR pin) is shifted and latched by the direction according to the SHL signal input. In dual-type common application mode, 80-bit registers are divided by two blocks and controlled Independently (refer to NOTE 3). Voltage level shifter block for high voltage part. The inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. These values are input in to the driver. Selects the output voltage level according to M and latched data value. If the data value is "High" the driver output is at selected voltage level (V0 or V5), and in the reverse case the driver output value is at the non-selected level (V12 or V43). In segment driver application mode, non-selected output value is V2 or V3 and when in common driver application, this value becomes V1 or V4.
NT7086
COM / SEG
Clock control
COM / SEG
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Data latch control
SEG
Power down function
SEG
Output level selector 20x4-bitsegm ent data bi-directional shift register 80-bit data latch / common data bi-directional shift register
COM / SEG
SEG
COM / SEG
80-bit level shifter
SEG
80-bit 4-level driver
SEG
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NEOTEC SEMICONDUCTOR LTD. PIN DESCRIPTION
PIN VDD VSS VEE
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NT7086
I/O
V0,V12, V43,V5
I
SC1~SC80
O
CL2
I
M
I
CL1
I
FUNCTION Logical "High" input port (+5V10%, +3V 10%) Power supply 0V (GND) Logical "Low" for high voltage part LCD driver Bias supply voltage input to drive the LCD. output Bias voltage divided by the resistance is voltage usually used as a supply voltage source (refer level to NOTE 2). Display data output pin which corresponds to the respective latch contents. One of V0, V12, LCD driver V34 and V5 is selected as a display driving output voltage source according to the combination of the latched data level and M signal (refer to NOTE 1). Clock pulse input for the bi-directional shift register. - In segment driver application mode, the data is shifted to 20 x4-bit segment data shift. The clock pulse, which was input when the Data shift enable bit (ELB/ERB) is in not active clock condition, is invalid. - In common driver application mode, the data is shifted to 80-bit common data bi-directional shift register by the CL1 clock. Hence, this clock pin is not used (Open or connect this pin to VDD). AC signal Alternate signal input pin for LCD driving. Normal for LCD frame inversion signal is input in to this pin. driver output - In segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. Data latch CL1 pulse "High" level initializes clock power-down function block. - In common driver application mode, CL1 is used as a shifting clock of common output data.
NAME
INTERFACE Power
Power
LCD
Controller
Controller
Controller
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NEOTEC SEMICONDUCTOR LTD. PIN DESCRIPTION (CONTINUED)
PIN I/O FUNCTION Control input pin to fix the driver output (SC1~SC80) to V0 level, during "Low" value Display input. LCD becomes non-selected by V0 level OFF control output from every output of segment drivers and every output of common drivers. When CS = "Low", NT7086 is used as an COM / SEG 80-bit segment driver. mode When CS = "High", NT7086 is set to an 80-bit control common driver According to the input value of the AMS and the CS pin, application mode of NT7086 is differs as shown below. CS AMS AMS I Application mode select 0 0 1 1 0 1 0 1 Application mode COM/SEG 4-bit parallel interface mode SEG 1-bit serial interface mode Single type application Mode COM Dual type application mode NAME
NT7086
INTERFACE
DISPOFFB
I
Controller
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CS
I
VDD/VSS
VDD/VSS
D1_SID, D2_DL, D3_DM, D4_DR
Display data input/ serial input I/O data/ left , right data input output
-In segment driver mode, these pins are used as 4-bit data input pin (when 4-bit parallel interface mode AMS= "low"), or D1_SID is used as serial data input pin and other pins are not used (connect these to VDD) (when 1-bit serial interface mode AMS= "high"). -In common driver mode, the data is shifted from D2_DL (D4_DR) to D4_DR (D2_DL), when in single interface mode (AMS= "Low"). In dual-type application case, the data are shifted from D2_DL and D3_DM (D4_DR and D3_DM) to D4_DR(D2_DL). In each case the direction of the data shift and the connection of data pins are determined by SHL input (refer to NOTE 3, NOT 4).
Controller
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NEOTEC SEMICONDUCTOR LTD. PIN DESCRIPTION (CONTINUED)
PIN SHL I/O FUNCTION When SHL = "Low", data is shifted from left Shift to right. direction I When SHL = "High", the direction is reversed. control (refer to NOTE3) -In segment driver mode, the internal operation is enabled only when enable input (ELB or ERB) is "Low" (power down function). When several drivers a serially connected, the enable state of each driver is shifted according to the SHL input. Connect Enable data these pins as below. I/O input/ Segment driver output SHL ELB ERB L Output (open) Input (VSS) H Input (VSS) Output(open) -In common driver mode, the power down function is not used. Open these pins. NOTE 1. Output level control M L L H H X Latched data L H L H X DISPOFFB H H H H L "X": don't care Output level (CS1~CS80) SEG Mode COM Mode V12(V2) V12(V1) V0 V5 V43(V3) V43(V4) V5 V0 V0 V0 NAME
NT7086
INTERFACE
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VDD/VSS
ELB, ERB
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NEOTEC SEMICONDUCTOR LTD.
NOTE 2. LCD Driving Voltage Application Circuit (1) Segment driver application (CS = "Low")
VDD V0 R
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NT7086
C
VDD V0
to COM driver
V1 V2 V3 V4
R (n-4)R R
SEG1~SEG80
to LCD panel
V12
NT7086
V43
to COM driver
V0,V5 Selection level V2,V3 Non-selection level V5 VSS * n=9 (when 1/64 duty) to 17 (when 1/256 duty)
R V5
VEE
(2) Common driver application (CS = "High")
VDD V0 R R (n-4)R R V4 R V5 V5 VSS * n=9 (when 1/64 duty) to 17 (when 1/256 duty) V43 V1 V2 V3
to SEG driver NT7086
C
VDD V0 V12
COM1~COM80
to LCD panel
V0,V5 Selection level V1,V4 Non-selection level
VEE
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NEOTEC SEMICONDUCTOR LTD.
NOTE 3. Data Shift Direction according to Control Signals (1) When CS = "Low" (segment driver application) Application AMS SHL Data Direction mode
SSSS CCCC 1234
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NT7086
Input pin
S C 7 6 S C 7 7 S C 7 8 S C 7 9 S C 8 0
S C 7 ........ 3
S C 7 4
S C 7 5
L
D1 D2 D3 D4
D D D D ........ D D D D D D D D 1234 12341234
Shift direction Last data Frist data
L
4-bit parallel data transfer mode (SEG)
SSSS CCCC 1234
S C 7 ........ 3
S C 7 4
S C 7 5
S C 7 6
S C 7 7
S C 7 8
S C 7 9
S C 8 0
D1_SID, D2_DL, D3_DM, D4_DR
H
D D D D ........ D D D D D D D D 4321 43214321
Shift direction Frist data
D1 D2 D3 D4 S C 7 4 S C 7 5 S C 7 6
Last data
L 1-bit serial data transfer mode (SEG) H
SSSS CCCC 1234
S C ........ 7 3
S C 7 7
S C 7 8
S C 7 9
S C 8 0
Shift direction Last data (D1_SID) S C ........ 7 3 S C 7 4 S C 7 5 S C 7 6 S C 7 7 S C 7 8 Frist data
H
D1_SID
SSSS CCCC 1234 S C 7 9 S C 8 0
Shift direction Frist data
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Last data
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NEOTEC SEMICONDUCTOR LTD.
(2) When CS = "High" (common driver application) Application AMS SHL Data Direction mode
..... SSS CCC 123 S C 3 8 S C 3 9 S C 4 0 S C 4 1 S C 4 2 S C 4 3 ..... S C 7 8 S C 7 9 S C 8 0
NT7086
Input pin
.....
.....
L
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D2_DL
Shift direction Input data (D2_DL) ..... SSS CCC 123 ..... Output data (D4_DR)
L
Single-type Application mode (COM)
.....
S C 3 8
S C 3 9
S C 4 0
S C 4 1
S C 4 2
S C 4 3
.....
S C 7 8
S C 7 9
S C 8 0
H
Shift direction Output data (D2_DL) Input data (D4_DR)
D4_DR
Shift direction ..... SSS CCC 123 S C 3 8 S C 3 9 S C 4 0 S C 4 1 S C 4 2 S C 4 3 ..... S C 7 8 S C 7 9 S C 8 0
L
.....
.....
D2_DL, D3_DM
H
Dual-type Application mode (COM)
Input data 1 (D2_DL)
Input data 2 (D3_DM) Shift direction .....
Output data (D4_DR)
H
SSS CCC 123
.....
S C 3 8
S C 3 9
S C 4 0
S C 4 1
S C 4 2
S C 4 3
.....
.....
S C 7 8
S C 7 9
S C 8 0
D4_DR, D3_DM
Output data (D2_DL)
Input data 2 (D3_DM)
Input data 1 (D4_DR)
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NEOTEC SEMICONDUCTOR LTD.
NOTE 4. Usage of Data Pins COM / SEG (CS pin) Application mode (AMS pin) Data interface pin SHL D1_SID D2_DL D2 (input) D3_DM D3 (input)
NT7086
D4_DR D4(input)
4-bit parallel interface SEG mode (AMS = "Low") (CS 1-bit serial interface mode ="Low") www..com (AMS = "High") single-type application mode (AMS = "Low") COM (CS ="High" dual-type application mode ) (AMS = "High")
X D1 (input) X L H L open H
SID (input) open DL (input) DL (output) DL (input1) DL (output2)
Connect to VDD Open DM (input2) DM (input2) DR (output) DR (input) DR (output2) DR (input1)
MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Power supply voltage VDD Driver supply voltage VLCD Input voltage VIN Operating temperature Topr Storage temperature Tstg NOTE: Voltage greater than above may do damage to the circuit. Value -0.3~+7.0 0~+30 -0.3~VDD+0.3 -30~+85 -55~+150 Unit V
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NEOTEC SEMICONDUCTOR LTD. ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (1) Segment Driver Application Characteristic Operating Voltage 1 Input voltage www..com (1) Input voltage (2) Input leakage current 1 (1) Input leakage current 2 (3) On resistance(4) Supply current(5) NOTES: Symbol VDD VLCD VIH VIL VOH VOL IIL1 IIL2 RON ISTBY IDD IEE Test Condition VIN=VDD-VEE ICH=-0.4mA IOH=-0.4mA VIN=VDD to VSS VIN=VDD to VEE ION=100A fCL1=32kHZ, M=VSS VSS PIN VDD=5V fCL1=32kHZ FM=80HZ VDD=3V VDD=5V
NT7086
(VSS = 0V, Ta = - 30 ~ +85C) Min. Typ. Max. Unit 2.7 5.5 6 28 V 0.8VDD VDD 0 0.2VDD VDD-0.4 V 0.4 -10 -25 2 10 A 25 4 100 5 2 500 k A mA A
1. Applied to CL1, CL2, ELB, ERB, D1_SID - D4_DR, SHL, DISPOFFB, M, CS, AMS pin 2. ELB, ERB pin 3. V0, V12, V43, V5 pin 4. VLCD = VDD - VEE, V0 = VDD = 5V, V5= VEE = -23 V V12 = VDD-2/n(VLCD), V43 = VEE+2/n(VLCD), n = 17 (1/256 duty, 1/17 bias) 5. V0 = VDD, V12 = 1.71V(VDD = 5V) or -0.06V (VDD = 3V), V43 = -19.71 V(VDD = 5V) or -19.94V (VDD = 3V), V5 = VEE = -23V, no-load condition (1/256 duty, 1/17 bias) 4-bit parallel interface mode ISTBY : VDD = 5V, fCL2 = 5.12MHz, SHL = VSS, DISPOFFB = VDD, M = VSS, display data pattern = 0000 IDD : VDD = 3V, fCL2 = 4MHz, display data pattern = 0101 VDD = 5 V, fCL2 = 5.12MHz, display data pattern = 0101 IEE : VDD = 5V, fCL2 = 5.12MHz, display data pattern = 0101, VEE pin
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DC CHARACTERISTICS (CONTINUED) (2) Common Driver Application Characteristic Symbol Test Condition Operating VDD Voltage 1 VLCD VIN=VDD-VEE Input voltage VIH (1) VIL Input voltage VOH ICH=-0.4mA www..com (3) VOL IOH=-0.4mA Input leakage IIL1 VIN=VDD to VSS current 1 (1) Input leakage VIN=0V, VDD=5V(Pull up) IIL2 current 2 (2) Input leakage IIL3 VIN=VDD to VEE current 3 (4) ION=100A On resistance(5) RON ISTBY fCL1=32kHZ, M=VSS VSS PIN Supply VDD=5V IDD current(6) fCL1=32kHZ FM=80HZ VDD=3V IEE VDD=5V NOTES:
NT7086
(VSS = 0V, Ta = - 30 ~ +85C) Min. Typ. Max. Unit 2.7 5.5 6 28 V 0.8VDD VDD 0 0.2VDD VDD-0.4 V 0.4 -10 -50 -25 -125 2 10 A -250 25 4 100 200 120 150 k A
1. Applied to CL1, D2_DL (SHL = LOW), D4_DR (SHL = HIGH), SHL, DISPOFFB, M, CS, AMS pin 2. Pull-up input pins : CL2, D1_SID, D3_DM (AMS = HIGH), ELB (SHL = LOW), ERB (SHL = HIGH) 3. D2_DL (SHL = HIGH) , D4_DR (SHL = LOW) pin 4. V0, V12, V43, V5 pin 5. VLCD = VDD-VEE, V0 = VDD = 5V, V5 = VEE = -23V V12 = VDD-1/n(VLCD), V43 = VEE+1/n(VLCD), n = 17(1/256 duty, 1/17 bias) 6. V0 = VDD, V12 = 3.35V (VDD = 5V) or 1.47V (VDD = 3V), V43 = -21.35V (VDD = 5 V) or -21.47V (VDD = 3 V), V5 = VEE = -23 V, no-load condition (1/256 duty, 1/17 bias) single-type mode operation : AMS = VSS, SHL = VSS, DISPOFFB = VDD D1_SID = D3_DM = VDD, D4_DR = OPEN, ELB = ERB = OPEN, ISTBY : VDD = 5V, M = VSS, D2_DL = VSS IDD : fM = 80Hz, D2_DL = VDD VDD = 3 V, display data pattern = 10000000..., 01000000..., 00100000..., 00010000..., .. VDD = 5 V, display data pattern = 10000000..., 01000000..., 00100000..., 00010000..., .. IEE : fM = 80Hz, D2_DL = VDD VDD = 5V, current through VEE Pin, display data pattern = 10000000..., 01000000..., 00100000..., 00010000...
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AC CHARACTERISTICS (1) Segment Driver Application
NT7086
(VSS = 0V, Ta = - 30 ~ +85C) (1) VDD=5V10% (2) VDD=3V10% Characteristic Symbol Test condition Unit Min. Typ. Max. Min. Typ. Max. Clock cycle time tCY Duty=50% 125 250 Clock pulse width tWCK 45 95 Clock rise/ fall time tR / tF 30 Data set-up time tDS 30 65 www..com Data hold time tDH 30 65 ns Clock set-up time tCS 80 120 Clock hold time tCH 80 120 ELB output 60 125 Propagation delay time tPHL ERB output 60 125 ELB input 30 65 ELB,ERB set-up time tPSU ERB input 30 65 DISPOFFB low pulse s tWDL 1.2 1.2 width DISPOFFB clear time tCD 100 100 ns M - OUT tPD1 1.0 1.2 propagation delay time CL1 - OUT s CL=15pF tPD2 1.0 1.2 propagation delay time DISPOFFB - OUT tPD3 1.0 propagation delay time (2) Common Driver Application Characteristic Clock cycle time Clock pulse width Clock rise/ fall time Data set-up time Data hold time DISPOFFB low pulse width DISPOFFB clear time Output delay time M - OUT propagation delay time CL1 - OUT propagation delay time DISPOFFB - OUT propagation delay time (VSS = 0V, Ta = - 30 ~ +85C) (1) VDD=5V10% (2) VDD=3V10% Symbol Test condition Unit Min. Typ. Max. Min. Typ. Max. tCY Duty=50% 250 500 tWCK 45 95 ns tR / tF 50 50 tDS 30 65 TDH 30 65 tWDL tCD tDL tPD1 tPD2 tPD3 CL=15pF 1.2 100 200 1.0 1.0 1.0 1.2 100 250 1.2 1.2 1.2 s s ns
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NEOTEC SEMICONDUCTOR LTD.
(3) Segment Driver Application Timing
CL1
0.8VDD 0.2VDD
NT7086
tWCK tCS tWCK
0.2VDD
0.8VDD 0.2VDD
tCH
0.8VDD 0.2VDD
CL2
0.8VDD 0.2VDD
tWCK
0.8VDD
tR
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tF tCY
tDS
tDH
0.8VDD 0.2VDD
D1_SID - D4_DR DISPOFFB tWDL tCD
CL1 1 CL2 ELB, ERB (Output 1) ELB, ERB (Input 2) 2 3 19
0.2VDD
20 tPHL
0.8VDD
0.2VDD
tPSU
0.2VDD
M CL1
0.8VDD 0.2VDD
tPD1
0.2VDD
tPD2
0.8VDD 0.2VDD
DISPOFFB
tPD3 SC1 - SC80 (Latched data)
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(4) Common Driver Application Timing
tCY 0.8VDD 0.8VDD tDWCKH tF tDS
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NT7086
CL1
0.2VDD tR
0.2VDD tF tDH 0.8VDD 0.2VDD tDL 0.8VDD 0.2VDD
(*1) DI
0.8VDD 0.2VDD
(*1) DO
tWDL tCD
DISPOFFB
(*1) When in single-type interface mode DI=>DDL(SHL=L), D4_DR(SHL=H) DO=>D4_DR(SHL=L), D2_DL(SHL=H) When in dual-type interface mode DI=>D2_DL and D3_DM(SHL=L),D4_DR and D3_DM(SHL=H) DO=>D4_DR(SHL=L), D2_DL(SHL=H)
M CL1 DISPOFFB SC1 - SC80 (Latched data)
0.8VDD 0.2VDD tPD1 tPD2 0.2VDD 0.8VDD 0.2VDD tPD3
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NT7086
POWER DOWN FUNCTION In the case of cascade connection of segment mode drivers, NT7086 has a "power down function" In order to reduce the power consumption. SHL Enable input L H
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Enable output ELB ERB
ERB ELB
Current driver status While ERB ="Low", current driver is enabled. While ELB ="Low", current driver is enabled.
The other drivers status Disabled Disabled
* In the case of common driver application, power down function does not work.
CL1
1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1
CL2 ELB1(input1) ERB1/ELB2 (Output1/Input2) ERB2/ELB3 (Output2/Input3) ERB3/ELB4 (Output3/Input4) ELB4(Output)
NOTES: 1. SHL = High (ELB = Input, ERB = Output) 2. When in 4-bit parallel interface mode: n = 20 When in 1-bit serial interface mode: n = 80
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OPERATION TIMING DIAGRAM (1) 4-bit parallel mode interface segment driver When SHL= "Low"
19 SC5 SC6 SC7 SC8 20 1 2 3 19 SC5 SC6 SC7 SC8 20 1 2
NT7086
CL2 D1_SID
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SC1 SC77 SC73 SC69 SC2 SC78 SC74 SC70 SC3 SC79 SC75 SC71 SC4 SC80 SC76 SC72
SC1 SC77 SC73 SC2 SC78 SC74 SC3 SC79 SC75 SC4 SC80 SC76
D2_DL D3_DM D4_DR ERB(Input) ELB(Onput) CL1 SC1 - SC80
When SHL= "High"
19 20 1 2 3 19 20 1 2 SC8 SC7 SC6 SC5
CL2 D1_SID D2_DL D3_DM D4_DR ELB(Input) ERB(Onput) CL1 SC1 - SC80
SC76 SC80 SC4 SC75 SC79 SC3 SC74 SC78 SC2 SC73 SC77 SC1
SC8 SC12 SC7 SC11 SC6 SC10 SC5 SC9
SC76 SC80 SC4 SC75 SC79 SC3 SC74 SC78 SC2 SC73 SC77 SC1
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(2) 1-bit serial mode interface segment driver When SHL= "Low"
79 SC2 80 1 2 3 79 SC2 80 1 2
NT7086
CL2 D1_SID ERB(Input) www..com ELB(Onput) CL1 SC1 - SC80
SC1 SC80 SC79 SC78
SC1 SC80 SC79
When SHL= "High"
79 80 1 2 SC2 3 SC3 79 80 1 2 SC2
CL2 D1_SID ELB(Input) ERB(Onput) CL1 SC1 - SC80
SC79 SC80 SC1
SC79 SC80 SC1
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NEOTEC SEMICONDUCTOR LTD.
(3) Single type interface mode common driver When SHL= "Low"
NT7086
CL1 D2_DL
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79
80
1
2
79
80
1
2
D4_DR
COM_DATA1 COM_DATA2 COM_DATA3 COM_DATA79 COM_DATA80 Current Driver's COMMON area
When SHL= "High"
CL1 D4_DR D2_DL COM_DATA1 COM_DATA2 COM_DATA3 COM_DATA79 COM_DATA80 Current Driver's COMMON area 79 80 1 2 79 80 1 2
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(4) Dual-type interface mode common driver When SHL= "Low"
1 CL1 D2_DL D3_DM D4_DR www..com COM_DATA1 COM_DATA2 COM_DATA3 COM_DATA39 COM_DATA40 COM_DATA41 COM_DATA42 COM_DATA43 COM_DATA79 COM_DATA80 2 3 39 40 1 2 3 39 40
NT7086
When SHL= "High"
1 CL1 D2_DL D3_DM D4_DR COM_DATA1 COM_DATA2 COM_DATA3 COM_DATA39 COM_DATA40 COM_DATA41 COM_DATA42 COM_DATA43 COM_DATA79 COM_DATA80 2 3 39 40 1 2 3 39 40
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NEOTEC SEMICONDUCTOR LTD.
(5) Common / Segment driver timing (1/200 duty)
199 200 CL1 Latched data (SEG) M COM_DATA1 COM_DATA199
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NT7086
1
200
1
199
200
1
199 200
COM_DATA200 COM1
V0 V1 V4 V5 V0 V1 V4 V5 V0 V1 V4 V5
COM199
COM200
SEG_DATA1
V0 V1 V2 V3 V4 V5
SEG1
1 CL2 CL1 D1 - D4 Latched data M Enable Out
2
18
19
20
1
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NEOTEC SEMICONDUCTOR LTD. APPLICATION INFORMATION
1-bit serial interface mode (80 Ch. Segment mode) a) Lower view (SHL= L, AMS= H)
NT7086
LCD PANEL
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S1
S80
S81
S160
Sn
Sn+80
SC80 ERB
SC1 ELB
SC80 ERB
SC1 ELB
SC80 ERB
SC1 ELB
CS NT7086 AMS D2_DL SHL D1_SID D4_DR 1-bit serial data input
CS NT7086 AMS D2_DL SHL D1_SID D4_DR
CS NT7086 AMS D2_DL SHL D1_SID D4_DR
b) Upper view (SHL= H, AMS= H)
1-bit serial data input D2_DL - D1_SIDSHL D4_DR AMS NT7086 CS ELB SC1 ERB SC80 D2_DL - D1_SIDSHL D4_DR AMS NT7086 CS ELB SC1 ERB SC80 D2_DL - D1_SIDSHL D4_DR AMS NT7086 CS ELB SC1 ERB SC80
S1
S80
S81
S160
Sn
Sn+80
LCD PANEL
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4-bit parallel interface mode (80 Ch. Segment driver) a) Lower view (SHL= L, AMS = L)
NT7086
LCD PANEL
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S1
S80
S81
S160
Sn
Sn+80
SC80 ERB
SC1 ELB
SC80 ERB
SC1 ELB
SC80 ERB
SC1 ELB
CS NT7086 AMS SHL D1_SID - D4_DR 4-bit serial data input 4
CS NT7086 AMS SHL D1_SID - D4_DR 4
CS NT7086 AMS SHL D1_SID - D4_DR 4
b) Upper view (SHL= H, AMS = L)
4-bit serial data input
4 SHL AMS NT7086 CS ERB SC80
4 D1_SID - D4_DR SHL AMS NT7086 CS ERB SC80
4 D1_SID - D4_DR SHL AMS NT7086 CS ERB SC80
D1_SID - D4_DR
ELB SC1
ELB SC1
ELB SC1
S1
S80
S81
S160
Sn
Sn+80
LCD PANEL
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Single type interface mode (80 Ch. Common driver)
input data 1 D4_DR SC80 C1
NT7086
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CS AMS SHL
NT7086
D2_DL
SC1
C80
D4_DR
SC80
C81
CS AMS SHL
NT7086
LCD PANEL
SC1 C160
D2_DL
D4_DR
SC80
C161
CS AMS SHL
NT7086
D2_DL
SC1
C240
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Dual-type interface mode (40 Ch. + 40Ch. Common driver)
NT7086
input data 1 D4_DR SC80 C1
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CS AMS SHL
NT7086
D2_DL
SC1
C80
D4_DR
SC80
C81
LCD PANEL (1/2)
CS AMS SHL
NT7086
D2_DL
SC1
C160
input data 2
D3_DM D4_DR
NT7086
SC80 SC40 SC41 SC1
C161 C200 C201 C240
CS AMS SHL
D2_DL
D4_DR
SC80
C241
CS AMS SHL
NT7086
LCD PANEL (2/2)
D2_DL SC1 C320
D4_DR
SC80
C321
CS AMS SHL
NT7086
D2_DL
SC1
C400
NOTE: Using this application mode (dual-type common mode), the duty ratio can be reduced to half. In case, 1/200 duty can be used to driver the 400 common LCD panel.
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NEOTEC SEMICONDUCTOR LTD. APPLICATION CIRCUIT EXAMPLE
VDD V0 R V1 COM R V2 4 SEG V3 SEG R V4 COM R V5 COM /SEG 4 4 4 4 COM /SEG
NT7086
4
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V0-V5 D1_SID - D4_DR CL1 DISPOFFB M CL2 ELB ERB NT7086 AMS CS SHL SC1 . . . . . . . . . . . SC80 S1 S80
V0-V5 D1_SID - D4_DR CL1 DISPOFFB M CL2 ELB ERB NT7086 AMS CS SHL SC1 . . . . . . . . . . . SC80 S81 S160
V0-V5 D1_SID - D4_DR CL1 DISPOFFB M CL2 ELB ERB NT7086 AMS CS SHL SC1 . . . . . . . . . . . SC80 S161 S240
VSS VEE
M DISPOFFB CS AMS SHL V0-V5
NT7086
D4_DR SC80 SC1
C1
4
CL1 D2_DL D4_DR SC80
C80 C81
M DISPOFFB CS AMS SHL V0-V5
NT7086
240 X 240 LCD MODULE
C160 C161
SC1 CL1 D2_DL D4_DR SC80
4
M DISPOFFB CS AMS SHL V0-V5
NT7086
Controller DISPOFFB FRAME(M) COM_DATA D1-D4 CL1 CL2
SC1 CL1 D2_DL C240
4
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NEOTEC SEMICONDUCTOR LTD. PRECAUTIONS
NT7086
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows.
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When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power.
And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level V5 on /DISPOFF function. Then, disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here.
VDD VDD VSS VDD /DISPOFF VSS VSS VEE VEE
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NEOTEC SEMICONDUCTOR LTD. VERSION HISTORY:
Date 6/5/2002 7/24/2002 12/04/2002 1. 1. 1. 2. 3. Description Add the notice of substrate connection. Add the LQFP PKG description. Add precautions of power supply. Add order number ( page 2 ) Add TQFP package
NT7086
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