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SQ606 Digital CCTV Processor
DCTV-2 DCTV-2
Brief Specification
Version 1.0 - July 11th, 2005
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SERVICE & QUALITY TECHNOLOGY CO., LTD. 6F, No.150, Sec.4 Chengde Rd., Shrlin Chiu 111, Taipei, Taiwan, R.O.C. Tel: 886-2-66111177 Fax: 886-2-66106777 http://www.sq.com.tw/
Service & Quality Technology All Rights Reserved.
Digital CCTV Processor
SQ606
REVISION HISTORY
Document NO: BE0506061 REVISION # 1.0 DATE July 11 , 2005
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DESCRIPTION Formal Release
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Digital CCTV Processor
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TABLE OF CONTENTS
1. INTRODUCTION .........................................................................................................4
1.1 GENERAL DESCRIPTION...................................................................................................... 4 1.2 FEATURES ......................................................................................................................... 4 1.3 APPLICATIONS.................................................................................................................... 4 SYSTEM OVERVIEW ............................................................................................................... 5 2.1 SYSTEM BLOCK DIAGRAM................................................................................................... 5 2.2 PIN INFORMATION............................................................................................................... 6 2.2.1 PIN ASSIGNMENT .................................................................................................. 6 2.2.2 PIN LIST ............................................................................................................... 7 2.2.3 PIN DESCRIPTIONS.............................................................................................. 10 ELECTRICAL CHARACTERISTICS ...................................................................................... 14 3.1 ABSOLUTE MAXIMUM RATING............................................................................................ 14 3.2 OPERATION CONDITIONS .................................................................................................. 14 3.3 DC CHARACTERISTICS OF 3.3V I/O CELLS ....................................................................... 14 PACKAGING ........................................................................................................................... 15 4.1 LQFP 176-PIN PACKAGE.................................................................................................. 15 4.2 ORDERING INFORMATION.................................................................................................. 16
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Digital CCTV Processor
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1.
INTRODUCTION
1.1
General Description The SQ606 is a highly integrated and cost-effective Digital CCTV processor for DIY home security systems. It can not only support the standard CCIR-656 input and interface to major brands of TV decoders, but also transmit input images into JPEG format/motion JPEG format based on the embedded high-efficiency JPEG encoder engine. The SQ606 supports real-time video display on TV screen in either NTSC or PAL format. Moreover, this processor is equipped with a motion detection function. When there is any moving object
detected, the images will be auto-recorded and saved. For storage media, the processor supports up to 16MB SDRAM, flash memory, and SD card. In addition to the featured H/W and F/W functions, the C++
programming platform is able to simplify the development on firmware platform and speed up the overall development schedule. 1.2 Features Display Embedded TV encoder for both NTSC and PAL composite video Supports OSD display on TV Built-in 8-bit DAC Built-in CCIR656 CODEC Supported memory interface Supports 1Mx16, 4Mx16, 8Mx16 SDRAM and auto refresh function
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Supports external ROM (up to 1MB) Supports SD/MMC/NAND-type Flash Compression Built-in JPEG CODEC (4:2:2, 4:2:0) Software system capability C++ programming Supports UART/USB 1.1 interface Supports MSDC, Mass Storage Provides GPIOs Operation clock: 54/27 MHz (12 MHz Crystal) Operation voltage: 3.3V
1.3
Applications DVR Real-time Monitoring
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Digital CCTV Processor
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2.
SYSTEM OVERVIEW
The SQ606 contains all necessary hardware supports: a JPEG CODEC, a image scalar, a CCIR656 CODEC, a SDRAM controller, an USB 1.1 device controller, a memory card controller, a GPU, an OSD controller, and a TV encoder.
2.1
System Block Diagram
S86 CPU
Flash ROM / SDRAM
SDRAM Controller
GPU
CCIR656 Input
CCIR656 Decoder
OSD Controller
Image Scalar
CCIR656 Encoder
CCIR656 Output
JPEC CODEC
TV Encoder
NTSC/PAL TV
PC
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USB 1.1 Device Controller
Memory Card Controller
SD / MMC / NAND-type Flash
GPIO
- Serial Port - Interrupt - Trigger
FIGURE 2-1: SQ606 SYSTEM BLOCK DIAGRAM
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2.2 2.2.1
Pin Information Pin Assignment
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FIGURE 2-2: PIN ASSIGNMENT DIAGRAM
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2.2.2
Pin List
TABLE 2-1: PIN LIST
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 www..com 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
NAME SD_WR SD_UDQM SD_LDQM SD_CLK VCCK NC NC WR RD UCS SPI NC NC NC GND GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 VCCK GPIO9 GPIO10 SD_CS FLASH_CD FLASH_PC GPIO14 LED GPIO16 GPIO17 GPIO18 GPIO19 GND
PIN NO 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
NAME X1 X2 BYPASSPLL PLLVDD_40 PLLGND_40 PLLVDD_45 PLLGND_45 VDDA IOUT VSSA COMP BIASOUT FSA REFOUT REFIN VCCK VSS NC USB_VDD DP DN USB_GND VDD33 VIDEO_CLKOUT NC VIDEO_HSYNC VIDEO_VSYNC SCAN_KEY_S0 SCAN_KEY_S1 SCAN_KEY_S2 SCAN_KEY_S3 SCAN_KEY_L0 SCAN_KEY_L1 SCAN_KEY_L2 SCAN_KEY_L3
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PIN NO 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 www..com 94 95 96 97 98 99 100 101 102 103 104 105
NAME NC GND GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 RESERVED VIDEO_HCLK VIDEO_D7 VIDEO_D6 VIDEO_D5 VIDEO_D4 VIDEO_D3 VIDEO_D2 VIDEO_D1 VIDEO_D0 VCCK RST D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
PIN NO 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
NAME D15 GND ADDR0 ADDR1 ADDR2 ADDR3 VCCK ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 GND RESERVE USB_IN SCL SDA VCCK FLASH_CLE/SD_CLK FLASH_RE_N/SD_DI FLASH_WR_N/SD_DO FLASH_ALE/SD_CS0 FLASH_WP_N/SD_CS1 NC
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PIN NO 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158
NAME RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE GND NC NC RESERVE RESERVE FLASH_R_B NC VCCK FLASH_D0 FLASH_D1 FLASH1_CE_N FLASH2_CE_N
PIN NO 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
NAME FLASH_D2 FLASH_D3 PIO24 TX1 RX1 PIO27 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 GND SD_ADDR10 SD_BA0 SD_BA1 SD_CKE NC SD_RAS SD_CAS
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2.2.3
Pin Descriptions
TABLE 2-2: POWER SUPPLY PINS
PIN NO 5, 23, 51, 89, 112, 134, 154 15, 35, 72, 107, 129, 147, 169 39 40 41 42 43 45 52 54 57 58
NAME VCCK
I/O PWR
DESCRIPTION Power; digital VDD = 3.3V
GND
PWR
Ground
PLLVDD_40 PLLGND_40 PLLVDD_45 PLLGND_45 VDDA VSSA VSS USB_VDD USB_GND VDD33
PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR
Power for PLL X 4, 3.3V Ground for PLL X 4 Power for PLL X 4.5, 3.3V Ground for PLL X 4.5 DAC Power; analog VDD = 3.3V DAC Ground; analog ground DAC Ground; digital ground USB Power; analog VDD = 3.3V USB Ground; analog ground Power; digital VDD = 3.3V TABLE 2-3: SYSTEM PINS
PIN NO 30 36 37 www..com 38 90
NAME LED X1 X2 BYPASSPLL RST
I/O O I I/O I I
DESCRIPTION System indicating LED 12MHz Crystal In 12MHz Crystal Out Bypass PLL function System reset, active low
TABLE 2-4: ADDRESS AND DATA PINS PIN NO 8 9 10 91106 108111 NAME WR RD UCS D[0:15] ADDR[0:3] I/O O O O I/O I/O DESCRIPTION Flash ROM write Flash ROM read Flash ROM chip select Data Bus[0:15] Address Bus[0:3] ADDR0: pull low for 16-bit ROM pull high for 8-bit ROM ADDR1: pull low for operating at 54MHz frequency pull high for operating at 48MHz frequency ADDR2: pull low for watchdog reset to all system pull high for watchdog reset to CPU only
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PIN NO 113124 125128
NAME ADDR[4:15] ADDR[16:19]
I/O O I/O
DESCRIPTION Address Bus[4:15] Address Bus[16:19] ADDR16~ADDR19: pull low for normal operation
TABLE 2-5: SDRAM INTERFACE CONTROL PINS PIN NO 1 2 3 4 26 NAME SD_WR SD_UDQM SD_LDQM SD_CLK SD_CS I/O O O O O O DESCRIPTION SDRAM Write Enable SDRAM Upper Byte Data I/O Mask SDRAM Lower Byte Data I/O Mask 54MHz Clock Output SDRAM Chip Select When SD_CS is low, the command decoder is enabled; when it is high, the command decoder is disabled. As long as the command decoder is disabled, all new commands will be ignored while the previous operations continue. 170 SD_ADDR10 O SDRAM Address[10] Only SDRAM Address 10 is used. 171172 SD_BA[0:1] O SDRAM Back Address[0:1] These two signals are used to determine which back is to be activated. 173 SD_CKE O SDRAM Clock Enable When SD_CKE is high, the SD CLK signal is activated; when it is low, the SD CLK signal is deactivated. Thus it initiates one of the following three modes: Power Down Mode, Suspend Mode, and Self Refresh Mode. 175 www..com SD_RAS O SDRAM Row Address Select This signal is sampled at the positive clock rising edge, and is used to select the command to be executed. 176 SD_CAS O SDRAM Column Address Select
TABLE 2-6: SD/MMC CARD INTERFACE PINS PIN NO 135 136 137 NAME I/O DESCRIPTION SD Card Clock SD Card I/F Data In SD Card I/F Data Out
FLASH_CLE/SD_CLK O FLASH_RE_N/SD_DI I FLASH_WR_N/ SD_DO O
138
FLASH_ALE/ SD_CS0
O
SD Card I/F Output Enable[0]
139
FLASH_WP_N/ SD_CS1
O
SD Card I/F Output Enable[1]
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TABLE 2-7: NAND-TYPE FLASH INTERFACE PINS PIN NO 27 28 152 155156 157 158 159160 165168 NAME FLASH_CD FLASH_PC FLASH_R_B FLASH_D[0:1] FLASH1_CE_N FLASH2_CE_N FLASH_D[2:3] FLASH_D[4:7] I/O I O I I/O O O I/O I/O DESCRIPTION NAND-type Flash Memory Detection NAND-type Flash Power Control NAND-type Flash Ready/Busy NAND-type Flash Data Bus[0:1] NAND-type Flash 1 Chip Enable NAND-type Flash 2 Chip Enable NAND-type Flash Data Bus[2:3] NAND-type Flash Data Bus[4:7]
TABLE 2-8: USB (MSDC) CONTROLLER PINS PIN NO 55 56 131 NAME DP DN USB_IN I/O I/O I/O I DESCRIPTION USB Data + Differential Bus; Analog USB Data - Differential Bus; Analog USB Plug-in detect TABLE 2-9: VIDEO INPUT INTERFACE PIN NO 59 61 62 80 8188 www..com NAME VIDEO_CLKOUT VIDEO_HSYNC VIDEO_VSYNC VIDEO_HCLK VIDEO_D[0:7] I/O O I I I I DESCRIPTION CLKOUT, 27MHz (CCIR-601 only) Horizontal synchronized signal (CCIR-601 only) Vertical synchronized signal (CCIR-601 only) Sampling clock, 27MHz (CCIR-656/CCIR-601) Decoder Data Input Bit[0:7] (CCIR-656/CCIR-601)
TABLE 2-10: GENERAL PURPOSE I/O PORT PINS PIN NO 1622 2425 29 3134 7378 161 164 NAME GPIO[2:8] GPIO[9:10] GPIO14 GPIO[16:19] GPIO[33:38] PIO24 PIO27 I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION General Purpose I/O[2:8] General Purpose I/O[9:10] General Purpose I/O[14] General Purpose I/O[16:19] General Purpose I/O[33:38] S86 PIO[24] S86 PIO[27]
TABLE 2-11: UART INTERFACE PINS PIN NO 161 162 NAME TX1 RX1 I/O O I DESCRIPTION UART1 data transmit pin UART1 data receive pin
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TABLE 2-12: SERIAL INTERFACE PINS PIN NO 132 133 11 NAME SCL SDA SPI I/O I I/O O DESCRIPTION Serial Interface Clock Serial Interface Data Serial Interface Enable TABLE 2-13: KEY SCAN PINS PIN NO 6366 6770 NAME SCAN_KEY_S[0:3] SCAN_KEY_L[0:3] I/O O I DESCRIPTION Key Scans Sending[0:3] Key Scans Latching[0:3] TABLE 2-14: TV DAC CONTROL PINS PIN NO 44 46 47 48 49 50 NAME IOUT COMP BIASOUT FSA REFOUT REFIN I/O O P P P P P DESCRIPTION TV analog signal out Compensation pin, connect 104P capacity to VDDA Current Bias, connect 104P capacity to VDDA Adjust the bias current Reference voltage Reference voltage
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3.
ELECTRICAL CHARACTERISTICS
3.1
Absolute Maximum Rating
TABLE 3-1: ABSOLUTE MAXIMUM RATING
SYMBOL VCC VIN3 VOUT3 TSTG
PARAMETER Power Supply Input Voltage of 3.3V I/O Output Voltage of 3.3V I/O Storage Temperature
MIN -0.3 -0.3 -0.3 -40
MAX 3.9 VCC+0.3 VCC+0.3 150
UNIT V V V
3.2
Operation Conditions
TABLE 3-2: OPERATION CONDITIONS
SYMBOL VCC VIN3 TJ
PARAMETER Power Supply Input Voltage of 3.3V with 5V Tolerance I/O Junction Operating Temperature: Commercial
MIN 3.0 0 0
TYP 3.3 3.3 25
MAX 3.6 5.25 115
UNIT V V
3.3
DC Characteristics of 3.3V I/O Cells
TABLE 3-3: DC CHARACTERISTICS OF 3.3V I/O CELLS
SYMBOL VCC VIL www..com VIH VTVT+ VOL VOH
PARAMETER Power Supply Input Low Voltage Input High Voltage Schmitt Trigger Negative Going Schmitt Trigger Positive Going Threshold Output Low Voltage Output High Voltage
CONDITIONS CMOS CMOS CMOS CMOS IOl = 4 mA IOH = -4 mA
MIN 3.0 0.7*VCC 0.9 2.4
TYP 3.3 1.2 2.1 -
MAX 3.6 0.3*VCC 2.5 0.4 -
UNIT V V V V V V V
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4.
PACKAGING
4.1
LQFP 176-pin Package Body size: 20 x 20 x 1.4mm
D
0.20 H A-B D
Symbol A A1 A2 b b1 c c1 D D1 E E1
e
132 133
89 88
A
B
SQ606
Dimension (mm) MIN NOM MAX 1.60 0.05 0.15 1.35 1.40 1.45 0.13 0.18 0.23 0.13 0.16 0.19 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.40 BSC 0.45 0.60 0.75 1.00 REF 0.08 0.08 0.20 0.075 0 3.5 7 0 11 11 0.20 12 12 13 13 -
Dimension (mil) MIN NOM MAX 63 2 6 53 55 57 5 7 9 5 6 7 4 8 4 6 866 BSC 787 BSC 866 BSC 787 BSC 16 BSC 18 3 3 0 0 11 11 8 24 39 REF 3.5 12 12 30 8 3 7 13 13 -
176 1
0.20 C A-B D
45 44
e b
L L1 R1 R2 Y 1 2 3 s
0.07M C A-B D
'X'
D1
E1
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D
S
E
2 1 R0.15
0.25mm A2 A
Base Metal b
A
b1
A1
A
S
3
Width Plating Section A-A
L L1
Detailed 'X' (20/1)
FIGURE 4-1: LQFP 176-PIN PACKAGE DIAGRAM
NOTES: 1. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm. Per side D1 and E1 are maximum plastic body size dimension including mold mismatch. 2. Dimension b does not include DAMBAR protrusion. Allowable DAMBAR protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Subject to Change Without Notice. PAGE 15 Version 1.0 - July 11 , 2005
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C1
C
Digital CCTV Processor
SQ606
4.2
Ordering Information
TABLE 4-1: ORDERING INFORMATION TABLE
TYPE NO SQ606
PACKAGE LQFP176
DESCRIPTION Low-profile Quad Flat Package, 176-pin
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