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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Document Title 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History
No.
0.0 0.1 0.2 0.3 Initial Draft Renewal Product Group Make a decision of PKG information Append 1.8V Operation Product to Data sheet 1) Add Errata tWC Specification 0.4 Relaxed value 50 60 tWH 15 20 tWP 25 40 tRC 50 60 tREH 15 20 tRP 30 40 tREA@ID Read 35 45 Mar.28.2004 Preliminary
History
Draft Date
Sep.17.2003 Oct.07.2003 Nov.08.2003 Dec.01.2003
Remark
Preliminary Preliminary Preliminary Preliminary
2) Modify the description of Device Operations - /CE Don't Care Enabled(Disabled) -> Sequential Row Read Disabled (Enabled) (Page22) 3) Add the description of System Interface Using CE don't care (Page37) 1) Delete Errata 2) Change Characteristics (3V Product) 0.5 tCRY Before After 60 + tr 70 + tr tREA@ID Read 35 45 Jun. 01. 2004 Preliminary
3) Delete Cache Program 0.6 1) Change TSOP1, WSOP1, FBGA package dimension 2) Edit TSOP1, WSOP1 package figures 3) Change FBGA package figure Oct. 20. 2004
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.6 / Oct. 2004 1
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
FAST BLOCK ERASE
- Block erase time: 2ms (Typ)
NAND INTERFACE
- x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities
STATUS REGISTER ELECTRONIC SIGNATURE
SUPPLY VOLTAGE
Sequential Row Read OPTION
: HY27USXX121M
- 3.3V device: VCC = 2.7 to 3.6V
- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX121M
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support - Automatic Memory Download
Memory Cell Array
- 528Mbit = 528 Bytes x 32 Pages x 4,096 Blocks
SERIAL NUMBER OPTION HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
PAGE SIZE
- x8 device : (512 + 16 spare) Bytes : HY27(U/S)S08121M - x16 device: (256 + 8 spare) Words : HY27(U/S)S16121M
DATA INTEGRITY
- 100,000 Program/Erase cycles - 10 years Data Retention
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes - x16 device: (8K + 256 spare) Words
PACKAGE
- HY27US(08/16)121M-T(P) : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - HY27US(08/16)121M-T (Lead) - HY27US(08/16)121M-TP (Lead Free) - HY27US08121M-V(P) : 48-Pin WSOP1 (12 x 17 x 0.7 mm) - HY27US08121M-V (Lead) - HY27US08121M-VP (Lead Free) - HY27(U/S)S(08/16)121M-F(P) : 63-Ball FBGA (8.5 x 15 x 1.2 mm) - HY27US(08/16)121M-F (Lead) - HY27US(08/16)121M-FP (Lead Free) - HY27SS(08/16)121M-F (Lead) - HY27SS(08/16)121M-FP (Lead Free)
PAGE READ / PROGRAM
- Random access: 12us (max) - Sequential access: 50ns (min) - Page program time: 200us (typ)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.6 / Oct. 2004 2
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
DESCRIPTION
The HYNIX HY27(U/S)SXX121M series is a family of non-volatile Flash memories that use NAND cell technology. The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hardware protection against program and erase operations. The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (PER) Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
The devices are available in the following packages: - 48-TSOP1 (12 x 20 x 1.2 mm) - 48-WSOP1 (12 x 17 x 0.7 mm) - 63-FBGA (8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch) Three options are available for the NAND Flash family: - Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from page 0. - Chip Enable Dont Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation. - A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest HYNIX Sales office. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to '1'.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Vcc
I/O8-15
I/O8-I/O15, x16
Data Input/Outputs for x16 Device Data Input/Output, Address Inputs, or Command Inputs for x8 and x16 device Address Latch Enable Command Latch Enable Chip Enable Read Enable Read/Busy (open-drain output) Write Enable Write Protect Supply Voltage Ground Not Connected Internally Do Not Use
I/O0-7 ALE
CE RE WE ALE CLE WP I/O0-I/O7, x8/x16
CLE CE
NAND Flash
RB
RE RB WE WP VCC
Vss
VSS NC DU
Figure 1: Logic Diagram
Table 1: Signal Name
Address Register/Counter
ALE CLE WE CE WP RE Command Register Command Interface Logic P/E/R Controller, High Voltage Generator
X Decoder
NAND Flash Memory Array
Page Buffer Cache Register Y Decoder
I/O Buffers & Latches
RB
I/O0-I/O7, x8/x16 I/O8-I/O15, x16
Figure 2. LOGIC BLOCK DIAGRAM
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
NC NC NC NC NC NC RB RE CE NC NC Vcc Vss NC NC CLE ALE WE WP NC NC NC NC NC
1
48
12 13
NAND Flash (x8)
37 36
24
25
NC NC NC NC I/O 7 I/O 6 I/O 5 I/O 4 NC NC NC Vcc Vss NC NC NC I/O 3 I/O 2 I/O 1 I/O 0 NC NC NC NC
NC NC NC NC NC NC RB RE CE NC NC Vcc Vss NC NC CLE ALE WE WP NC NC NC NC NC
1
48
12 13
NAND Flash (x16)
37 36
24
25
Vss I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 NC NC Vcc NC NC NC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 Vss
Figure 3. 48-TSOP1 Contactions, x8 and x16 Device
NC NC DU NC NC NC RB RE CE DU NC Vcc Vss NC DU CLE ALE WE WP NC NC DU NC NC
1
48
NAND Flash WSOP1 37 12 36 13 (x8)
24
25
NC NC DU NC I/O7 I/O6 I/O5 I/O4 NC DU NC Vcc Vss NC DU NC I/O3 I/O2 I/O1 I/O0 NC DU NC NC
Figure 4. 48-WSOP1 Contactions, x8 Device
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1 2 3 4 5 6 7 8 9 10
A B C D E F G H J K L M
NC NC
NC
NC NC WP NC NC NC NC NC NC VSS ALE RE NC NC NC I/O0 I/O1 I/O2 VSS CLE NC NC NC NC NC I/O3 CE NC NC NC NC NC VCC I/O4 WE NC NC NC NC NC I/O5 I/O6 RB NC NC NC NC VCC I/O7 VSS NC NC
NC NC
NC NC
NC NC
NC NC
Figure 5. 63-FBGA Contactions, x8 Device (Top view through package)
1 2 3 4 5 6 7 8 9 10
A B C D E F G H J K L M
NC NC
NC
NC NC
WP NC NC NC NC I/O8 I/O0 VSS ALE RE NC NC NC
I/O1
NC NC
VSS CLE NC NC NC
I/O10
CE NC NC NC I/O5
I/O12
WE NC NC NC I/O7
I/O14
RB NC NC NC NC VCC
I/O15
I/O9 I/O2
I/O3
I/O11
VCC
I/O4
I/O6
I/O13
VSS
NC NC
NC NC
NC NC
NC NC
Figure 6. 63-FBGA Contactions, x16 Device (Top view through package)
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
MEMORY ARRAY ORGANIZATION The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error Correction Codes, software flags or Bad Block identification. In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area and an 8 Word spare area. Refer to Figure 8, Memory Array Organization. Bad Blocks The NAND Flash 528 Byte/ 264 Word Page devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. The Bad Block Information is written prior to shipping (refer to Bad Block Management section for more details). The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that could develop later on. These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes.
x8 DEVICES Block= 32 Pages Page= 528 Bytes (512+16)
x16 DEVICES Block= 32 Pages Page= 264 Words (256+8)
1st half Page (256 bytes) Block Page
2nd half Page (256 bytes) Block Page 8 bits
Main Area
e ar Sp
ea Ar
16 bits 256 Words 8 Words
512 Bytes
16 Bytes
Page Buffer, 528 Bytes 512 Bytes 16 Bytes 8 bits
Page Buffer, 264 Words 256 Words 8 Words 16 bits
Figure 7. Memory Array Organization
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Inputs/Outputs (I/O0-I/O7) Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read opertion or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 can be left floating when the device is deselected or the outputs are disabled. Inputs/Outputs (I/O8-I/O15) Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data during a Read operation or input data during a Write operation. Command and Address Inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 can be left floating when the device is deselected or the outputs are disabled. Address Latch Enable (ALE) The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When ALE is high, the inputs are latched on the rising edge of Write Enable. Command Latch Enable (CLE) The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CLE is high, the inputs are latched on the rising edge of Write Enable. Chip Enable (CE) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, VIL, the device is selected. If Chip Enable goes high, VIH, while the device is busy, the device remains selected and does not go into standby mode. When the device is executing a Sequential Row Read operation, Chip Enable must be held low (from the second page read onwards) during the time that the device is busy (tBLBH1). If Chip Enable goes high during tBLBH1 the operation is aborted. Read Enable (RE) The Read Enable, RE, controls the sequential data output during Read operations. Data is valid tRLQV after the falling edge of RE. The falling edge of RE also increments the internal column address counter by one. Write Enable (WE). The Write Enable input, WE, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 1us (min) is required before the Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time. Write Protect (WP). The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, VIL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Ready/Busy (RB) The Ready/Busy output, RB, is an open-drain output that can be used to identify if the Program/ Erase/ Read (PER) Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pullup resistor. A Low will then indicate that one, or more, of the memories is busy. Refer to the Ready/Busy Signal Electrical Characteristics section for details on how to calculate the value of the pull-up resistor. VCC Supply Voltage VCC provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read,program and erase). An internal voltage detector disables all functions whenever VCC is below 2.5V (for 3V devices) or 1.5V (for 1.8V devices) to protect the device from any involuntary program/erase during power-transitions. Each device in a system should have VCC decoupled with a 0.1uF capacitor. The PCB track widths should be sufficient to carry the required program and erase currents VSS Ground Ground, VSS, is the reference for the power supply. It must be connected to the system ground. BUS OPERATIONS There are six standard bus operations that control the memory. Each of these is described in this section, see Tables 2, Bus Operations, for a summary. Command Input Command Input bus operations are used to give commands to the memory. Command are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure 21 and Table 14 for details of the timings requirements. Address Input Address Input bus operations are used to input the memory address. Four bus cycles are required to input the addresses for the 512Mb devices (refer to Tables 3 and 4, Address Insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure 22 and Table 14 for details of the timings requirements. Data Input Data Input bus operations are used to input the data to be programmed. Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 23 and Tables 14 and 15 for details of the timings requirements.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signature and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure 24 and Table 15 for details of the timings requirements. Write Protect Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. Standby When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power consumption is reduced.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 2. Bus Operation
BUS Operation Command Input Address Input Data Input Data Output Write Protect Standby CE VIL VIL VIL VIL X VIH ALE VIL VIH VIL VIL X X CLE VIH VIL VIL VIL X X RE VIH VIH VIH Falling X X WE Rising Rising Rising VIH X X WP X(2) X X X VIL X I/O0 - I/O7 Command Address Data Input Data Output X X I/O8 - I/O15(1) X X Data Input Data Output X X
Note : (1) Only for x16 devices. (2) WP must be VIH when issuing a program or erase command.
Table 3: Address Insertion, x8 Devices
Bus Cycle 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle I/O7 A7 A16 A24 VIL I/O6 A6 A15 A23 VIL I/O5 A5 A14 A22 VIL I/O4 A4 A13 A21 VIL I/O3 A3 A12 A20 VIL I/O2 A2 A11 A19 VIL I/O1 A1 A10 A18 VIL I/O0 A0 A9 A17 A25
Note: (1). A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section. (2). Any address input cycles will be ignored with tALS > 0ns.
Table4: Address Insertion, x16 Devices
Bus Cycle 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle I/O8-I/ O15 X X X VIL I/O7 A7 A16 A24 VIL I/O6 A6 A15 A23 VIL I/O5 A5 A14 A22 VIL I/O4 A4 A13 A21 VIL I/O3 A3 A12 A20 VIL I/O2 A2 A11 A19 VIL I/O1 A1 A10 A18 VIL I/O0 A0 A9 A17 A25
Note: (1). A8 is Don't Care in x16 devices. (2). Any address input cycles will be ignored with tALS > 0ns. (3). A1 is the Least Significant Address for x16 devices. (4). The 01h Command is not used in x16 devices.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
COMMAND SET All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/ O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security. The Commands are summarized in Table 5, Commands. Table 5: Command Set
FUNCTION READ A READ B READ C READ ELECTRINIC SIGNATURE READ STATUS REGISTER PAGE PROGRAM COPY BACK PROGRAM BLOCK ERASE RESET 1st CYCLE 00h 01h 50h 90h 70h 80h 00h 60h FFh 2nd CYCLE 10h 8Ah D0h 3rd CYCLE 10h Yes Yes Command accepted during busy
Note: (1). Any undefined command sequence will be ignored by the device. (2). Bus Write Operation(1st, 2nd and 3rd Cycle) : The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.
DEVICE OPERATIONS
Pointer Operations As the NAND Flash memories contain two different areas for x16 devices and three different areas for x8 devices (see Figure 8) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they select the most significant column address). The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device. - In x16 devices the Read A command (00h) sets the pointer to Area A (the whole of the main area) that is Words 0 to 255. - In x8 devices the Read A command (00h) sets the pointer to Area A (the first half of the main area) that is Bytes 0 to 255, and the Read B command (01h) sets the pointer to Area B (the second half of the main area) that is Bytes 256 to 511. In both the x8 and x16 devices the Read C command (50h), acts as a pointer to Area C (the spare memory area) that is Bytes 512 to 527 or Words 256 to 263. Once the Read A and Read C commands have been issued the pointer remains in the respective areas until another
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
pointer code is issued. However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A. The pointer operations can also be used before a program operation, that is the appropriate code (00h, 01h or 50h) can be issued before the program command 80h is issued (see Figure 9).
x8 Devices
Area A (00h) Area B (01h) Area C (50h)
x16 Devices
Area A (00h) Area C (50h)
Bytes 0-255
Bytes 256-511
Bytes 512-527
Words 0-256
Words 256-263
A
B
C
Page Buffer
A
C
Page Buffer
Pointer (00h, 01h, 50h)
Pointer (00h, 50h)
Figure 8. Pointer Operation
AREA A
I/O
00h
80h
Address Inputs
Data Input
10h
00h
80h
Address Inputs
Data Input
10h
AREA A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.
AREA B
I/O
01h
80h
Address Inputs
Data Input
10h
01h
80h
Address Inputs
Data Input
10h
AREA B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.
AREA C
I/O
50h
80h
Address Inputs
Data Input
10h
50h
80h
Address Inputs
Data Input
10h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
Figure 9. Pointer Operations for Programming
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section. The device defaults to Read A mode after powerup or a Reset operation. Devices, where page0 is read automatically at power-up, are available on request. When reading the spare area addresses: - A0 to A3 (x8 devices) - A0 to A2 (x16 devices) are used to set the start address of the spare area while addresses: - A4 to A7 (x8 devices) - A3 to A7 (x16 devices) are ignored. Once the Read A or Read C commands have been issued they do not need to be reissued for subsequent read operations as the pointer remains in the respective area. However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A and so another Read B command is required to start another read operation in Area B. Once a read command is issued three types of operations are available: Random Read, Page Read and Sequential Row Read. Random Read Each time the command is issued the first read is Random Read. Page Read After the Random Read access the page data is transferred to the Page Buffer in a time of tWHBH (refer to Table 15 for value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. Sequential Row Read After the data in last column of the page is output, if the Read Enable signal is pulsed and Chip Enable remains Low then the next page is automatically loaded into the Page Buffer and the read operation continues. A Sequential Row Read operation can only be used to read within a block. If the block changes a new read command must be issued. Refer to Figures 12 and 13 for details of Sequential Row Read operations. To terminate a Sequential Row Read operation set the Chip Enable signal to High for more than tEHEL. Sequential Row Read is not available when the Sequential row read option is disabled.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE CE WE ALE RE RB
tBLBH1 (read)
I/O
00h/ 01h/ 50h Command Code
Address Input
Busy
Data Output (sequentially)
Figure 10. Read (A, B, C) Operation
Note: 1. If tELWL is less than 10ns, tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns.
Read A Command, x8 Devices
Area A (1st half Page) A9-A25(1) Area B (2nd half Page) Area C (Spare) A9-A25(1)
Read A Command, x16 Devices
Area A (main area) Area C (50h)
A0-A7
A0-A7 Read C Command, x8/x16 Devices Area A A9-A25(1) A0-A3 (x8) A0-A2 (x16) A4-A7 (x8), A3-A7 (x16) are don't care Area A/B Area C (Spare)
Read B Command, x8 Devices Area A (1st half Page) A9-A25(1) Area B (2nd half Page) Area C (Spare)
A0-A7
Figure 11. Read Block Diagrams
Note: 1. Highest address depends on device density.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
RB
tBLBH1 (Read Busy time) Busy
tBLBH1 Busy 1st Page Output
tBLBH1 Busy 2nd Page Output Nth Page Output
I/O
00h/ 01h/50h Command Code
Address Inputs
Figure 12. Sequential Row Read Operation
Read A Command, x8 Devices Area A (1st half Page)
Block
Read A Command, x16 Devices Area A (main area)
1st Page 2nd Page Nth Page
Area B Area C (2nd half Page) (Spare)
Block
Area C (Spare)
1st Page 2nd Page Nth Page
Read B Command, x8 Devices Area A (1st half Page)
Block
Read C Command, x8/x16 Devices Area A Area A/B Area C (Spare)
1st Page 2nd Page N Page
th
Area B
Area C
(2nd half Page) (Spare)
Block
1st Page 2nd Page Nth Page
Figure 13. Sequential Row Read Block Diagrams
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Page Program The Page Program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. The max number of consecutive partial page program operations allowed in the same page is one in the main area and two in the spare area. After exceeding this a Block Erase command must be issued before any further program operations can take place in that page. Before starting a Page Program operation a Pointer operation can be performed to point to the area to be programmed. Refer to the Pointer Operations section and Figure 9 for details. Each Page Program operation consists of five steps (see Figure 14): 1. one bus cycle is required to setup the Page Program command 2. four bus cycles are then required to input the program address (refer to Table 3) 3. the data is then input (up to 528 Bytes/ 264 Words) and loaded into the Page Buffer 4. one bus cycle is required to issue the confirm command to start the Program/ Erase/Read Controller. 5. The Program/ Erase/Read Controller then programs the data into the array. Once the program operation has started the Status Register can be read using the Read Status Register command. During program operations the Status Register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the Program/ Erase/Read Controller bit SR6 is set to '1' and the Ready/ Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the Command Interface.
RB
tBLBH2 (Program Busy time)
Busy
I/O
80h
Address Inputs Page Program Setup Code
Data Input
10h Confirm Code
70h
SR0
Read Status Register
Figure 14. Page Program Operation
Note: Before starting a Page Program operation a Pointer operation can be performed. Refer to Pointer section for details.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. If the Copy Back Program operation fails an error is signalled in the Status Register. However as the standard external ECC cannot be used with the Copy Back operation bit error due to charge loss cannot be detected. For this reason it is recommended to limit the number of Copy Back operations on the same data and/or to improve the performance of the ECC. The Copy Back Program operation requires three steps: - 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). This operation copies all 264 Words/ 528 Bytes from the page into the Page Buffer. - 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 4 bus cycles to input the target page address. A25 must be the same for the Source and Target Pages. - 3. Then the confirm command is issued to start the P/E/R Controller. After a Copy Back Program operation, a partial page program is not allowed in the target page until the block has been erased. See Figure 15 for an example of the Copy Back operation.
RB
tBLBH1 (Read Busy time)
tBLBH2 (Program Busy time)
Busy I/O 00h Read Code Source Address Inputs 8Ah Copy Back Code Target Address Inputs 10h 70h SR0
Read Status Register
Figure 15. Copy Back Operation Block Erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to '1'. All previous data in the block is lost. An erase operation consists of three steps (refer to Figure 17): 1. One bus cycle is required to setup the Block Erase command. 2. Only three bus cycles for 512Mb devices are required to input the block address. The first cycle (A0 to A7) is not required as only addresses A14 to A25 (highest address depends on device density) are valid, A9 to A13 are ignored. In the last address cycle I/O0 to I/O7 must be set to VIL. 3. One bus cycle is required to issue the confirm command to start the P/E/R Controller.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Once the erase operation has completed the Status Register can be checked for errors.
tBLBH3 (Erase Busy time) RB Busy I/O 60h Block Erase Setup Code
Block Address Inputs
D0h Confirm Code
70h
SR0
Read Status Register
Figure 17. Block Erase Operation Reset The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued during any operation, the operation will be aborted. If it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. If the device has already been reset then the new Reset command will not be accepted. The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value of tBLBH4 depends on the operation that the device was performing when the command was issued, refer to Table 15 for the values. Read Status Register The device contains a Status Register which provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register information is present on the output data bus (I/O0- I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the Status Register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore if a Read Status Register command is issued during a Random Read cycle a new read command must be issued to continue with a Page Read or Sequential Row Read operation. The Status Register bits are summarized in Table 6, Status Register Bits. Refer to Table 6 in conjunction with the following text descriptions. Write Protection Bit (SR7) The Write Protection bit can be used to identify if the device is protected or not. If the Write Protection bit is set to '1' the device is not protected and program or erase operations are allowed. If the Write Protection bit is set to '0' the device is protected and program or erase operations are not allowed.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
P/E/R Controller Status Register bit SR6 has two different functions depending on the current operation. During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to '0', the P/E/R Controller is active (device is busy); when the bit is set to '1', the P/E/R Controller is inactive (device is ready). P/E/R Controller Bit (SR5) The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to '0', the P/E/R Controller is active (device is busy); when the bit is set to '1', the P/E/R Controller is inactive (device is ready). Error Bit (SR0) The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to '1' when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to '0' the operation has completed successfully. SR4, SR3 and SR2 are Reserved
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 6: Status Register Bit
Bit SR7 NAME Write Protection Program/Erase/Read Controller Program/ Erase/ Read Controller Reserved Generic Error Logic Level Definition Not Protected Protected P/E/R C Inactive, device ready P/E/R C active, device busy P/E/R C inactive, device ready P/E/R C active, device busy
'1' '0' '1' '0' '1' '0'
Don't Care
SR6
SR5 SR4, SR3, SR2 SR0
'1' '0'
Error - Operation failed No Error - Operation successful
Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these codes two steps are required: 1. first use one Bus Write cycle to issue the Read Electronic Signature command (90h) 2. then subsequent Bus Read operations will read the Manufacturer Code and the Device Code until another command is issued. Refer to Table, Read Electronic Signature for information on the addresses.
Part Number HY27US08121M HY27SS08121M HY27US16121M HY27SS16121M Manufacture Code ADh ADh 00ADh 00ADh Device Code 76h 36h 0056h 0046h Bus Width x8 x8 x16 x16
Automatic Page 0 Read at Power-Up Automatic Page 0 Read at Power-Up is an option available on all devices belonging to the NAND Flash 528 Byte/264 Word Page family. It allows the microcontroller to directly download boot code from page 0, without requiring any command or address input sequence. The Automatic Page 0 Read option is particularly suited for applications that boot from the NAND. Devices delivered with Automatic Page 0 Read at Power-Up can have the Sequential Row Read option either enabled ordisabled. Automatic Page 0 Read Description. At powerup, once the supply voltage has reached the threshold level, VCCth, all digital outputs revert to their reset state and the internal NAND device functions (reading, writing, erasing) are enabled. The device then automatically switches to read mode where, as in any read operation, the device is busy for a time tBLBH1 during the data is transferred to the Page Buffer. Once the data transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially on the I/O bus by pulsing the Read Enable, RE#, signal. Figures 18 and 19 show the power-up waveforms for devices featuring the Automatic Page 0 Read option.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Sequential Row Read Disabled If the device is delivered with Sequential row read disabled and Automatic Read Page 0 at Power-up, only the first page (Page 0) will be automatically read after the power-on sequence. Refer to Figure 18. Sequential Row Read Enabled If the device is delivered with the Automatic Page 0 Read option only (Sequential Row Read Enabled), the device will automatically enter Sequential Row Read mode after the power-up sequence, and start reading Page 0, Page 1, etc., until the last memory location is reached, each new page being accessed after a time tBLBH1. The Sequential Row Read operation can be inhibited or interrupted by de-asserting E (set to VIH) or by issuing a command. Refer to Figure 19.
Note: (1). VCCth is equal to 2.5V for 3.3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.
Vccth (1) Vcc WE
CE
ALE
CLE tBLBH1
RB
RE
I/O Busy
Data N
Data N+1
Data N+2
Last Data
Data Output from Address N to Last Byte or Word in Page
Figure 18. Sequential Row Read Disabled and Automatic Page 0 Read at power-up
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Vccth(1) Vcc
WE
CE
ALE
CLE
tBLBH1 (Read Busy time)
tBLBH1
tBLBH1
tBLBH1
RB
Busy Page 0 Data Out
Busy
Busy
Busy
I/O
Page 1 Data Out
Page 2 Data Out
Page Nth Data Out
Note: (1). VCCth is equal to 2.5V for 3.3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.
Figure 19. Automatic Page 0 Read at power-up (Sequential Row Read Enable) Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block where the 6th Byte/ 1st Word in the spare area of the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 20. Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block.
See the "Copy Back Program" section for more details.
Table 7: Block Failure
Operation Erase Program Read Rev 0.6 / Oct. 2004
Refer to Table 7 for the recommended procedure to follow if an error occurs during an operation.
Recommended Procedure Block Replacement Block Replacement or ECC ECC 23
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
START
Block Address= Block 0 Increment Block Address
Data =FFh? YES
NO
Update Bad Block table
Last block? YES
NO
END
Figure 20. Bad Block Management Flowchart
Table 8: Valid Block
Symbol NVB Para. # of Valid Block Min 4016 Max 4096 Unit Blocks
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 9.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 9: Program, Erase Time and Program Erase Endurance Cycles
NAND Flash Min Typ 200 2 100,000 10 Max 500 3
Parameters Page Program Time Block Erase Time Program/Erase Cycles (per block) Data Retention
Unit us ms cycles years
MAXIMUM RATING Stressing the device above the ratings listed in Table 10, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 10: Absolution Maximum Rating
NAND Flash Min -50 -65 1.8V devices 3.3 V devices 1.8V devices 3.3 V devices -0.6 -0.6 -0.6 -0.6 Max 125 150 2.7 4.6 2.7 4.6
Symbol TBIAS TSTG VIO(1)
Parameter Temperature Under Bias Storage Temperature Input or Output Voltage
Unit
o o
C C
V V V V
VCC
Supply Voltage
Note: (1). Minimum Voltage may undershoot to -2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may overshoot to VCC + 2V for less than 20ns during transitions on I/O pins.
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 11, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 11: Operating and AC Measurement Conditions
NAND Flash Min 1.8V devices Supply Voltage (VCC) 2.6V devices
(1)
Parameter
Max 1.95 2.8 3.6 70 85 30 30 100
Unit V V V
o
1.7 2.4 2.7 0 -40
3.3V devices Ambient Temperature (TA) Commercial Temp. Indurstrial Temp. 1.8V devices Load Capacitance (CL) (1 TTL GATE and CL) 2.6V devices
(1)
C
oC
pF pF pF VCC VCC 2.4 V V V V V V ns
3.3V devices 1.8V devices Input Pulses Voltages 2.6V devices(1) 0 0 0.4
3.3V devices 1.8V devices Input and Output Timing Ref. Voltages 2.6V devices
(1)
VCC/2 1.5 5
3.3V devices Input Rise and Fall Times Note : (1). TBD
Table 12: Capacitance
Symbol CIN CI/O
Parameter
Input Capacitance Input/Output Capacitance
Test Condition VIN = 0V VIL = 0V
Typ
Max 10 10
Unit
pF pF
Note: TA = 25oC, f = 1 MHz. CIN and CI/O are not 100% tested.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 13: DC Characteristics, 3.3V Device and 1.8V Device
Symbol 3.3V Device Test Condition Min Sequentia Read Operating Current Program Erase Stand-by Current (TTL) Stand-By Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage tRLRL minimum CE=VIL, IOUT = 0 mA CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0/VCC VIN= 0 to VCCmax VOUT= 0 to VCCmax 3.3V IOH = -400uA 1.8V IOH = -100uA Output Low Voltage Level 3.3V IOL = 2.1mA 1.8V IOL = 100uA Output Low Current (RB) 3.3V VOL = 0.4V 1.8V VOL = 0.1V VDD Supply Voltage (Erase and Program lockout) 2.5 1.5 V 8 10 3 4 mA 0.4 2.0 -0.3 Typ 10 10 10 10 Max 20 20 20 1 50 Min VCC-0.4 -0.3 Typ 8 8 8 10 Max 15 15 15 1 50 mA mA mA mA uA uA uA V V 1.8V Device Unit
Parameter
ICC1 ICC2 ICC3 ICC4 ICC5 ILI ILO VIH VIL VOH
10 10
VCC+0.3 0.8
10 10
VCC+0.3 0.4
Output High Voltage Level
2.4
-
-
VCC-0.1
-
-
V
VOL
-
-
0.1
V
IOL(RB)
VLKO
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 14: AC Characteristics for Command, Address, Data Input (3.3V and 1.8V Device)
Symbol tALLWL tALHWL tCLHWL tCLLWL tDVWH tELWL tWHALH tWHALL tWHCLH tWHCLL tWHDX tWHEH tWHWH tWLWH tWLWL Alt. Symbol tALS Parameter Address Latch Low to Write Enable Low Address Latch Hith to Write Enable Low Command Latch High to Write Enable Low Command Latch Low to Write Enable Low Data Valid to Write Enable High Chip Enable Low to Write Enable Low Write Enable High to Address Latch High Write Enable High to Address Latch Low Write Enable High to Command Latch High Write Enable High to Command Latch Low Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Write Enable Low ALE Setup time Min 3.3V Device 0 1.8V Device Unit ns
tCLS tDS tCS tALH
CL Setup time Data Setup time CE Setup time ALE Hold time
Min Min Min Min
0 20 0 10
ns ns ns ns
tCLH tDH tCH tWH tWP tWC
CLE hold time Data Hold time CE Hold time WE High Hold time WE Pulse Width Write Cycle time
Min Min Min Min Min Min 15 25(1) 50
10 10 10 20 60 80
ns ns ns ns ns ns
Note: 1. If tELWL is less than 10ns, tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device)
Alt. Symbol tALLRL1 tALLRL2 tBHRL tBLBH1 tBLBH2 tBLBH3 Symbol tAR1 tAR2 tRR tR tPROG tBERS Ready/Busy Low to Ready/Busy High 3.3V Device Min Min Min Read Busy time, 512Mb, 1Gb4) Program Busy time Erase Busy time Reset Busy time, during ready Reset Busy time, during read tBLBH4 tRST Reset Busy time, during program Reset Busy time, during erase tCLLRL tDZRL tEHBH tEHEL tEHQZ tELQV tRHBL tRHRL tCLR tIR tCRY tCEH tCHZ tCEA tRB tREH Command Latch Low to Read Enable Low Data Hi-Z to Read Enable Low Chip Enable High to Ready/Busy High (CE intercepted read) Chip Enable High to Chip Enable Low(2) Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Read Enable High to Ready/Busy Low Read Enable High to Read Enable Low Read Enable High to Output Hi-Z Read Enable Low to Read Enable High Read Enable Low to Read Enable Low Read Enable Low to Output Valid Write Enable High to Ready/Busy High Write Enable High to Ready/Busy Low Read Enable High Hold time Max Max Max Max Max Max Max Min Min Max Min Max Max Max Min Min Max Read Enable Pulse Width Read Cycle time Read Enable Access time Max Read ES Access time Max Max 45 12 100 15 us ns Min Min 30 50 35 60 ns 15 15 30 60 80 45 100 20 12 500 3 5 5 10 500 10 0 70+tr(1) 100 20 75 10 50 20 15 1.8V Device 25 80
Parameter Read Electronic Signature Read cycle
Unit ns ns ns us us ms us us us us ns ns ns ns ns ns ns ns
Address Latch Low to Read Enable Low Ready/Busy High to Read Enable Low
tRHQZ
tRHZ
ns
tRLRH tRLRL tRLQV tWHBH tWHBL
tRP tRC tREA tREADID tR tWB
ns ns
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Alt. Symbol tWHRL tWLWL Symbol tWHR tWC 3.3V Device Min Write Cycle time Min 50 60 80 1.8V Device
Parameter
Unit ns ns
Write Enable High to Read Enable Low Write Enable Low to Write Enable Low
Note: (1). The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 32, 33 and 34. (2). To break the sequential read cycle, CE must be held High for longer than tEHEL. (3). ES = Electronic Signature. (4). 1G DDP
CLE
tCLHWL (CLE Setup time) tELWL (CE Setup time) tHWCLL (CLE Hold time) tWHEH (CE Hold time)
CE
tWLWH
WE
tALLWL (ALE Setup time) tWHALH (ALE Hold time)
ALE
tDVWH (Data Setup time) tWHDX (Data Hold time)
I/O
Command
Figure 21. Command Latch AC Waveforms
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
tCLLWL CLE tELWL
(CE Setup time) (CLE Setup time)
tWLWL
tWLWL
tWLWL
CE
tWLWH WE tALHWL
(ALE Setup time)
tWLWH
tWLWH
tWLWH
tWHWL tWHALL
(ALE Hold time)
tWHWL tWHALL
tWHWL tWHALL
ALE tDVWH
(Data Setup time)
tDVWH tWHDX
(Data Hold time)
tDVWH tWHDX Address cycle 2 Address cycle 3
tDVWH tWHDX Address cycle 4 tWHDX
I/O
Address cycle 1
Figure 22. Address Latch AC Waveforms
tWHCLH (CLE Hold time)
CLE
tWHEH (CE Hold time)
CE
tALLWL (ALE Setup time) tWLWL
ALE
tWLWH tWLWH
tWLWH
WE
tDVWH (Data Setup time) tDVWH tWHDX (Data Hold time) Data In 0 Data In 1 tDVWH tWHDX Data In Last tWHDX
I/O
Figure 23. Data Input Latch AC Waveforms
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
tRLRL (Read Cycle time) tRHRL (RE High Holdtime) tRHQZ tRLQV tRLQV (RE Accesstime) tRLQV Data Out tEHQZ
CE RE
tRHQZ
I/O
tBHRL
Data Out
Data Out
RB
Figure 24. Sequential Data Output after Read AC Waveforms
Note:1. CLE = Low, ALE = Low, WE = High.
CLE
tCLHWL
tCLLRL tWHCLL tWHEH
CE
tELWL tWLWH
WE
tWHRL
tELQV
tEHQZ
RE
tDVWH (Data Setup time)
tDZRL tWHDX (Data Hold time) 70h tRLQV tRHQZ Status Register Output
I/O
Figure 25. Read Status Register AC Waveform
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE CE WE ALE RE
tALLRL1 tRLQV (Read ES Access time)
I/O
90h
00h
Man. code
Device code
Don't Care
Don't Care
Read Electronic Signature Command
1st Cycle Address
Manufacturer and Device Code
Reserved For Future Use
Figure 26. Read Electronic Signature AC Waveform
Note: Refer to table(To see Page 22) for the values of the manufacture and device codes.
CLE
tEHEL
CE
tWHWL tEHQZ tEHBH tWHBL
WE
ALE
tALLRL2 tWHBH tRLRL
(Read Cycle time)
tRHQZ
RE
tRLRH
tBLBH1
tRHBL
RB I/O
00h or 01h Command Code
Add.N cycle 1
Add.N cycle 2
Add.N cycle 3
Add.N cycle 4 Busy
Data N
Data N+1
Data N+2
Data Last
Address N Input
Data Output from Address N to Last Byte or Word in Page
Figure 27. Read Read A/ Read B Operation AC Waveform
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE CE WE
tWHALL
tWHBH
ALE
tALLRL2 tBHRL
RE
I/O
50h
Add. M cycle 1
Add. M cycle 2
Add. M cycle 3
Add. M cycle 4
Data M
Data Last
RB
Command Code
Address M Input Busy
Data Output from M to Last Byte or Word in Area C
Figure 28. Read C Operation, One Page AC Waveform
Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are don't care. 2. Only address cycle 4 is required.
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE
CE
tWLWL (Write Cycle time) tWLWL tWLWL
WE
tWHBL tBLBH2 (Program Busy time)
ALE
RE
I/O
80h
Add. N cycle 1
Add. N cycle 2
Add. N cycle 3
N
Last
10h
70h
SR0
RB
Page Program Setup Code Confirm Code
Address Input
Data Input
Page Program
Read Status Register
Figure 29. Page Program AC Waveform
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE
CE
tWLWL
(Write Cycle time)
WE
tBLBH3
(Erase Busy time)
ALE
RE
I/O
60h
Add. N cycle 1
Add. N cycle 2
Add. N cycle 3
D0h
70h
SR0
RB
Block Erase Setup Command
Block Address Input
Confirm Code
Block Erase
Read Status Register
Figure 30. Block Erase AC Waveform
WE
ALE
CLE RE I/O
FFh tBLBH4 (Reset Busy time)
RB
Figure 31. Reset AC Waveform
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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
System Interface Using CE don't care
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So, it is possible to connect NAND Flash to a microprocessor. The only function that was removed from standard NAND Flash to make CE don't care read operation was disabling of the automatic sequential read function.
CLE CE don't-care CE
WE
ALE
I/Ox
80h
Start Add(4Cycle)
Data Input
Data Input
10h
Figure 32. Program Operation with CE don't-care.
CLE If sequential row read enabled, CE must be held low during tR. CE CE don't-care
RE
ALE
R/B
tR
WE
I/Ox
00h
Start Add(4Cycle)
Data Output(sequential)
Figure 33. Read Operation with CE don't-care.
Rev 0.6 / Oct. 2004
37
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Ready/Busy Signal Electrical Characteristics Figures 32, 33 and 34 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor RP can be calculated using the following equation:
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP max is determined by the maximum value of tr.
ready
Vcc VOH VOL busy tf
Figure 34. Ready/Busy AC Waveform
tr
ibusy Rp Vcc
Device RB Open Drain Output
Vss
Figure 35. Ready/Busy Load Circuit
Rev 0.6 / Oct. 2004
38
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Vcc=1.8, CL=30pF 400 4
300
3 ibusy(mA) ibusy(mA)
tr, tf(ns)
200
1.7
2
100 30 1.7 1 2
0.85 60 1.7 3 Rp(K)
90 0.57 1.7 4
120 1 0.43 1.7
0
Vcc=3.3, CL=100pF 400 400 4
300
2.4
300
3
tr, tf(ns)
200
200 1.2 0.8 3.6 1 2 Rp(K)
tf ibusy tr
2
100
100
1 0.6
0
3.6 3
3.6 4
3.6
Figure 36. Resistor Value Waveform Timings for Ready/Busy Signal
Rev 0.6 / Oct. 2004
39
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 37. 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
Table 16: 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data millimeters
Min Typ Max 1.200 0.050 0.980 0.170 0.100 0.150 1.030 0.250 0.200 0.050 11.910 19.900 18.300 12.000 20.000 18.400 0.500 0.500 0 0.680 5 12.120 20.100 18.500
Symbol A A1 A2 B C CP D E E1 e L alpha
Rev 0.6 / Oct. 2004
40
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 38. 48-WSOP1 - 48-lead Plastic Very Very Thin Small Outline, 12 x 17mm, Package Outline
Table 17: 48-WSOP1 - 48-lead Plastic Thin Small Outline, 12 x 17mm, Package Mechanical Data
Symbol A A1 A2 B C CP D D E e L alpha 0.450 0 11.910 16.900 15.300 12.000 17.000 15.400 0.500 0.750 0 0.540 0.130 0.065
millimeters
Min Typ Max 0.700 0.080 0.620 0.230 0.175 0.050 12.120 17.100 15.500
Rev 0.6 / Oct. 2004
41
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 39. 63-FBGA - 8.5 x 15mm, 6x8 ball array 0.8mm pitch, Pakage Outline
Note: Drawing is not to scale.
Table 17: 48-WSOP1 - 48-lead Plastic Thin Small Outline, 12 x 17mm, Package Mechanical Data
Symbol A A1 A2 b D D1 D2 E E1 E2 e FD FD1 FE FE1 SD SE 14.90
millimeters
Min 1.00 0.21 0.79 0.40 8.40 Typ 1.10 0.26 0.84 0.45 8.50 4.00 7.20 15.00 5.60 8.80 0.80 2.25 0.65 4.70 3.10 0.40 0.40 15.10 Max 1.20 0.31 0.89 0.50 8.60
Rev 0.6 / Oct. 2004
42
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash MARKING INFORMATION
Package Marking Example
TSOP1 / WSOP1 / FBGA
K
O
R
H
Y
2
7
x
S
x
x
1
2
1
M
x
x
x
x
Y
W
W
x
x
- hynix - KOR - HY27xSxx121mTxB HY: HYNIX 27: NAND Flash x: Power Supply S: Classification xx: Bit Organization 12: Density 1: Mode M: Version x: Package Type x: Package Material x: Operating Temperature x: Bad Block
: Hynix Symbol : Origin Country : Part Number
: U(2.7V~3.6V), S(1.7V~2.2V) : Single Level Cell+Single Die : 08(x8), 16(x16) : 512Mb : 1nCE & 1R/nB; CE don't care : 1st Generation : T(TSOP1), V(WSOP1), F(FBGA) : Blank(Normal), P(Lead Free) : C(0~70), E(-25~85) I(-40~85) : B(Included Bad Block), S(1~5 Bad Block), P(All Good Block)
- Y: Year (ex: 4=year 2004, 05= year 2005) - ww: Work Week (ex: 12= work week 12) - xx: Process Code Note - Capital Letter - Small Letter : Fixed Item : Non-fixed Item
Rev 0.6 / Oct. 2004
43

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