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| User's Manual 78K0/KF1 8-Bit Single-Chip Microcontrollers www..com PD780143 PD780144 PD780146 PD780148 PD78F0148 PD780143(A) PD780144(A) PD780146(A) PD780148(A) PD78F0148(A) PD780143(A1) PD780144(A1) PD780146(A1) PD780148(A1) PD78F0148(A1) PD780143(A2) PD780144(A2) PD780146(A2) PD780148(A2) Document No. U15947EJ2V0UD00 (2nd edition) Date Published September 2003 N CP(K) (c) Printed in Japan [MEMO] www..com 2 User's Manual U15947EJ2V0UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. www..com 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. User's Manual U15947EJ2V0UD 3 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. www..com * The information in this document is current as of April, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U15947EJ2V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) www..com NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 J03.4 User's Manual U15947EJ2V0UD 5 Major Revisions in This Edition (1/3) Page Throughout Description Addition of products PD78F0148(A1), 780143(A2), 780144(A2), 780146(A2), 780148(A2) Under development Under mass production PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A), 780143(A1), 780144(A1), 780146(A1), 780148(A1) Modification of names of the following special function registers (SFRs) * Ports 0 to 7, and 12 to 14 Port registers 0 to 7, and 12 to 14 p.38 p.40 p.45 p.47 pp.55, 56 pp.57, 58 Addition of Cautions 3 and 4 to 1.4 Pin Configuration (Top View) Modification of 1.5 K1 Family Lineup Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions Addition of Table 2-1 Pin I/O Buffer Power Supplies Modification of descriptions in 2.2.12 AVREF, 2.2.15 REGC, and 2.2.20 VPP (flash memory versions only) Modification of the following contents in Table 2-2 Pin I/O Circuit Types * Modification of recommended connection when P60 to P63 are not used * Modification of I/O circuit type of P62 and P63 * Addition of Note to AVREF * Modification of recommended connection when VPP is not used pp.62 to 66 p.76 p.77 www..com Modification of Figure 3-1 Memory Map (PD780143) to Figure 3-5 Memory Map (PD78F0148) Modification of Figure 3-14 Data to Be Saved to Stack Memory Modification of Figure 3-15 Data to Be Restored from Stack Memory Modification of [Description example] in 3.4.4 Short direct addressing Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing, and 3.4.9 Stack addressing p.90 pp.93 to 95 p.96 p.98 Addition of Table 4-1 Pin I/O Buffer Power Supplies Modification of Table 4-3 Port Configuration pp.108, 111, 112, Modification of Figure 4-11 Block Diagram of P20 to P27, Figure 4-14 Block Diagram of P40 to P47, 114, 115 Figure 4-15 Block Diagram of P50 to P57, Figure 4-17 Block Diagram of P64, P65, and P67, and Figure 4-18 Block Diagram of P66 p.118 p.123 Addition of Remark to Figure 4-21 Block Diagram of P130 Deletion of input switch control register (ISC) from and addition of port registers (P0 to P7, P12 to P14) to 4.3 Registers Controlling Port Function p.124 Modification of setting of output latch of P40 to P47, P50 to P57, P64, P65, and P67 in and addition of Note 2 to Table 4-5 Settings of Port Mode Register and Output Latch When Using Alternate Function p.128 p.129 p.132 p.134 p.139 p.142 p.143 Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode, and (2) Input mode Addition of Caution to 5.1 External Bus Interface Addition of Note to Figure 5-2 Format of Memory Expansion Mode Register (MEM) Addition of Caution 2 to Figure 5-4 Format of Memory Expansion Wait Setting Register (MM) Addition of Remark to Figure 5-8 External Memory Read Modify Write Timing Modification of Figure 6-1 Block Diagram of Clock Generator Addition of Note to 6.3 (1) Processor clock control register (PCC) 6 User's Manual U15947EJ2V0UD Major Revisions in This Edition (2/3) Page p.148 Description Addition of Cautions 2 and 3 to Figure 6-6 Format of Oscillation Stabilization Time Counter Status Register (OSTC) pp.150 to 152 Modification of Figure 6-8 Examples of External Circuit of X1 Oscillator, Figure 6-9 Examples of External Circuit of Subsystem Clock Oscillator, and Figure 6-10 Examples of Incorrect Resonator Connection p.157 p.159 p.160 p.163 p.165 p.168 p.212 p.230 p.255 p.261 Modification of Notes 4 and 5 in Figure 6-13 Status Transition Diagram (2) Modification of Note 4 and illustration in Figure 6-13 Status Transition Diagram (4) Modification of Table 6-3 Relationship Between Operation Clocks in Each Operation Status Modification of Note in Figure 6-14 Switching from Ring-OSC Clock to X1 Input Clock (Flowchart) Addition of Note to Figure 6-16 Switching from X1 Input Clock to Subsystem Clock (Flowchart) Revision of CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Revision of CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Revision of CHAPTER 9 8-BIT TIMERS H0 AND H1 Modification of Figure 10-1 Watch Timer Block Diagram Addition of Figure 10-4 Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) p.272 p.277 p.299 p.320 www..com Modification of Figure 12-1 Block Diagram of Clock Output/Buzzer Output Controller Revision of CHAPTER 13 A/D CONVERTER Revision of CHAPTER 14 SERIAL INTERFACE UART0 Revision of CHAPTER 15 SERIAL INTERFACE UART6 Revision of CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Revision of CHAPTER 17 SERIAL INTERFACE CSIA0 Revision of CHAPTER 18 MULTIPLIER/DIVIDER Addition of Note to INTVLI, POC, and LVI in Table 19-1 Interrupt Source List Addition of Note 2 to Table 19-2 Flags Corresponding to Interrupt Request Sources Addition of Caution 2 to Figure 19-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) Addition of Caution to Table 19-3 Ports Corresponding to EGPn and EGNn Addition of software interrupt request item to Table 19-5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing p.358 p.378 p.418 pp.429, 430 p.433 p.434 p.437 p.442 p.446 p.448 Modification of Figure 20-1 Block Diagram of Key Interrupt Modification of Table 21-1 Relationship Between HALT Mode, STOP Mode, and Clock in old edition to Table 21-1 Relationship Between Operation Clocks in Each Operation Status p.450 Addition of Cautions 2 and 3 to Figure 21-1 Format of Oscillation Stabilization Time Counter Status Register (OSTC) p.452 p.456 Modification of Table 21-1 Operating Statuses in HALT Mode Addition of (3) When subsystem clock is used as CPU clock to Figure 21-4 HALT Mode Release by RESET Input p.457 Modification of the following items in Table 21-4 Operating Statuses in STOP Mode * 8-bit timer H0 * Serial interfaces UART0 and UART6 Modification of Figure 22-1 Block Diagram of Reset Function to Figure 22-4 Timing of Reset in STOP Mode by RESET Input pp.462 to 464 User's Manual U15947EJ2V0UD 7 Major Revisions in This Edition (3/3) Page p.467 Description Modification of mask flag register 1H (MK1H) in Table 22-1 Hardware Statuses After Reset Acknowledgment p.469 p.471 pp.474, 475 Modification of Figure 23-1 Block Diagram of Clock Monitor Addition of operation mode to Table 23-2 Operation Status of Clock Monitor (When CLME = 1) Addition of (6) Clock monitor status after X1 input clock oscillation is stopped by software and (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software to Figure 23-3 Timing of Clock Monitor p.476 p.477 p.480 p.480 p.482 p.483 Addition of Note to description in 24.1 Functions of Power-on-Clear Circuit Modification of Figure 24-1 Block Diagram of Power-on-Clear Circuit Addition of Note to description in 25.1 Functions of Low-Voltage Detector Modification of Figure 25-1 Block Diagram of Low-Voltage Detector Modification of Note 5 in Figure 25-2 Format of Low-Voltage Detection Register (LVIM) Addition of Note 2 and Caution to Figure 25-3 Format of Low-Voltage Detection Level Selection Register (LVIS) pp.485, 487 Modification of Figure 25-4 Timing of Low-Voltage Detector Internal Reset Signal Generation and Figure 25-5 Timing of Low-Voltage Detector Interrupt Signal Generation p.491 Partial modification of description of (2) When used as interrupt under www..com Revision of CHAPTER 26 REGULATOR Addition of Note to CHAPTER 27 MASK OPTIONS Revision of CHAPTER 28 PD78F0148 (no modification of 28.1 Internal Memory Size Switching Register and 28.2 Internal Expansion RAM Size Switching Register) Partial modification of operation of "RETI" in 29.2 Operation List Revision of CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) p.495 p.524 p.529 p.554 p.575 p.593 p.604 p.606 p.608 p.609 p.622 Addition of CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Addition of CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Addition of CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Addition of A.3 Control Software Addition of in-circuit emulator "IE-78K0K1-ET" to A.5 Debugging Tools (Hardware) Modification of part number of RX78K0 in A.7 Embedded Software Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN Addition of APPENDIX D REVISION HISTORY The mark shows major revised points. 8 User's Manual U15947EJ2V0UD INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KF1 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KF1: PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A), 780143(A1), 780144(A1), 780146(A1), 780148(A1), 78F0148(A1), 780143(A2), 780144(A2), 780146(A2), and 780148(A2) Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/KF1 manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/KF1 User's Manual (This Manual) * Pin functions 78K/0 Series User's Manual Instructions * CPU functions * Instruction set * Explanation of each instruction www..com * Internal block functions * Interrupts * Other on-chip peripheral functions * Electrical specifications How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * When using this manual as the manual for (A) grade products, (A1) grade products, and (A2) grade products: Only the quality grade differs between standard products and (A), (A1), and (A2) grade products. Read the part number as follows. * PD780143 PD780143(A), 780143(A1), 780143(A2) * * * * PD780144 PD780144(A), 780144(A1), 780144(A2) PD780146 PD780146(A), 780146(A1), 780146(A2) PD780148 PD780148(A), 780148(A1), 780148(A2) PD78F0148 PD78F0148(A), 78F0148(A1) * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. * How to interpret the register format: For a bit number enclosed in brackets, the bit name is defined as a reserved word in the assembler, and is already defined in the header file named sfrbit.h in the C compiler. User's Manual U15947EJ2V0UD 9 * To check the details of a register when you know the register name. See APPENDIX C REGISTER INDEX. * To know details of the 78K/0 Series instructions. Refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). Caution Examples in this manual employ the "standard" quality grade for general electronics. circuit actually used. Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: xxx (overscore over pin and signal name) Note: Caution: Footnote for item marked with Note in the text. Information requiring particular attention When using examples in this manual for the "special" quality grade, review the quality grade of each part and/or Remark: Supplementary information ... xxxx or xxxxB Numerical representations: Binary ... xxxx Decimal Hexadecimal Related Documents ... xxxxH The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices www..com Document Name 78K0/KF1 User's Manual 78K/0 Series Instructions User's Manual Document No. This manual U12326E Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (Windows TM Document No. U14445E U14446E U11789E U14297E U14298E Based) U15373E U15802E External Part User Open Interface Specifications ID78K Series Integrated Debugger Ver. 2.30 or Later RX78K0 Real-Time OS Operation (Windows Based) Fundamentals Installation Project Manager Ver. 3.12 or Later (Windows Based) U15185E U11537E U11536E U14610E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. 10 User's Manual U15947EJ2V0UD Documents Related to Development Tools (Hardware) (User's Manuals) Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-78K0K1-ET In-Circuit Emulator IE-780148-NS-EM1 Emulation Board Document No. U13731E U14889E To be prepared To be prepared Documents Related to Flash Memory Programming Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E Other Documents Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) www..com Document No. X13769X Note C11531E C10983E C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. User's Manual U15947EJ2V0UD 11 CONTENTS CHAPTER 1 OUTLINE............................................................................................................................. 33 1.1 Features ..................................................................................................................................... 33 1.2 Applications .............................................................................................................................. 34 1.3 Ordering Information ................................................................................................................ 35 1.4 Pin Configuration (Top View)................................................................................................... 38 1.5 K1 Family Lineup ...................................................................................................................... 40 1.5.1 1.5.2 78K0/Kx1 product lineup .............................................................................................................. 40 V850ES/Kx1 product lineup ......................................................................................................... 42 1.6 1.7 Block Diagram........................................................................................................................... 44 Outline of Functions ................................................................................................................. 45 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 47 2.1 Pin Function List....................................................................................................................... 47 2.2 Description of Pin Functions ................................................................................................... 51 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 www..com P00 to P06 (port 0) ....................................................................................................................... 51 P10 to P17 (port 1) ....................................................................................................................... 52 P20 to P27 (port 2) ....................................................................................................................... 52 P30 to P33 (port 3) ....................................................................................................................... 53 P40 to P47 (port 4) ....................................................................................................................... 53 P50 to P57 (port 5) ....................................................................................................................... 53 P60 to P67 (port 6) ....................................................................................................................... 54 P70 to P77 (port 7) ....................................................................................................................... 54 P120 (port 12) .............................................................................................................................. 54 P130 (port 13) .............................................................................................................................. 54 P140 to P145 (port 14) ................................................................................................................. 55 AVREF............................................................................................................................................ 55 AVSS ............................................................................................................................................. 55 RESET ......................................................................................................................................... 56 REGC........................................................................................................................................... 56 X1 and X2..................................................................................................................................... 56 XT1 and XT2 ................................................................................................................................ 56 VDD and EVDD ............................................................................................................................... 56 VSS and EVSS................................................................................................................................ 56 VPP (flash memory versions only) ................................................................................................. 56 IC (mask ROM versions only)....................................................................................................... 56 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.2.17 2.2.18 2.2.19 2.2.20 2.2.21 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................ 57 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 61 3.1 Memory Space........................................................................................................................... 61 3.1.1 3.1.2 3.1.3 3.1.4 Internal program memory space................................................................................................... 67 Internal data memory space ......................................................................................................... 68 Special function register (SFR) area ............................................................................................ 68 Data memory addressing ............................................................................................................. 69 User's Manual U15947EJ2V0UD 12 3.2 Processor Registers................................................................................................................. 74 3.2.1 3.2.2 3.2.3 Control registers............................................................................................................................74 General-purpose registers ............................................................................................................78 Special function registers (SFRs)..................................................................................................79 Relative addressing.......................................................................................................................84 Immediate addressing...................................................................................................................85 Table indirect addressing ..............................................................................................................86 Register addressing ......................................................................................................................86 Implied addressing ........................................................................................................................87 Register addressing ......................................................................................................................88 Direct addressing ..........................................................................................................................89 Short direct addressing .................................................................................................................90 Special function register (SFR) addressing...................................................................................91 Register indirect addressing..........................................................................................................92 Based addressing .........................................................................................................................93 Based indexed addressing............................................................................................................94 Stack addressing...........................................................................................................................95 3.3 Instruction Address Addressing............................................................................................. 84 3.3.1 3.3.2 3.3.3 3.3.4 3.4 Operand Address Addressing................................................................................................. 87 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 www..com CHAPTER 4 PORT FUNCTIONS........................................................................................................... 96 4.1 Port Functions .......................................................................................................................... 96 4.2 Port Configuration .................................................................................................................... 98 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 Port 0 ............................................................................................................................................99 Port 1 ..........................................................................................................................................103 Port 2 ..........................................................................................................................................108 Port 3 ..........................................................................................................................................109 Port 4 ..........................................................................................................................................111 Port 5 ..........................................................................................................................................112 Port 6 ..........................................................................................................................................113 Port 7 ..........................................................................................................................................116 Port 12 ........................................................................................................................................117 Port 13 ........................................................................................................................................118 Port 14 ........................................................................................................................................119 4.3 4.4 Registers Controlling Port Function..................................................................................... 123 Port Function Operations ...................................................................................................... 128 4.4.1 4.4.2 4.4.3 Writing to I/O port ........................................................................................................................128 Reading from I/O port..................................................................................................................128 Operations on I/O port.................................................................................................................128 CHAPTER 5 EXTERNAL BUS INTERFACE ...................................................................................... 129 5.1 External Bus Interface............................................................................................................ 129 5.2 Registers Controlling External Bus Interface...................................................................... 132 5.3 External Bus Interface Function Timing .............................................................................. 135 5.4 Example of Connection with Memory................................................................................... 140 User's Manual U15947EJ2V0UD 13 CHAPTER 6 CLOCK GENERATOR .................................................................................................... 141 6.1 Functions of Clock Generator ............................................................................................... 141 6.2 Configuration of Clock Generator......................................................................................... 141 6.3 Registers Controlling Clock Generator ................................................................................ 143 6.4 System Clock Oscillator......................................................................................................... 150 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 X1 oscillator................................................................................................................................ 150 Subsystem clock oscillator ......................................................................................................... 150 When subsystem clock is not used ............................................................................................ 153 Ring-OSC oscillator.................................................................................................................... 153 Prescaler .................................................................................................................................... 153 6.5 6.6 6.7 6.8 Clock Generator Operation .................................................................................................... 154 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock ......................... 161 Time Required for CPU Clock Switchover ........................................................................... 162 Clock Switching Flowchart and Register Setting ................................................................ 163 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 Switching from Ring-OSC clock to X1 input clock ...................................................................... 163 Switching from X1 input clock to Ring-OSC clock ...................................................................... 164 Switching from X1 input clock to subsystem clock ..................................................................... 165 Switching from subsystem clock to X1 input clock ..................................................................... 166 Register settings......................................................................................................................... 167 www..com CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01......................................................... 168 7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 ......................................................... 168 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01................................................... 169 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 .......................................... 174 7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 ......................................................... 185 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 Interval timer operation............................................................................................................... 185 PPG output operations ............................................................................................................... 188 Pulse width measurement operations ........................................................................................ 191 External event counter operation................................................................................................ 199 Square-wave output operation ................................................................................................... 202 One-shot pulse output operation ................................................................................................ 204 7.5 Cautions for 16-Bit Timer/Event Counters 00 and 01.......................................................... 209 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 212 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 ........................................................... 212 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51..................................................... 214 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................ 216 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 ......................................................... 221 8.4.1 8.4.2 8.4.3 8.4.4 Operation as interval timer ......................................................................................................... 221 Operation as external event counter .......................................................................................... 223 Square-wave output operation ................................................................................................... 224 PWM output operation................................................................................................................ 225 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51............................................................ 229 14 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 230 9.1 Functions of 8-Bit Timers H0 and H1.................................................................................... 230 9.2 Configuration of 8-Bit Timers H0 and H1 ............................................................................. 230 9.3 Registers Controlling 8-Bit Timers H0 and H1 .................................................................... 234 9.4 Operation of 8-Bit Timers H0 and H1.................................................................................... 239 9.4.1 9.4.2 9.4.3 Operation as interval timer/square-wave output..........................................................................239 Operation as PWM output mode .................................................................................................242 Carrier generator mode operation (8-bit timer H1 only)...............................................................248 CHAPTER 10 WATCH TIMER ............................................................................................................. 255 10.1 Functions of Watch Timer ..................................................................................................... 255 10.2 Configuration of Watch Timer ............................................................................................... 257 10.3 Register Controlling Watch Timer ........................................................................................ 257 10.4 Watch Timer Operations ........................................................................................................ 259 10.4.1 10.4.2 Watch timer operation .................................................................................................................259 Interval timer operation ...............................................................................................................260 10.5 Cautions for Watch Timer...................................................................................................... 261 CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 262 11.1 Functions of Watchdog Timer............................................................................................... 262 11.2 Configuration of Watchdog Timer ........................................................................................ 264 11.3 Registers Controlling Watchdog Timer................................................................................ 265 11.4 Operation of Watchdog Timer ............................................................................................... 267 11.4.1 11.4.2 11.4.3 11.4.4 Watchdog timer operation when "Ring-OSC cannot be stopped" is selected by mask option.....267 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by mask option ..........................................................................................................................................268 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by mask option) ............................................................................................................269 Watchdog timer operation in HALT mode (when "Ring-OSC can be stopped by software" is selected by mask option) ............................................................................................................271 www..com CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 272 12.1 Functions of Clock Output/Buzzer Output Controller ........................................................ 272 12.2 Configuration of Clock Output/Buzzer Output Controller .................................................. 273 12.3 Register Controlling Clock Output/Buzzer Output Controller ........................................... 273 12.4 Clock Output/Buzzer Output Controller Operations ........................................................... 276 12.4.1 12.4.2 Clock output operation ................................................................................................................276 Operation as buzzer output.........................................................................................................276 CHAPTER 13 A/D CONVERTER ......................................................................................................... 277 13.1 Functions of A/D Converter................................................................................................... 277 13.2 Configuration of A/D Converter ............................................................................................ 278 13.3 Registers Used in A/D Converter .......................................................................................... 280 13.4 A/D Converter Operations ..................................................................................................... 286 13.4.1 Basic operations of A/D converter...............................................................................................286 User's Manual U15947EJ2V0UD 15 13.4.2 13.4.3 Input voltage and conversion results .......................................................................................... 288 A/D converter operation mode.................................................................................................... 289 13.5 How to Read A/D Converter Characteristics Table ............................................................. 292 13.6 Cautions for A/D Converter.................................................................................................... 294 CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 299 14.1 Functions of Serial Interface UART0 .................................................................................... 299 14.2 Configuration of Serial Interface UART0 .............................................................................. 300 14.3 Registers Controlling Serial Interface UART0 ..................................................................... 303 14.4 Operation of Serial Interface UART0..................................................................................... 308 14.4.1 14.4.2 14.4.3 Operation stop mode.................................................................................................................. 308 Asynchronous serial interface (UART) mode ............................................................................. 309 Dedicated baud rate generator................................................................................................... 315 CHAPTER 15 SERIAL INTERFACE UART6 ...................................................................................... 320 15.1 Functions of Serial Interface UART6 .................................................................................... 320 15.2 Configuration of Serial Interface UART6 .............................................................................. 324 15.3 Registers Controlling Serial Interface UART6 ..................................................................... 327 15.4 Operation of Serial Interface UART6..................................................................................... 335 15.4.1 15.4.2 15.4.3 www..com Operation stop mode.................................................................................................................. 335 Asynchronous serial interface (UART) mode ............................................................................. 336 Dedicated baud rate generator................................................................................................... 351 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 ................................................................ 358 16.1 Functions of Serial Interfaces CSI10 and CSI11 .................................................................. 358 16.2 Configuration of Serial Interfaces CSI10 and CSI11 ........................................................... 359 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11................................................... 361 16.4 Operation of Serial Interfaces CSI10 and CSI11 .................................................................. 367 16.4.1 16.4.2 Operation stop mode.................................................................................................................. 367 3-wire serial I/O mode ................................................................................................................ 368 CHAPTER 17 SERIAL INTERFACE CSIA0........................................................................................ 378 17.1 Functions of Serial Interface CSIA0...................................................................................... 378 17.2 Configuration of Serial Interface CSIA0 ............................................................................... 379 17.3 Registers Controlling Serial Interface CSIA0....................................................................... 381 17.4 Operation of Serial Interface CSIA0 ...................................................................................... 390 17.4.1 17.4.2 Operation stop mode.................................................................................................................. 390 3-wire serial I/O mode ................................................................................................................ 391 17.4.3 3-wire serial I/O mode with automatic transmit/receive function................................................. 396 CHAPTER 18 MULTIPLIER/DIVIDER ................................................................................................... 418 18.1 Functions of Multiplier/Divider .............................................................................................. 418 18.2 Configuration of Multiplier/Divider........................................................................................ 418 18.3 Register Controlling Multiplier/Divider ................................................................................. 423 18.4 Operations of Multiplier/Divider ............................................................................................ 424 16 User's Manual U15947EJ2V0UD 18.4.1 18.4.2 Multiplication operation ...............................................................................................................424 Division operation........................................................................................................................426 CHAPTER 19 INTERRUPT FUNCTIONS ............................................................................................ 428 19.1 Interrupt Function Types ....................................................................................................... 428 19.2 Interrupt Sources and Configuration.................................................................................... 428 19.3 Registers Controlling Interrupt Functions ........................................................................... 432 19.4 Interrupt Servicing Operations.............................................................................................. 439 19.4.1 19.4.2 19.4.3 19.4.4 Maskable interrupt request acknowledgement ............................................................................439 Software interrupt request acknowledgment ...............................................................................441 Multiple interrupt servicing ..........................................................................................................442 Interrupt request hold ..................................................................................................................445 CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 446 20.1 Functions of Key Interrupt..................................................................................................... 446 20.2 Configuration of Key Interrupt .............................................................................................. 446 20.3 Register Controlling Key Interrupt........................................................................................ 447 CHAPTER 21 STANDBY FUNCTION.................................................................................................. 448 21.1 Standby Function and Configuration ................................................................................... 448 21.1.1 21.1.2 www..com Standby function .........................................................................................................................448 Registers controlling standby function.........................................................................................450 HALT mode .................................................................................................................................452 STOP mode ................................................................................................................................457 21.2 Standby Function Operation ................................................................................................. 452 21.2.1 21.2.2 CHAPTER 22 RESET FUNCTION ....................................................................................................... 461 22.1 Register for Confirming Reset Source ................................................................................. 468 CHAPTER 23 CLOCK MONITOR ........................................................................................................ 469 23.1 Functions of Clock Monitor ................................................................................................... 469 23.2 Configuration of Clock Monitor............................................................................................. 469 23.3 Registers Controlling Clock Monitor .................................................................................... 470 23.4 Operation of Clock Monitor ................................................................................................... 471 CHAPTER 24 POWER-ON-CLEAR CIRCUIT ..................................................................................... 476 24.1 Functions of Power-on-Clear Circuit .................................................................................... 476 24.2 Configuration of Power-on-Clear Circuit ............................................................................. 477 24.3 Operation of Power-on-Clear Circuit .................................................................................... 477 24.4 Cautions for Power-on-Clear Circuit .................................................................................... 478 CHAPTER 25 LOW-VOLTAGE DETECTOR ....................................................................................... 480 25.1 Functions of Low-Voltage Detector ...................................................................................... 480 25.2 Configuration of Low-Voltage Detector................................................................................ 480 25.3 Registers Controlling Low-Voltage Detector....................................................................... 481 User's Manual U15947EJ2V0UD 17 25.4 Operation of Low-Voltage Detector ...................................................................................... 484 25.5 Cautions for Low-Voltage Detector....................................................................................... 488 CHAPTER 26 REGULATOR ................................................................................................................. 492 26.1 Outline of Regulator ............................................................................................................... 492 CHAPTER 27 MASK OPTIONS ........................................................................................................... 494 CHAPTER 28 PD78F0148................................................................................................................... 495 28.1 28.2 28.3 28.4 28.5 28.6 Internal Memory Size Switching Register ............................................................................ 496 Internal Expansion RAM Size Switching Register............................................................... 497 Writing with Flash Programmer ............................................................................................ 498 Programming Environment.................................................................................................... 505 Communication Mode ............................................................................................................ 505 Processing of Pins on Board................................................................................................. 509 28.6.1 28.6.2 28.6.3 28.6.4 28.6.5 28.6.6 28.6.7 www..com VPP pin........................................................................................................................................ 509 Serial interface pins.................................................................................................................... 510 RESET pin.................................................................................................................................. 512 Port pins ..................................................................................................................................... 512 REGC pin ................................................................................................................................... 512 Other signal pins ........................................................................................................................ 512 Power supply.............................................................................................................................. 512 Controlling flash memory............................................................................................................ 513 Flash memory programming mode............................................................................................. 514 Selecting communication mode.................................................................................................. 514 Communication commands ........................................................................................................ 515 28.7 Programming Method............................................................................................................. 513 28.7.1 28.7.2 28.7.3 28.7.4 CHAPTER 29 INSTRUCTION SET....................................................................................................... 516 29.1 Conventions Used in Operation List..................................................................................... 516 29.1.1 29.1.2 Operand identifiers and specification methods........................................................................... 516 Description of operation column ................................................................................................. 517 29.1.3 Description of flag operation column .......................................................................................... 517 29.2 Operation List.......................................................................................................................... 518 29.3 Instructions Listed by Addressing Type .............................................................................. 526 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS).............................................. 529 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) ................................ 554 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) ................................ 575 CHAPTER 33 PACKAGE DRAWINGS ................................................................................................ 591 18 User's Manual U15947EJ2V0UD CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS........................................................... 593 CHAPTER 35 CAUTIONS FOR WAIT ................................................................................................ 596 35.1 Cautions for Wait .................................................................................................................... 596 35.2 Peripheral Hardware That Generates Wait........................................................................... 597 35.3 Example of Wait Occurrence................................................................................................. 598 APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 599 A.1 Software Package ................................................................................................................... 602 A.2 Language Processing Software ............................................................................................ 603 A.3 Control Software..................................................................................................................... 604 A.4 Flash Memory Writing Tools ................................................................................................. 604 A.5 Debugging Tools (Hardware) ................................................................................................ 605 A.5.1 A.5.2 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A ...............................................605 When using in-circuit emulator IE-78K0K1-ET ............................................................................606 A.6 A.7 Debugging Tools (Software).................................................................................................. 607 Embedded Software ............................................................................................................... 608 APPENDIX B NOTES ON TARGET SYSTEM DESIGN................................................................... 609 APPENDIX C REGISTER INDEX......................................................................................................... 614 C.1 Register Index (In Alphabetical Order with Respect to Register Names)......................... 614 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................ 618 APPENDIX D REVISION HISTORY ..................................................................................................... 622 www..com User's Manual U15947EJ2V0UD 19 LIST OF FIGURES (1/10) Figure No. 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 www..com Title Page Pin I/O Circuit List .....................................................................................................................................59 Memory Map (PD780143).......................................................................................................................62 Memory Map (PD780144).......................................................................................................................63 Memory Map (PD780146).......................................................................................................................64 Memory Map (PD780148).......................................................................................................................65 Memory Map (PD78F0148) ....................................................................................................................66 Correspondence Between Data Memory and Addressing (PD780143) ..................................................69 Correspondence Between Data Memory and Addressing (PD780144) ..................................................70 Correspondence Between Data Memory and Addressing (PD780146) ..................................................71 Correspondence Between Data Memory and Addressing (PD780148) ..................................................72 Correspondence Between Data Memory and Addressing (PD78F0148)................................................73 Format of Program Counter ......................................................................................................................74 Format of Program Status Word ...............................................................................................................74 Format of Stack Pointer ............................................................................................................................75 Data to Be Saved to Stack Memory ..........................................................................................................76 Data to Be Restored from Stack Memory .................................................................................................77 Configuration of General-Purpose Registers ............................................................................................78 Port Types ................................................................................................................................................96 Block Diagram of P00, P03, and P05 .......................................................................................................99 Block Diagram of P01 and P06...............................................................................................................100 Block Diagram of P02 .............................................................................................................................101 Block Diagram of P04 .............................................................................................................................102 Block Diagram of P10 .............................................................................................................................103 Block Diagram of P11 and P14...............................................................................................................104 Block Diagram of P12 and P15...............................................................................................................105 Block Diagram of P13 .............................................................................................................................106 Block Diagram of P16 and P17...............................................................................................................107 Block Diagram of P20 to P27..................................................................................................................108 Block Diagram of P30 to P32..................................................................................................................109 Block Diagram of P33 .............................................................................................................................110 Block Diagram of P40 to P47..................................................................................................................111 Block Diagram of P50 to P57..................................................................................................................112 Block Diagram of P60 to P63..................................................................................................................113 Block Diagram of P64, P65, and P67 .....................................................................................................114 Block Diagram of P66 .............................................................................................................................115 Block Diagram of P70 to P77..................................................................................................................116 Block Diagram of P120 ...........................................................................................................................117 Block Diagram of P130 ...........................................................................................................................118 Block Diagram of P140 and P141...........................................................................................................119 User's Manual U15947EJ2V0UD 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 20 LIST OF FIGURES (2/10) Figure No. Title Page 4-23 4-24 4-25 4-26 4-27 4-28 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 6-1 www..com Block Diagram of P142 ........................................................................................................................... 120 Block Diagram of P143 ........................................................................................................................... 121 Block Diagram of P144 and P145........................................................................................................... 122 Format of Port Mode Register ................................................................................................................ 123 Format of Port Register .......................................................................................................................... 126 Format of Pull-up Resistor Option Register ............................................................................................ 127 Memory Map When Using External Bus Interface .................................................................................. 130 Format of Memory Expansion Mode Register (MEM)............................................................................. 132 Pins Specified for Address (with PD780143) ........................................................................................ 133 Format of Memory Expansion Wait Setting Register (MM)..................................................................... 134 Instruction Fetch from External Memory ................................................................................................. 136 External Memory Read Timing ............................................................................................................... 137 External Memory Write Timing ............................................................................................................... 138 External Memory Read Modify Write Timing .......................................................................................... 139 Connection Example of PD780144 and Memory.................................................................................. 140 Block Diagram of Clock Generator ......................................................................................................... 142 Format of Processor Clock Control Register (PCC) ............................................................................... 144 Format of Ring-OSC Mode Register (RCM) ........................................................................................... 145 Format of Main Clock Mode Register (MCM) ......................................................................................... 146 Format of Main OSC Control Register (MOC) ........................................................................................ 147 Format of Oscillation Stabilization Time Counter Status Register (OSTC) ............................................. 148 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................... 149 Examples of External Circuit of X1 Oscillator ......................................................................................... 150 Examples of External Circuit of Subsystem Clock Oscillator .................................................................. 150 Examples of Incorrect Resonator Connection ........................................................................................ 151 Subsystem Clock Feedback Resistor ..................................................................................................... 153 Timing Diagram of CPU Default Start Using Ring-OSC ......................................................................... 155 Status Transition Diagram ...................................................................................................................... 156 Switching from Ring-OSC Clock to X1 Input Clock (Flowchart).............................................................. 163 Switching from X1 Input Clock to Ring-OSC Clock (Flowchart).............................................................. 164 Switching from X1 Input Clock to Subsystem Clock (Flowchart) ............................................................ 165 Switching from Subsystem Clock to X1 Input Clock (Flowchart) ............................................................ 166 Block Diagram of 16-Bit Timer/Event Counter 00 ................................................................................... 169 Block Diagram of 16-Bit Timer/Event Counter 01 (PD780146, 780148, and 78F0148 Only) ............... 170 Format of 16-Bit Timer Counter 0n (TM0n)............................................................................................. 171 Format of 16-Bit Timer Capture/Compare Register 00n (CR00n)........................................................... 171 Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)........................................................... 173 Format of 16-Bit Timer Mode Control Register 00 (TMC00) ................................................................... 175 User's Manual U15947EJ2V0UD 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 7-1 7-2 7-3 7-4 7-5 7-6 21 LIST OF FIGURES (3/10) Figure No. Title Page 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 www..com Format of 16-Bit Timer Mode Control Register 01 (TMC01) ...................................................................176 Format of Capture/Compare Control Register 00 (CRC00) ....................................................................177 Format of Capture/Compare Control Register 01 (CRC01) ....................................................................178 Format of 16-Bit Timer Output Control Register 00 (TOC00)..................................................................179 Format of 16-Bit Timer Output Control Register 01 (TOC01)..................................................................180 Format of Prescaler Mode Register 00 (PRM00) ....................................................................................182 Format of Prescaler Mode Register 01 (PRM01) ....................................................................................183 Format of Port Mode Register 0 (PM0) ...................................................................................................184 Control Register Settings for Interval Timer Operation ...........................................................................186 Interval Timer Configuration Diagram .....................................................................................................187 Timing of Interval Timer Operation .........................................................................................................187 Control Register Settings for PPG Output Operation ..............................................................................189 Configuration Diagram of PPG Output....................................................................................................190 PPG Output Operation Timing ................................................................................................................190 CR01n Capture Operation with Rising Edge Specified ...........................................................................191 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI00n and CR01n Are Used) ............................................................192 Configuration Diagram for Pulse Width Measurement with Free-Running Counter ................................193 Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) .........................................................................193 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter...............194 Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified)....................................................................................................................195 Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) .............................................................................196 Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified).......................................................................197 Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) ...................................................................................................................198 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) .......198 Control Register Settings in External Event Counter Mode (with Rising Edge Specified).......................200 Configuration Diagram of External Event Counter ..................................................................................201 External Event Counter Operation Timing (with Rising Edge Specified).................................................201 Control Register Settings in Square-Wave Output Mode........................................................................202 Square-Wave Output Operation Timing..................................................................................................203 Control Register Settings for One-Shot Pulse Output with Software Trigger ..........................................205 Timing of One-Shot Pulse Output Operation with Software Trigger........................................................206 Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) ...................................................................................................................207 Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) ...........208 Start Timing of 16-Bit Timer Counter 0n (TM0n).....................................................................................209 User's Manual U15947EJ2V0UD 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 22 LIST OF FIGURES (4/10) Figure No. Title Page 7-41 7-42 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 www..com Operation Timing of OVF0n Flag............................................................................................................ 210 Capture Register Data Retention Timing ................................................................................................ 210 Block Diagram of 8-Bit Timer/Event Counter 50 ..................................................................................... 212 Block Diagram of 8-Bit Timer/Event Counter 51 ..................................................................................... 213 Format of 8-Bit Timer Counter 5n (TM5n)............................................................................................... 214 Format of 8-Bit Timer Compare Register 5n (CR5n) .............................................................................. 215 Format of Timer Clock Selection Register 50 (TCL50) ........................................................................... 216 Format of Timer Clock Selection Register 51 (TCL51) ........................................................................... 217 Format of 8-Bit Timer Mode Control Register 50 (TMC50) ..................................................................... 218 Format of 8-Bit Timer Mode Control Register 51 (TMC51) ..................................................................... 219 Format of Port Mode Register 1 (PM1)................................................................................................... 220 Format of Port Mode Register 3 (PM3)................................................................................................... 220 Interval Timer Operation Timing ............................................................................................................. 221 External Event Counter Operation Timing (with Rising Edge Specified) ................................................ 223 Square-Wave Output Operation Timing ................................................................................................. 225 PWM Output Operation Timing............................................................................................................... 227 Timing of Operation with CR5n Changed ............................................................................................... 228 8-Bit Timer Counter 5n Start Timing ....................................................................................................... 229 Block Diagram of 8-Bit Timer H0 ............................................................................................................ 231 Block Diagram of 8-Bit Timer H1 ............................................................................................................ 232 Format of 8-Bit Timer H Compare Register 0n (CMP0n) ........................................................................ 233 Format of 8-Bit Timer H Compare Register 1n (CMP1n) ........................................................................ 233 Format of 8-Bit Timer H Mode Register 0 (TMHMD0) ............................................................................ 235 Format of 8-Bit Timer H Mode Register 1 (TMHMD1) ............................................................................ 237 Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) .............................................................. 238 Format of Port Mode Register 1 (PM1)................................................................................................... 238 Register Setting During Interval Timer/Square-Wave Output Operation ................................................ 239 Timing of Interval Timer/Square-Wave Output Operation....................................................................... 240 Register Setting in PWM Output Mode................................................................................................... 242 Operation Timing in PWM Output Mode ................................................................................................. 244 Transfer Timing ...................................................................................................................................... 249 Register Setting in Carrier Generator Mode ........................................................................................... 250 Carrier Generator Mode Operation Timing ............................................................................................. 252 Watch Timer Block Diagram ................................................................................................................... 255 Format of Watch Timer Operation Mode Register (WTM) ...................................................................... 258 Operation Timing of Watch Timer/Interval Timer .................................................................................... 260 Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) .... 261 8-16 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 10-1 10-2 10-3 10-4 User's Manual U15947EJ2V0UD 23 LIST OF FIGURES (5/10) Figure No. Title Page 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 12-1 12-2 12-3 12-4 13-1 13-2 13-3 13-4 www..com Block Diagram of Watchdog Timer .........................................................................................................264 Format of Watchdog Timer Mode Register (WDTM)...............................................................................265 Format of Watchdog Timer Enable Register (WDTE) .............................................................................266 Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)...............................269 Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)........269 Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock).........270 Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock) ............................271 Operation in HALT Mode ........................................................................................................................271 Block Diagram of Clock Output/Buzzer Output Controller.......................................................................272 Format of Clock Output Selection Register (CKS) ..................................................................................274 Format of Port Mode Register 14 (PM14) ...............................................................................................275 Remote Control Output Application Example..........................................................................................276 Block Diagram of A/D Converter.............................................................................................................277 Format of A/D Converter Mode Register (ADM) .....................................................................................281 Timing Chart When Boost Reference Voltage Generator Is Used ..........................................................282 Format of Analog Input Channel Specification Register (ADS)...............................................................283 Format of A/D Conversion Result Register (ADCR) ...............................................................................284 Format of Power-Fail Comparison Mode Register (PFM) .......................................................................285 Format of Power-Fail Comparison Threshold Register (PFT).................................................................285 Basic Operation of A/D Converter...........................................................................................................287 Relationship Between Analog Input Voltage and A/D Conversion Result ...............................................288 A/D Conversion Operation ......................................................................................................................289 Power-Fail Detection (When PFEN = 1 and PFCM = 0) .........................................................................290 Overall Error ...........................................................................................................................................292 Quantization Error...................................................................................................................................292 Zero-Scale Error ............................................................................................................... 293 Full-Scale Error.......................................................................................................................................293 Integral Linearity Error........................................................................................................ 293 Differential Linearity Error .......................................................................................................................293 Circuit Configuration of Series Resistor String........................................................................................294 Analog Input Pin Connection ..................................................................................................................295 Timing of A/D Conversion End Interrupt Request Generation ................................................................296 Timing of A/D Converter Sampling and A/D Conversion Start Delay ......................................................297 Internal Equivalent Circuit of ANIn Pin ....................................................................................................298 Block Diagram of Serial Interface UART0...............................................................................................301 Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0)......................................303 Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)............................305 Format of Baud Rate Generator Control Register 0 (BRGC0) ................................................................306 User's Manual U15947EJ2V0UD 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 14-1 14-2 14-3 14-4 24 LIST OF FIGURES (6/10) Figure No. Title Page 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 www..com Format of Port Mode Register 1 (PM1)................................................................................................... 307 Format of Normal UART Transmit/Receive Data.................................................................................... 310 Example of Normal UART Transmit/Receive Data Waveform................................................................ 310 Transmission Completion Interrupt Request Timing............................................................................... 312 Reception Completion Interrupt Request Timing .................................................................................... 313 Noise Filter Circuit .................................................................................................................................. 314 Configuration of Baud Rate Generator ................................................................................................... 315 Permissible Baud Rate Range During Reception ................................................................................... 318 LIN Transmission Operation ................................................................................................................... 321 LIN Reception Operation ........................................................................................................................ 322 Port Configuration for LIN Reception Operation ..................................................................................... 323 Block Diagram of Serial Interface UART6 .............................................................................................. 325 Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6)...................................... 327 Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)............................ 329 Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)................................ 330 Format of Clock Selection Register 6 (CKSR6) ...................................................................................... 331 Format of Baud Rate Generator Control Register 6 (BRGC6)................................................................ 332 Format of Asynchronous Serial Interface Control Register 6 (ASICL6) .................................................. 333 Format of Input Switch Control Register (ISC)........................................................................................ 334 Format of Port Mode Register 1 (PM1)................................................................................................... 334 Format of Normal UART Transmit/Receive Data.................................................................................... 338 Example of Normal UART Transmit/Receive Data Waveform................................................................ 339 Normal Transmission Completion Interrupt Request Timing .................................................................. 341 Example of Continuous Transmission Processing Flow ......................................................................... 343 Timing of Starting Continuous Transmission .......................................................................................... 344 Timing of Ending Continuous Transmission ........................................................................................... 345 Reception Completion Interrupt Request Timing .................................................................................... 346 Reception Error Interrupt ........................................................................................................................ 347 Noise Filter Circuit .................................................................................................................................. 348 Example of Setting Procedure of SBF Transmission (Flowchart) ........................................................... 349 SBF Transmission .................................................................................................................................. 349 SBF Reception ....................................................................................................................................... 350 Configuration of Baud Rate Generator ................................................................................................... 352 Permissible Baud Rate Range During Reception ................................................................................... 355 Data Frame Length During Continuous Transmission............................................................................ 357 Block Diagram of Serial Interface CSI10 ................................................................................................ 359 Block Diagram of Serial Interface CSI11 (PD780146, 780148, and 78F0148 Only)............................. 360 Format of Serial Operation Mode Register 10 (CSIM10) ........................................................................ 361 Format of Serial Operation Mode Register 11 (CSIM11) ........................................................................ 362 User's Manual U15947EJ2V0UD 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 15-25 15-26 15-27 16-1 16-2 16-3 16-4 25 LIST OF FIGURES (7/10) Figure No. Title Page 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 www..com Format of Serial Clock Selection Register 10 (CSIC10)..........................................................................363 Format of Serial Clock Selection Register 11 (CSIC11)..........................................................................365 Format of Port Mode Register 0 (PM0) ...................................................................................................366 Format of Port Mode Register 1 (PM1) ...................................................................................................366 Timing in 3-Wire Serial I/O Mode ............................................................................................................372 Timing of Clock/Data Phase ...................................................................................................................374 Output Operation of First Bit ...................................................................................................................375 Output Value of SO1n Pin (Last Bit) .......................................................................................................376 Block Diagram of Serial Interface CSIA0 ................................................................................................380 Format of Automatic Data Transfer Address Count Register 0 (ADTC0)................................................381 Format of Serial Operation Mode Specification Register 0 (CSIMA0) ....................................................382 Format of Serial Status Register 0 (CSIS0) ............................................................................................383 Format of Serial Trigger Register 0 (CSIT0) ...........................................................................................385 Format of Divisor Selection Register 0 (BRGCA0) .................................................................................386 Format of Automatic Data Transfer Address Point Specification Register 0 (ADTP0) ............................386 Format of Automatic Data Transfer Interval Specification Register 0 (ADTI0) ........................................388 Format of Port Mode Register 14 (PM14) ...............................................................................................389 3-Wire Serial I/O Mode Timing................................................................................................................393 Format of Transmit/Receive Data ...........................................................................................................394 Transfer Bit Order Switching Circuit........................................................................................................395 Automatic Transmission/Reception Mode Operation Timings ................................................................399 Automatic Transmission/Reception Mode Flowchart ..............................................................................400 Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) ........................................................................................401 Automatic Transmission Mode Operation Timing ...................................................................................403 Automatic Transmission Mode Flowchart ...............................................................................................404 Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) ...................405 Repeat Transmission Mode Operation Timing........................................................................................407 Repeat Transmission Mode Flowchart....................................................................................................408 Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) .......................409 Format of CSIA0 Transmit/Receive Data................................................................................................411 Automatic Transmission/Reception Suspension and Restart .................................................................412 System Configuration When Busy Control Option Is Used .....................................................................413 Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1) ........................................414 Busy Signal and Wait Release (When BUSYLV0 = 1)............................................................................414 Operation Timing When Busy & Strobe Control Options Are Used (When BUSYLV0 = 1).....................415 Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 0)........................416 Automatic Transmit/Receive Interval Time .............................................................................................417 17-10 17-11 17-12 17-13 17-14 17-15 17-16 17-17 17-18 17-19 17-20 17-21 17-22 17-23 17-24 17-25 17-26 17-27 17-28 17-29 26 User's Manual U15947EJ2V0UD LIST OF FIGURES (8/10) Figure No. Title Page 18-1 18-2 18-3 18-4 18-5 18-6 18-7 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 www..com Block Diagram of Multiplier/Divider......................................................................................................... 419 Format of Remainder Data Register 0 (SDR0) ....................................................................................... 420 Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L) ................................................... 421 Format of Multiplication/Division Data Register B0 (MDB0).................................................................... 422 Format of Multiplier/Divider Control Register 0 (DMUC0) ....................................................................... 423 Timing Chart of Multiplication Operation (00DAH x 0093H) ................................................................... 425 Timing Chart of Division Operation (DCBA2586H / 0018H)................................................................... 427 Basic Configuration of Interrupt Function ............................................................................................... 431 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) .................................................... 434 Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) ................................................ 435 Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H)......................................... 436 Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN)................................................................... 437 Format of Program Status Word............................................................................................................. 438 Interrupt Request Acknowledgment Processing Algorithm ..................................................................... 440 Interrupt Request Acknowledgment Timing (Minimum Time) ................................................................. 441 Interrupt Request Acknowledgment Timing (Maximum Time) ................................................................ 441 Examples of Multiple Interrupt Servicing ................................................................................................ 443 Interrupt Request Hold ........................................................................................................................... 445 Block Diagram of Key Interrupt............................................................................................................... 446 Format of Key Return Mode Register (KRM).......................................................................................... 447 Format of Oscillation Stabilization Time Counter Status Register (OSTC) ............................................. 450 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................... 451 HALT Mode Release by Interrupt Request Generation .......................................................................... 454 HALT Mode Release by RESET Input.................................................................................................... 455 Operation Timing When STOP Mode Is Released ................................................................................. 458 STOP Mode Release by Interrupt Request Generation.......................................................................... 459 STOP Mode Release by RESET Input ................................................................................................... 460 Block Diagram of Reset Function ........................................................................................................... 462 Timing of Reset by RESET Input............................................................................................................ 463 Timing of Reset Due to Watchdog Timer Overflow................................................................................. 463 Timing of Reset in STOP Mode by RESET Input ................................................................................... 464 Format of Reset Control Flag Register (RESF) ...................................................................................... 468 Block Diagram of Clock Monitor ............................................................................................................. 469 Format of Clock Monitor Mode Register (CLM) ...................................................................................... 470 Timing of Clock Monitor .......................................................................................................................... 472 User's Manual U15947EJ2V0UD 19-10 19-11 20-1 20-2 21-1 21-2 21-3 21-4 21-5 21-6 21-7 22-1 22-2 22-3 22-4 22-5 23-1 23-2 23-3 27 LIST OF FIGURES (9/10) Figure No. Title Page 24-1 24-2 24-3 25-1 25-2 25-3 25-4 25-5 25-6 26-1 26-2 28-1 28-2 28-3 28-4 www..com Block Diagram of Power-on-Clear Circuit ...............................................................................................477 Timing of Internal Reset Signal Generation in Power-on-Clear Circuit ...................................................477 Example of Software Processing After Release of Reset .......................................................................478 Block Diagram of Low-Voltage Detector .................................................................................................480 Format of Low-Voltage Detection Register (LVIM) .................................................................................482 Format of Low-Voltage Detection Level Selection Register (LVIS).........................................................483 Timing of Low-Voltage Detector Internal Reset Signal Generation.........................................................485 Timing of Low-Voltage Detector Interrupt Signal Generation..................................................................487 Example of Software Processing After Release of Reset .......................................................................489 Block Diagram of Regulator Periphery....................................................................................................492 REGC Pin Connection ............................................................................................................................493 Format of Internal Memory Size Switching Register (IMS) .....................................................................496 Format of Internal Expansion RAM Size Switching Register (IXS) .........................................................497 Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode ......................500 Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode .............501 Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode.....................................502 Example of Wiring Adapter for Flash Memory Writing in UART (UART0 + HS) Mode............................503 Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode.....................................504 Environment for Writing Program to Flash Memory ................................................................................505 Communication with Dedicated Flash Programmer (CSI10)...................................................................505 Communication with Dedicated Flash Programmer (CSI10 + HS)..........................................................506 Communication with Dedicated Flash Programmer (UART0).................................................................506 Communication with Dedicated Flash Programmer (UART0 + HS)........................................................507 Communication with Dedicated Flash Programmer (UART6).................................................................507 Example of Connection of VPP Pin ..........................................................................................................509 Signal Collision (Input Pin of Serial Interface).........................................................................................510 Malfunction of Other Device....................................................................................................................511 Signal Collision (RESET Pin)..................................................................................................................512 Flash Memory Manipulation Procedure ..................................................................................................513 Flash Memory Programming Mode.........................................................................................................514 Communication Commands....................................................................................................................515 Development Tool Configuration ............................................................................................................600 Distance Between IE System and Conversion Adapter ..........................................................................609 Connection Conditions of Target System (When Using NP-80GC-TQ) ..................................................610 Connection Conditions of Target System (When Using NP-H80GC-TQ)................................................611 Connection Conditions of Target System (When Using NP-80GK) ........................................................612 User's Manual U15947EJ2V0UD 28-5 28-6 28-7 28-8 28-9 28-10 28-11 28-12 28-13 28-14 28-15 28-16 28-17 28-18 28-19 28-20 A-1 B-1 B-2 B-3 B-4 28 LIST OF FIGURES (10/10) Figure No. B-5 Title Page Connection Conditions of Target System (When Using NP-H80GK-TQ) ............................................... 613 www..com User's Manual U15947EJ2V0UD 29 LIST OF TABLES (1/3) Table No. 1-1 2-1 2-2 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 4-4 4-5 5-1 www..com Title Page Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions ...................................37 Pin I/O Buffer Power Supplies ..................................................................................................................47 Pin I/O Circuit Types .................................................................................................................................57 Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS).....................................................................61 Internal ROM Capacity..............................................................................................................................67 Vector Table .............................................................................................................................................67 Internal Expansion RAM Capacity ............................................................................................................68 Special Function Register List ..................................................................................................................80 Pin I/O Buffer Power Supplies ..................................................................................................................96 Port Functions...........................................................................................................................................97 Port Configuration .....................................................................................................................................98 Pull-up Resistor of Port 6 ........................................................................................................................113 Settings of Port Mode Register and Output Latch When Using Alternate Function ................................124 Pin Functions in External Memory Expansion Mode...............................................................................129 State of Ports 4 to 6 Pins in External Memory Expansion Mode.............................................................129 Configuration of Clock Generator ...........................................................................................................141 Relationship Between CPU Clock and Minimum Instruction Execution Time .........................................145 Relationship Between Operation Clocks in Each Operation Status ........................................................160 Oscillation Control Flags and Clock Oscillation Status ...........................................................................160 Maximum Time Required to Switch Between Ring-OSC Clock and X1 Input Clock ...............................161 Maximum Time Required for CPU Clock Switchover..............................................................................162 Clock and Register Setting .....................................................................................................................167 Configuration of 16-Bit Timer/Event Counters 00 and 01........................................................................169 CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins ........................................................172 CR01n Capture Trigger and Valid Edge of TI00n Pin (CRC0n2 = 1) ......................................................173 Configuration of 8-Bit Timer/Event Counters 50 and 51..........................................................................214 Configuration of 8-Bit Timers H0 and H1 ................................................................................................230 Watch Timer Interrupt Time ....................................................................................................................256 Interval Timer Interval Time ....................................................................................................................256 Watch Timer Configuration .....................................................................................................................257 Watch Timer Interrupt Time ....................................................................................................................259 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 7-3 8-1 9-1 10-1 10-2 10-3 10-4 30 User's Manual U15947EJ2V0UD LIST OF TABLES (2/3) Table No. Title Page 10-5 11-1 11-2 11-3 12-1 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 14-5 www..com Interval Timer Interval Time .................................................................................................................... 260 Loop Detection Time of Watchdog Timer ............................................................................................... 262 Mask Option Setting and Watchdog Timer Operation Mode .................................................................. 263 Configuration of Watchdog Timer ........................................................................................................... 264 Clock Output/Buzzer Output Controller Configuration ............................................................................ 273 Registers of A/D Converter Used on Software ....................................................................................... 278 Settings of ADCS and ADCE.................................................................................................................. 282 A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)........................ 297 Resistance and Capacitance Values of Equivalent Circuit (Reference Values)...................................... 298 Configuration of Serial Interface UART0 ................................................................................................ 300 Relationship Between Register Settings and Pins.................................................................................. 309 Cause of Reception Error ....................................................................................................................... 314 Set Data of Baud Rate Generator........................................................................................................... 317 Maximum/Minimum Permissible Baud Rate Error .................................................................................. 319 Configuration of Serial Interface UART6 ................................................................................................ 324 Relationship Between Register Settings and Pins.................................................................................. 337 Cause of Reception Error ....................................................................................................................... 347 Set Data of Baud Rate Generator........................................................................................................... 354 Maximum/Minimum Permissible Baud Rate Error .................................................................................. 356 Configuration of Serial Interfaces CSI10 and CSI11............................................................................... 359 Relationship Between Register Settings and Pins.................................................................................. 369 SO1n Output Status ............................................................................................................................... 377 Configuration of Serial Interface CSIA0.................................................................................................. 379 Relationship Between Buffer RAM Address Values and ADTP0 Setting Values .................................... 387 Relationship Between Register Settings and Pins.................................................................................. 392 Relationship Between Register Settings and Pins.................................................................................. 397 Configuration of Multiplier/Divider........................................................................................................... 418 Functions of MDA0 During Operation Execution .................................................................................... 422 Interrupt Source List ............................................................................................................................... 429 Flags Corresponding to Interrupt Request Sources................................................................................ 433 Ports Corresponding to EGPn and EGNn .............................................................................................. 437 Time from Generation of Maskable Interrupt Request Until Servicing .................................................... 439 User's Manual U15947EJ2V0UD 15-1 15-2 15-3 15-4 15-5 16-1 16-2 16-3 17-1 17-2 17-3 17-4 18-1 18-2 19-1 19-2 19-3 19-4 31 LIST OF TABLES (3/3) Table No. Title Page 19-5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing .......................................................................................................................442 20-1 20-2 21-1 21-2 21-3 21-4 21-5 22-1 22-2 23-1 23-2 www..com Assignment of Key Interrupt Detection Pins............................................................................................446 Configuration of Key Interrupt .................................................................................................................446 Relationship Between Operation Clocks in Each Operation Status ........................................................448 Operating Statuses in HALT Mode .........................................................................................................452 Operation in Response to Interrupt Request in HALT Mode...................................................................456 Operating Statuses in STOP Mode.........................................................................................................457 Operation in Response to Interrupt Request in STOP Mode ..................................................................460 Hardware Statuses After Reset Acknowledgment ..................................................................................465 RESF Status When Reset Request Is Generated ..................................................................................468 Configuration of Clock Monitor................................................................................................................469 Operation Status of Clock Monitor (When CLME = 1) ............................................................................471 Flash Memory Versions Supporting Mask Options of Mask ROM Versions ...........................................494 Differences Between PD78F0148 and Mask ROM Versions ................................................................495 Internal Memory Size Switching Register Settings .................................................................................496 Internal Expansion RAM Size Switching Register Settings.....................................................................497 Wiring Between PD78F0148 and Dedicated Flash Programmer ..........................................................498 Pin Connection .......................................................................................................................................508 Pins Used by Each Serial Interface ........................................................................................................510 Communication Modes ...........................................................................................................................514 Flash Memory Control Commands .........................................................................................................515 Response Commands ............................................................................................................................515 Operand Identifiers and Specification Methods ......................................................................................516 Surface Mounting Type Soldering Conditions.........................................................................................593 Registers That Generate Wait and Number of CPU Wait Clocks ...........................................................597 Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter)........598 Distance Between IE System and Conversion Adapter ..........................................................................609 27-1 28-1 28-2 28-3 28-4 28-5 28-6 28-7 28-8 28-9 29-1 34-1 35-1 35-2 B-1 32 User's Manual U15947EJ2V0UD CHAPTER 1 OUTLINE 1.1 Features Minimum instruction execution time can be changed from high speed (0.2 s: @ 10 MHz operation with X1 input clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits x 32 registers (8 bits x 8 registers x 4 banks) ROM, RAM capacities Item Program Memory (ROM) Part Number Data Memory Internal High-Speed RAM Mask ROM 24 KB 32 KB 48 KB 60 KB Flash memory 60 KB Note Internal Expansion RAM - PD780143 PD780144 PD780146 PD780148 PD78F0148 1024 bytes 1024 bytes 1024 bytes Note Note The internal flash memory and internal expansion RAM capacities can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). Buffer RAM: 32 bytes (can be used for transfer in 3-wire serial I/O mode with automatic transmit/receive function) www..com External memory expansion space: 64 KB (with external bus interface function) On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) Short startup is possible via the CPU default start using the on-chip Ring-OSC On-chip clock monitor function using on-chip Ring-OSC On-chip watchdog timer (operable with Ring-OSC clock) On-chip multiplier/divider On-chip key interrupt function On-chip clock output/buzzer output controller On-chip regulator I/O ports: 67 (N-ch open drain: 4) Timer PD780143, 780144: 7 channels PD780146, 780148, 78F0148: 8 channels Serial interface PD780143, 780144: 3 channels (UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI/UART automatic transmit/receive function: 1 channel) PD780146, 780148, 78F0148: 4 channels (UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI: 1 channel, CSI/UART CSI with automatic transmit/receive function: 1 channel) 10-bit resolution A/D converter: 8 channels Note Select either of the functions of these alternate-function pins. Note Note : 1 channel, CSI with : 1 channel, User's Manual U15947EJ2V0UD 33 CHAPTER 1 OUTLINE Supply voltage: VDD = 2.7 to 5.5 V (standard product, (A) grade product) VDD = 3.3 to 5.5 V ((A1) grade product, (A2) grade product) Operating ambient temperature: TA = -40 to +85C (standard product, (A) grade product) TA = -40 to +105C (flash memory version of (A1) grade product) TA = -40 to +110C (mask ROM version of (A1) grade product) TA = -40 to +125C (mask ROM version of (A2) grade product) 1.2 Applications Automotive equipment * System control for body electricals (power windows, keyless entry reception, etc.) * Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances * Outdoor air conditioner units * Microwave ovens, electric rice cookers Industrial equipment * Pumps * Vending machines * FA (Factory Automation) www..com 34 User's Manual U15947EJ2V0UD CHAPTER 1 OUTLINE 1.3 Ordering Information (1) Mask ROM versions Part Number Package 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special PD780143GK-xxx-9EU PD780143GC-xxx-8BT PD780144GK-xxx-9EU PD780144GC-xxx-8BT PD780146GK-xxx-9EU PD780146GC-xxx-8BT PD780148GK-xxx-9EU PD780148GC-xxx-8BT PD780143GK(A)-xxx-9EU PD780143GC(A)-xxx-8BT PD780144GK(A)-xxx-9EU PD780144GC(A)-xxx-8BT PD780146GK(A)-xxx-9EU PD780146GC(A)-xxx-8BT PD780148GK(A)-xxx-9EU PD780148GC(A)-xxx-8BT PD780143GK(A1)-xxx-9EU PD780143GC(A1)-xxx-8BT www..com PD780144GK(A1)-xxx-9EU PD780144GC(A1)-xxx-8BT PD780146GK(A1)-xxx-9EU PD780146GC(A1)-xxx-8BT PD780148GK(A1)-xxx-9EU PD780148GC(A1)-xxx-8BT PD780143GK(A2)-xxx-9EU PD780143GC(A2)-xxx-8BT PD780144GK(A2)-xxx-9EU PD780144GC(A2)-xxx-8BT PD780146GK(A2)-xxx-9EU PD780146GC(A2)-xxx-8BT PD780148GK(A2)-xxx-9EU PD780148GC(A2)-xxx-8BT Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. User's Manual U15947EJ2V0UD 35 CHAPTER 1 OUTLINE (2) Flash memory versions Part Number Package 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special Special PD78F0148M1GK-9EU PD78F0148M1GC-8BT PD78F0148M2GK-9EU PD78F0148M2GC-8BT PD78F0148M3GK-9EU PD78F0148M3GC-8BT PD78F0148M4GK-9EU PD78F0148M4GC-8BT PD78F0148M5GK-9EU PD78F0148M5GC-8BT PD78F0148M6GK-9EU PD78F0148M6GC-8BT PD78F0148M1GK(A)-9EU PD78F0148M1GC(A)-8BT PD78F0148M2GK(A)-9EU PD78F0148M2GC(A)-8BT PD78F0148M3GK(A)-9EU PD78F0148M3GC(A)-8BT PD78F0148M4GK(A)-9EU PD78F0148M4GC(A)-8BT www..com PD78F0148M5GK(A)-9EU PD78F0148M5GC(A)-8BT PD78F0148M6GK(A)-9EU PD78F0148M6GC(A)-8BT PD78F0148M1GK(A1)-9EU PD78F0148M1GC(A1)-8BT PD78F0148M2GK(A1)-9EU PD78F0148M2GC(A1)-8BT PD78F0148M5GK(A1)-9EU PD78F0148M5GC(A1)-8BT PD78F0148M6GK(A1)-9EU PD78F0148M6GC(A1)-8BT Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. 36 User's Manual U15947EJ2V0UD CHAPTER 1 OUTLINE Mask ROM versions (PD780143, 780144, 780146, and 780148) include mask options. When ordering, it is possible to select "Power-on-clear (POC) circuit can be used/cannot be used", "Ring-OSC clock can be stopped/cannot be stopped by software" and "Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to P63)". Flash memory versions corresponding to the mask options of the mask ROM versions are as follows. Table 1-1. Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions Mask Option POC Circuit POC cannot be used Ring-OSC Cannot be stopped Flash Memory Versions (Part Number) PD78F0148M1GK-9EU PD78F0148M1GC-8BT PD78F0148M1GK(A)-9EU PD78F0148M1GC(A)-8BT PD78F0148M1GK(A1)-9EU PD78F0148M1GC(A1)-8BT PD78F0148M2GK-9EU PD78F0148M2GC-8BT PD78F0148M2GK(A)-9EU PD78F0148M2GC(A)-8BT PD78F0148M2GK(A1)-9EU PD78F0148M2GC(A1)-8BT PD78F0148M3GK-9EU PD78F0148M3GC-8BT PD78F0148M3GK(A)-9EU PD78F0148M3GC(A)-8BT PD78F0148M4GK-9EU PD78F0148M4GC-8BT PD78F0148M4GK(A)-9EU PD78F0148M4GC(A)-8BT PD78F0148M5GK-9EU PD78F0148M5GC-8BT PD78F0148M5GK(A)-9EU PD78F0148M5GC(A)-8BT PD78F0148M5GK(A1)-9EU PD78F0148M5GC(A1)-8BT PD78F0148M6GK-9EU PD78F0148M6GC-8BT PD78F0148M6GK(A)-9EU PD78F0148M6GC(A)-8BT PD78F0148M6GK(A1)-9EU PD78F0148M6GC(A1)-8BT Can be stopped by software POC used (VPOC = 2.85 V 0.15 V) Cannot be stopped www..com Can be stopped by software POC used (VPOC = 3.5 V 0.2 V) Cannot be stopped Can be stopped by software User's Manual U15947EJ2V0UD 37 CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) * 80-pin plastic TQFP (fine pitch) (12 x 12) * 80-pin plastic QFP (14 x 14) P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P70/KR0 P71/KR1 P72/KR2 P73/KR3 P74/KR4 P75/KR5 P76/KR6 P77/KR7 P40/AD0 P41/AD1 P42/AD2 P43/AD3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVREF AVSS P120/INTP0 P33/TI51/TO51/INTP4 P32/INTP3 P31/INTP2 P30/INTP1 IC (VPP) VDD REGC VSS X1 X2 RESET XT1 XT2 P130 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P00/TI000 P01/TI010/TO00 P02/SO11Note P03/SI11Note www..com Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. Cautions 1. Connect the IC (Internally Connected) pin directly to VSS. 2. Connect the AVSS pin to VSS. 3. Connect the REGC pin as follows. Standard Product and (A) Grade Product When regulator is used When regulator is not used Connect to VSS via a capacitor (1 F: recommended) Connect directly to VDD (A1) Grade Product and (A2) Grade Product - (Regulator cannot be used.) 4. Connect the VPP pin to EVSS or VSS during normal operation. Remark Figures in parentheses apply only to the PD78F0148. User's Manual U15947EJ2V0UD 38 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P140/PCL/INTP6 P141/BUZ/BUSY0/INTP7 P63 P62 EVSS EVDD P61 P60 P142/SCKA0 P143/SIA0 P144/SOA0 P145/STB0 P06/TI011Note/TO01Note P05/SSI11Note/TI001Note P04/SCK11Note CHAPTER 1 OUTLINE Pin Identification A8 to A15: AD0 to AD7: ANI0 to ANI7: ASTB: AVREF: AVSS: BUSY0: BUZ: EVDD: EVSS: IC: KR0 to KR7: P00 to P06: P10 to P17: P20 to P27: P30 to P33: P40 to P47: P50 to P57: P60 to P67: P70 to P77: P120: www..com Address bus Address/data bus Analog input Address strobe Analog reference voltage Analog ground Serial busy input Buzzer output Power supply for port Ground for port Internally connected Key return Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Port 13 Port 14 Programmable clock output REGC: RESET: RxD0, RxD6: RD: SCK10, SCK11Note, SCKA0: SI10, SI11 SOA1: SSI11Note: STB0: TI000, TI010, TI001Note, TI011Note, TI50, TI51: TO00, TO01 Note Note Regulator capacitance Reset Receive data Read strobe Serial clock input/output , SIA0: Serial data input Serial data output Serial interface chip select input Serial strobe SO10, SO11Note, INTP0 to INTP7: External interrupt input Timer input , Timer output Transmit data Power supply Programming power supply Ground Wait Write strobe Crystal oscillator (X1 input clock) Crystal oscillator (Subsystem clock) TO50, TO51, TOH0, TOH1: TxD0, TxD6: VDD: VPP: VSS: WAIT: WR: X1, X2: XT1, XT2: P130: P140 to P145: PCL: Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. User's Manual U15947EJ2V0UD 39 CHAPTER 1 OUTLINE 1.5 1.5.1 K1 Family Lineup 78K0/Kx1 product lineup 78K0/KB1: 30-pin (7.62 mm 0.65 mm pitch) PD78F0103 PD780103 PD780102 PD780101 Flash memory: 24 KB, RAM: 768 bytes Mask ROM: 24 KB, RAM: 768 bytes Mask ROM: 16 KB, RAM: 768 bytes Mask ROM: 8 KB, RAM: 512 bytes 78K0/KC1: 44-pin (10 x 10 mm 0.8 mm pitch) PD78F0114 PD780114 PD780113 PD780112 PD780111 Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes 78K0/KD1: 52-pin (10 x 10 mm 0.65 mm pitch) PD78F0124 PD780124 PD780123 www..com Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes PD780122 PD780121 78K0/KE1: 64-pin (10 x 10 mm 0.5 mm pitch, 12 x 12 mm 0.65 mm pitch, 14 x 14 mm 0.8 mm pitch) PD78F0134 PD780134 PD780133 PD780132 PD780131 Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes PD78F0138 PD780138 Flash memory: 60 KB, RAM: 2 KB Mask ROM: 60 KB, RAM: 2 KB Mask ROM: 48 KB, RAM: 2 KB PD780136 78K0/KF1: 80-pin (12 x 12 mm 0.5 mm pitch, 14 x 14 mm 0.65 mm pitch) PD78F0148 PD780148 PD780146 PD780144 PD780143 Flash memory: 60 KB, RAM: 2 KB Mask ROM: 60 KB, RAM: 2 KB Mask ROM: 48 KB, RAM: 2 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB 40 User's Manual U15947EJ2V0UD CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number Item Package Internal memory (bytes) Mask ROM 30 pins 8 K 16 K 24 K Flash memory RAM Power supply voltage Minimum instruction execution time 0.2 s (when 10 MHz, VDD = 4.0 to 5.5 V) 0.24 s (when 8.38 MHz, VDD = 3.3 to 5.5 V) 0.4 s (when 5 MHz, VDD = 2.7 to 5.5 V) - 512 - 24 K 768 512 - 44 pins 8 K 24 K 16 K 32 K - 32 K 1K 512 - 52 pins 8 K 24 K 16 K 32 K - 32 K 1K 512 - 64 pins 8 K 24 K 16 K 32 K - 32 K 1K - 48 K 60 K - 60 K 2K 1K - 80 pins 24 K 48 K 32 K 60 K - 60 K 2K - 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 VDD = 2.7 to 5.5 V Clock X1 input Sub Ring-OSC 2 to 10 MHz 32.768 kHz 240 kHz (TYP.) 17 4 1 - 1 ch 1 ch 2 ch - 1 ch Note Port CMOS I/O CMOS input CMOS output N-ch open-drain I/O 19 26 8 38 54 4 2 ch 2 ch 1 ch 2 ch Timer 16 bits (TM0) 8 bits (TM5) www..com 8 bits (TMH) For watch WDT Serial 3-wire CSI interface Automatic transmit/ receive 3-wire CSI UART Note 1 ch 1 ch - - 1 ch 1 ch 4 ch 6 11 - 12 4 ch Provided 7 15 8 16 8 ch 9 2 ch 1 ch 2 ch 1 ch UART supporting LIN-bus 10-bit A/D converter Interrupt External Internal Key return input Reset RESET pin POC LVI Clock monitor WDT Multiplier/divider ROM correction Standby function Operating ambient temperature - - 9 19 17 20 8 ch 2.85 V 0.15 V/3.5 V 0.20 V (selectable by mask option) 3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Provided Provided 16 bits x 16 bits, 32 bits / 16 bits Provided HALT/STOP mode Standard products, special (A) products: -40 to +85C Special (A1) products: -40 to +110C (mask ROM version), -40 to +105C (flash memory version) Special (A2) products: -40 to +125C (mask ROM version) - Note Select either of the functions of these alternate-function pins. User's Manual U15947EJ2V0UD 41 CHAPTER 1 OUTLINE 1.5.2 V850ES/Kx1 product lineup V850ES/KF1 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) PD703208 PD703208Y PD703209 PD703209Y PD703210 PD703210Y PD70F3210 PD70F3210Y Mask ROM: 64 KB, RAM: 4 KB I2C products Mask ROM: 96 KB, RAM: 4 KB I2C products Mask ROM: 128 KB, RAM: 6 KB I2C products Flash memory: 128 KB, RAM: 6 KB I2C products V850ES/KG1 100-pin plastic LQFP (fine pitch) (14 x 14) PD703212 PD703212Y PD703213 PD703213Y www..com Mask ROM: 64 KB, RAM: 4 KB I2C products Mask ROM: 96 KB, RAM: 4 KB I2C products Mask ROM: 128 KB, RAM: 6 KB I2C products Flash memory: 128 KB, RAM: 6 KB I2C products PD703214 PD703214Y PD70F3214 PD70F3214Y V850ES/KJ1 144-pin plastic LQFP (fine pitch) (20 x 20) PD703216 PD703216Y PD703217 PD703217Y PD70F3217 PD70F3217Y Mask ROM: 96 KB, RAM: 6 KB I2C products Mask ROM: 128 KB, RAM: 6 KB I2C products Flash memory: 128 KB, RAM: 6 KB I2C products 42 User's Manual U15947EJ2V0UD CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Function Part No. Timer 8-Bit 16-Bit TMH Watch WDT 2 ch 2 ch 2 ch 1 ch 2 ch CSI 2 ch Serial Interface CSIA 1 ch UART 2 ch IC - 1 ch - 1 ch - 1 ch - 1 ch 2 ch 4 ch 2 ch 1 ch 2 ch 2 ch 2 ch 2 ch - 1 ch - 1 ch - 1 ch - 1 ch 2 ch 6 ch 2 ch 1 ch 2 ch 3 ch 2 ch 3 ch - 2 ch - 2 ch - 2 ch 16 ch 2 ch 12 ch 128 - 8 ch 2 ch 6 ch 84 - 8 ch - 6 ch 67 - 2 A/D D/A RTO I/O Other PD703208 PD703208Y V850ES/KF1 V850ES/KG1 www..com PD703209 PD703209Y PD703210 PD703210Y PD70F3210 PD70F3210Y PD703212 PD703212Y PD703213 PD703213Y PD703214 PD703214Y PD70F3214 PD70F3214Y PD703216 PD703216Y PD703217 PD703217Y PD70F3217 PD70F3217Y V850ES/KJ1 User's Manual U15947EJ2V0UD 43 CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 TI000/P00 16-bit timer/ event counter 00 Port 0 7 P00 to P06 Port 1 TO01Note/TI011Note/P06 TI001Note/P05 16-bit timer/Note event counter 01 8 P10 to P17 Port 2 8 P20 to P27 TOH0/P15 8-bit timer H0 Port 3 4 P30 to P33 Port 4 TOH1/P16 8-bit timer H1 Port 5 TI50/TO50/P17 8-bit timer/ event counter 50 8 P40 to P47 8 P50 to P57 Port 6 8 P60 to P67 TI51/TO51/P33 8-bit timer/ event counter 51 Port 7 8 P70 to P77 Port 12 Watch timer Port 13 Watchdog timer 78K/0 CPU core ROM (Flash memory) P120 P130 Port 14 6 P140 to P145 RxD0/P11 TxD0/P10 Serial interface UART0 Buzzer output BUZ/P141 RxD6/P14 TxD6/P13 www..com Serial interface UART6 Internal high-speed RAM Internal expansion RAMNote Clock output control PCL/P140 SI10/P11 SO10/P12 SCK10/P10 SI11Note/P03 SO11Note/P02 SCK11Note/P04 SSI11Note/P05 SIA0/P143 SOA0/P144 SCKA0/P142 STB0/P145 BUSY0/P141 ANI0/P20 to ANI7/P27 AVREF AVSS INTP0/P120 INTP1/P30 to INTP4/P33 INTP5/P16 INTP6/P140, INTP7/P141 2 4 8 Serial interface CSI10 Clock monitor Power on clear/ low voltage indicator Key return 8 POC/LVI control KR0/P70 to KR7/P77 Serial interface CSI11Note Reset control Serial interface CSIA0 8 8 External access A/D converter AD0/P40 to AD7/P47 A8/P50 to A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 Ring-OSC Interrupt control RESET X1 X2 XT1 XT2 System control Multiplier & divider IC VDD, VSS, EVDD EVSS (VPP) Voltage regulator REGC Note PD780146, 780148, and 78F0148 only. Remark Items in parentheses are available only in the PD78F0148. User's Manual U15947EJ2V0UD 44 CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) Item PD780143 24 KB PD780144 32 KB PD780146 48 KB PD780148 60 KB PD78F0148 60 KB Note Internal memory ROM (flash memory) High-speed RAM Expansion RAM Buffer RAM Memory space X1 input clock (oscillation frequency) Standard products, (A) grade products (A1) grade products (A2) grade products Ring-OSC clock (oscillation frequency) Subsystem clock (oscillation frequency) www..com 1 KB - 32 bytes 64 KB Ceramic/crystal/external clock oscillation REGC pin is connected directly to VDD: 10 MHz (VDD = 4.0 to 5.5 V), 8.38 MHz (VDD = 3.3 to 5.5 V), 5 MHz (VDD = 2.7 to 5.5 V) 1 F capacitor is connected to REGC pin: 8.38 MHz (VDD = 4.0 to 5.5 V) REGC pin is connected directly to VDD: 10 MHz (VDD = 4.5 to 5.5 V), 8.38 MHz (VDD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V) REGC pin is connected directly to VDD: 8.38 MHz (VDD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V) On-chip Ring oscillation (240 kHz (TYP.)) Note 1 KB 1 KB Crystal/external clock oscillation (32.768 kHz) 8 bits x 32 registers (8 bits x 8 registers x 4 banks) 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (X1 input clock: @ fXP = 10 MHz operation) 8.3 s/16.6 s/33.2 s/66.4 s/132.8 s (TYP.) (Ring-OSC clock: @ fR = 240 kHz (TYP.) operation) 122 s (subsystem clock: @ fXT = 32.768 kHz operation) General-purpose registers Minimum instruction execution time Instruction set * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * BCD adjust, etc. * Bit manipulate (set, reset, test, and Boolean operation) I/O ports Total: CMOS I/O CMOS input CMOS output N-ch open-drain I/O Timers 67 54 8 1 4 * 16-bit timer/event counter: 2 channels (1 channel only in the PD780143, 780144) * 8-bit timer/event counter: 2 channels * 8-bit timer: * Watch timer * Watchdog timer: Timer outputs 5 (PWM output: 3) 2 channels 1 channel 1 channel 6 (PWM output: 3) Clock output * 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (X1 input clock: 10 MHz) * 32.768 kHz (subsystem clock: 32.768 kHz) Buzzer output 1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (X1 input clock: 10 MHz) Note The internal flash memory capacity and internal expansion RAM capacity can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). User's Manual U15947EJ2V0UD 45 CHAPTER 1 OUTLINE (2/2) Item A/D converter Serial interface PD780143 PD780144 PD780146 PD780148 PD78F0148 10-bit resolution x 8 channels * UART mode supporting LIN-bus: * 3-wire serial I/O mode: (None in the PD780143, 780144) 1 channel 1 channel * 3-wire serial I/O mode with automatic transmit/receive function: 1 channel Note * 3-wire serial I/O mode/UART mode : 1 channel Multiplier/divider * 16 bits x 16 bits = 32 bits (multiplication) * 32 bits / 16 bits = 32 bits remainder of 16 bits (division) Vectored interrupt sources Key interrupt Reset Internal External 17 9 Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7). * Reset using RESET pin * Internal reset by watchdog timer * Internal reset by clock monitor * Internal reset by power-on-clear * Internal reset by low-voltage detector Supply voltage Standard products, (A) grade products: VDD = 2.7 to 5.5 V (A1) grade products, (A2) grade products: VDD = 3.3 to 5.5 V Operating ambient temperature * Standard products, (A) grade products: TA = -40 to +85C * (A1) grade products: TA = -40 to +110C (mask ROM versions), -40 to +105C (flash memory versions) * (A2) grade products: TA = -40 to +125C (mask ROM versions) www..com 20 Package * 80-pin plastic QFP (14 x 14) * 80-pin plastic TQFP (fine pitch) (12 x 12) Note Select either of the functions of these alternate-function pins. An outline of the timer is shown below. 16-Bit Timer/ Event Counters 00 Note 1 and 01 TM00 Operation mode Function Interval timer External event counter Timer output PPG output PWM output Pulse width measurement Square-wave output Interrupt source TM01 Note 1 8-Bit Timer/ Event Counters 50 and 51 TM50 TM51 8-Bit Timers H0 and H1 Watch Timer Watchdog Timer TMH0 TMH1 Note 2 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 output 1 output - 2 inputs 1 output 2 1 output 1 output - 2 inputs 1 output 2 1 output - 1 output - 1 output 1 1 output - 1 output - 1 output 1 - 1 output - 1 output - 1 output 1 - 1 output - 1 output - 1 output 1 - - - - - - 1 - - - - - - - Notes 1. 2. Remark 16-bit timer/event counter 01 is available only in the PD780146, 780148, and 78F0148. The watch timer function and interval timer function can be used simultaneously. TM51 and TMH1 can be used in combination as a carrier generator mode. 46 User's Manual U15947EJ2V0UD CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply AVREF EVDD VDD Corresponding Pins P20 to P27 Port pins other than P20 to P27 Pins other than port pins (1) Port pins (1/2) Pin Name P00 P01 P02 P03 P04 www..com I/O I/O Function Port 0. 7-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. After Reset Input Alternate Function TI000 TI010/TO00 SO11 SI11 Note Note SCK11 SSI11 TI011 I/O Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input Note P05 P06 P10 P11 P12 P13 P14 P15 P16 P17 P20 to P27 Input Port 2. 8-bit input-only port. Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 4. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input Note /TI001 Note Note /TO01 Note SCK10/TxD0 SI10/RxD0 SO10 TxD6 RxD6 TOH0 TOH1/INTP5 TI50/TO50 ANI0 to ANI7 P30 to P32 I/O Input INTP1 to INTP3 P33 INTP4/TI51/TO51 P40 to P47 I/O Input AD0 to AD7 Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. User's Manual U15947EJ2V0UD 47 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name P50 to P57 I/O I/O Port 5. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 to P63 I/O Port 6. 8-bit I/O port. Input/output can be specified in 1-bit units. N-ch open-drain I/O port. Use of an on-chip pull-up resistor can be specified by a mask option only for mask ROM versions. Use of an on-chip pull-up resistor can be specified by a software setting. RD WR WAIT ASTB I/O Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. 1-bit I/O port. www..com Function After Reset Input Alternate Function A8 to A15 Input - P64 P65 P66 P67 P70 to P77 Input KR0 to KR7 Input INTP0 Use of an on-chip pull-up resistor can be specified by a software setting. P130 Output Port 13. 1-bit output-only port. P140 P141 I/O Port 14. 6-bit I/O port. Input/output can be specified in 1-bit units. P142 P143 P144 P145 Use of an on-chip pull-up resistor can be specified by a software setting. Input PCL/INTP6 BUZ/BUSY0/ INTP7 SCKA0 SIA0 SOA0 STB0 Output - 48 User's Manual U15947EJ2V0UD CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name INTP0 INTP1 to INTP3 INTP4 INTP5 INTP6 INTP7 SI10 SI11 Note I/O Input Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P120 P30 to P32 P33/TI51/TO51 P16/TOH1 P140/PCL P141/BUZ/BUSY0 Input Serial data input to serial interface Input P11/RxD0 P03 P143 SIA0 SO10 SO11 Note Output Serial data output from serial interface Input P12 P02 P144 SOA0 SCK10 SCK11 Note I/O Clock input/output for serial interface Input P10/TxD0 P04 P142 SCKA0 SSI11 Note Input Input Output Input Serial interface chip select input Serial interface busy input Serial interface strobe output Serial data input to asynchronous serial interface Input Input Input Input P05/TI001 P141/BUZ/INTP7 P145 P11/SI10 P14 BUSY0 STB0 RxD0 www..com RxD6 TxD0 TxD6 TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 External count clock input to 16-bit timer/event counter 01 Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01 Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 Capture trigger input to capture register (CR001) of 16-bit timer/event counter 01 Output Note Output Serial data output from asynchronous serial interface Input P10/SCK10 P13 Input P00 TI001 Note P05/SSI11 Note TI010 TI011 TO00 TO01 TI50 TI51 TO50 TO51 TOH0 TOH1 Output Note P01/TO00 P06/TO01 Input Note 16-bit timer/event counter 00 output 16-bit timer/event counter 01 output P01/TI010 P06/TI011 Note Input External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 8-bit timer/event counter 50 output 8-bit timer/event counter 51 output 8-bit timer H0 output 8-bit timer H1 output Input P17/TO50 P33/TO51/INTP4 Input P17/TI50 P33/TI51/INTP4 P15 P16/INTP5 Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. User's Manual U15947EJ2V0UD 49 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Pin Name PCL BUZ AD0 to AD7 A8 to A15 RD WR WAIT ASTB I/O Output Output I/O Output Output Output Input Output Function Clock output (for trimming of X1 input clock, subsystem clock) Buzzer output Lower address/data bus for external memory expansion Higher address bus for external memory expansion Strobe signal output for external memory read operation Strobe signal output for external memory write operation Wait insertion on external memory access Strobe output that externally latches address information output to ports 4 and 5 for access to external memory ANI0 to ANI7 AVREF Input Input - A/D converter analog input A/D converter reference voltage input and positive power supply for port 2 AVSS A/D converter ground potential. Make the same potential as EVSS or VSS. KR0 to KR7 REGC Input - Key interrupt input Connecting regulator output stabilization capacitor. When using the regulator, connect to VSS via a capacitor (1 F: recommended). When the regulator is not used, connect directly to VDD. www..com After Reset Input Input Input Input Input Input Input Input Alternate Function P140/INTP6 P141/INTP7/BUSY0 P40 to P47 P50 to P57 P64 P65 P66 P67 Input - - P20 to P27 - - Input - P70 to P77 - RESET X1 X2 XT1 XT2 VDD EVDD VSS EVSS IC VPP Input Input - Input - - - - - - - System reset input Connecting resonator for X1 input clock oscillation - - - - - - - - - - - - - - Connecting resonator for subsystem clock oscillation - - Positive power supply (except for ports) Positive power supply for ports Ground potential (except for ports) Ground potential for ports Internally connected. Connect directly to EVSS or VSS. Flash memory programming mode setting. High-voltage application for program write/verify. Connect to EVSS or VSS in normal operation mode. - - - - - - 50 User's Manual U15947EJ2V0UD CHAPTER 2 PIN FUNCTIONS 2.2 2.2.1 Description of Pin Functions P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P06 function as a 7-bit I/O port. P00 to P06 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input. (a) TI000, TI001Note These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit timer/event counters 00 and 01. (b) TI010, TI011Note These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event counters 00 and 01. (c) TO00, TO01Note www..com These are timer output pins. (d) SI11Note This is a serial interface serial data input pin. (e) SO11Note This is a serial interface serial data output pin. (f) SCK11Note This is a serial interface serial clock I/O pin. (g) SSI11Note This is a serial interface chip select input pin. Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. User's Manual U15947EJ2V0UD 51 CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. (a) SI10 This is a serial interface serial data input pin. (b) SO10 This is a serial interface serial data output pin. (c) SCK10 This is a serial interface serial clock I/O pin. (d) RxD0, RxD6 These are the serial data input pins of the asynchronous serial interface. www..com (e) TxD0, TxD6 These are the serial data output pins of the asynchronous serial interface. (f) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (g) TO50, TOH0, and TOH1 These are timer output pins. (h) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 P20 to P27 (port 2) P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit input-only port. (2) Control mode P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input pins, see (5) ANI0/P20 to ANI7/P27 in 13.6 Cautions for A/D Converter. 52 User's Manual U15947EJ2V0UD CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input pins and timer I/O pins. (a) INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin. 2.2.5 P40 to P47 (port 4) P40 to P47 function as an 8-bit I/O port. These pins also function as address/data bus pins. www..com The following operation modes can be specified. (1) Port mode P40 to P47 function as an 8-bit I/O port. P40 to P47 can be set to input or output in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4). (2) Control mode P40 to P47 function as the pins for the lower address/data bus (AD0 to AD7) in external memory expansion mode. Caution The external bus interface function cannot be used in (A1) grade products and (A2) grade products. 2.2.6 P50 to P57 (port 5) P50 to P57 function as an 8-bit I/O port. These pins also function as address bus pins. The following operation modes can be specified. (1) Port mode P50 to P57 function as an 8-bit I/O port. P50 to P57 can be set to input or output in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). (2) Control mode P50 to P57 function as the pins for the higher address bus (A8 to A15) in external memory expansion mode. Caution The external bus interface function cannot be used in (A1) grade products and (A2) grade products. User's Manual U15947EJ2V0UD 53 CHAPTER 2 PIN FUNCTIONS 2.2.7 mode. P60 to P67 (port 6) P60 to P67 function as an 8-bit I/O port. These pins also function as control pins in external memory expansion The following operation modes can be specified. (1) Port mode P60 to P67 function as an 8-bit I/O port. P60 to P67 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). P60 to P63 are N-ch open-drain pins. Use of an on-chip pull-up resistor can be specified by a mask option only for mask ROM versions. Use of an on-chip pull-up resistor can be specified for P64 to P67 by pull-up resistor option register 6 (PU6). (2) Control mode P64 to P67 function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode. Cautions 1. P66 functions as an I/O port if the external wait is not used in external memory expansion mode. 2. The external bus interface function cannot be used in (A1) grade products and (A2) grade products. 2.2.8 P70 to P77 (port 7) P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins. The following operation modes can be specified in 1-bit units. www..com (1) Port mode P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P77 function as key interrupt input pins. 2.2.9 P120 (port 12) P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input. The following operation modes can be specified. (1) Port mode P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). (2) Control mode P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.10 P130 (port 13) P130 functions as a 1-bit output-only port. 54 User's Manual U15947EJ2V0UD CHAPTER 2 PIN FUNCTIONS 2.2.11 P140 to P145 (port 14) P140 to P145 function as a 6-bit I/O port. These pins also function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. The following operation modes can be specified in 1-bit units. (1) Port mode P140 to P145 function as a 6-bit I/O port. P140 to P145 can be set to input or output in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). (2) Control mode P140 to P145 function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. (a) INTP6, INTP7 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) PCL This is a clock output pin. (c) BUZ This is a buzzer output pin. www..com (d) SIA0 This is a serial interface serial data input pin. (e) SOA0 This is a serial interface serial data output pin. (f) SCKA0 This is a serial interface serial clock I/O pin. (g) BUSY0 This is a serial interface busy input pin. (h) STB0 This is a serial interface strobe output pin. 2.2.12 AVREF This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin directly to EVDD or VDDNote. Note Connect port 2 directly to EVDD when it is used as a digital port. 2.2.13 AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the EVSS pin or VSS pin. User's Manual U15947EJ2V0UD 55 CHAPTER 2 PIN FUNCTIONS 2.2.14 RESET This is the active-low system reset input pin. 2.2.15 REGC This is the pin for connecting the capacitor for the regulator. When using the regulator, connect this pin to VSS via a capacitor (1 F: recommended). When the regulator is not used, connect this pin directly to VDD pin. Caution A regulator cannot be used with (A1) grade products and (A2) grade products. connect the REGC pin of these products directly to VDD. 2.2.16 X1 and X2 These are the pins for connecting a resonator for X1 input clock. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin. 2.2.17 XT1 and XT2 These are the pins for connecting a resonator for subsystem clock. When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin. 2.2.18 VDD and EVDD VDD is the positive power supply pin for other than ports. EVDD is the positive power supply pin for ports. 2.2.19 VSS and EVSS VSS is the ground potential pin for other than ports. www..com Be sure to EVSS is the ground potential pin for ports. 2.2.20 VPP (flash memory versions only) This is a pin for flash memory programming mode setting and high-voltage application for program write/verify. Connect to EVSS or VSS in the normal operation mode. 2.2.21 IC (mask ROM versions only) The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KF1 at shipment. Connect it directly to EVSS or VSS pin with the shortest possible wire in the normal operation mode. When a potential difference is produced between the IC pin and the EVSS or VSS pin because the wiring between these two pins is too long or external noise is input to the IC pin, the user's program may not operate normally. * Connect the IC pin directly to EVSS or VSS. EVSS or VSS IC As short as possible 56 User's Manual U15947EJ2V0UD CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2. Pin I/O Circuit Types (1/2) Pin Name P00/TI000 P01/TI010/TO00 P02/SO11 P03/SI11 Note I/O Circuit Type 8-A I/O I/O Input: Recommended Connection of Unused Pins Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Note P04/SCK11 P05/SSI11 P06/TI011 Note Note /TI001 Note Note /TO01 Note P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 www..com Note Note 5-A 8-A 5-A 8-A P17/TI50/TO50 P20/ANI0 to P27/ANI7 P30/INTP1 to P32/INTP3 P33/TI51/TO51/INTP4 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60, P61 (Mask ROM version) P60, P61 (Flash memory version) P62, P63 (Mask ROM version) P62, P63 (Flash memory version) P64/WD P65/WR P66/WAIT P67/ASTB P70/KR0 to P77/KR7 P120/INTP0 8-A 13-S 13-R 13-V 13-W 5-A Input: Independently connect to EVDD or EVSS via a resistor. Input: Independently connect to EVDD via a resistor. 5-A 9-C 8-A Input I/O Connect to EVDD or EVSS. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Output: Leave this pin open at low-level output after clearing the output latch of the port to 0. Output: Leave open. Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. User's Manual U15947EJ2V0UD 57 CHAPTER 2 PIN FUNCTIONS Table 2-2. Pin I/O Circuit Types (2/2) Pin Name P130 P140/PCL/INTP6 P141/BUZ/BUSY0/INTP7 P142/SCKA0 P143/SIA0 P144/SOA0 P145/STB RESET XT1 XT2 AVREF AVSS IC VPP Connect to EVSS or VSS. - 2 16 - Input - Connect directly to EVDD or VDD. Leave open. Connect directly to EVDD or VDD Note I/O Circuit Type 3-C 8-A I/O Output I/O Recommended Connection of Unused Pins Leave open. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. 5-A . Connect directly to EVSS or VSS. Note Connect port 2 directly to EVDD when it is used as a digital port. www..com 58 User's Manual U15947EJ2V0UD CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 8-A EVDD Pullup enable P-ch VDD IN Data Schmitt-triggered input with hysteresis characteristics Output disable P-ch IN/OUT N-ch Type 3-C Type 9-C EVDD P-ch Data www..com IN P-ch N-ch AVSS + - Comparator OUT N-ch VREF (threshold voltage) Input enable Type 5-A EVDD Type 13-R Pullup enable VDD Data P-ch P-ch IN/OUT Data Output disable IN/OUT N-ch Output disable N-ch Input enable User's Manual U15947EJ2V0UD 59 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-S Type 13-W Mask option EVDD IN/OUT Data Output disable N-ch IN/OUT Data Output disable N-ch Input enable Middle-voltage input buffer Type 13-V EVDD Mask option Type 16 Feedback cut-off IN/OUT P-ch Data Output disable N-ch www..com Input enable Middle-voltage input buffer XT1 XT2 60 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space 78K0/KF1 products can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all 78K0/KF1 products are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. Table 3-1. Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) IMS IXS 0CH PD780143 PD780144 PD780146 PD780148 PD78F0148 C6H C8H CCH CFH 0AH Value corresponding to mask ROM version www..com User's Manual U15947EJ2V0UD 61 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (PD780143) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH 5FFFH Reserved Buffer RAM 32 x 8 bits Reserved 0800H 07FFH External memory 38912 x 8 bits Program area 0080H 007FH CALLT table area 0040H 003FH Internal ROM 24576 x 8 bits 0000H 0000H Vector table area 1000H 0FFFH CALLF entry area Program area Data memory space www..com ROM/RAM space in which instructions can be fetched 6000H 5FFFH 62 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD780144) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH 7FFFH Reserved Buffer RAM 32 x 8 bits Reserved 0800H 07FFH Program area ROM/RAM space in which instructions can be fetched 8000H 7FFFH External memory 30720 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Internal ROM 32768 x 8 bits 0000H 0000H Vector table area 1000H 0FFFH CALLF entry area Program area Data memory space www..com User's Manual U15947EJ2V0UD 63 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD780146) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Reserved BFFFH Buffer RAM 32 x 8 bits Reserved 1000H 0FFFH CALLF entry area Internal expansion RAM 1024 x 8 bits F400H F3FFH ROM/RAM space in which instructions can be fetched C000H BFFFH External memory 13312 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H 0800H 07FFH Program area Program area Data memory space www..com Internal ROM 49152 x 8 bits 0000H 64 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (PD780148) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Reserved EFFFH Buffer RAM 32 x 8 bits Reserved 1000H 0FFFH CALLF entry area Internal expansion RAM 1024 x 8 bits F400H F3FFH ROM/RAM space in which instructions can be fetched F000H EFFFH External memory 1024 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Internal ROM 61440 x 8 bits 0000H 0000H Vector table area 0800H 07FFH Program area Program area Data memory space www..com User's Manual U15947EJ2V0UD 65 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (PD78F0148) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Reserved EFFFH Buffer RAM 32 x 8 bits Reserved 1000H 0FFFH CALLF entry area Internal expansion RAM 1024 x 8 bits F400H F3FFH ROM/RAM space in which instructions can be fetched F000H EFFFH Flash memory 61440 x 8 bits 0000H 0040H 003FH Vector table area 0000H External memory 1024 x 8 bits 0080H 007FH CALLT table area 0800H 07FFH Program area Program area Data memory space www..com 66 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KF1 products incorporate internal ROM (mask ROM or flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Structure Internal ROM Capacity 24576 x 8 bits (0000H to 5FFFH) 32768 x 8 bits (0000H to 7FFFH) 49152 x 8 bits (0000H to BFFFH) 61440 x 8 bits (0000H to EFFFH) Flash memory 61440 x 8 bits (0000H to EFFFH) PD780143 PD780144 PD780146 PD780148 PD78F0148 Mask ROM The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset signal input or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-3. Vector Table Vector Table Address 0000H Interrupt Source RESET input, POC, LVI, clock monitor, WDT 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10/INTST0 INTTMH1 INTTMH0 INTTM50 Vector Table Address 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 0038H 003AH 003CH Interrupt Source INTTM000 INTTM010 INTAD INTSR0 INTWTI INTTM51 INTKR INTWT INTP6 INTP7 INTDMU INTCSI11 Note www..com INTTM001 INTTM011 INTACSI Note Note Note Available only in the PD780146, 780148, and 78F0148. User's Manual U15947EJ2V0UD 67 CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space 78K0/KF1 products incorporate the following RAMs. (1) Internal high-speed RAM The internal high-speed RAM is allocated to the area FB00H to FEFFH in a 1024 x 8 bits configuration. The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per one bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. (2) Internal expansion RAM Table 3-4. Internal Expansion RAM Capacity Part Number Internal Expansion RAM - PD780143 PD780144 PD780146 www..com 1024 x 8 bits (F400H to F7FFH) PD780148 PD78F0148 The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed. 3.1.3 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (see Table 3-5 Special Function Register List in 3.2.3 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 68 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KF1, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Figures 3-6 to 3-10 show correspondence between data memory and addressing. For details of each addressing mode, see 3.4 Operand Address Addressing. Figure 3-6. Correspondence Between Data Memory and Addressing (PD780143) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH SFR addressing General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH www..com FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH Direct addressing Reserved Register indirect addressing Buffer RAM 32 x 8 bits Reserved Based addressing Based indexed addressing External memory 38912 x 8 bits 6000H 5FFFH Internal ROM 24576 x 8 bits 0000H User's Manual U15947EJ2V0UD 69 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Correspondence Between Data Memory and Addressing (PD780144) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH SFR addressing General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH Direct addressing Register indirect addressing Buffer RAM 32 x 8 bits Reserved Based addressing Based indexed addressing Reserved www..com External memory 30720 x 8 bits 8000H 7FFFH Internal ROM 32768 x 8 bits 0000H 70 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Correspondence Between Data Memory and Addressing (PD780146) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH SFR addressing General-purpose registers 32 x 8 bits Register addressing Short direct addressing Reserved Buffer RAM 32 x 8 bits Direct addressing Reserved Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 1024 x 8 bits www..com F400H F3FFH External memory 13312 x 8 bits C000H BFFFH Internal ROM 49152 x 8 bits 0000H User's Manual U15947EJ2V0UD 71 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Correspondence Between Data Memory and Addressing (PD780148) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH SFR addressing General-purpose registers 32 x 8 bits Register addressing Short direct addressing Reserved Buffer RAM 32 x 8 bits Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing www..com Internal expansion RAM 1024 x 8 bits F400H F3FFH External memory 1024 x 8 bits F000H EFFFH Internal ROM 61440 x 8 bits 0000H 72 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Correspondence Between Data Memory and Addressing (PD78F0148) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH FA00H F9FFH F800H F7FFH SFR addressing General-purpose registers 32 x 8 bits Register addressing Short direct addressing Reserved Buffer RAM 32 x 8 bits Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing www..com Internal expansion RAM 1024 x 8 bits F400H F3FFH External memory 1024 x 8 bits F000H EFFFH Flash memory 61440 x 8 bits 0000H User's Manual U15947EJ2V0UD 73 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/KF1 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-11. Format of Program Counter 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW www..com instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-12. Format of Program Status Word 7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupts are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. 74 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (see 19.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) cannot be acknowledged. Actual interrupt request acknowledgment is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. www..com Figure 3-13. Format of Stack Pointer 15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-14 and 3-15. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using the stack. User's Manual U15947EJ2V0UD 75 CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP FEE0H FEE0H FEDFH Register pair higher Register pair lower SP FEDEH FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH PC15 to PC8 PC7 to PC0 SP FEDEH FEDEH (c) Interrupt, BRK instructions (when SP = FEE0H) www..com SP FEE0H FEE0H FEDFH FEDEH PSW PC15 to PC8 PC7 to PC0 SP FEDDH FEDDH 76 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH Register pair higher Register pair lower SP FEDEH FEDEH (b) RET instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH PC15 to PC8 PC7 to PC0 SP FEDEH FEDEH (c) RETI, RETB instructions (when SP = FEDDH) www..com SP FEE0H FEE0H FEDFH FEDEH PSW PC15 to PC8 PC7 to PC0 SP FEDDH FEDDH User's Manual U15947EJ2V0UD 77 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-16. Configuration of General-Purpose Registers (a) Absolute name 16-bit processing FEFFH R7 BANK0 FEF8H RP3 R6 R5 BANK1 FEF0H www..com 8-bit processing RP2 R4 R3 BANK2 FEE8H RP1 R2 R1 BANK3 FEE0H 15 RP0 R0 0 7 0 (b) Function name 16-bit processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H BC C A BANK3 FEE0H 15 0 7 0 AX X DE E B BANK2 FEE8H 8-bit processing 78 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined by the header file "sfrbit.h" in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols can be written as an instruction operand. * R/W www..com Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: Read only W: Write only * Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon RESET input. User's Manual U15947EJ2V0UD 79 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF07H FF08H FF09H FF0AH FF0BH FF0CH FF0DH FF0EH FF0FH FF10H FF11H www..com After Reset 00H 00H Undefined 00H 00H 00H 00H 00H Undefined 8 Bits - 16 Bits - - - - - - - - Port register 0 Port register 1 Port register 2 Port register 3 Port register 4 Port register 5 Port register 6 Port register 7 A/D conversion result register P0 P1 P2 P3 P4 P5 P6 P7 ADCR R/W R/W R R/W R/W R/W R/W R/W R - Receive buffer register 6 Transmit buffer register 6 Port register 12 Port register 13 Port register 14 Serial I/O shift register 10 16-bit timer counter 00 RXB6 TXB6 P12 P13 P14 SIO10 TM00 R R/W R/W R/W R/W R R - - - - - - - - - - - FFH FFH 00H 00H 00H 00H 0000H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF1FH FF20H FF21H FF23H FF24H FF25H FF26H FF27H FF28H FF29H FF2AH FF2BH 16-bit timer capture/compare register 000 CR000 R/W - - 0000H 16-bit timer capture/compare register 010 CR010 R/W - - 0000H 8-bit timer counter 50 8-bit timer compare register 50 8-bit timer H compare register 00 8-bit timer H compare register 10 8-bit timer H compare register 01 8-bit timer H compare register 11 8-bit timer counter 51 Port mode register 0 Port mode register 1 Port mode register 3 Port mode register 4 Port mode register 5 Port mode register 6 Port mode register 7 A/D converter mode register Analog input channel specification register Power-fail comparison mode register Power-fail comparison threshold register TM50 CR50 CMP00 CMP10 CMP01 CMP11 TM51 PM0 PM1 PM3 PM4 PM5 PM6 PM7 ADM ADS PFM PFT R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - - - - - - - - - - - - - - - - - - - - - - - - - 00H 00H 00H 00H 00H 00H 00H FFH FFH FFH FFH FFH FFH FFH 00H 00H 00H 00H 80 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF2CH FF2EH FF30H FF31H FF33H FF34H FF35H FF36H FF37H FF3CH FF3EH FF40H FF41H FF43H FF47H FF48H FF49H FF4AH www..com After Reset FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Undefined 00H 01H 8 Bits 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - Port mode register 12 Port mode register 14 Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 6 Pull-up resistor option register 7 Pull-up resistor option register 12 Pull-up resistor option register 14 Clock output selection register 8-bit timer compare register 51 8-bit timer mode control register 51 Memory expansion mode register External interrupt rising edge enable register External interrupt falling edge enable register Serial I/O shift register 11 Note PM12 PM14 PU0 PU1 PU3 PU4 PU5 PU6 PU7 PU12 PU14 CKS CR51 TMC51 MEM EGP EGN SIO11 SOTB11 ISC ASIM6 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W - - - - - - - - - - - - - FF4CH FF4FH FF50H Transmit buffer register 11 Note Input switch control register Asynchronous serial interface operation mode register 6 FF53H Asynchronous serial interface reception error status register 6 ASIS6 R 00H FF55H Asynchronous serial interface transmission status register 6 ASIF6 R 00H FF56H FF57H FF58H FF60H FF61H FF62H FF63H FF64H FF65H FF66H FF67H FF68H FF69H FF6AH Clock selection register 6 Baud rate generator control register 6 Asynchronous serial interface control register 6 Remainder data register 0 CKSR6 BRGC6 ASICL6 SDR0 SDR0L SDR0H R/W R/W R/W R 00H FFH 16H 00H 00H Multiplication/division data register A0 MDA0L MDA0LL R/W MDA0LH 00H 00H MDA0H MDA0HL R/W MDA0HH 00H 00H Multiplication/division data register B0 MDB0 MDB0L MDB0H R/W - - 00H 00H Multiplier/divider control register 0 8-bit timer H mode register 0 Timer clock selection register 50 DMUC0 TMHMD0 TCL50 R/W R/W R/W - - - - 00H 00H 00H Note PD780146, 780148, and 78F0148 only. User's Manual U15947EJ2V0UD 81 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF6BH FF6CH FF6DH FF6EH FF6FH FF70H 8-bit timer mode control register 50 8-bit timer H mode register 1 8-bit timer H carrier control register 1 Key return mode register Watch timer operation mode register Asynchronous serial interface operation mode register 0 FF71H FF72H FF73H Baud rate generator control register 0 Receive buffer register 0 Asynchronous serial interface reception error status register 0 FF74H FF80H FF81H FF84H FF88H FF89H FF8CH www..com After Reset 00H 00H 00H 00H 00H 01H 8 Bits - 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TMC50 TMHMD1 TMCYC1 KRM WTM ASIM0 R/W R/W R/W R/W R/W R/W - - - - - - - - - - - - - - - - BRGC0 RXB0 ASIS0 R/W R R 1FH FFH 00H Transmit shift register 0 Serial operation mode register 10 Serial clock selection register 10 Transmit buffer register 10 Serial operation mode register 11 Serial clock selection register 11 Timer clock selection register 51 Serial operation mode specification register 0 Serial status register 0 Serial trigger register 0 Divisor selection register 0 Automatic data transfer address point specification register 0 Note 1 TXS0 CSIM10 CSIC10 SOTB10 CSIM11 CSIC11 TCL51 CSIMA0 CSIS0 CSIT0 BRGCA0 ADTP0 W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FFH 00H 00H Undefined 00H 00H 00H 00H 00H 00H 03H 00H Note 1 FF90H FF91H FF92H FF93H FF94H FF95H Automatic data transfer interval specification register 0 ADTI0 R/W 00H FF96H FF97H FF98H FF99H FFA0H FFA1H FFA2H FFA3H FFA4H FFA9H FFACH FFB0H FFB1H Serial I/O shift register 0 Automatic data transfer address count register 0 Watchdog timer mode register Watchdog timer enable register Ring-OSC mode register Main clock mode register Main OSC control register SIOA0 ADTC3 WDTM WDTE RCM MCM MOC R/W R R/W R/W R/W R/W R/W R R/W R/W R R 00H 00H 67H 9AH 00H 00H 00H 00H 05H 00H 00H Note 2 Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register Clock monitor mode register Reset control flag register 16-bit timer counter 01 Note 1 OSTS CLM RESF TM01 0000H Notes 1. 2. PD780146, 780148, and 78F0148 only. This value varies depending on the reset source. User's Manual U15947EJ2V0UD 82 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (4/4) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FFB2H FFB3H FFB4H FFB5H FFB6H FFB7H FFB8H FFB9H FFBAH FFBBH FFBCH FFBDH FFBEH FFBFH FFE0H FFE1H FFE2H FFE3H www..com After Reset 0000H 8 Bits - 16 Bits 16-bit timer capture/compare register 001 Note 1 CR001 R/W - 16-bit timer capture/compare register 011 Note 1 CR011 R/W - - 0000H 16-bit timer mode control register 01 Prescaler mode register 01 Note 1 Note 1 TMC01 PRM01 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - - - - - - - - - - - - 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Capture/compare control register 01 Note 1 CRC01 TOC01 TMC00 PRM00 CRC00 TOC00 LVIM LVIS IF0 IF0L IF0H IF1 IF1L IF1H MK0 16-bit timer output control register 01 16-bit timer mode control register 00 Prescaler mode register 00 Capture/compare control register 00 16-bit timer output control register 00 Low-voltage detection register Note 1 Low-voltage detection level selection register Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt request flag register 1H Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Interrupt mask flag register 1H Priority specification flag register 0L Priority specification flag register 0H Priority specification flag register 1L Priority specification flag register 1H Internal memory size switching register Note 2 R/W R/W R/W R/W 00H 00H FFE4H FFE5H FFE6H FFE7H FFE8H FFE9H FFEAH FFEBH FFF0H FFF4H FFF8H FFFBH MK0L R/W MK0H R/W FFH FFH MK1 MK1L R/W MK1H R/W FFH DFH PR0 PR0L R/W PR0H R/W FFH FFH PR1 PR1L R/W PR1H R/W FFH FFH IMS Note 2 R/W R/W R/W R/W - - - - CFH 0CH 10H 00H Internal expansion RAM size switching register Memory expansion wait setting register Processor clock control register IXS MM PCC Notes 1. 2. PD780146, 780148, and 78F0148 only. The default value of IMS and IXS are fixed (IMS = CFH, IXS = 0CH) in all 78K0/KF1 products regardless of the internal memory capacity. Therefore, set the following value to each product. IMS IXS 0CH PD780143 PD780144 PD780146 PD780148 PD78F0148 C6H C8H CCH CFH 0AH Value corresponding to mask ROM version User's Manual U15947EJ2V0UD 83 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 www..com 0 ... PC indicates the start address of the instruction after the BR instruction. 8 7 S 6 0 jdisp8 15 PC 0 When S = 0, all bits of are 0. When S = 1, all bits of are 1. 84 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 In the case of CALLF !addr11 instruction www..com 76 fa10-8 4 3 CALLF 0 fa7-0 15 PC 0 0 0 0 11 10 1 87 0 User's Manual U15947EJ2V0UD 85 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. [Illustration] 7 Operation code 1 6 1 5 ta4-0 1 0 1 15 Effective address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective address+1 High Addr. www..com 15 PC 8 7 0 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 86 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KF1 instruction words, the following instructions employ implied addressing. Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to Be Specified by Implied Addressing A register for multiplicand and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values that become decimal correction targets A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] www..com In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. User's Manual U15947EJ2V0UD 87 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL `r' and `rp' can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r Operation code 0 1 1 0 0 0 1 0 Register specify code www..com INCW DE; when selecting DE register pair as rp Operation code 1 0 0 0 0 1 0 0 Register specify code 88 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 www..com 0 OP code addr16 (lower) addr16 (upper) Memory User's Manual U15947EJ2V0UD 89 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to the [Illustration]. [Operand format] Identifier saddr saddrp Description Immediate data that indicate label or FE20H to FF1FH Immediate data that indicate label or FE20H to FF1FH (even address only) [Description example] MOV 0FE30H, A; when transferring value of A register to saddr (FE30H) Operation code www..com 1 1 1 1 0 0 1 0 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) [Illustration] 7 OP code saddr-offset 0 Short direct memory 15 Effective address 1 1 1 1 1 1 1 87 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 90 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier sfr sfrp Special function register name 16-bit manipulatable special function register name (even address only) Description [Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H (sfr-offset) [Illustration] www..com 7 OP code sfr-offset 0 SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0 User's Manual U15947EJ2V0UD 91 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [DE], [HL] Description [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code 1 0 0 0 0 1 0 1 [Illustration] 16 DE D 87 E The memory address specified with the register pair DE 0 www..com 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 92 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [HL + byte] Description [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 [Illustration] www..com 16 HL H 87 L 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 +10 User's Manual U15947EJ2V0UD 93 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [HL + B], [HL + C] Description [Description example] In the case of MOV A, [HL + B] (selecting B register) Operation code 1 0 1 0 1 0 1 1 [Illustration] 16 www..com 8 H + 7 L 0 HL 7 B 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 94 User's Manual U15947EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed. [Description example] In the case of PUSH DE (saving DE register) Operation code 1 0 1 1 0 1 0 1 [Illustration] 7 SP FEE0H FEE0H FEDFH SP FEDEH FEDEH D E Memory 0 www..com User's Manual U15947EJ2V0UD 95 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AVREF and EVDD. The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply AVREF EVDD Corresponding Pins P20 to P27 Port pins other than P20 to P27 78K0/KF1 products are provided with the ports shown in Figure 4-1, which enable variety of control operations. The functions of each port are shown in Table 4-2. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Types P50 P00 Port 5 www..com Port 0 P06 P57 P10 P60 Port 1 Port 6 P17 P67 P20 P70 Port 2 Port 7 P27 P77 P30 Port 12 Port 13 P120 P130 P140 Port 14 Port 4 P145 P47 P33 P40 Port 3 96 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (1/2) Pin Name P00 P01 P02 P03 P04 P05 P06 P10 P11 P12 P13 P14 P15 P16 P17 P20 to P27 Input Port 2. 8-bit input-only port. P30 to P32 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. www..com I/O I/O Port 0. 7-bit I/O port. Function After Reset Input Alternate Function TI000 TI010/TO00 SO11 SI11 Note Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Note SCK11 SSI11 TI011 I/O Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input Note Note /TI001 Note Note /TO01 Note SCK10/TxD0 SI10/RxD0 SO10 TxD6 RxD6 TOH0 TOH1/INTP5 TI50/TO50 Input ANI0 to ANI7 Input INTP1 to INTP3 P33 Use of an on-chip pull-up resistor can be specified by a software setting. INTP4/TI51/TO51 P40 to P47 I/O Port 4. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input AD0 to AD7 P50 to P57 I/O Port 5. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input A8 to A15 Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. User's Manual U15947EJ2V0UD 97 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (2/2) Pin Name P60 to P63 I/O I/O Port 6. 8-bit I/O port. Input/output can be specified in 1-bit units. Function N-ch open-drain I/O port. Use of an on-chip pull-up resistor can be specified by a mask option only for mask ROM versions. P64 P65 P66 P67 P70 to P77 I/O Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting. P130 Output Port 13. 1-bit output-only port. P140 P141 www..com After Reset Input Alternate Function - Use of an on-chip pull-up resistor can be specified by a software setting. RD WR WAIT ASTB Input KR0 to KR7 Input INTP0 Output - I/O Port 14. 6-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input PCL/INTP6 BUZ/BUSY0/ INTP7 SCKA0 SIA0 SOA0 STB0 P142 P143 P144 P145 4.2 Port Configuration Ports consist of the following hardware. Table 4-3. Port Configuration Item Control registers Configuration Port mode register (PM0, PM1, PM3 to PM7, PM12, PM14) Port register (P0 to P7, P12 to P14) Pull-up resistor option register (PU0, PU1, PU3 to PU7, PU12, PU14) Port Pull-up resistor Total: 67 (CMOS I/O: 54, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4) * Mask ROM version Total: 58 (software control: 54, mask option specification: 4) * Flash memory version: Total: 54 98 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). This port can also be used for timer I/O, serial interface data I/O, and clock I/O. RESET input sets port 0 to input mode. Figures 4-2 to 4-5 show block diagrams of port 0. Caution When P02/SO11Note, P03/SI11Note, and P04/SCK11Note are used as general-purpose ports, do not write to serial clock selection register 11 (CSIC11). Figure 4-2. Block Diagram of P00, P03, and P05 EVDD WRPU PU0 PU00, PU03, PU05 P-ch Alternate function RD www..com Internal bus WRPORT Output latch (P00, P03, P05) WRPM PM0 PM00, PM03, PM05 Selector P00/TI000, P03/SI11Note, P05/SSI11Note/TI001Note Note Available only in the PD780146, 780148, and 78F0148. PU0: RD: Pull-up resistor option register 0 Read signal PM0: Port mode register 0 WRxx: Write signal User's Manual U15947EJ2V0UD 99 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 and P06 EVDD WRPU PU0 PU01, PU06 P-ch Alternate function RD Selector Internal bus WRPORT Output latch (P01, P06) WRPM PM0 PM01, PM06 P01/TI010/TO00, P06/TI011Note/TO01Note Alternate function www..com Note Available only in the PD780146, 780148, and 78F0148. PU0: RD: Pull-up resistor option register 0 Read signal PM0: Port mode register 0 WRxx: Write signal 100 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 EVDD WRPU PU0 PU02 RD P-ch Internal bus WRPORT Output latch (P02) WRPM PM0 PM02 Selector P02/SO11Note Alternate function www..com Note Available only in the PD780146, 780148, and 78F0148. PU0: RD: Pull-up resistor option register 0 Read signal PM0: Port mode register 0 WRxx: Write signal User's Manual U15947EJ2V0UD 101 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P04 EVDD WRPU PU0 PU04 P-ch Alternate function RD Internal bus WRPORT Output latch (P04) WRPM PM0 PM04 Selector P04/SCK11Note Alternate function www..com Note Available only in the PD780146, 780148, and 78F0148. PU0: RD: Pull-up resistor option register 0 Read signal PM0: Port mode register 0 WRxx: Write signal 102 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. RESET input sets port 1 to input mode. Figures 4-6 to 4-10 show block diagrams of port 1. Caution When P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 are used as general-purpose ports, do not write to serial clock selection register 10 (CSIC10). Figure 4-6. Block Diagram of P10 EVDD WRPU PU1 PU10 P-ch Alternate function RD www..com Internal bus WRPORT Output latch (P10) WRPM PM1 PM10 Selector P10/SCK10/TxD0 Alternate function PU1: RD: Pull-up resistor option register 1 Read signal PM1: Port mode register 1 WRxx: Write signal User's Manual U15947EJ2V0UD 103 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P11 and P14 EVDD WRPU PU1 PU11, PU14 P-ch Alternate function RD Internal bus Selector WRPORT Output latch (P11, P14) WRPM PM1 PM11, PM14 P11/SI10/RxD0, P14/RxD6 PU1: www..com Pull-up resistor option register 1 Read signal PM1: Port mode register 1 RD: WRxx: Write signal 104 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P12 and P15 EVDD WRPU PU1 PU12, PU15 RD P-ch Internal bus WRPORT Output latch (P12, P15) WRPM PM1 PM12, PM15 Selector P12/SO10 P15/TOH0 Alternate function www..com PU1: RD: Pull-up resistor option register 1 Read signal PM1: Port mode register 1 WRxx: Write signal User's Manual U15947EJ2V0UD 105 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P13 EVDD WRPU PU1 PU13 RD P-ch Internal bus WRPORT Output latch (P13) WRPM PM1 PM13 Selector P13/TxD6 Alternate function www..com PU1: RD: Pull-up resistor option register 1 Read signal PM1: Port mode register 1 WRxx: Write signal 106 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P16 and P17 EVDD WRPU PU1 PU16, PU17 P-ch Alternate function RD Internal bus WRPORT Output latch (P16, P17) WRPM PM1 PM16, PM17 Selector P16/TOH1/INTP5, P17/TI50/TO50 Alternate function www..com PU1: RD: Pull-up resistor option register 1 Read signal PM1: Port mode register 1 WRxx: Write signal User's Manual U15947EJ2V0UD 107 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-11 shows a block diagram of port 2. Figure 4-11. Block Diagram of P20 to P27 RD Internal bus A/D converter P20/ANI0 to P27/ANI7 www..com RD: Read signal 108 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input. RESET input sets port 3 to input mode. Figures 4-12 and 4-13 show block diagrams of port 3. Figure 4-12. Block Diagram of P30 to P32 EVDD WRPU PU3 PU30 to PU32 P-ch Alternate function RD Internal bus WRPORT Output latch (P30 to P32) WRPM PM3 PM30 to PM32 Selector www..com P30/INTP1 to P32/INTP3 PU3: RD: Pull-up resistor option register 3 Read signal PM3: Port mode register 3 WRxx: Write signal User's Manual U15947EJ2V0UD 109 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P33 EVDD WRPU PU3 PU33 P-ch Alternate function RD Selector Internal bus WRPORT Output latch (P33) WRPM PM3 PM33 P33/INTP4/TI51/TO51 Alternate function www..com PU3: RD: Pull-up resistor option register 3 Read signal PM3: Port mode register 3 WRxx: Write signal 110 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (PU4). This port can also be used as an address/data bus in external memory expansion mode. RESET input sets port 4 to input mode. Figure 4-14 shows a block diagram of port 4. Figure 4-14. Block Diagram of P40 to P47 EVDD WRPU PU4 PU40 to PU47 RD Alternate function P-ch Selector WRPORT Internal bus Output latch (P40 to P47) Selector P40/AD0 to P47/AD7 www..com Alternate function WRPM PM4 PM40 to PM47 Memory expansion mode register (MEM) PU4: RD: Pull-up resistor option register 4 Read signal PM4: Port mode register 4 WRxx: Write signal User's Manual U15947EJ2V0UD 111 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is an 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 5 (PU5). This port can also be used as an address bus in external memory expansion mode. RESET input sets port 5 to input mode. Figure 4-15 shows a block diagram of port 5. Figure 4-15. Block Diagram of P50 to P57 EVDD WRPU PU5 PU50 to PU57 P-ch RD Selector WRPORT Internal bus Output latch (P50 to P57) Selector P50/A8 to P57/A15 www..com Alternate function WRPM PM5 PM50 to PM57 Memory expansion mode register (MEM) PU5: RD: Pull-up resistor option register 5 Read signal PM5: Port mode register 5 WRxx: Write signal 112 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is an 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). This port has the following functions for pull-up resistors. These functions differ depending on the higher 4 bits/lower 4 bits of the port, and whether the product is a mask ROM version or a flash memory version. Table 4-4. Pull-up Resistor of Port 6 Higher 4 Bits (Pins P64 to P67) Mask ROM version An on-chip pull-up resistor can be connected in 1-bit units by PU6 Flash memory version Lower 4 Bits (Pins P60 to P63) An on-chip pull-up resistor can be specified in 1-bit units by mask option On-chip pull-up resistors are not provided PU6: Pull-up resistor option register 6 The P60 to P63 pins are N-ch open-drain pins. The P64 to P67 pins can also be used for the control signal output function in external memory expansion mode. RESET input sets port 6 to input mode. Figures 4-16 to 4-18 show block diagrams of port 6. Caution P66 can be used as an I/O port when an external wait is not used in external memory expansion mode. Figure 4-16. Block Diagram of P60 to P63 www..com EVDD RD Mask option resistor Mask ROM versions only No pull-up resistor for flash memory versions Selector Internal bus WRPORT Output latch (P60 to P63) P60 to P63 WRPM PM6 PM60 to PM63 PM6: Port mode register 6 RD: Read signal WRxx: Write signal User's Manual U15947EJ2V0UD 113 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P64, P65, and P67 EVDD WRPU PU6 PU64, PU65, PU67 P-ch RD Selector WRPORT Internal bus Output latch (P64, P65, P67) Selector P64/RD, P65/WR, P67/ASTB Alternate function WRPM PM6 PM64, PM65, PM67 Memory expansion mode register (MEM) www..com PU6: RD: Pull-up resistor option register 6 Read signal PM6: Port mode register 6 WRxx: Write signal 114 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P66 EVDD WRPU PU6 PU66 RD Alternate function P-ch Selector Internal bus WRPORT Output latch (P66) Selector P66/WAIT WRPM PM6 PM66 Memory expansion mode register (MEM) PU6: RD: www..com Pull-up resistor option register 6 Read signal PM6: Port mode register 6 WRxx: Write signal User's Manual U15947EJ2V0UD 115 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). This port can also be used for key return input. RESET input sets port 7 to input mode. Figure 4-19 shows a block diagram of port 7. Figure 4-19. Block Diagram of P70 to P77 EVDD WRPU PU7 PU70 to PU77 P-ch Alternate function RD Internal bus WRPORT Output latch (P70 to P77) WRPM PM7 PM70 to PM77 Selector www..com P70/KR0 to P77/KR7 PU7: RD: Pull-up resistor option register 7 Read signal PM7: Port mode register 7 WRxx: Write signal 116 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). This port can also be used for external interrupt input. RESET input sets port 12 to input mode. Figure 4-20 shows a block diagram of port 12. Figure 4-20. Block Diagram of P120 EVDD WRPU PU12 PU120 P-ch Alternate function RD Internal bus WRPORT Output latch (P120) WRPM PM12 PM120 Selector www..com P120/INTP0 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WRxx: Write signal User's Manual U15947EJ2V0UD 117 CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 13 Port 13 is a 1-bit output-only port. Figure 4-21 shows a block diagram of port 13. Figure 4-21. Block Diagram of P130 RD Internal bus WRPORT Output latch (P130) P130 RD: Read signal WRxx: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level immediately after reset is released, the output signal of P130 can be dummy-output as the reset signal to the CPU. www..com 118 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 14 Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, busy input, buzzer output, and clock output. RESET input sets port 14 to input mode. Figures 4-22 to 4-25 show block diagrams of port 14. Figure 4-22. Block Diagram of P140 and P141 EVDD WRPU PU14 PU140, PU141 P-ch Alternate function RD Selector Internal bus WRPORT Output latch (P140, P141) WRPM PM14 PM140, PM141 www..com P140/PCL/INTP6, P141/BUZ/BUSY0/INTP7 Alternate function PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal User's Manual U15947EJ2V0UD 119 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P142 EVDD WRPU PU14 PU142 P-ch Alternate function RD Internal bus WRPORT Output latch (P142) WRPM PM14 PM142 Selector P142/SCKA0 Alternate function www..com PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal 120 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P143 EVDD WRPU PU14 PU143 P-ch Alternate function RD Internal bus WRPORT Output latch (P143) WRPM PM14 PM143 Selector P143/SIA0 PU14: Pull-up resistor option register 14 www..com PM14: Port mode register 14 RD: Read signal WRxx: Write signal User's Manual U15947EJ2V0UD 121 CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P144 and P145 EVDD WRPU PU14 PU144, PU145 RD P-ch Internal bus WRPORT Output latch (P144, P145) WRPM PM14 PM144, PM145 Selector P144/SOA0, P145/STB0 Alternate function www..com PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal 122 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. * Port mode registers (PM0, PM1, PM3 to PM7, PM12, PM14) * Port registers (P0 to P7, P12 to P14) * Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14) (1) Port mode registers (PM0, PM1, PM3 to PM7, PM12, and PM14) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table 4-5. Figure 4-26. Format of Port Mode Register Symbol PM0 7 1 7 PM1 PM17 7 www..com 6 PM06 6 PM16 6 1 6 PM46 6 PM56 6 PM66 6 PM76 6 1 6 1 5 PM05 5 PM15 5 1 5 PM45 5 PM55 5 PM65 5 PM75 5 1 5 PM145 4 PM04 4 PM14 4 1 4 PM44 4 PM54 4 PM64 4 PM74 4 1 4 PM144 3 PM03 3 PM13 3 PM33 3 PM43 3 PM53 3 PM63 3 PM73 3 1 3 PM143 2 PM02 2 PM12 2 PM32 2 PM42 2 PM52 2 PM62 2 PM72 2 1 2 PM142 1 PM01 1 PM11 1 PM31 1 PM41 1 PM51 1 PM61 1 PM71 1 1 1 PM141 0 PM00 0 PM10 0 PM30 0 PM40 0 PM50 0 PM60 0 PM70 0 PM120 0 PM140 Address FF20H After reset FFH R/W R/W FF21H FFH R/W PM3 1 7 FF23H FFH R/W PM4 PM47 7 FF24H FFH R/W PM5 PM57 7 FF25H FFH R/W PM6 PM67 7 FF26H FFH R/W PM7 PM77 7 FF27H FFH R/W PM12 1 7 FF2CH FFH R/W PM14 1 FF2EH FFH R/W PMmn Pmn pin I/O mode selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 1 Output mode (output buffer on) Input mode (output buffer off) User's Manual U15947EJ2V0UD 123 CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Pin Name Alternate Function Function Name P00 P01 TI000 TI010 TO00 P02 P03 P04 SO11 SI11 Note 1 PMxx I/O Input Input Output Output Input Input Output 1 1 0 0 1 1 0 1 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 1 0 x x x x 1 Note 2 Note 2 Pxx x x 0 0 x x 1 x x x 0 x 1 1 x x 0 1 x 0 0 x x 0 x x x 0 Note 1 SCK11 Note 1 P05 SSI11 TI001 Note 1 Input Input Input Output Input Output Note 1 P06 TI011 TO01 Note 1 Note 1 P10 SCK10 TxD0 P11 SI10 RxD0 P12 P13 P14 www..com Output Input Input Output Output Input Output Output Input Input Output Input Input Input Output I/O Output Output Output Input Output SO10 TxD6 RxD6 TOH0 TOH1 INTP5 P15 P16 P17 TI50 TO50 P30 to P32 P33 INTP1 to INTP3 INTP4 TI51 TO51 P40 to P47 P50 to P57 P64 P65 P66 P67 AD0 to AD7 A8 to A15 RD WR WAIT ASTB Note 2 Note 2 Note 2 x x Note 2 Note 2 Notes 1. 2. SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the PD780146, 780148, and 78F0148. When using the alternate functions of the P40 to P47, P50 to P57, and P64 to P67 pins, select the function by using the memory expansion mode register (MEM). Remark x: Pxx: Don't care Port output latch User's Manual U15947EJ2V0UD PMxx: Port mode register 124 CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Alternate Function Function Name P70 to P77 P120 P140 KR0 to KR7 INTP0 PCL INTP6 P141 BUZ BUSY0 INTP7 P142 SCKA0 I/O Input Input Output Input Output Input Input Input Output P143 P144 P145 SIA0 SOA0 STB0 Input Output Output 1 1 0 1 0 1 1 1 0 1 0 0 x x 0 x 0 x x x 1 x 0 0 PMxx Pxx Remark x: Pxx: Don't care Port output latch PMxx: Port mode register www..com User's Manual U15947EJ2V0UD 125 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H (but P2 is undefined). Figure 4-27. Format of Port Register Symbol P0 7 0 7 P1 P17 7 P2 P27 7 P3 0 7 P4 P47 7 P5 P57 7 P6 P67 7 P7 P77 7 P12 0 7 P13 0 7 P14 0 6 P06 6 P16 6 P26 6 0 6 P46 6 P56 6 P66 6 P76 6 0 6 0 6 0 5 P05 5 P15 5 P25 5 0 5 P45 5 P55 5 P65 5 P75 5 0 5 0 5 P145 4 P04 4 P14 4 P24 4 0 4 P44 4 P54 4 P64 4 P74 4 0 4 0 4 P144 3 P03 3 P13 3 P23 3 P33 3 P43 3 P53 3 P63 3 P73 3 0 3 0 3 P143 2 P02 2 P12 2 P22 2 P32 2 P42 2 P52 2 P62 2 P72 2 0 2 0 2 P142 1 P01 1 P11 1 P21 1 P31 1 P41 1 P51 1 P61 1 P71 1 0 1 0 1 P141 0 P00 0 P10 0 P20 0 P30 0 P40 0 P50 0 P60 0 P70 0 P120 0 P130 0 P140 FF0EH 00H (output latch) R/W FF0DH 00H (output latch) R/W FF0CH 00H (output latch) R/W FF07H 00H (output latch) R/W FF06H 00H (output latch) R/W FF05H 00H (output latch) R/W FF04H 00H (output latch) R/W FF03H 00H (output latch) R/W FF02H Undefined R FF01H 00H (output latch) R/W Address FF00H After reset 00H (output latch) R/W R/W www..com Pmn m = 0 to 7, 12 to 14; n = 0 to 7 Output data control (in output mode) Input data read (in input mode) Input low level Input high level 0 1 Output 0 Output 1 126 User's Manual U15947EJ2V0UD CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, or P140 to P145 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified. On-chip pull-up resistors cannot be connected for bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1, PU3 to PU7, PU12, and PU14. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Caution Use of a pull-up resistor can be specified for P60 to P63 pins by a mask option only in the mask ROM versions. Figure 4-28. Format of Pull-up Resistor Option Register Symbol PU0 7 0 7 PU1 PU17 7 PU3 0 7 www..com 6 PU06 6 PU16 6 0 6 PU46 6 PU56 6 PU66 6 PU76 6 0 6 0 5 PU05 5 PU15 5 0 5 PU45 5 PU55 5 PU65 5 PU75 5 0 5 PU145 4 PU04 4 PU14 4 0 4 PU44 4 PU54 4 PU64 4 PU74 4 0 4 PU144 3 PU03 3 PU13 3 PU33 3 PU43 3 PU53 3 0 3 PU73 3 0 3 PU143 2 PU02 2 PU12 2 PU32 2 PU42 2 PU52 2 0 2 PU72 2 0 2 PU142 1 PU01 1 PU11 1 PU31 1 PU41 1 PU51 1 0 1 PU71 1 0 1 PU141 0 PU00 0 PU10 0 PU30 0 PU40 0 PU50 0 0 0 PU70 0 PU120 0 PU140 Address FF30H After reset 00H R/W R/W FF31H 00H R/W FF33H 00H R/W PU4 PU47 7 FF34H 00H R/W PU5 PU57 7 FF35H 00H R/W PU6 PU67 7 FF36H 00H R/W PU7 PU77 7 FF37H 00H R/W PU12 0 7 FF3CH 00H R/W PU14 0 FF3EH 00H R/W PUmn Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 1 On-chip pull-up resistor not connected On-chip pull-up resistor connected User's Manual U15947EJ2V0UD 127 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared by reset. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. 4.4.2 www..com Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared by reset. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. 128 User's Manual U15947EJ2V0UD CHAPTER 5 EXTERNAL BUS INTERFACE 5.1 External Bus Interface The external bus interface connects external devices to areas other than the internal ROM, RAM, and SFR areas. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc. The external bus interface is usable only when the X1 clock is selected as the CPU clock. Caution The external bus interface function cannot be used in (A1) grade products and (A2) grade products. Table 5-1. Pin Functions in External Memory Expansion Mode Pin Function When External Device Is Connected Name AD0 to AD7 A8 to A15 RD WR WAIT ASTB www..com Alternate Function Function Multiplexed address/data bus Address bus Read strobe signal Write strobe signal Wait signal Address strobe signal P40 to P47 P50 to P57 P64 P65 P66 P67 Table 5-2. State of Ports 4 to 6 Pins in External Memory Expansion Mode External Expansion Mode Single-chip mode 256-byte expansion mode 4 KB expansion mode 16 KB expansion mode Full-address mode Port Address/data Address/data Address/data Address/data Port Port 4 0 to 7 0 Port Port Address Address Address Port Port 1 2 Port 5 3 4 5 6 7 0 Port Port Port Port Port RD, WR, WAIT, ASTB RD, WR, WAIT, ASTB RD, WR, WAIT, ASTB RD, WR, WAIT, ASTB 1 2 Port 6 3 4 5 6 7 Caution When the external wait function is not used, the WAIT pin can be used as a port in all modes. User's Manual U15947EJ2V0UD 129 CHAPTER 5 EXTERNAL BUS INTERFACE The memory maps when the external bus interface is used are as follows. Figure 5-1. Memory Map When Using External Bus Interface (1/2) (a) Memory map of PD780143 and of PD78F0148 when internal ROM (flash memory) size is 24 KB FFFFH SFR FF00H FEFFH Internal high-speed RAM FB00H FAFFH Reserved FA20H FA1FH Buffer RAM FA00H F9FFH Reserved F800H F7FFH F800H F7FFH FA00H F9FFH Reserved FA20H FA1FH Buffer RAM FB00H FAFFH Reserved FF00H FEFFH Internal high-speed RAM (b) Memory map of PD780144 and of PD78F0148 when internal ROM (flash memory) size is 32 KB FFFFH SFR www..com Full-address mode (when MM2 to MM0 = 111) Full-address mode (when MM2 to MM0 = 111) C000H BFFFH A000H 9FFFH 16 KB expansion mode (when MM2 to MM0 = 101) 7000H 6FFFH 4 KB expansion mode (when MM2 to MM0 = 100) 6100H 60FFH 6000H 5FFFH 8100H 80FFH 8000H 7FFFH 16 KB expansion mode (when MM2 to MM0 = 101) 9000H 8FFFH 4 KB expansion mode (when MM2 to MM0 = 100) 256-byte expansion mode (when MM2 to MM0 = 011) 256-byte expansion mode (when MM2 to MM0 = 011) Single-chip mode Single-chip mode 0000H 0000H 130 User's Manual U15947EJ2V0UD CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-1. Memory Map When Using External Bus Interface (2/2) (c) Memory map of PD780146 and of PD78F0148 when internal ROM (flash memory) size is 48 KB FFFFH SFR FF00H FEFFH Internal high-speed RAM FB00H FAFFH Reserved FA20H FA1FH Buffer RAM FA00H F9FFH Reserved F800H F7FFH Internal expansion RAM F400H F3FFH F400H F3FFH F800H F7FFH Internal expansion RAM FA00H F9FFH Reserved FA20H FA1FH Buffer RAM FB00H FAFFH Reserved FF00H FEFFH Internal high-speed RAM (d) Memory map of PD780148 and of PD78F0148 when internal ROM (flash memory) size is 60 KB FFFFH SFR www..com Full-address mode (when MM2 to MM0 = 111) or 16 KB expansion mode (when MM2 to MM0 = 101) Full-address mode (when MM2 to MM0 = 111) or 16 KB expansion mode (when MM2 to MM0 = 101) or 4 KB expansion mode (when MM2 to MM0 = 100) D000H CFFFH 4 KB expansion mode (when MM2 to MM0 = 100) C100H C0FFH C000H BFFFH F100H F0FFH F000H EFFFH 256-byte expansion mode (when MM2 to MM0 = 011) 256-byte expansion mode (when MM2 to MM0 = 011) Single-chip mode Single-chip mode 0000H 0000H User's Manual U15947EJ2V0UD 131 CHAPTER 5 EXTERNAL BUS INTERFACE 5.2 Registers Controlling External Bus Interface The external bus interface is controlled by the following two registers. * Memory expansion mode register (MEM) * Memory expansion wait setting register (MM) (1) Memory expansion mode register (MEM) MEM sets the external expansion area. MEM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears MEM to 00H. Figure 5-2. Format of Memory Expansion Mode Register (MEM) Address: FF47H Symbol MEM 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 MM2 1 MM1 0 MM0 MM2 MM1 MM0 Single-chip/memory P40 to P47, P50 to P57, P64 to P67 pin state P56, P57 P64 to P67 expansion mode selection P40 to P47 P50 to P53 P54, P55 0 0 www..com 0 1 0 1 Single-chip mode Memory mode Note Port mode AD0 to AD7 A8 to A11 Port mode Port mode P64 = RD P65 = WR P66 = WAIT P67 = ASTB A12, A13 Port mode 256-byte expansion mode 1 0 0 4 KB mode 1 0 1 16 KB mode 1 1 1 Full-address mode Other than above Setting prohibited A14, A15 132 User's Manual U15947EJ2V0UD CHAPTER 5 EXTERNAL BUS INTERFACE Note When the CPU accesses the external memory expansion area, the lower bits of the address to be accessed are output to the specified pins (except in the full-address mode). Figure 5-3. Pins Specified for Address (with PD780143) External Expansion Mode 256-byte expansion mode Address Accessed by CPU 6000H 6001H 6055H 60FEH 60FFH 4 KB expansion mode 6000H 6001H 6100H 6FFFH 16 KB expansion mode 6000H 7000H 8000H 9000H www..com Pins Specified for Address A15 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (1) (1) (1) 0 0 1 A14 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (0) (0) (0) 1 1 1 A13 (1) (1) (1) (1) (1) (1) (1) (1) (1) 1 1 0 0 0 1 1 1 A12 (0) (0) (0) (0) (0) (0) (0) (0) (0) 0 1 0 1 1 0 0 1 A11 (0) (0) (0) (0) (0) 0 0 0 1 0 0 0 0 1 0 0 0 A10 (0) (0) (0) (0) (0) 0 0 0 1 0 0 0 0 1 0 0 1 A9 (0) (0) (0) (0) (0) 0 0 0 1 0 0 0 0 1 0 0 1 A8 (0) (0) (0) (0) (0) 0 0 1 1 0 0 0 0 1 0 0 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 1 9FFFH Full-address mode 6000H 6001H F7FFH Remark The value in ( ) is not actually output. This pin can be used as a port pin. User's Manual U15947EJ2V0UD 133 CHAPTER 5 EXTERNAL BUS INTERFACE (2) Memory expansion wait setting register (MM) MM sets the number of waits. MM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 5-4. Format of Memory Expansion Wait Setting Register (MM) Address: FFF8H Symbol MM 7 0 After reset: 10H 6 0 R/W 5 PW1 4 PW0 3 0 2 0 1 0 0 0 PW1 0 0 1 1 PW0 0 1 0 1 No wait Wait (one wait state inserted) Setting prohibited Wait control by external wait pin Wait control Cautions 1. To control wait with external wait pin, be sure to set WAIT/P66 pin to input mode (set bit 6 (PM66) of port mode register 6 (PM6) to 1). 2. If the external wait pin is not used for wait control, the WAIT/P66 pin can be used as an I/O port pin. www..com 134 User's Manual U15947EJ2V0UD CHAPTER 5 EXTERNAL BUS INTERFACE 5.3 External Bus Interface Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data read and instruction fetch from external memory. During internal memory read, the read strobe signal is not output (maintains high level). (2) WR pin (Alternate function: P65) Write strobe signal output pin. The write strobe signal is output in data write to external memory. During internal memory write, the write strobe signal is not output (maintains high level). (3) WAIT pin (Alternate function: P66) External wait signal input pin. When the external wait is not used, the WAIT pin can be used as an I/O port. During internal memory access, the external wait signal is ignored. (4) ASTB pin (Alternate function: P67) Address strobe signal output pin. The address strobe signal is output regardless of data access and instruction fetch from external memory. During internal memory access, the address strobe signal is output. (5) AD0 to AD7, A8 to A15 pins (Alternate function: P40 to P47, P50 to P57) www..com Address/data signal output pins. Valid signal is output or input during data accesses and instruction fetches from external memory. These signals change even during internal memory access (output values are undefined). The timing charts are shown in Figures 5-5 to 5-8. User's Manual U15947EJ2V0UD 135 CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-5. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting ASTB RD AD0 to AD7 Lower address Instruction code A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB RD AD0 to AD7 Lower address Instruction code A8 to A15 Internal wait signal (1-clock wait) Higher address www..com (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD AD0 to AD7 Lower address Instruction code A8 to A15 Higher address WAIT 136 User's Manual U15947EJ2V0UD CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-6. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB RD AD0 to AD7 Lower address Read data A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB RD AD0 to AD7 Lower address Read data A8 to A15 Internal wait signal (1-clock wait) Higher address www..com (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD AD0 to AD7 Lower address Read data A8 to A15 Higher address WAIT User's Manual U15947EJ2V0UD 137 CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-7. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB WR Hi-Z AD0 to AD7 Lower address Write data A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB WR Lower address AD0 to AD7 Hi-Z Write data A8 to A15 Internal wait signal (1-clock wait) Higher address www..com (c) External wait (PW1, PW0 = 1, 1) setting ASTB WR Lower address AD0 to AD7 Hi-Z Write data A8 to A15 Higher address WAIT 138 User's Manual U15947EJ2V0UD CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-8. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB RD WR Lower address Hi-Z Read data Write data AD0 to AD7 A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB RD WR Lower address Hi-Z Read data Write data AD0 to AD7 www..com A8 to A15 Internal wait signal (1-clock wait) Higher address (c) External wait (PW1, PW0 = 1, 1) setting ASTB RD WR Lower address Hi-Z Read data Write data AD0 to AD7 A8 to A15 Higher address WAIT Remark The read-modify-write timing is that of an operation when a bit manipulation instruction is executed. User's Manual U15947EJ2V0UD 139 CHAPTER 5 EXTERNAL BUS INTERFACE 5.4 Example of Connection with Memory An example of connecting the PD780144 with external memory (in this example, SRAM) is shown in Figure 5-9. In addition, the external bus interface function is used in the full-address mode, and the addresses from 0000H to 7FFFH (32 KB) are allocated to internal ROM, and the addresses after 8000H to SRAM. Figure 5-9. Connection Example of PD780144 and Memory VDD PD780144 RD WR Address bus A8 to A14 74HC573 LE Q0 to Q7 AD0 to AD7 D0 to D7 OE PD43256B CS OE WE I/O1 to I/O8 A0 to A14 Data bus ASTB www..com 140 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. * X1 oscillator The X1 oscillator oscillates a clock of fXP = 2.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the main OSC control register (MOC) and processor clock control register (PCC). * Ring-OSC oscillator The Ring-OSC oscillator oscillates a clock of fR = 240 kHz (TYP.). Oscillation can be stopped by setting the Ring-OSC mode register (RCM) when "Can be stopped by software" is set by a mask option and the X1 input clock is used as the CPU clock. * Subsystem clock oscillator The subsystem clock oscillator oscillates a clock of fXT = 32.768 kHz. Oscillation cannot be stopped. When subsystem clock oscillator is not used, setting not to use the on-chip feedback resistor is possible using the processor clock control register (PCC), and the operating current can be reduced in the STOP mode. Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency www..com 6.2 Configuration of Clock Generator The clock generator consists of the following hardware. Table 6-1. Configuration of Clock Generator Item Control registers Processor clock control register (PCC) Ring-OSC mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Oscillator X1 oscillator Ring-OSC oscillator Subsystem clock oscillator Configuration User's Manual U15947EJ2V0UD 141 CHAPTER 6 CLOCK GENERATOR Figure 6-1. Block Diagram of Clock Generator Internal bus Main OSC control register (MOC) MCC CLS MSTOP Main clock mode register (MCM) Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 3 STOP X1 oscillation stabilization time counter Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) 4 Controller Control signal Processor clock control register (PCC) CLS CSS PCC2 PCC1 PCC0 MCS MCM0 C P U CPU clock (fCPU) X1 X1 oscillator X2 fXP fX Operation clock switch fX 2 Ring-OSC oscillator Prescaler fX 22 fX 23 fX 24 Selector fCPU fR www..com Watch clock, clock output function Prescaler Clock to peripheral hardware Mask option 1: Cannot be stopped 0: Can be stopped RSTOP Ring-OSC mode register (RCM) Internal bus Prescaler 8-bit timer H1, watchdog timer 1/2 fXT Subsystem clock oscillator XT1 XT2 FRC 142 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR 6.3 Registers Controlling Clock Generator The following six registers are used to control the clock generator. * Processor clock control register (PCC) * Ring-OSC mode register (RCM) * Main clock mode register (MCM) * Main OSC control register (MOC) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) The PCC register is used to select the CPU clock, the division ratio, main system clock oscillator operation/stop and whether to use the on-chip feedback resistorNote of the subsystem clock oscillator. The PCC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PCC to 00H. Note The feedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage. When the subsystem clock is not used, the operating current in the STOP mode can be reduced by setting bit 6 (FRC) of PCC to 1 (see Figure 6-11 Subsystem Clock Feedback Resistor). www..com User's Manual U15947EJ2V0UD 143 CHAPTER 6 CLOCK GENERATOR Figure 6-2. Format of Processor Clock Control Register (PCC) Address: FFFBH Symbol PCC After reset: 00H <6> FRC R/W Note 1 <7> MCC <5> CLS <4> CSS 3 0 2 PCC2 Note 2 1 PCC1 0 PCC0 MCC 0 1 Oscillation possible Oscillation stopped Control of X1 oscillator operation FRC 0 1 Subsystem clock feedback resistor selection On-chip feedback resistor used On-chip feedback resistor not used Note 3 CLS 0 1 Note 4 CPU clock status X1 input clock or Ring-OSC clock Subsystem clock CSS PCC2 PCC1 PCC0 CPU clock (fCPU) selection MCM0 = 0 MCM0 = 1 fXP fXP/2 2 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 fX fX/2 fX/2 fX/2 fX/2 2 fR fR/2 fR/2 fR/2 fR/2 www..com 0 0 1 1 0 0 0 0 1 fXP/2 fXP/2 fXP/2 2 3 3 3 4 4 4 fXT/2 Other than above Setting prohibited Notes 1. 2. Bit 5 is read-only. When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator operation. When the CPU is operating on the Ring-OSC clock, use bit 7 (MSTOP) of the main OSC control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP instruction should not be used. 3. 4. This bit can be set to 1 only when the subsystem clock is not used. Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register (MCM) are 1. Caution Be sure to clear bit 3 to 0. 144 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR Remarks 1. MCM0: Bit 0 of main clock mode register (MCM) 2. fX: Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC clock oscillation frequency) 3. fR: Ring-OSC clock oscillation frequency 4. fXP: X1 input clock oscillation frequency 5. fXT: Subsystem clock oscillation frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KF1. Therefore, the relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in the Table 6-2. Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) X1 Input Clock 0.2 s 0.4 s 2 Note Minimum Instruction Execution Time: 2/fCPU Ring-OSC Clock 8.3 s (TYP.) 16.6 s (TYP.) 33.2 s (TYP.) 66.4 s (TYP.) 132.8 s (TYP.) - - 122.1 s Note Subsystem Clock (at 32.768 kHz Operation) - - - - - (at 10 MHz Operation) fX fX/2 fX/2 fX/2 fX/2 (at 240 kHz (TYP.) Operation) 0.8 s 1.6 s 3.2 s 3 4 fXT/2 Note The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC clock) (see Figure 6-4). www..com (2) Ring-OSC mode register (RCM) This register sets the operation mode of Ring-OSC. This register is valid when "Can be stopped by software" is set for Ring-OSC by a mask option, and the X1 input clock or subsystem clock is selected as the CPU clock. If "Cannot be stopped" is selected for Ring-OSC by a mask option, settings for this register are invalid. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 6-3. Format of Ring-OSC Mode Register (RCM) Address: FFA0H Symbol RCM 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 0 1 0 <0> RSTOP RSTOP 0 1 Ring-OSC oscillating Ring-OSC stopped Ring-OSC oscillating/stopped Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting RSTOP. User's Manual U15947EJ2V0UD 145 CHAPTER 6 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (X1 input clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 6-4. Format of Main Clock Mode Register (MCM) Address: FFA1H Symbol MCM 7 0 After reset: 00H 6 0 R/W Note 5 0 4 0 3 0 2 0 <1> MCS <0> MCM0 MCS 0 1 Operates with Ring-OSC clock Operates with X1 input clock CPU clock status MCM0 0 1 Ring-OSC clock X1 input clock Selection of clock supplied to CPU Note Bit 1 is read-only. Cautions 1. When Ring-OSC clock is selected as the clock to be supplied to the CPU, the www..com divided clock of the Ring-OSC oscillator output (fX) is supplied to the peripheral hardware (fX = 240 kHz (TYP.)). Operation of the peripheral hardware with Ring-OSC clock cannot be guaranteed. Therefore, when Ring-OSC clock is selected as the clock supplied to the CPU, do not use peripheral hardware. In addition, stop the peripheral hardware before switching the clock supplied to the CPU from the X1 input clock to the Ring-OSC clock. Note, however, that the following peripheral hardware can be used when the CPU operates on the Ring-OSC clock. * Watchdog timer * Clock monitor * 8-bit timer H1 when fR/27 is selected as count clock * Peripheral hardware selecting external clock as the clock source (Except when external count clock of TM0n (n = 0, 1) is selected (TI00n valid edge)) 2. Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1 input clock operation (bit 4 (CSS) of the processor clock control register (PCC) is changed from 1 to 0). 146 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the X1 input clock. This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock. Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 6-5. Format of Main OSC Control Register (MOC) Address: FFA2H Symbol MOC After reset: 00H <7> MSTOP 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 0 MSTOP 0 1 X1 oscillator operating X1 oscillator stopped Control of X1 oscillator operation Cautions 1. Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting MSTOP. 2. To stop X1 oscillation when the CPU is operating on the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC) to 1 (setting by MSTOP is not possible). www..com User's Manual U15947EJ2V0UD 147 CHAPTER 6 CLOCK GENERATOR (5) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, MSTOP = 1, and MCC = 1 clear OSTC to 00H. Figure 6-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H Symbol OSTC 7 0 After reset: 00H 6 0 R 5 0 4 MOST11 3 MOST13 2 MOST14 1 MOST15 0 MOST16 MOST11 1 1 1 1 1 MOST13 0 1 1 1 1 MOST14 0 0 1 1 1 MOST15 0 0 0 1 1 MOST16 0 0 0 0 1 Oscillation stabilization time status 2 /fXP min. (204.8 s min.) 11 2 /fXP min. (819.2 s min.) 13 2 /fXP min. (1.64 ms min.) 2 /fXP min. (3.27 ms min.) 2 /fXP min. (6.55 ms min.) 16 15 14 Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. If the STOP mode is entered and then released while the Ring-OSC clock is being www..com used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. Values in parentheses are reference values for operation with fXP = 10 MHz. 2. fXP: X1 input clock oscillation frequency 148 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU clock. After STOP mode is released with Ring-OSC selected as CPU clock, the oscillation stabilization time must be confirmed by OSTC. OSTS can be set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 05H. Figure 6-7. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H Symbol OSTS 7 0 After reset: 05H 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS2 0 0 0 1 1 OSTS1 0 1 1 0 0 Other than above OSTS0 1 0 1 0 1 11 Oscillation stabilization time selection 2 /fXP (204.8 s) 2 /fXP (819.2 s) 13 2 /fXP (1.64 ms) 2 /fXP (3.27 ms) 2 /fXP (6.55 ms) Setting prohibited 16 15 14 www..com Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 2. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. Values in parentheses are reference values for operation with fXP = 10 MHz. 2. fXP: X1 input clock oscillation frequency User's Manual U15947EJ2V0UD 149 CHAPTER 6 CLOCK GENERATOR 6.4 6.4.1 System Clock Oscillator X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 8.38 MHz, 10 MHz when REGC pin is connected directly to VDD) connected to the X1 and X2 pins. An external clock can be input to the X1 oscillator when the REGC pin is connected directly to VDD. In this case, input the clock signal to the X1 pin and input the inverse signal to the X2 pin. Figure 6-8 shows examples of the external circuit of the X1 oscillator. Figure 6-8. Examples of External Circuit of X1 Oscillator (a) Crystal, ceramic oscillation VSS X1 (b) External clock External clock X1 X2 Crystal resonator or ceramic resonator X2 6.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (Standard: 32.768 kHz) connected to the XT1 and XT2 pins. www..com External clocks can be input to the subsystem clock oscillator when the REGC pin is connected directly to VDD. In this case, input the clock signal to the XT1 pin and the inverse signal to the XT2 pin. Figure 6-9 shows examples of external circuit of the subsystem clock oscillator. Figure 6-9. Examples of External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation (b) External clock VSS XT1 32.768 kHz XT2 External clock XT1 XT2 Cautions are listed on the next page. 150 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR Cautions 1. When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the Figure 6-10 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 6-10 shows examples of incorrect resonator connection. Figure 6-10. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT www..com VSS X1 X2 VSS X1 X2 Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. User's Manual U15947EJ2V0UD 151 CHAPTER 6 CLOCK GENERATOR Figure 6-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 High current VSS X1 X2 A B High current C (e) Signals are fetched www..com VSS X1 X2 Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. 152 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR 6.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. XT1: Connect directly to EVDD or VDD XT2: Leave open In this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator when the X1 input clock and Ring-OSC clock stop. To minimize leakage current, the above on-chip feedback resistor can be set not to be used via bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins as described above. Figure 6-11. Subsystem Clock Feedback Resistor FRC P-ch Feedback resistor XT1 XT2 www..com Remark The feedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage. 6.4.4 Ring-OSC oscillator Ring-OSC oscillator is incorporated in the 78K0/KF1. "Can be stopped by software" or "Cannot be stopped" can be selected by a mask option. The Ring-OSC clock always oscillates after RESET release (240 kHz (TYP.)). 6.4.5 Prescaler The prescaler generates various clocks by dividing the X1 oscillator output when the X1 input clock is selected as the clock to be supplied to the CPU. Caution When the Ring-OSC clock is selected as the clock supplied to the CPU, the prescaler generates various clocks by dividing the Ring-OSC oscillator output (fX = 240 kHz (TYP.)). User's Manual U15947EJ2V0UD 153 CHAPTER 6 CLOCK GENERATOR 6.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. * X1 input clock fXP * Ring-OSC clock fR * Subsystem clock fXT * CPU clock fCPU * Clock to peripheral hardware The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the 78K0/KF1, thus enabling the following. (1) Enhancement of security function When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the on-chip Ring-OSC clock, so the device can be started by the Ring-OSC clock after reset release by the clock monitor (detection of X1 input clock stop). Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) Improvement of performance Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total www..com performance can be improved. A timing diagram of the CPU default start using Ring-OSC is shown in Figure 6-12. 154 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR Figure 6-12. Timing Diagram of CPU Default Start Using Ring-OSC X1 input clock (fXP) Ring-OSC clock (fR) Subsystem clock (fXT) RESET Switched by software CPU clock Operation stopped: 17/fR Ring-OSC clock X1 input clock X1 oscillation stabilization time: 211/fXP to 216/fXPNote Note Check using the oscillation stabilization time counter status register (OSTC). (a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is cleared to 0 and the Ring-OSC clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the www..com Ring-OSC clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks). During the RESET period, oscillation of the X1 input clock and Ring-OSC clock is stopped. (b) After RESET release, the CPU clock can be switched from the Ring-OSC clock to the X1 input clock using bit 0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using bit 1 (MCS) of MCM. (c) Ring-OSC can be set to stopped/oscillating using the Ring-OSC mode register (RCM) when "Can be stopped by software" is selected for the Ring-OSC by a mask option, if the X1 input or subsystem clock is used as the CPU clock. Make sure that MCS is 1 at this time. (d) When Ring-OSC is used as the CPU clock, the X1 input clock can be set to stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time. When the subsystem clock is used as the CPU clock, whether the X1 input clock stops or oscillates can be set by the processor clock control register (PCC). In addition, HALT mode can be used during operation with the subsystem clock, but STOP mode cannot be used (subsystem clock oscillation cannot be stopped by the STOP instruction). (e) Select the X1 input clock oscillation stabilization time (211/fXP, 213/fXP, 214/fXP, 215/fXP, 216/fXP) using the oscillation stabilization time select register (OSTS) when releasing STOP mode while X1 input clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is released and Ring-OSC clock is being used as the CPU clock, check the X1 input clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC). User's Manual U15947EJ2V0UD 155 CHAPTER 6 CLOCK GENERATOR A status transition diagram of this product is shown in Figure 6-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 6-3 and 6-4, respectively. Figure 6-13. Status Transition Diagram (1/4) (1) When "Ring-OSC can be stopped by software" is selected by mask option (when subsystem clock is not used) HALTNote 4 Interrupt Interrupt HALT instruction Status 4 RSTOP = 0 CPU clock: fXP fXP: Oscillating fR: Oscillation stopped RSTOP = 1Note 1 Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating Interrupt HALT instruction MCM0 = 0 MCM0 = 1Note 2 HALT instruction HALT instruction Interrupt Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating MSTOP = 1Note 3 Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating MSTOP = 0 Interrupt STOP instruction STOP instruction Interrupt STOP instruction STOP instruction Interrupt Interrupt STOPNote 4 www..com Reset release ResetNote 5 Notes 1. 2. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 3. 4. When shifting from status 2 to status 1, make sure that MCS is 0. When "Ring-OSC can be stopped by software" is selected by a mask option, the watchdog timer stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer. However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0. 5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT) 156 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (2/4) (2) When "Ring-OSC can be stopped by software" is selected by mask option (when subsystem clock is used) Status 6 CPU clock: fXT fXP: Oscillation stopped fR: Oscillating/ oscillation stopped MCC = 1 MCC = 0 HALT instruction Interrupt HALTNote 4 HALT instruction Interrupt HALT instruction Interrupt HALT instruction HALT instruction Interrupt Status 5 CPU clock: fXT fXP: Oscillating fR: Oscillating/ oscillation stopped CSS = 0Note 5 CSS = 1Note 5 Status 4 Status 3 CPU clock: fXP RSTOP = 0 CPU clock: fXP fXP: Oscillating fXP: Oscillating fR: Oscillation RSTOP = 1Note 1 fR: Oscillating stopped Interrupt Status 1 Status 2 MCM0 = 0 MSTOP = 1Note 3 CPU clock: fR CPU clock: fR fXP: Oscillation fXP: Oscillating stopped MCM0 = 1Note 2 fR: Oscillating MSTOP = 0 fR: Oscillating STOP STOP instruction instruction Interrupt Interrupt Interrupt STOPNote 4 Reset release STOP instruction www..com ResetNote 6 Notes 1. 2. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 3. 4. When shifting from status 2 to status 1, make sure that MCS is 0. When "Ring-OSC can be stopped by software" is selected by a mask option, the clock supply to the watchdog timer is stopped after the HALT or STOP instruction has been executed, regardless of the setting of bit 0 (RSTOP) of the Ring-OSC mode register (RCM) and bit 0 (MCM0) of the main clock mode register (MCM). 5. 6. The operation cannot be shifted between subsystem clock operation and Ring-OSC operation. All reset sources (RESET input, POC, LVI, clock monitor, and WDT) User's Manual U15947EJ2V0UD 157 CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (3/4) (3) When "Ring-OSC cannot be stopped" is selected by mask option (when subsystem clock is not used) HALT Interrupt Interrupt HALT instruction HALT instruction Interrupt HALT instruction Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating MCM0 = 0 MCM0 = 1Note 1 Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating MSTOP = 1Note 2 MSTOP = 0 STOP instruction Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating Interrupt STOP instruction STOP instruction Interrupt Interrupt STOPNote 3 Reset release ResetNote 4 Notes 1. www..com Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 2. 3. When shifting from status 2 to status 1, make sure that MCS is 0. The watchdog timer operates using Ring-OSC even in STOP mode if "Ring-OSC cannot be stopped" is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer overflow after STOP instruction execution. 4. All reset sources (RESET input, POC, LVI, clock monitor, and WDT) 158 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (4/4) (4) When "Ring-OSC cannot be stopped" is selected by mask option (when subsystem clock is used) Status 5 CPU clock: fXT fXP: Oscillation stopped fR: Oscillating Interrupt MCC = 0 MCC = 1 HALT instruction Status 4 CPU clock: fXT fXP: Oscillating fR: Oscillating Interrupt HALT HALT instruction CSS = 0Note 4 CSS = 1Note 4 Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating www..com Interrupt HALT instruction MCM0 = 0 MCM0 = 1Note 1 Interrupt HALT instruction Interrupt HALT instruction Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating MSTOP = 1Note 2 MSTOP = 0 STOP instruction Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating Interrupt STOP instruction STOP instruction Interrupt Interrupt STOPNote 3 Reset release ResetNote 5 Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 2. 3. When shifting from status 2 to status 1, make sure that MCS is 0. The watchdog timer operates using Ring-OSC even in STOP mode if "Ring-OSC cannot be stopped" is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer overflow after STOP instruction execution. 4. 5. The operation cannot be shifted between subsystem clock operation and Ring-OSC operation. All reset sources (RESET input, POC, LVI, clock monitor, and WDT) User's Manual U15947EJ2V0UD 159 CHAPTER 6 CLOCK GENERATOR Table 6-3. Relationship Between Operation Clocks in Each Operation Status Status Operation Mode Reset STOP HALT Oscillating Stopped X1 Oscillator MSTOP = 0 MSTOP = 1 MCC = 0 Stopped MCC = 1 Stopped Oscillating Oscillating Stopped Ring-OSC Oscillator Note 1 Note 2 RSTOP = 0 RSTOP = 1 Subsystem CPU Clock Clock Oscillator After Release Prescaler Clock Supplied to Peripherals MCM0 = 0 MCM0 = 1 Oscillating Ring-OSC Stopped Note 3 Note 4 Stopped Ring-OSC X1 Notes 1. 2. 3. 4. When "Cannot be stopped" is selected for Ring-OSC by a mask option. When "Can be stopped by software" is selected for Ring-OSC by a mask option. Operates using the CPU clock at STOP instruction execution. Operates using the CPU clock at HALT instruction execution. Caution The RSTOP setting is valid only when "Can be stopped by software" is set for Ring-OSC by a mask option. Remark MSTOP: Bit 7 of the main OSC control register (MOC) MCC: MCM0: Bit 7 of the processor clock control register (PCC) Bit 0 of the main clock mode register (MCM) Table 6-4. Oscillation Control Flags and Clock Oscillation Status X1 Oscillator www..com RSTOP: Bit 0 of the Ring-OSC mode register (RCM) Ring-OSC Oscillator Oscillating MSTOP = 1 Note RSTOP = 0 RSTOP = 1 Stopped Setting prohibited Oscillating MSTOP = 0 Note RSTOP = 0 RSTOP = 1 Oscillating Stopped MCC = 1 Note RSTOP = 0 RSTOP = 1 Stopped Oscillating Stopped MCC = 0 Note RSTOP = 0 RSTOP = 1 Oscillating Oscillating Stopped Note Setting X1 oscillator oscillating/stopped differs depending on the CPU clock used. * When the Ring-OSC clock is used as the CPU clock: Set using the MSTOP bit * When the subsystem clock is used as the CPU clock: Set using the MCC bit Caution The RSTOP setting is valid only when "Can be stopped by software" is set for Ring-OSC by a mask option. Remark MSTOP: Bit 7 of the main OSC control register (MOC) MCC: Bit 7 of the processor clock control register (PCC) RSTOP: Bit 0 of the Ring-OSC mode register (RCM) 160 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR 6.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (see Table 6-5). Bit 1 (MCS) of MCM is used to judge that operation is performed using either the Ring-OSC clock or X1 input clock. To stop the original clock after switching the clock, wait for the number of clocks shown in Table 6-5. Table 6-5. Maximum Time Required to Switch Between Ring-OSC Clock and X1 Input Clock PCC PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 PCC0 0 1 0 1 0 fXP/fR + 1 clock fXP/2fR + 1 clock fXP/4fR + 1 clock fXP/8fR + 1 clock fXP/16fR + 1 clock Time Required for Switching X1Ring-OSC Ring-OSCX1 2 clocks Caution To calculate the maximum time, set fR = 120 kHz. Remarks 1. PCC: Processor clock control register 2. fXP: X1 input clock oscillation frequency 3. fR: Ring-OSC clock oscillation frequency www..com 4. The maximum time is the number of clocks of the CPU clock before switching. User's Manual U15947EJ2V0UD 161 CHAPTER 6 CLOCK GENERATOR 6.7 Time Required for CPU Clock Switchover The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on the pre-switchover clock for several instructions (see Table 6-6). Whether the system is operating on the X1 input clock (or Ring-OSC clock) or the subsystem clock can be ascertained using bit 5 (CLS) of the PCC register. Table 6-6. Maximum Time Required for CPU Clock Switchover Set Value Before Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 Set Value After Switchover 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x 16 clocks 16 clocks 16 clocks 16 clocks fXP/fXT clocks (306 clocks) 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks fXP/2fXT clocks (153 clocks) 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks fXP/4fXT clocks (77 clocks) 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks fXP/8fXT clocks (39 clocks) 1 www..com 0 x 0 x 1 clock 1 clock 1 clock 1 clock fXP/16fXT clocks (20 clocks) 1 x 1 clock 1 clock 1 clock 1 clock 1 clock Remarks 1. The maximum time is the number of clocks of the CPU clock before switching. 2. Figures in parentheses apply to operation with fXP = 10 MHz and fXT = 32.768 kHz. Caution Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the X1 input clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the X1 input clock (changing CSS from 1 to 0). 162 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR 6.8 6.8.1 Clock Switching Flowchart and Register Setting Switching from Ring-OSC clock to X1 input clock Figure 6-14. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart) After reset release Register initial value after reset PCC = 00H RCM = 00H MCM = 00H MOC = 00H OSTC = 00H OSTS = 05HNote ; fCPU = fR ; Ring-OSC oscillation ; Ring-OSC clock operation ; X1 oscillation ; Oscillation stabilization time status register ; Oscillation stabilization time fXP/216 Each processing OSTC checkNote www..com ; X1 oscillation stabilization time status check Ring-OSC clock operation X1 oscillation stabilization time has not elapsed X1 oscillation stabilization time has elapsed PCC setting Ring-OSC clock operation (dividing set PCC) MCM.0 1 MCM.1 (MCS) is changed from 0 to 1 X1 input clock operation X1 input clock operation Note Check the oscillation stabilization wait time of the X1 oscillator after reset release using the OSTC register and then switch to the X1 input clock operation after the oscillation stabilization wait time has elapsed. The OSTS register setting is valid only after STOP mode is released by interrupt during X1 input clock operation. User's Manual U15947EJ2V0UD 163 CHAPTER 6 CLOCK GENERATOR 6.8.2 Switching from X1 input clock to Ring-OSC clock Figure 6-15. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart) Register setting in X1 input clock operation PCC.7 (MCC) = 0 PCC.4 (CSS) = 0 MCM = 03H ; X1 oscillation ; X1 input clock or Ring-OSC clock ; X1 input clock operation Yes: RSTOP = 1 X1 input clock operation RCM.0Note (RSTOP) = 1? ; Ring-OSC oscillating? No: RSTOP = 0 RSTOP = 0 MCM0 0 www..com ; Ring-OSC clock operation MCM.1 (MCS) is changed from 1 to 0 Ring-OSC clock operation Ring-OSC clock operation Note Required only when "clock can be stopped by software" is selected for Ring-OSC by a mask option. 164 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR 6.8.3 Switching from X1 input clock to subsystem clock Figure 6-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart) Register setting in X1 input clock operation PCC.7 (MCC) = 0 PCC.4 (CSS) = 0 MCM = 03H ; X1 oscillation ; X1 input clock or Ring-OSC clock ; X1 input clock operation X1 input clock operation CSS 1Note ; Subsystem clock operation MCS = 1 not changed. CLS is changed from 0 to 1. Subsystem clock Subsystem clock operation Note Set CSS to 1 after confirming that oscillation of the subsystem clock is stabilized. www..com User's Manual U15947EJ2V0UD 165 CHAPTER 6 CLOCK GENERATOR 6.8.4 Switching from subsystem clock to X1 input clock Figure 6-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart) PCC.4 (CSS) = 1 MCM = 03H ; Subsystem clock operation No: X1 oscillating MCC = 1? ; X1 oscillating? Yes: X1 oscillation stopped MCC 0 Subsystem clock operation ; X1 oscillation enabled OSTC check X1 oscillation stabilization time not elapsed ; Wait for X1 oscillation stabilization time X1 oscillation stabilization time elapsed www..com CSS 0 ; X1 input clock operation CLS is changed from 1 to 0. MCS = 1 not changed. X1 input clock operation X1 input clock operation 166 User's Manual U15947EJ2V0UD CHAPTER 6 CLOCK GENERATOR 6.8.5 Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. Table 6-7. Clock and Register Setting fCPU Mode PCC Register Setting Flag MCM MOC RCM Note 1 Status Flag PCC MCM Register Register Register Register Register MCC X1 input clock Note 2 CSS 0 0 0 0 1 1 1 1 MCM0 1 1 0 0 1 1 1 Note 5 SO MSTOP R T P 0 0 0 1 0 0 0 0 Note 6 CLS 0 0 0 0 1 1 1 1 MCS 1 1 0 0 1 1 1 1 Ring-OSC oscillating Ring-OSC stopped 0 0 0 0 Note 3 0 1 0 0 0 0 1 1 Ring-OSC clock X1 oscillating X1 stopped Subsystem clock Note 4 X1 oscillating, Ring-OSC oscillating X1 stopped, Ring-OSC oscillating X1 oscillating, Ring-OSC stopped X1 stopped, Ring-OSC stopped 0 1 0 1 Note 5 Note 6 Note 5 Note 6 1 Note 5 Note 6 Notes 1. 2. 3. www..com Valid only when "clock can be stopped by software" is selected for Ring-OSC by a mask option. Do not set MCC = 1 or MSTOP = 1 during X1 input clock operation (even if MCC = 1 or MSTOP = 1 is set, the X1 oscillation does not stop). Do not set MCC = 1 during Ring-OSC operation (even if MCC = 1 is set, the X1 oscillation does not stop). To stop X1 oscillation during Ring-OSC operation, use MSTOP. Shifting to subsystem clock operation mode must be performed from the X1 input clock operation mode. From subsystem clock operation mode, only X1 input clock operation mode can be shifted to. Do not set MCM0 = 0 (shifting to Ring-OSC) during subsystem clock operation. Do not set MSTOP = 1 during subsystem clock operation (even if MSTOP = 1 is set, X1 oscillation does not stop). To stop X1 oscillation during subsystem clock operation, use MCC. 4. 5. 6. User's Manual U15947EJ2V0UD 167 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 The PD780143 and 780144 incorporate 16-bit timer/event counter 00, and the PD780146, 780148, and 78F0148 incorporate 16-bit timer/event counters 00 and 01. 7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01Note have the following functions. * Interval timer * PPG output * Pulse width measurement * External event counter * Square-wave output * One-shot pulse output (1) Interval timer 16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval. (2) PPG output 16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can be set freely. www..com (3) Pulse width measurement 16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal. (4) External event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (5) Square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (6) One-shot pulse output 16-bit timer/event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely. Note Available only for the PD780146, 780148, and 78F0148. 168 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 consist of the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Timer counter Register Timer input Timer output Control registers 16 bits (TM0n) 16-bit timer capture/compare register: 16 bits (CR00n, CR01n) TI00n, TI01n TO0n, output controller 16-bit timer mode control register 0n (TMC0n) 16-bit timer capture/compare control register 0n (CRC0n) 16-bit timer output control register 0n (TOC0n) Prescaler mode register 0n (PRM0n) Port mode register 0 (PM0) Port register 0 (P0) Configuration Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: Figures 7-1 and 7-2 show the block diagrams. Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 00 www..com Internal bus Capture/compare control register 00 (CRC00) CRC002CRC001 CRC000 Selector INTTM000 Selector TI010/TO00/P01 Noise eliminator 16-bit timer capture/compare register 000 (CR000) Match Selector fX fX/22 fX/28 16-bit timer counter 00 (TM00) Match Clear Output controller Output latch (P01) PM01 TO00/TI010/ P01 fX Noise eliminator 2 Noise eliminator 16-bit timer capture/compare register 010 (CR010) Selector TI000/P00 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus User's Manual U15947EJ2V0UD 169 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 (PD780146, 780148, and 78F0148 Only) Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 Selector INTTM001 Selector TI011/TO01/P06 Noise eliminator 16-bit timer capture/compare register 001 (CR001) Match Selector fX fX/24 fX/26 16-bit timer counter 01 (TM01) Match Clear Output controller Output latch (P06) PM06 TO01/TI011/ P06 fX Noise eliminator 2 Noise eliminator 16-bit timer capture/compare register 011 (CR011) Selector TI001/P05 INTTM011 CRC012 PRM011 PRM010 Prescaler mode register 01 (PRM01) TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 16-bit timer output 16-bit timer mode control register 01 control register 01 (TOC01) (TMC01) Internal bus www..com 170 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n) Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) Symbol FF11H (TM00) FFB1H (TM01) After reset: 0000H R FF10H (TM00) FFB0H (TM01) TM0n (n = 0, 1) The count value is reset to 0000H in the following cases. <1> At RESET input <2> If TMC0n3 and TMC0n2 are cleared <3> If the valid edge of TI00n is input in the mode in which clear & start occurs when inputting the valid edge of TI00n <4> If TM0n and CR00n match in the mode in which clear & start occurs on a match of TM0n and CR00n <5> OSPT0n is set in one-shot pulse output mode (2) 16-bit timer capture/compare register 00n (CR00n) CR00n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC0n0) of capture/compare control register www..com 0n (CRC0n). CR00n can be set by a 16-bit memory manipulation instruction. RESET input clears this register to 0000H. Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n) Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001) Symbol FF13H (CR000) FFB3H (CR001) After reset: 0000H R/W FF12H (CR000) FFB2H (CR001) CR00n (n = 0, 1) * When CR00n is used as a compare register The value set in CR00n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an interrupt request (INTTM00n) is generated if they match. The set value is held until CR00n is rewritten. * When CR00n is used as a capture register It is possible to select the valid edge of the TI00n pin or the TI01n pin as the capture trigger. The TI00n or TI01n pin valid edge is set using prescaler mode register 0n (PRM0n) (see Table 7-2). User's Manual U15947EJ2V0UD 171 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1) CR00n Capture Trigger TI00n Pin Valid Edge ES0n1 Falling edge Rising edge No capture operation Rising edge Falling edge Both rising and falling edges 0 0 1 ES0n0 1 0 1 (2) TI01n pin valid edge selected as capture trigger (CRC0n1 = 0, CRC0n0 = 1) CR00n Capture Trigger TI01n Pin Valid Edge ES1n1 Falling edge Rising edge Both rising and falling edges Falling edge Rising edge Both rising and falling edges 0 0 1 ES1n0 0 1 1 Remarks 1. Setting ES0n1, ES0n0 = 1, 0 and ES1n1, ES1n0 = 1, 0 is prohibited. 2. ES0n1, ES0n0: ES1n1, ES1n0: Bits 5 and 4 of prescaler mode register 0n (PRM0n) Bits 7 and 6 of prescaler mode register 0n (PRM0n) CRC0n1, CRC0n0: Bits 1 and 0 of capture/compare control register 0n (CRC0n) 3. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 www..com Cautions 1. Set a value other than 0000H in CR00n in the mode in which clear & start occurs on a match of TM0n and CR00n. However, in the free-running mode and in the clear mode using the valid edge of TI00n, if CR00n is cleared to 0000H, an interrupt request (INTTM00n) is generated when the value of CR00n changes from 0000H to 0001H following overflow (FFFFH). 2. When P01 or P06 is used as the valid edge input pin of TI01n, it cannot be used as the timer output (TO0n). Moreover, when P01 or P06 is used as TO0n, it cannot be used as the valid edge input pin of TI01n. 3. When CR00n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 4. Do not rewrite CR00n during TM0n operation. 172 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n (CRC0n). CR01n can be set by a 16-bit memory manipulation instruction. RESET input clears this register to 0000H. Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n) Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011) Symbol FF15H (CR010) FFB5H (CR011) After reset: 0000H R/W FF14H (CR010) FFB4H (CR011) CR01n (n = 0, 1) * When CR01n is used as a compare register The value set in the CR01n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an interrupt request (INTTM01n) is generated if they match. The set value is held until CR01n is rewritten. * When CR01n is used as a capture register It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n valid edge is set by prescaler mode register 0n (PRM0n) (see Table 7-3). Table 7-3. CR01n Capture Trigger and Valid Edge of TI00n Pin (CRC0n2 = 1) www..com CR01n Capture Trigger TI00n Pin Valid Edge ES0n1 ES0n0 0 1 1 Falling edge Rising edge Both rising and falling edges Falling edge Rising edge Both rising and falling edges 0 0 1 Remarks 1. Setting ES0n1, ES0n0 = 1, 0 is prohibited. 2. ES0n1, ES0n0: Bits 5 and 4 of prescaler mode register 0n (PRM0n) CRC0n2: Bit 2 of capture/compare control register 0n (CRC0n) 3. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Cautions 1. If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is generated after the TM0n register overflows, after the timer is cleared and started on a match between the TM0n register and the CR00n register, or after the timer is cleared by the valid edge of TI00n or a one-shot trigger. 2. When CR01n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 3. CR01n can be rewritten during TM0n operation. For details, see Caution 2 in Figure 7-20. User's Manual U15947EJ2V0UD 173 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 The following six registers are used to control 16-bit timer/event counters 00 and 01. * 16-bit timer mode control register 0n (TMC0n) * Capture/compare control register 0n (CRC0n) * 16-bit timer output control register 0n (TOC0n) * Prescaler mode register 0n (PRM0n) * Port mode register 0 (PM0) * Port register 0 (P0) (1) 16-bit timer mode control register 0n (TMC0n) This register sets the 16-bit timer operating mode, 16-bit timer counter 0n (TM0n) clear mode, and output timing, and detects an overflow. TMC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC0n to 00H. Caution 16-bit timer counter 0n (TM0n) starts operation at the moment TMC0n2 and TMC0n3 are set to values other than 0, 0 (operation stop mode), respectively. Clear TMC0n2 and TMC0n3 to 0, 0 to stop the operation. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 www..com 174 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH Symbol TMC00 7 0 6 0 After reset: 00H 5 0 4 0 R/W 3 2 1 <0> TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear mode selection TO00 inversion timing selection Interrupt request generation 0 0 0 0 0 1 0 1 0 Operation stop (TM00 cleared to 0) Free-running mode No change Not generated Match between TM00 and CR000 or match between TM00 and CR010 Generated on match between TM00 and CR000, or match between TM00 and CR010 0 1 1 Match between TM00 and CR000, match between TM00 and CR010 or TI000 valid edge - 1 1 1 0 0 1 0 1 0 Clear & start occurs on TI000 valid edge Clear & start occurs on match between TM00 and CR000 Match between TM00 and CR000 or match between TM00 and CR010 1 1 1 Match between TM00 and CR000, match between TM00 and CR010 or TI000 valid edge www..com OVF00 0 1 Overflow not detected Overflow detected 16-bit timer counter 00 (TM00) overflow detection Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag. 2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00). 3. If any of the following modes is selected: the mode in which clear & start occurs on match between TM00 and CR000, the mode in which clear & start occurs at the TI00 valid edge, or free-running mode, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. Remarks 1. TO00: 2. TI000: 3. TM00: 16-bit timer/event counter 00 output pin 16-bit timer/event counter 00 input pin 16-bit timer counter 00 4. CR000: 16-bit timer capture/compare register 000 5. CR010: 16-bit timer capture/compare register 010 User's Manual U15947EJ2V0UD 175 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H Symbol TMC01 7 0 6 0 After reset: 00H 5 0 4 0 R/W 3 2 1 <0> TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 TMC011 Operating mode and clear mode selection TO01 inversion timing selection Interrupt request generation 0 0 0 0 0 1 0 1 0 Operation stop (TM01 cleared to 0) Free-running mode No change Not generated Match between TM01 and CR001 or match between TM01 and CR011 Generated on match between TM01 and CR001, or match between TM01 and CR011 0 1 1 Match between TM01 and CR001, match between TM01 and CR011 or TI001 valid edge - 1 1 1 0 0 1 0 1 0 Clear & start occurs on TI001 valid edge Clear & start occurs on match between TM01 and CR001 Match between TM01 and CR001 or match between TM01 and CR011 1 1 1 Match between TM01 and CR001, match between TM01 and CR011 or TI001 valid edge www..com OVF01 0 1 Overflow not detected Overflow detected 16-bit timer counter 01 (TM01) overflow detection Cautions 1. Timer operation must be stopped before writing to bits other than the OVF01 flag. 2. Set the valid edge of the TI001/P05 pin using prescaler mode register 01 (PRM01). 3. If any of the following modes is selected: the mode in which clear & start occurs on match between TM01 and CR001, the mode in which clear & start occurs at the TI01 valid edge, or free-running mode, when the set value of CR001 is FFFFH and the TM01 value changes from FFFFH to 0000H, the OVF01 flag is set to 1. Remarks 1. TO01: 2. TI001: 3. TM01: 16-bit timer/event counter 01 output pin 16-bit timer/event counter 01 input pin 16-bit timer counter 01 4. CR001: 16-bit timer capture/compare register 001 5. CR011: 16-bit timer capture/compare register 011 176 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) This register controls the operation of the 16-bit timer capture/compare registers (CR00n, CR01n). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0n to 00H. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: Figure 7-8. Format of Capture/Compare Control Register 00 (CRC00) Address: FFBCH Symbol CRC00 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 CRC002 1 CRC001 0 CRC000 CRC002 0 1 CR010 operating mode selection Operates as compare register Operates as capture register CRC001 0 1 CR000 capture trigger selection Captures on valid edge of TI010 Captures on valid edge of TI000 by reverse phase www..com CRC000 0 1 CR000 operating mode selection Operates as compare register Operates as capture register Cautions 1. Timer operation must be stopped before setting CRC00. 2. When the mode in which clear & start occurs on a match between TM00 and CR000 is selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. 3. The capture operation is not performed if both the rising and falling edges are specified as the valid edge of TI000. 4. To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00). User's Manual U15947EJ2V0UD 177 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-9. Format of Capture/Compare Control Register 01 (CRC01) Address: FFB8H Symbol CRC01 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 CRC012 1 CRC011 0 CRC010 CRC012 0 1 CR011 operating mode selection Operates as compare register Operates as capture register CRC011 0 1 CR001 capture trigger selection Captures on valid edge of TI011 Captures on valid edge of TI001 by reverse phase CRC010 0 1 CR001 operating mode selection Operates as compare register Operates as capture register Cautions 1. Timer operation must be stopped before setting CRC01. 2. When the mode in which clear & start occurs on a match between TM01 and CR001 is selected with 16-bit timer mode control register 01 (TMC01), CR001 should not be specified as a capture register. www..com 3. The capture operation is not performed if both the rising and falling edges are specified as the valid edge of TI001. 4. To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 01 (PRM01). (3) 16-bit timer output control register 0n (TOC0n) This register controls the operation of 16-bit timer/event counter 0n output controller. It sets/resets the timer output F/F (LV0n), enables/disables output inversion and 16-bit timer/event counter 0n timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software. TOC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TOC0n to 00H. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 178 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-10. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH Symbol TOC00 7 0 After reset: 00H <6> OSPT00 R/W <5> OSPE00 4 TOC004 <3> LVS00 <2> LVR00 1 TOC001 <0> TOE00 OSPT00 0 1 One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger OSPE00 0 1 One-shot pulse output operation control Successive pulse output mode One-shot pulse output mode Note TOC004 0 1 Timer output F/F control using match of CR010 and TM00 Disables inversion operation Enables inversion operation LVS00 0 0 www..com LVR00 0 1 0 1 No change Timer output F/F status setting Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited 1 1 TOC001 0 1 Timer output F/F control using match of CR000 and TM00 Disables inversion operation Enables inversion operation TOE00 0 1 Timer output control Disables output (output fixed to level 0) Enables output Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. Timer operation must be stopped before setting other than TOC004. 2. If LVS00 and LVR00 are read, 0 is read. 3. OSPT00 is automatically cleared after data is set, so 0 is read. 4. Do not set OSPT00 to 1 other than in one-shot pulse output mode. 5. A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required to write to OSPT00 successively. 6. Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously. User's Manual U15947EJ2V0UD 179 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-11. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H Symbol TOC01 7 0 After reset: 00H <6> OSPT01 R/W <5> OSPE01 4 TOC014 <3> LVS01 <2> LVR01 1 TOC011 <0> TOE01 OSPT01 0 1 One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger OSPE01 0 1 One-shot pulse output operation control Successive pulse output mode One-shot pulse output mode Note TOC014 0 1 Timer output F/F control using match of CR011 and TM01 Disables inversion operation Enables inversion operation LVS01 0 0 www..com LVR01 0 1 0 1 No change Timer output F/F status setting Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited 1 1 TOC011 0 1 Timer output F/F control using match of CR001 and TM01 Disables inversion operation Enables inversion operation TOE01 0 1 Timer output control Disables output (output fixed to level 0) Enables output Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI001 valid edge. In the mode in which clear & start occurs on a match between the TM01 register and CR001 register, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. Timer operation must be stopped before setting other than TOC014. 2. If LVS01 and LVR01 are read, 0 is read. 3. OSPT01 is automatically cleared after data is set, so 0 is read. 4. Do not set OSPT01 to 1 other than in one-shot pulse output mode. 5. A write interval of two cycles or more of the count clock selected by prescaler mode register 01 (PRM01) is required to write to OSPT01 successively. 6. Do not set LVS01 to 1 before TOE01, and do not set LVS01 and TOE01 to 1 simultaneously. 180 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) This register is used to set the 16-bit timer counter 0n (TM0n) count clock and TI00n and TI01n input valid edges. PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM0n to 00H. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: www..com User's Manual U15947EJ2V0UD 181 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-12. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH Symbol PRM00 7 ES101 After reset: 00H 6 ES100 R/W 5 ES001 4 ES000 3 0 2 0 1 PRM001 0 PRM000 ES101 0 0 1 1 ES100 0 1 0 1 Falling edge Rising edge Setting prohibited TI010 valid edge selection Both falling and rising edges ES001 0 0 1 1 ES000 0 1 0 1 Falling edge Rising edge Setting prohibited TI000 valid edge selection Both falling and rising edges PRM001 0 0 1 www..com PRM000 0 1 0 1 fX (10 MHz) fX/2 (2.5 MHz) fX/2 (39.06 kHz) TI000 valid edge Note 8 2 Count clock selection 1 Note The external clock requires a pulse two cycles longer than internal clock (fX). Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 00 is not guaranteed. When an external clock is used and when the Ring-OSC clock is selected and supplied to the CPU, the operation of 16-bit timer/event counter 00 is not guaranteed, either, because the Ring-OSC clock is supplied as the sampling clock to eliminate noise. 2. Always set data to PRM00 after stopping the timer operation. 3. If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode using the valid edge of TI000 and the capture trigger. 4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when reenabling operation after the operation has been stopped once, the rising edge is not detected. 5. When P01 is used as the TI010 valid edge, it cannot be used as the timer output (TO00), and when used as TO00, it cannot be used as the TI010 valid edge. Remarks 1. fX: X1 input clock oscillation frequency 2. TI000, TI010: 16-bit timer/event counter 00 input pin 3. Figures in parentheses are for operation with fX = 10 MHz. 182 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-13. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H Symbol PRM01 7 ES111 After reset: 00H 6 ES110 R/W 5 ES011 4 ES010 3 0 2 0 1 PRM011 0 PRM010 ES111 0 0 1 1 ES110 0 1 0 1 Falling edge Rising edge Setting prohibited TI011 valid edge selection Both falling and rising edges ES011 0 0 1 1 ES010 0 1 0 1 Falling edge Rising edge Setting prohibited TI001 valid edge selection Both falling and rising edges PRM011 0 0 1 www..com PRM010 0 1 0 1 fX (10 MHz) fX/2 (625 kHz) fX/2 (156.25 kHz) TI001 valid edge Note 6 4 Count clock selection 1 Note The external clock requires a pulse two cycles longer than internal clock (fX). Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 01 is not guaranteed. When an external clock is used and when the Ring-OSC clock is selected and supplied to the CPU, the operation of 16-bit timer/event counter 01 is not guaranteed, either, because the Ring-OSC clock is supplied as the sampling clock to eliminate noise. 2. Always set data to PRM01 after stopping the timer operation. 3. If the valid edge of TI001 is to be set for the count clock, do not set the clear & start mode using the valid edge of TI001 and the capture trigger. 4. If the TI001 or TI011 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI001 pin or TI011 pin to enable the operation of 16-bit timer counter 01 (TM01). Care is therefore required when pulling up the TI001 or TI011 pin. However, when reenabling operation after the operation has been stopped once, the rising edge is not detected. 5. When P06 is used as the TI011 valid edge, it cannot be used as the timer output (TO01), and when used as TO01, it cannot be used as the TI011 valid edge. Remarks 1. fX: X1 input clock oscillation frequency 2. TI001, TI011: 16-bit timer/event counter 01 input pin 3. Figures in parentheses are for operation with fX = 10 MHz. User's Manual U15947EJ2V0UD 183 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01Note/TI011Note pins for timer output, clear PM01 and PM06 and the output latches of P01 and P06 to 0. When using the P01/TO00/TI010 and P06/TO01Note/TI011Note pins for timer input, clear PM01 and PM06 to 0. At this time, the output latches of P01 and P06 may be 0 or 1. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0 to FFH. Figure 7-14. Format of Port Mode Register 0 (PM0) Address: FF20H Symbol PM0 7 1 6 After reset: FFH 5 4 R/W 3 2 1 0 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n 0 1 P0n pin I/O mode selection (n = 0 to 6) Output mode (output buffer on) Input mode (output buffer off) Note Available only for the PD780146, 780148, and 78F0148. www..com 184 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4 7.4.1 Operation of 16-Bit Timer/Event Counters 00 and 01 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-15 allows operation as an interval timer. Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-15 for the set value). <2> Set any value to the CR00n register. <3> Set the count clock by using the PRM0n register. <4> Set the TMC0n register to start the operation (see Figure 7-15 for the set value). Caution CR00n cannot be rewritten during TM0n operation. Remark For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 00n (CR00n) as the interval. When the count value of 16-bit timer counter 0n (TM0n) matches the value set in CR00n, counting continues with the TM0n value cleared to 0 and the interrupt request signal (INTTM00n) is generated. The count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler mode register 0n (PRM0n). www..com Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 185 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-15. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0/1 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0/1 0/1 0 CR00n used as compare register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0/1 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) www..com Remarks 1. 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details. 2. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 186 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-16. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00n (CR00n) INTTM00n fX (fX)Note 1 fX/22 (fX/24)Note 1 fX/28 (fX/26)Note 1 TI000/P00 (TI001/P05)Note 1 Noise eliminator Selector 16-bit timer counter 0n (TM0n) Note 2 OVF0n Clear circuit fX Notes 1. 2. Frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. OVF0n is set to 1 only when 16-bit timer capture/compare register 00n is set to FFFFH. Figure 7-17. Timing of Interval Timer Operation t Count clock www..com TM0n count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N Timer operation enabled CR00n INTTM00n N N Interrupt acknowledged Interrupt acknowledged Remark Interval time = (N + 1) x t N = 0001H to FFFFH n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 187 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-18 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-18 for the set value). <2> Set any value to the CR00n register as the cycle. <3> Set any value to the CR01n register as the duty factor. <4> Set the TOC0n register (see Figure 7-18 for the set value). <5> Set the count clock by using the PRM0n register. <6> Set the TMC0n register to start the operation (see Figure 7-18 for the set value). Caution To change the value of the duty factor (the value of the CR01n register) during operation, see Caution 2 in Figure 7-20 PPG Output Operation Timing. Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. In the PPG output operation, rectangular waves are output from the TO0n pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 01n (CR01n) and in 16-bit timer capture/compare register 00n (CR00n), respectively. www..com Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 188 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-18. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0 x 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n 0 0 1 0/1 0/1 1 1 Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited). www..com Inverts output on match between TM0n and CR01n. Disables one-shot pulse output. (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0/1 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Cautions 1. Values in the following range should be set in CR00n and CR01n: 0000H CR01n < CR00n FFFFH 2. The cycle of the pulse generated through PPG output (CR00n setting value + 1) has a duty of (CR01n setting value + 1)/(CR00n setting value + 1). Remark x: Don't care n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 189 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-19. Configuration Diagram of PPG Output 16-bit timer capture/compare register 00n (CR00n) fX (fX)Note fX/2 (fX/24)Note 2 Selector fX/28 (fX/26)Note TI000/P00 (TI001/P05)Note Noise eliminator fX 16-bit timer counter 0n (TM0n) Clear circuit Output controller TO00/TI010/P01 ( TO01/TI011/P06 ) 16-bit timer capture/compare register 01n (CR01n) Note Frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. Figure 7-20. PPG Output Operation Timing t Count clock www..com TM0n count value N 0000H 0001H M-1 M N-1 N 0000H 0001H Clear CR00n capture value CR01n capture value TO0n Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M Clear Cautions 1. CR00n cannot be rewritten during TM0n operation. 2. In the PPG output operation, change the pulse width (rewrite CR01n) during TM0n operation using the following procedure. <1> Disable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 0) <2> Disable the INTTM01n interrupt (TMMK01n = 1) <3> Rewrite CR01n <4> Wait for 1 cycle of the TM0n count clock <5> Enable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 1) <6> Clear the interrupt request flag of INTTM01n (TMIF01n = 0) <7> Enable the INTTM01n interrupt (TMMK01n = 0) Remarks 1. 0000H M < N FFFFH 2. n = 0: PD780143, 780144, n = 0, 1: PD780146, 780148, 78F0148 190 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer counter 0n (TM0n). There are two measurement methods: measuring with TM0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00n pin. When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 0n (PRM0n) and the valid level of the TI00n or TI01n pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-21. CR01n Capture Operation with Rising Edge Specified Count clock TM0n TI00n Rising edge detection CR01n INTTM01n N N-3 N-2 N-1 N N+1 www..com Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figures 7-22, 7-25, 7-27, and 7-29 for the set value). <2> Set the count clock by using the PRM0n register. <3> Set the TMC0n register to start the operation (see Figures 7-22, 7-25, 7-27, and 7-29 for the set value). Caution To use two capture registers, set the TI00n and TI01n pins. Remarks 1. For the setting of the TI00n (or TI01n) pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n (or INTTM01n) interrupt, see CHAPTER 19 FUNCTIONS. 3. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 INTERRUPT User's Manual U15947EJ2V0UD 191 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an external interrupt request signal (INTTM01n) is set. Specify both the rising and falling edges by using bits 4 and 5 (ES0n0 and ES0n1) of PRM0n. Sampling is performed using the count clock selected by PRM0n, and a capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI00n and CR01n Are Used) (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 0 1 0/1 0 Free-running mode (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 1 0/1 0 CR00n used as compare register CR01n used as capture register www..com (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 1 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 192 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-23. Configuration Diagram for Pulse Width Measurement with Free-Running Counter fX (fX)Note Selector fX/22 (fX/24)Note fX/2 (fX/2 ) 8 6 Note 16-bit timer counter 0n (TM0n) OVF0n TI00n 16-bit timer capture/compare register 01n (CR01n) INTTM01n Internal bus Note Frequencies without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16bit timer/event counter 01. Figure 7-24. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock www..com TM0n count value TI00n pin input CR01n capture value INTTM01n OVF0n 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 D0 D1 D2 D3 Note (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t Note Clear OVF0n by software. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 193 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI00n pin and the TI01n pin. When the edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set. Also, when the edge specified by bits 6 and 7 (ES1n0 and ES1n1) of PRM0n is input to the TI01n pin, the value of TM0n is taken into 16-bit timer capture/compare register 00n (CR00n) and an interrupt request signal (INTTM00n) is set. Specify both the rising and falling edges as the edges of the TI00n and TI01n pins, by using bits 4 and 5 (ES0n0 and ES0n1) and bits 6 and 7 (ES1n0 and ES1n1) of PRM0n. Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n), and a capture operation is only performed when a valid level of the TI00n or TI01n pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-25. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 0 1 0/1 0 Free-running mode www..com (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 1 0 1 CR00n used as capture register Captures valid edge of TI01n pin to CR00n. CR01n used as capture register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 1 1 1 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Specifies both edges for pulse width detection. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 194 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-26. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM0n count value TI00n pin input CR01n capture value INTTM01n TI01n pin input CR00n capture value INTTM00n OVF0n Note D1 D2 + 1 D0 D1 D2 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t (10000H - D1 + (D2 + 1)) x t www..com Note Clear OVF0n by software. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 195 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI00n pin. When the rising or falling edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set. Also, when the inverse edge to that of the capture operation is input into CR01n, the value of TM0n is taken into 16-bit timer capture/compare register 00n (CR00n). Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n), and a capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width. Figure 7-27. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 0 1 0/1 0 Free-running mode (b) Capture/compare control register 0n (CRC0n) www..com 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 1 1 1 CR00n used as capture register Captures to CR00n at inverse edge to valid edge of TI00n. CR01n used as capture register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 196 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-28. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM0n count value TI00n pin input CR01n capture value CR00n capture value INTTM01n OVF0n (D1 - D0) x t (10000H - D1 + D2) x t Note (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 Note Clear OVF0n by software. (4) Pulse width measurement by means of restart When input of a valid edge to the TI00n pin is detected, the count value of 16-bit timer counter 0n (TM0n) is taken into 16-bit timer capture/compare register 01n (CR01n), and then the pulse width of the signal input to the TI00n www..com pin is measured by clearing TM0n and restarting the count operation. Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n). Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n) and a capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 197 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-29. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 0 0/1 0 Clears and starts at valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC00n 1 1 1 CR00n used as capture register Captures to CR00n at inverse edge to valid edge of TI00n. CR01n used as capture register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). www..com Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Figure 7-30. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) t Count clock TM0n count value TI00n pin input CR01n capture value CR00n capture value INTTM01n D1 x t D2 x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 198 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-31 for the set value). <2> Set the count clock by using the PRM0n register. <3> Set any value to the CR00n register (0000H cannot be set). <4> Set the TMC0n register to start the operation (see Figure 7-31 for the set value). Remarks 1. For the setting of the TI00n pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. The external event counter counts the number of external clock pulses input to the TI00n pin using 16-bit timer counter 0n (TM0n). TM0n is incremented each time the valid edge specified by prescaler mode register 0n (PRM0n) is input. When the TM0n count value matches the 16-bit timer capture/compare register 00n (CR00n) value, TM0n is cleared to 0 and the interrupt request signal (INTTM00n) is generated. Input a value other than 0000H to CR00n (a count operation with 1-bit pulse cannot be carried out). Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n). Sampling is performed using the internal clock (fX) and an operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width. www..com User's Manual U15947EJ2V0UD 199 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-31. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0/1 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0/1 0/1 0 CR00n used as compare register (c) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0 1 3 0 2 0 PRM0n1 PRM0n0 1 1 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) www..com Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 200 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 00n (CR00n) Match INTTM00n Clear fX Noise eliminator 16-bit timer counter 0n (TM0n) OVF0nNote Valid edge of TI00n Note OVF0n is set to 1 only when CR00n is set to FFFFH. Figure 7-33. External Event Counter Operation Timing (with Rising Edge Specified) TI00n pin input TM0n count value CR00n INTTM00n www..com 0000H 0001H 0002H 0003H 0004H 0005H N N-1 N 0000H 0001H 0002H 0003H Caution When reading the external event counter count value, TM0n should be read. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 201 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 7-34 for the set value). <3> Set the TOC0n register (see Figure 7-34 for the set value). <4> Set any value to the CR00n register (0000H cannot be set). <5> Set the TMC0n register to start the operation (see Figure 7-34 for the set value). Caution CR00n cannot be rewritten during TM0n operation. Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 00n (CR00n). The TO0n pin output status is reversed at intervals determined by the count value preset to CR00n + 1 by setting bit 0 (TOE0n) and bit 1 (TOC0n1) of 16-bit timer output control register 0n (TOC0n) to 1. This enables a square wave with any selected frequency to be output. Figure 7-34. Control Register Settings in Square-Wave Output Mode (1/2) www..com (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0/1 0/1 0 CR00n used as compare register 202 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 0/1 0/1 1 1 Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited). Does not invert output on match between TM0n and CR01n. Disables one-shot pulse output. (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n 0/1 0/1 0/1 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Remark www..com 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details. n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Figure 7-35. Square-Wave Output Operation Timing Count clock TM0n count value CR00n INTTM00n TO0n pin output 0000H 0001H 0002H N N-1 N 0000H 0001H 0002H N-1 N 0000H Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 203 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.6 One-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI00n pin input). Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figures 7-36 and 7-38 for the set value). <3> Set the TOC0n register (see Figures 7-36 and 7-38 for the set value). <4> Set any value to the CR00n and CR01n registers (0000H cannot be set). <5> Set the TMC0n register to start the operation (see Figures 7-36 and 7-38 for the set value). Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n (if necessary, INTTM01n) interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO0n pin by setting 16-bit timer mode control register 0n (TMC0n), capture/compare control register 0n (CRC0n), and 16-bit timer output control register 0n (TOC0n) as shown in Figure 7-36, and by setting bit 6 (OSPT0n) of the TOC0n register to 1 by software. By setting the OSPT0n bit to 1, 16-bit timer/event counter 0n is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 01n (CR01n). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 00n www..com (CR00n)Note. Even after the one-shot pulse has been output, the TM0n register continues its operation. To stop the TM0n register, the TMC0n3 and TMC0n2 bits of the TMC0n register must be cleared to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR00n register and inactive with the CR01n register. Do not set N to M. Cautions 1. Do not set the OSPT0n bit while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. 2. When using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the TI00n pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI00n pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 204 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-36. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 0 TMC0n2 TMC0n1 1 0 OVF0n 0 Free-running mode (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0 0/1 0 CR00n as compare register CR01n as compare register (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 0 1 1 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 www..com Enables TO0n output. Inverts output upon match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited.) Inverts output upon match between TM0n and CR01n. Sets one-shot pulse output mode. Set to 1 for output. (d) Prescaler mode register 0n (PRM0n) ES1n1 PRM0n 0/1 ES1n0 0/1 ES0n1 0/1 ES0n0 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Caution Do not set 0000H to the CR00n and CR01n registers. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 205 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-37. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0n to 0CH (TM0n count starts) Count clock TM0n count 0000H 0001H CR01n set value CR00n set value OSPT0n INTTM01n INTTM00n TO0n pin output N M N N+1 N M 0000H N-1 N N M M-1 M M+1 M+2 N M Caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0n3 and TMC0n2 bits. Remark N www..com A one-shot pulse can be output from the TO0n pin by setting 16-bit timer mode control register 0n (TMC0n), capture/compare control register 0n (CRC0n), and 16-bit timer output control register 0n (TOC0n) as shown in Figure 7-38, and by using the valid edge of the TI00n pin as an external trigger. The valid edge of the TI00n pin is specified by bits 4 and 5 (ES0n0, ES0n1) of prescaler mode register 0n (PRM0n). The rising, falling, or both the rising and falling edges can be specified. When the valid edge of the TI00n pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 01n (CR01n). After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 00n (CR00n)Note. Note The case where N < M is described here. When N > M, the output becomes active with the CR00n register and inactive with the CR01n register. Do not set N to M. Caution Even if the external trigger is generated again while the one-shot pulse is output, it is ignored. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 206 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-38. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 1 0 0 OVF0n 0 Clears and starts at valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0 0/1 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n www..com OSPT0n OSPE0n TOC0n4 0 1 1 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 0 Enables TO0n output. Inverts output upon match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited.) Inverts output upon match between TM0n and CR01n. Sets one-shot pulse output mode. (d) Prescaler mode register 0n (PRM0n) ES1n1 PRM0n 0/1 ES1n0 0/1 ES0n1 0 ES0n0 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies the rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Caution Do not set 0000H to the CR00n and CR01n registers. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 207 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-39. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC0n is set to 08H (TM0n count starts) t Count clock TM0n count value 0000H 0001H CR01n set value CR00n set value TI00n pin input INTTM01n INTTM00n TO0n pin output N M 0000H N M N N+1 N+2 N M M-2 M-1 M N M M+1 M+2 Caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0n2 and TMC0n3 bits. Remark N www..com n = 0, 1: PD780146, 780148, 78F0148 208 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.5 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 0n (TM0n) is started asynchronously to the count clock. Figure 7-40. Start Timing of 16-Bit Timer Counter 0n (TM0n) Count clock TM0n count value 0000H 0001H 0002H 0003H 0004H Timer start (2) 16-bit timer capture/compare register setting (in the mode in which clear & start occurs on match between TM0n and CR00n) Set 16-bit timer capture/compare registers 00n and 01n (CR00n and CR01n) to other than 0000H. This means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 0n is used as an event counter. (3) Capture register data retention timing The values of 16-bit timer capture/compare registers 00n and 01n (CR00n and CR01n) are not guaranteed after 16-bit timer/event counter 0n has been stopped. (4) Valid edge setting www..com Set the valid edge of the TI00n pin after clearing bits 2 and 3 (TMC0n2 and TMC0n3) of 16-bit timer mode control register 0n (TMC0n) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n). (5) Re-triggering one-shot pulse (a) One-shot pulse output by software When a one-shot pulse is output, do not set the OSPT0n bit to 1. Do not output the one-shot pulse again until INTTM00n, which occurs upon a match with the CR00n register, or INTTM01n, which occurs upon a match with the CR01n register, occurs. (b) One-shot pulse output with external trigger If the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) One-shot pulse output function When using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the TI00n pin or its alternate function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI00n pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 209 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (6) Operation of OVF0n flag <1> The OVF0n flag is also set to 1 in the following case. When any of the following modes is selected: the mode in which clear & start occurs on a match between TM0n and CR00n, the mode in which clear & start occurs at the TI0n valid edge, or the free-running mode CR00n is set to FFFFH TM0n is counted up from FFFFH to 0000H. Figure 7-41. Operation Timing of OVF0n Flag Count clock CR00n TM0n OVF0n INTTM00n FFFFH FFFEH FFFFH 0000H 0001H <2> Even if the OVF0n flag is cleared before the next count clock (before TM0n becomes 0001H) after the occurrence of TM0n overflow, the OVF0n flag is re-set newly and clear is disabled. www..com (7) Conflicting operations Conflict between the read period of the 16-bit timer capture/compare register (CR00n/CR01n) and capture trigger input (CR00n/CR01n used as capture register) Capture trigger input has priority. The data read from CR00n/CR01n is undefined. Figure 7-42. Capture Register Data Retention Timing Count clock TM0n count value Edge input INTTM01n Capture read signal CR01n capture value X N+2 M+1 N N+1 N+2 M M+1 M+2 Capture Capture, but read value is not guaranteed Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 210 User's Manual U15947EJ2V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (8) Timer operation <1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare register 01n (CR01n). <2> Regardless of the CPU's operation mode, when the timer stops, the input signals to the TI00n/TI01n pins are not acknowledged. <3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI00n valid edge. In the mode in which clear & start occurs on a match between the TM0n register and CR00n register, one-shot pulse output is not possible because an overflow does not occur. (9) Capture operation <1> If TI00n valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for TI00n is not possible. <2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 0n (PRM0n). <3> The capture operation is performed at the falling edge of the count clock. An interrupt request input (INTTM00n/INTTM01n), however, is generated at the rise of the next count clock. (10) Compare operation A capture operation may not be performed for CR00n/CR01n set in compare mode even if a capture trigger has been input. www..com (11) Edge detection <1> If the TI00n or TI01n pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the TI00n or TI01n pin to enable the 16-bit timer counter 0n (TM0n) operation, a rising edge is detected immediately after the operation is enabled. Be careful therefore when pulling up the TI00n or TI01n pin. However, the rising edge is not detected at restart after the operation has been stopped once. <2> The sampling clock used to remove noise differs when the TI00n valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fX, and in the latter case the count clock is selected by prescaler mode register 0n (PRM0n). The capture operation is only performed when a valid level is detected twice by sampling the valid edge, thus eliminating noise with a short pulse width. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: User's Manual U15947EJ2V0UD 211 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. * Interval timer * External event counter * Square-wave output * PWM output Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Mask circuit 8-bit timer compare register 50 (CR50) TI50/TO50/P17 fX fX/2 fX/22 fX/26 fX/28 fX/213 Match Selector Selector Note 1 INTTM50 To TMH0 To UART0 To UART6 TO50/ TI50/P17 Output latch (P17) PM17 8-bit timer OVF counter 50 (TM50) Clear www..com R Note 2 S R Invert level 3 Selector TCL502 TCL501 TCL500 Timer clock selection register 50 (TCL50) TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus Notes 1. 2. Timer output F/F PWM output F/F 212 User's Manual U15947EJ2V0UD Selector S Q INV CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus Mask circuit 8-bit timer compare register 51 (CR51) TI51/TO51/P33/INTP4 fX fX/2 fX/24 fX/26 fX/28 fX/212 Match Selector Note 1 INTTM51 Selector 8-bit timer OVF counter 51 (TM51) Clear Selector S Q INV R Note 2 S R Invert level TO51/TI51/ P33/INTP4 Output latch (P33) PM33 3 Selector TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51) TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus Notes 1. 2. Timer output F/F PWM output F/F www..com User's Manual U15947EJ2V0UD 213 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Timer register Register Timer input Timer output Control registers 8-bit timer counter 5n (TM5n) 8-bit timer compare register 5n (CR5n) TI5n TO5n Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 1 (PM1) or port mode register 3 (PM3) Port register 1 (P1) or port register 3 (P3) Configuration (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 8-3. Format of 8-Bit Timer Counter 5n (TM5n) Address: FF16H (TM50), FF1FH (TM51) Symbol www..com After reset: 00H R TM5n (n = 0, 1) In the following situations, the count value is cleared to 00H. <1> RESET input <2> When TCE5n is cleared <3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and CR5n. 214 User's Manual U15947EJ2V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match. In PWM mode, when the TO5n pin becomes active due to a TM5n overflow and the values of TM5n and CR5n match, the TO5n pin becomes inactive. The value of CR5n can be set within 00H to FFH. RESET input clears CR5n to 00H. Figure 8-4. Format of 8-Bit Timer Compare Register 5n (CR5n) Address: FF17H (CR50), FF41H (CR51) Symbol CR5n (n = 0, 1) After reset: 00H R/W Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation. 2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 www..com User's Manual U15947EJ2V0UD 215 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) * Port mode register 1 (PM1) or port mode register 3 (PM3) * Port register 1 (P1) or port register 3 (P3) (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of TI5n input. TCL5n can be set by an 8-bit memory manipulation instruction. RESET input clears TCL5n to 00H. Remark n = 0, 1 Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50) Address: FF6AH Symbol TCL50 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL502 1 TCL501 0 TCL500 TCL502 www..com TCL501 0 0 1 1 0 0 1 1 TCL500 0 1 0 1 0 1 0 1 TI50 falling edge TI50 rising edge fX (10 MHz) fX/2 (5 MHz) fX/2 (2.5 MHz) fX/2 (156.25 kHz) fX/2 (39.06 kHz) fX/2 (1.22 kHz) 13 8 6 2 Count clock selection 0 0 0 0 1 1 1 1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer/event counter 50 is not guaranteed. 2. When rewriting TCL50 to other data, stop the timer operation beforehand. 3. Be sure to clear bits 3 to 7 to 0. Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz. 216 User's Manual U15947EJ2V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH Symbol TCL51 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL512 1 TCL511 0 TCL510 TCL512 0 0 0 0 1 1 1 1 TCL511 0 0 1 1 0 0 1 1 TCL510 0 1 0 1 0 1 0 1 TI51 falling edge TI51 rising edge fX (10 MHz) fX/2 (5 MHz) fX/2 (625 kHz) fX/2 (156.25 kHz) fX/2 (39.06 kHz) fX/2 (2.44 kHz) 12 8 6 4 Count clock selection Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer/event counter 51 is not guaranteed. 2. When rewriting TCL51 to other data, stop the timer operation beforehand. 3. Be sure to clear bits 3 to 7 to 0. Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz. www..com User's Manual U15947EJ2V0UD 217 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip-flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode <5> Timer output control TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark n = 0, 1 Figure 8-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF6BH Symbol TMC50 After reset: 00H <7> TCE50 6 TMC506 R/W 5 0 4 0 <3> LVS50 <2> LVR50 1 TMC501 <0> TOE50 TCE50 0 1 www..com TM50 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC506 0 1 TM50 operating mode selection Mode in which clear & start occurs on a match between TM50 and CR50 PWM (free-running) mode LVS50 0 0 1 1 LVR50 0 1 0 1 No change Timer output F/F status setting Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TMC501 In other modes (TMC506 = 0) Timer F/F control In PWM mode (TMC506 = 1) Active level selection Active-high Active-low 0 1 Inversion operation disabled Inversion operation enabled TOE50 0 1 Timer output control Output disabled (TM50 output is low level) Output enabled (Refer to the next page for Caution and Remark.) 218 User's Manual U15947EJ2V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H Symbol TMC51 After reset: 00H <7> TCE51 6 TMC516 R/W 5 0 4 0 <3> LVS51 <2> LVR51 1 TMC511 <0> TOE51 TCE51 0 1 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516 0 1 TM51 operating mode selection Mode in which clear & start occurs on a match between TM51 and CR51 PWM (free-running) mode LVS51 0 0 1 1 LVR51 0 1 0 1 No change Timer output F/F status setting Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TMC511 www..com In other modes (TMC516 = 0) Timer F/F control In PWM mode (TMC516 = 1) Active level selection Active-high Active-low 0 1 Inversion operation disabled Inversion operation enabled TOE51 0 1 Timer output control Output disabled (TM51 output is low level) Output enabled Cautions 1. The settings of LVS5n and LVR5n are valid in other than PWM mode. 2. Do not rewrite following bits simultaneously. * TMC5n1 and TOE5n * TMC5n6 and TOE5n * TMC5n1 and TMC5n6 * TMC5n6 and LVS5n, LVR5n * TOE5n and LVS5n, LVR5n 3. Stop operation before rewriting TMC5n6. Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE5n to 0. 2. If LVS5n and LVR5n are read, the value is 0. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin regardless of the value of TCE5n. 4. n = 0, 1 User's Manual U15947EJ2V0UD 219 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0. When using the P17/TO50/TI50 and P33/TO51/TI51 pins for timer input, set PM17 and PM33 to 1. The output latches of P17 and P33 at this time may be 0 or 1. PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 8-9. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) Figure 8-10. Format of Port Mode Register 3 (PM3) Address: FF23H Symbol www..com After reset: FFH 6 0 R/W 5 0 4 0 3 PM33 2 PM32 1 PM31 0 PM30 7 0 PM3 PM3n 0 1 P3n pin I/O mode selection (n = 0 to 3) Output mode (output buffer on) Input mode (output buffer off) 220 User's Manual U15947EJ2V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4 8.4.1 Operations of 8-Bit Timer/Event Counters 50 and 51 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). Setting <1> Set the registers. * TCL5n: Select the count clock. * CR5n: * TMC5n: Compare value Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. (TMC5n = 0000xxx0B x = Don't care) <2> After TCE5n = 1 is set, the count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> INTTM5n is generated repeatedly at the same interval. Clear TCE5n to 0 to stop the count operation. Caution Do not write other values to CR5n during operation. www..com Figure 8-11. Interval Timer Operation Timing (1/2) (a) Basic operation t Count clock TM5n count value 00H 01H N 00H 01H N 00H 01H N Count start CR5n TCE5n INTTM5n N Clear N Clear N N Interrupt acknowledged Interval time Interrupt acknowledged Interval time Remark Interval time = (N + 1) x t N = 00H to FFH n = 0, 1 User's Manual U15947EJ2V0UD 221 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H t Count clock TM5n 00H CR5n TCE5n INTTM5n Interval time 00H 00H 00H 00H (c) When CR5n = FFH t Count clock TM5n www..com 01 FF FE FF FF 00 FE FF FF 00 CR5n TCE5n INTTM5n Interrupt acknowledged Interval time Interrupt acknowledged Remark n = 0, 1 222 User's Manual U15947EJ2V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected. When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Whenever the TM5n value matches the value of CR5n, INTTM5n is generated. Setting <1> Set each register. * Set the port mode register (PM17 or PM33)Note to 1. * TCL5n: Select TI5n input edge. TI5n falling edge TCL5n = 00H TI5n rising edge TCL5n = 01H * CR5n: Compare value CR5n, disable the timer F/F inversion operation, disable timer output. (TMC5n = 0000xx00B x = Don't care) <2> When TCE5n = 1 is set, the number of pulses input from TI5n is counted. <3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match. Note 8-bit timer/event counter 50: PM17 www..com * TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and 8-bit timer/event counter 51: PM33 Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified) TI5n Count start TM5n count value CR5n INTTM5n 00 01 02 03 04 05 N-1 N N 00 01 02 03 Remark N = 00H to FFH n = 0, 1 User's Manual U15947EJ2V0UD 223 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). Setting <1> Set each register. Note Note * Clear the port output latch (P17 or P33) and port mode register (PM17 or PM33) to 0. * TCL5n: Select the count clock. * CR5n: Compare value CR5n. LVS5n 1 0 LVR5n 0 1 Timer Output F/F Status Setting High-level output Low-level output * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and Timer output F/F inversion enabled Timer output enabled (TMC5n = 00001011B or 00000111B) <2> After TCE5n = 1 is set, the count operation starts. www..com <3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is cleared to 00H. <4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from TO5n. The frequency is as follows. Frequency = 1/2t (N + 1) (N: 00H to FFH) Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 Caution Do not write other values to CR5n during operation. Remark n = 0, 1 224 User's Manual U15947EJ2V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. Square-Wave Output Operation Timing t Count clock TM5n count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H Count start CR5n N TO5nNote Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n). 8.4.4 PWM output operation 8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of TMC5n. The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). www..com PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n. Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 User's Manual U15947EJ2V0UD 225 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. Note Note * Clear the port output latch (P17 or P33) and port mode register (PM17 or PM33) to 0. * TCL5n: Select the count clock. * CR5n: Compare value The timer output F/F is not changed. TMC5n1 0 1 Active-high Active-low Active Level Selection * TMC5n: Stop the count operation, select PWM mode. Timer output enabled (TMC5n = 01000001B or 01000011B) <2> The count operation starts when TCE5n = 1. Clear TCE5n to 0 to stop the count operation. Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 PWM output operation www..com <1> PWM output (output from TO5n) outputs an inactive level until an overflow occurs. <2> When an overflow occurs, the active level is output. The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive. For details of timing, see Figures 8-14 and 8-15. The cycle, active-level width, and duty are as follows. * Cycle = 28t * Active-level width = Nt * Duty = N/28 (N = 00H to FFH) Remark n = 0, 1 226 User's Manual U15947EJ2V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) t Count clock TM5n CR5n TCE5n INTTM5n TO5n <1> <5> <2> Active level <3> Inactive level Active level 00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H (b) CR5n = 00H t Count clock TM5n CR5n www..com 00H 01H 00H FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n L Inactive level Inactive level (c) CR5n = FFH t TM5n CR5n TCE5n INTTM5n TO5n 00H 01H FFH FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H Inactive level Active level Active level Inactive level Inactive level Remarks 1. <1> to <3> and <5> in Figure 8-14 (a) correspond to <1> to <3> and <5> in PWM output operation in 8.4.4 (1) PWM output basic operation. 2. n = 0, 1 User's Manual U15947EJ2V0UD 227 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH Value is transferred to CR5n at overflow immediately after change. t Count clock TM5n CR5n TCE5n INTTM5n TO5n <2> <1> CR5n change (N M) H N N+1 N+2 N FFH 00H 01H 02H M M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 (b) CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow. t Count clock www..com TM5n CR5n TCE5n INTTM5n TO5n N N+1 N+2 N H FFH 00H 01H 02H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2 <1> CR5n change (N M) <2> Caution When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). 228 User's Manual U15947EJ2V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Figure 8-16. 8-Bit Timer Counter 5n Start Timing Count clock TM5n count value 00H Timer start 01H 02H 03H 04H Remark n = 0, 1 www..com User's Manual U15947EJ2V0UD 229 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. * Interval timer * PWM output mode * Square-wave output * Carrier generator mode (8-bit timer H1 only) 9.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 consist of the following hardware. Table 9-1. Configuration of 8-Bit Timers H0 and H1 Item Timer register Registers 8-bit timer counter Hn 8-bit timer H compare register 0n (CMP0n) 8-bit timer H compare register 1n (CMP1n) Timer output Control registers www..com Configuration TOHn 8-bit timer H mode register n (TMHMDn) 8-bit timer H carrier control register 1 (TMCYC1) Port mode register 1 (PM1) Port register 1 (P1) Note Note 8-bit timer H1 only Remark n = 0, 1 Figures 9-1 and 9-2 show the block diagrams. 230 User's Manual U15947EJ2V0UD Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode control register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H compare register 10 (CMP10) 8-bit timer H compare register 00 (CMP00) www..com 3 2 Decoder Selector Match fX fX/2 fX/22 fX/26 fX/210 8-bit timer/ event counter 50 output Interrupt generator F/F R Output controller Level inversion Output latch (P15) PM15 TOH0/P15 CHAPTER 9 8-BIT TIMERS H0 AND H1 User's Manual U15947EJ2V0UD Selector 8-bit timer counter H0 Clear PWM mode signal 1 0 INTTMH0 Timer H enable signal 231 www..com Selector 232 8-bit timer H mode control register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 2 Decoder User's Manual U15947EJ2V0UD Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H carrier control register 1 RMC1 NRZB1 NRZ1 (TMCYC1) Reload/ interrupt control INTTM51 TOH1/ INTP5/ P16 8-bit timer H compare register 11 (CMP11) 8-bit timer H compare register 01 (CMP01) CHAPTER 9 8-BIT TIMERS H0 AND H1 Selector Match fX fX/22 fX/24 fX/26 fX/212 fR/27 Interrupt generator F/F R Output controller Level inversion Output latch (P16) PM16 8-bit timer counter H1 Carrier generator mode signal PWM mode signal 1 0 INTTMH1 Clear Timer H enable signal CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) Symbol CMP0n (n = 0, 1) 7 6 5 4 After reset: 00H 3 R/W 2 1 0 Caution CMP0n cannot be rewritten during timer count operation. (2) 8-bit timer H compare register 1n (CMP1n) This register can be read or written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n) Address: FF19H (CMP10), FF1BH (CMP11) Symbol CMP1n (n = 0, 1) 7 6 5 4 After reset: 00H 3 R/W 2 1 0 www..com CMP1n can be rewritten during timer count operation. An interrupt request signal (INTTMHn) is generated if the values of the timer counter and CMP1n match after setting CMP1n in carrier generator mode. The timer counter value is cleared at the same time. If the CMP1n value is rewritten during timer operation, transferring is performed at the timing at which the counter value and CMP1n value match. If the transfer timing and writing from CPU to CMP1n conflict, transfer is not performed. Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). Remark n = 0, 1 User's Manual U15947EJ2V0UD 233 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register 1 (TMCYC1) * Port mode register 1 (PM1) * Port register 1 (P1) Note 8-bit timer H1 only (1) 8-bit timer H mode register n (TMHMDn) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark n = 0, 1 Note www..com 234 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H <7> TMHMD0 TMHE0 After reset: 00H 6 CKS02 R/W 5 CKS01 4 CKS00 3 2 <1> <0> TOEN0 TMMD01 TMMD00 TOLEV0 TMHE0 0 1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS02 0 0 0 0 1 1 CKS01 0 0 1 1 0 0 CKS00 0 1 0 1 0 1 fX fX/2 fX/2 fX/2 2 6 Count clock (fCNT) selection (10 MHz) (5 MHz) (2.5 MHz) (156.25 kHz) (9.77 kHz) fX/210 TM50 outputNote Setting prohibited Other than above TMMD01 TMMD00 0 1 www..com Timer operation mode Interval timer mode PWM output mode Setting prohibited 0 0 Other than above TOLEV0 0 1 Low level High level Timer output level control (in default mode) TOEN0 0 1 Disables output Enables output Timer output control Note To select the TM50 output as a count clock, start operation by setting 8-bit timer/event counter 50 in the PWM output mode (bit 6 (TMC506) of the TMC50 register = 1), and then set CKS02, CKS01, and CKS00 to 1, 0, and 1, respectively. Set the high/low level width of the count clock so that the specifications of the input width of TI50 are satisfied (see AC Characteristics (1) Basic operation in CHAPTER 30 to CHAPTER 32). It is not necessary to enable the TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1). User's Manual U15947EJ2V0UD 235 CHAPTER 9 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H0 is not guaranteed. 2. When TMHE0 = 1, setting the other bits of the TMHMD0 register is prohibited. 3. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to the CMP10 register). Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz www..com 236 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH <7> TMHMD1 TMHE1 After reset: 00H 6 CKS12 R/W 5 CKS11 4 CKS10 3 2 <1> <0> TOEN1 TMMD11 TMMD10 TOLEV1 TMHE1 0 1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS12 0 0 0 0 1 1 CKS11 0 0 1 1 0 0 CKS10 0 1 0 1 0 1 fX fX/2 fX/2 fX/2 2 4 6 Count clock (fCNT) selection (10 MHz) (2.5 MHz) (625 kHz) (156.25 kHz) (2.44 kHz) (1.88 kHz (TYP.)) fX/212 fR/2 7 Other than above Setting prohibited TMMD11 TMMD10 0 0 www..com Timer operation mode Interval timer mode Carrier generator mode PWM output mode Setting prohibited 0 1 0 1 Other than above TOLEV1 0 1 Low level High level Timer output level control (in default mode) TOEN1 0 1 Disables output Enables output Timer output control Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H1 is not guaranteed (except when CKS12, CKS11, CKS10 = 1, 0, 1 (fR/27)). 2. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. 3. In the PWM output mode and carrier generator mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 4. When the carrier generator mode is used, set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. User's Manual U15947EJ2V0UD 237 CHAPTER 9 8-BIT TIMERS H0 AND H1 Remarks 1. fX: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency 3. Figures in parentheses apply to operation at fX = 10 MHz, fR = 240 kHz (TYP.). (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-7. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) Address: FF6DH After reset: 00H R/WNote <0> TMCYC1 0 0 0 0 0 RMC1 NRZB1 NRZ1 RMC1 0 0 1 1 NRZB1 0 1 0 1 Low-level output Remote control output High-level output Low-level output Carrier pulse output NRZ1 www..com Carrier pulse output status flag Carrier output disabled status (low-level status) Carrier output enabled status (RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status) 0 1 Note Bit 0 is read-only. (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 9-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 238 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4 9.4.1 Operation of 8-Bit Timers H0 and H1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected. By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%) is output from TOHn. (1) Usage Generates the INTTMHn signal repeatedly at the same interval. <1> Set each register. Figure 9-9. Register Setting During Interval Timer/Square-Wave Output Operation (i) Setting timer H mode register n (TMHMDn) TMHEn TMHMDn 0 CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 0 0 0/1 TOENn 0/1 Timer output setting Timer output level inversion setting www..com Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP0n register setting * Compare value (N) <2> Count operation starts when TMHEn = 1. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. Interval time = (N +1)/fCNT <4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear TMHEn to 0. Remark n = 0, 1 User's Manual U15947EJ2V0UD 239 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 8-bit timer counter Hn 00H 01H N 00H Clear 01H N 00H Clear 01H 00H CMP0n N TMHEn INTTMHn Interval time TOHn www..com <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <3> The INTTMHn signal and TOHn output become inactive by clearing the TMHEn bit to 0 during timer Hn operation. If these are inactive from the first, the level is retained. Remark n = 0, 1 N = 01H to FEH 240 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn 00H 01H FEH FFH 00H Clear FEH FFH 00H Clear CMP0n FFH TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H www..com Count clock Count start 8-bit timer counter Hn 00H CMP0n 00H TMHEn INTTMHn TOHn Interval time Remark n = 0, 1 User's Manual U15947EJ2V0UD 241 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM output mode is as follows. TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn and the CMP1n register match. (1) Usage In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> Set each register. Figure 9-11. Register Setting in PWM Output Mode (i) Setting timer H mode register n (TMHMDn) CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 1 0 0/1 TOENn 1 TMHEn TMHMDn 0 www..com Timer output enabled Timer output level inversion setting PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP0n register * Compare value (N): Cycle setting (iii) Setting CMP1n register * Compare value (M): Duty setting Remarks 1. n = 0, 1 2. 00H CMP1n (M) < CMP0n (N) FFH <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time, the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n register. 242 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 <4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N+1)/fCNT Duty = Active width : Total width of PWM = (M + 1) : (N + 1) At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0 bits of the TMHMDn register) are required to transfer the CMP1n register value after rewriting the register. 2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). www..com User's Manual U15947EJ2V0UD 243 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH Remark n = 0, 1 Figure 9-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP0n A5H CMP1n www..com 01H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> TOHn (TOLEVn = 1) <2> <3> <4> <1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0). <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted, the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output. <4> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1 244 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n FFH CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) www..com (c) Operation when CMP0n = FFH, CMP1n = FEH Count clock 8-bit timer counter Hn 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP0n FFH CMP1n FEH TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 User's Manual U15947EJ2V0UD 245 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP0n 01H CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) www..com Remark n = 0, 1 246 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n A5H CMP1n 01H <2> 01H (03H) <2>' 03H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> www..com <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0). <2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output becomes active, and the INTTMHn signal is output. <4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the CMP1n register and the CMP1n register value is changed (<2>'). However, three count clocks or more are required from when the CMP1n register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1 User's Manual U15947EJ2V0UD 247 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output. (1) Carrier generation In carrier generator mode, 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse waveform and 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform. Rewriting the CMP11 register during 8-bit timer H1 operation is possible but rewriting the CMP01 register is prohibited. (2) Carrier output control Carrier output is controlled by the interrupt request signal (INTTM51) of 8-bit timer/event counter 51 and the NRZB1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the outputs is shown below. RMC1 Bit 0 0 1 1 NRZB1 Bit 0 1 0 1 Output Low-level output High-level output Low-level output Carrier pulse output www..com 248 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below. Figure 9-13. Transfer Timing TMHE1 8-bit timer H1 count clock INTTM51 INTTM5H1 <1> NRZ1 0 <2> NRZB1 1 0 1 1 0 RMC1 <1> www..com The INTTM51 signal is synchronized with the count clock of 8-bit timer H1 and is output as the INTTM5H1 signal. The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal. <2> Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed. 2. When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. User's Manual U15947EJ2V0UD 249 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode (i) Setting 8-bit timer H mode register 1 (TMHMD1) CKS12 0/1 CKS11 0/1 CKS10 0/1 TMMD11 TMMD10 TOLEV1 0 1 0/1 TOEN1 0/1 TMHE1 TMHMD1 0 Timer output enabled Timer output level inversion setting Carrier generator mode selection Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (iii) CMP11 register setting * Compare value www..com (iv) TMCYC1 register setting * RMC1 = 1 ... Remote control output enable bit * NRZB1 = 0/1 ... carrier output enable bit (v) TCL51 and TMC51 register setting * See 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51. <2> When TMHE1 = 1, 8-bit timer H1 starts counting. <3> When TCE51 of 8-bit timer mode control register 51 (TMC51) is set to 1, 8-bit timer/event counter 51 starts counting. <4> After the count operation is enabled, the first compare register to be compared is the CMP01 register. When the count value of 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. <5> When the count value of 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. <6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated. <7> The INTTM51 signal is synchronized with count clock of 8-bit timer H1 and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <8> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin. <9> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. 250 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/fCNT Duty = High-level width : Carrier clock output width = ( M + 1) : (N + M + 2) Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. (4) Timing chart The carrier output control timing is shown below. Cautions 1. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. 2. In the carrier generator mode, three operating clocks (signal selected by CKS12 to CKS10 bits of TMHMD1 register) or more are required from when the CMP11 register value is changed to when the value is transferred to the register. 3. Be sure to set the RMC1 bit before the count operation is started. www..com User's Manual U15947EJ2V0UD 251 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> INTTM5n www..com 00H N 00H N 00H N 00H N N 00H N 00H N N <3> <4> 00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H INTTM5Hn NRZBn NRZn Carrier clock TOHn <7> 0 0 1 <6> 1 0 1 0 0 1 0 <1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to 00H. <4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the INTTM5H1 signal. <6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <7> When NRZ1 = 0 is set, the TOH1 output becomes low level. 252 User's Manual U15947EJ2V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> INTTM5n INTTM5Hn www..com 00H N 00H 01H M 00H N N 00H 01H M 00H N 00H M <3> <4> 00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H NRZBn NRZn Carrier clock 0 0 1 1 0 0 1 1 0 0 <6> TOHn <7> <1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to 00H. <4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the INTTM5H1 signal. <6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1. <7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). User's Manual U15947EJ2V0UD 253 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H CMP01 <3> CMP11 M M (L) N <3>' L TMHE1 INTTMH1 <2> Carrier clock <1> <4> <5> www..com <1> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <2> When the count value of 8-bit timer counter H1 matches the CMP01 register value, 8-bit timer counter H1 is cleared and the INTTMH1 signal is output. <3> The CMP11 register can be rewritten during 8-bit timer H1 operation, however, the changed value (L) is latched. The CMP11 register is changed when the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match (<3>'). <4> When the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match, the INTTMH1 signal is output, the carrier signal is inverted, and 8-bit timer counter H1 is cleared to 00H. <5> The timing at which the count value of 8-bit timer counter H1 and the CMP11 register value match again is indicated by the value after the change (L). 254 User's Manual U15947EJ2V0UD CHAPTER 10 WATCH TIMER 10.1 Functions of Watch Timer The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. Figure 10-1. Watch Timer Block Diagram Selector Clear Selector fWX 5-bit counter Clear fWX/25 Selector fWX/24 INTWT fX/27 fXT fW 11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 Selector INTWTI www..com WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency fWX: fW or fW/29 User's Manual U15947EJ2V0UD 255 CHAPTER 10 WATCH TIMER (1) Watch timer When the X1 input clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time 2 /fW 2 /fW 2 /fW 2 /fW 14 13 5 4 When Operated at fXT = 32.768 kHz 488 s 977 s 0.25 s 0.5 s When Operated at fX = 10 MHz 205 s 410 s 0.105 s 0.210 s Remark fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency (2) Interval timer Interrupt requests (INTWTI) are generated at preset time intervals. Table 10-2. Interval Timer Interval Time Interval Time 2 /fW 2 /fW www..com 5 4 When Operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.3 ms 62.5 ms When Operated at fX = 10 MHz 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 Remark fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency 256 User's Manual U15947EJ2V0UD CHAPTER 10 WATCH TIMER 10.2 Configuration of Watch Timer The watch timer consists of the following hardware. Table 10-3. Watch Timer Configuration Item Counter Prescaler Control register 5 bits x 1 11 bits x 1 Watch timer operation mode register (WTM) Configuration 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). * Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. WTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears WTM to 00H. www..com User's Manual U15947EJ2V0UD 257 CHAPTER 10 WATCH TIMER Figure 10-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH Symbol WTM 7 WTM7 After reset: 00H 6 WTM6 R/W 5 WTM5 4 WTM4 3 WTM3 2 WTM2 <1> WTM1 <0> WTM0 WTM7 0 1 fX/2 (78.125 kHz) fXT (32.768 kHz) 7 Watch timer count clock selection WTM6 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 5 4 Prescaler interval time selection WTM3 www..com WTM2 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 4 5 13 14 Interrupt time selection 0 0 1 1 WTM1 0 1 Clear after operation stop Start 5-bit counter operation control WTM0 0 1 Watch timer operation enable Operation stop (clear both prescaler and timer) Operation enable Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT) 2. fX: X1 input clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 4. Figures in parentheses apply to operation with fX = 10 MHz, fXT = 32.768 kHz. 258 User's Manual U15947EJ2V0UD CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the X1 input clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts. When these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops. When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by clearing WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 211 x 1/fW seconds occurs in the first overflow (INTWT) after zero-second start. The interrupt request is generated at the following time intervals. Table 10-4. Watch Timer Interrupt Time WTM3 WTM2 Interrupt Time Selection 14 When Operated at fXT = 32.768 kHz (WTM7 = 1) When Operated at fX = 10 MHz (WTM7 = 0) 0.210 s 0.105 s 410 s 205 s 0 0 1 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 4 5 13 0.5 s 0.25 s 977 s 488 s Remark fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency www..com User's Manual U15947EJ2V0UD 259 CHAPTER 10 WATCH TIMER 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM). When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is cleared to 0, the count operation stops. Table 10-5. Interval Timer Interval Time WTM6 WTM5 WTM4 4 Interval Time When Operated at fXT = 32.768 kHz (WTM7 = 1) 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.3 ms 62.5 ms When Operated at fX = 10 MHz (WTM7 = 0) 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 5 Remark www..com fX: X1 input clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) nxT T nxT Overflow Overflow Remark fW: Watch timer clock frequency n: The number of times of interval timer operations Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0) 260 User's Manual U15947EJ2V0UD CHAPTER 10 WATCH TIMER 10.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bit 3 (WTM3) of WTM. This is because there is a delay of one 11-bit prescaler output cycle until the 5-bit counter starts counting. Subsequently, however, the INTWT signal is generated at the specified intervals. Figure 10-4. Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) It takes 0.515625 seconds for the first INTWT to be generated (29 x 1/32768 = 0.015625 s longer). INTWT is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s 0.5 s INTWT www..com User's Manual U15947EJ2V0UD 261 CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 22 RESET FUNCTION. Table 11-1. Loop Detection Time of Watchdog Timer Loop Detection Time During Ring-OSC Clock Operation fR/2 (8.53 ms) fR/2 (17.07 ms) fR/2 (34.13 ms) fR/2 (68.27 ms) fR/2 (136.53 ms) fR/2 (273.07 ms) fR/2 (546.13 ms) fR/2 (1.09 s) www..com 18 17 16 15 14 13 12 11 During X1 Input Clock Operation fXP/2 (819.2 s) 13 fXP/2 (1.64 ms) fXP/2 (3.28 ms) fXP/2 (6.55 ms) fXP/2 (13.11 ms) fXP/2 (26.21 ms) fXP/2 (52.43 ms) fXP/2 (104.86 ms) 20 19 18 17 16 15 14 Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency 3. Figures in parentheses apply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz The operation mode of the watchdog timer (WDT) is switched according to the mask option setting of the on-chip Ring-OSC as shown in Table 11-2. 262 User's Manual U15947EJ2V0UD CHAPTER 11 WATCHDOG TIMER Table 11-2. Mask Option Setting and Watchdog Timer Operation Mode Mask Option Ring-OSC Cannot Be Stopped Watchdog timer clock source Operation after reset Operation starts with the maximum interval (fR/2 ). Operation mode selection The interval can be changed only once. 18 Ring-OSC Can Be Stopped by Software * Selectable by software (fXP, fR or stopped) * When reset is released: fR Operation starts with maximum interval (fR/2 ). The clock selection/interval can be changed only once. 18 Fixed to fR Note 1 . Features The watchdog timer cannot be stopped. The watchdog timer can be stopped in standby mode Note 2 . Notes 1. 2. As long as power is being supplied, Ring-OSC oscillation cannot be stopped (except in the reset period). The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer. <1> If the clock source is fXP, clock supply to the watchdog timer is stopped under the following conditions. * When fXP is stopped * In HALT/STOP mode * During oscillation stabilization time <2> If the clock source is fR, clock supply to the watchdog timer is stopped under the following conditions. * If the CPU clock is fXP and if fR is stopped by software before execution of the STOP www..com instruction * In HALT/STOP mode Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency User's Manual U15947EJ2V0UD 263 CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 11-3. Configuration of Watchdog Timer Item Control registers Configuration Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 11-1. Block Diagram of Watchdog Timer fR/22 fXP/2 4 Clock input controller 2 fR/211 to fR/218 16-bit counter Selector or fXP/213 to fXP/220 3 Output controller Internal reset signal Clear 3 Watchdog timer enable register (WDTE) 0 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 Watchdog timer mode register (WDTM) Internal bus Mask option (to set "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software") www..com 264 User's Manual U15947EJ2V0UD CHAPTER 11 WATCHDOG TIMER 11.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. * Watchdog timer mode register (WDTM) * Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. RESET input sets this register to 67H. Figure 11-2. Format of Watchdog Timer Mode Register (WDTM) Address: FF98H Symbol WDTM 7 0 After reset: 67H 6 1 R/W 5 1 4 WDCS4 3 WDCS3 2 WDCS2 1 WDCS1 0 WDCS0 WDCS4 0 0 1 www..com Note 1 WDCS3 0 1 x Note 1 Operation clock selection Ring-OSC clock (fR) X1 input clock (fXP) Watchdog timer operation stopped WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 Overflow time setting During Ring-OSC clock operation 11 During X1 input clock operation fXP/2 (819.2 s) 13 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fR/2 (8.53 ms) fR/2 (17.07 ms) fR/2 (34.13 ms) fR/2 (68.27 ms) fR/2 (136.53 ms) fR/2 (273.07 ms) fR/2 (546.13 ms) fR/2 (1.09 s) 18 17 16 15 14 13 12 fXP/2 (1.64 ms) fXP/2 (3.28 ms) fXP/2 (6.55 ms) fXP/2 (13.11 ms) fXP/2 (26.21 ms) fXP/2 (52.43 ms) fXP/2 (104.86 ms) 20 19 18 17 16 15 14 Notes 1. 2. If "Ring-OSC cannot be stopped" is specified by a mask option, this cannot be set. The RingOSC clock will be selected no matter what value is written. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1). User's Manual U15947EJ2V0UD 265 CHAPTER 11 WATCHDOG TIMER Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT. 2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when "Ring-OSC cannot be stopped" is selected by a mask option, other values are ignored). 3. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing attempted a second time, an internal reset signal is generated. 4. WDTM cannot be set by a 1-bit memory manipulation instruction. Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency 3. x: Don't care 4. Figures in parentheses apply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 9AH. Figure 11-3. Format of Watchdog Timer Enable Register (WDTE) Address: FF99H Symbol www..com After reset: 9AH 6 R/W 5 4 3 2 1 0 7 WDTE Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. 3. The value read from WDTE is 9AH (this differs from the written value (ACH)). 266 User's Manual U15947EJ2V0UD CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Watchdog timer operation when "Ring-OSC cannot be stopped" is selected by mask option The operation clock of watchdog timer is fixed to the Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Ring-OSC clock * Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2. * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. The operation clock (Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored. 2. As soon as WDTM is written, the counter of the watchdog timer is cleared. Notes 1. Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the Ring-OSC can be selected as www..com the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution. User's Manual U15947EJ2V0UD 267 CHAPTER 11 WATCHDOG TIMER 11.4.2 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by mask option The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Ring-OSC clock oscillation frequency (fR) * Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2, 3. * Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4). Ring-OSC clock (fR) X1 input clock (fXP) Watchdog timer operation stopped * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. As soon as WDTM is written, the counter of the watchdog timer is cleared. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and x, respectively, an internal reset signal is not generated even if the following processing is performed. * WDTM is written a second time. * A 1-bit memory manipulation instruction is executed to WDTE. * A value other than ACH is written to WDTE. Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. For the watchdog timer operation during STOP mode and HALT mode in each status, see 11.4.3 Watchdog timer operation in STOP mode and 11.4.4 Watchdog timer operation in HALT mode. Notes 1. 2. 3. www..com 268 User's Manual U15947EJ2V0UD CHAPTER 11 WATCHDOG TIMER 11.4.3 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by mask option) The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or Ring-OSC clock is being used. (1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (fXP) when the STOP instruction is executed When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 11-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock) Normal operation CPU operation fXP STOP Oscillation stabilization time Normal operation Oscillation stopped fR Watchdog timer www..com Oscillation stabilization time (set by OSTS register) Operating Operation stopped Operating (2) When the CPU clock is the X1 input clock (fXP) and the watchdog timer operation clock is the Ring-OSC clock (fR) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 11-5. Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock) Normal operation CPU operation fXP STOP Oscillation stabilization time Normal operation Oscillation stopped fR Watchdog timer Oscillation stabilization time (set by OSTS register) Operating Operation stopped Operating User's Manual U15947EJ2V0UD 269 CHAPTER 11 WATCHDOG TIMER (3) When the CPU clock is the Ring-OSC clock (fR) and the watchdog timer operation clock is the X1 input clock (fXP) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. <1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses. <2> The CPU clock is switched to the X1 input clock (fXP). Figure 11-6. Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock) <1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) has elapsed Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR www..com STOP Clock supply stopped Normal operation (Ring-OSC clock) Oscillation stabilization time (set by OSTS register) 17 clocks Watchdog timer Operating Operation stopped Operating <2> Timing when counting is started after the CPU clock is switched to the X1 input clock (fXP) Normal operation (Ring-OSC clock) Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR 17 clocks Watchdog timer Operating Operation stopped Operating Oscillation stabilization time (set by OSTS register) Clock supply stopped CPU clock fR fXPNote STOP Normal operation (X1 input clock) Note Confirm the oscillation stabilization time of fXP using the oscillation stabilization time counter status register (OSTC). 270 User's Manual U15947EJ2V0UD CHAPTER 11 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (fR) during STOP instruction execution When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 11-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock) Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR 17 clocks Watchdog timer Operating Operation stopped Operating Oscillation stabilization time (set by OSTS register) STOP Clock supply stopped Normal operation (Ring-OSC clock) 11.4.4 Watchdog timer operation in HALT mode (when "Ring-OSC can be stopped by software" is selected by mask option) The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the X1 input clock (fXP), Ring-OSC clock (fR), or subsystem clock (fXT), or whether the operation clock of the watchdog www..com timer is the X1 input clock (fXP) or Ring-OSC clock (fR). After HALT mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 11-8. Operation in HALT Mode CPU operation Normal operation fXP HALT Normal operation fR fXT Watchdog timer Operating Operation stopped Operating User's Manual U15947EJ2V0UD 271 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS. Figure 12-1 shows the block diagram of clock output/buzzer output controller. Figure 12-1. Block Diagram of Clock Output/Buzzer Output Controller fX Prescaler 8 4 fX/210 to fX/213 Selector BUZ/BUSY0/ INTP7/P141 Output latch (P141) BCS0, BCS1 PM141 BZOE Selector fX to fX/27 fXT Clock controller PCL/INTP6/P140 CLOE www..com Output latch (P140) PM140 BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 Clock output selection register (CKS) Internal bus 272 User's Manual U15947EJ2V0UD CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller consists of the following hardware. Table 12-1. Clock Output/Buzzer Output Controller Configuration Item Control registers Configuration Clock output selection register (CKS) Port mode register 14 (PM14) Port register 14 (P14) 12.3 Register Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller. * Clock output selection register (CKS) * Port mode register 14 (PM14) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CKS to 00H. www..com User's Manual U15947EJ2V0UD 273 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-2. Format of Clock Output Selection Register (CKS) Address: FF40H Symbol CKS After reset: 00H <7> BZOE 6 BCS1 R/W 5 BCS0 <4> CLOE 3 CCS3 2 CCS2 1 CCS1 0 CCS0 BZOE 0 1 BUZ output enable/disable specification Clock division circuit operation stopped. BUZ fixed to low level. Clock division circuit operation enabled. BUZ output enabled. BCS1 0 0 1 1 BCS0 0 1 0 1 fX/2 (9.77 kHz) fX/2 (4.88 kHz) fX/2 (2.44 kHz) fX/2 (1.22 kHz) 13 12 11 10 BUZ output clock selection CLOE 0 1 PCL output enable/disable specification Clock division circuit operation stopped. PCL fixed to low level. Clock division circuit operation enabled. PCL output enabled. CCS3 www..com CCS2 0 0 0 0 1 1 1 1 0 CCS1 0 0 1 1 0 0 1 1 0 CCS0 0 1 0 1 0 1 0 1 0 fX (10 MHz) fX/2 (5 MHz) PCL output clock selection 0 0 0 0 0 0 0 0 1 fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (312.5 kHz) fX/2 (156.25 kHz) fX/2 (78.125 kHz) fXT (32.768 kHz) Setting prohibited 7 6 5 4 3 2 Other than above Remarks 1. fX: X1 input clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. Figures in parentheses are for operation with fX = 10 MHz or fXT = 32.768 kHz. 274 User's Manual U15947EJ2V0UD CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output and the P141/BUSY0/INTP7/BUZ pin for buzzer output, clear PM140, PM141 and the output latch of P140, P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM14 to FFH. Figure 12-3. Format of Port Mode Register 14 (PM14) Address: FF2EH Symbol PM14 7 1 After reset: FFH 6 1 5 PM145 R/W 4 PM144 3 PM143 2 PM142 1 PM141 0 PM140 PM14n 0 1 P14n pin I/O mode selection (n = 0 to 5) Output mode (output buffer on) Input mode (output buffer off) www..com User's Manual U15947EJ2V0UD 275 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.4 Clock Output/Buzzer Output Controller Operations 12.4.1 Clock output operation The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status). <2> Set bit 4 (CLOE) of CKS to 1 to enable clock output. Remark The clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. As shown in Figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). When stopping output, do so after securing high level of the clock. Figure 12-4. Remote Control Output Application Example CLOE * Clock output * 12.4.2 Operation as buzzer output The buzzer frequency is output as the following procedure. www..com <1> Select the buzzer output frequency with bits 5 and 6 (BCS0, BCS1) of the clock output selection register (CKS) (buzzer output in disabled status). <2> Set bit 7 (BZOE) of CKS to 1 to enable buzzer output. 276 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER 13.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI7. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. (2) Power-fail detection function This function is used to detect a voltage drop in a battery. The A/D conversion result (ADCR register value) and power-fail comparison threshold register (PFT) value are compared. comparative condition has been matched. Figure 13-1. Block Diagram of A/D Converter AVREF ADCS bit ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 INTAD is generated only when a Sample & hold circuit Selector www..com AVSS Successive approximation register (SAR) Tap selector Voltage comparator AVSS INTAD Controller Comparator 3 A/D conversion result register (ADCR) Power-fail comparison threshold register (PFT) ADS2 ADS1 ADS0 ADCS FR2 FR1 FR0 ADCE PFEN PFCM Analog input channel specification register (ADS) A/D converter mode register (ADM) Internal bus Power-fail comparison mode register (PFM) User's Manual U15947EJ2V0UD 277 CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter consists of the following hardware. Table 13-1. Registers of A/D Converter Used on Software Item Registers Configuration Successive approximation register (SAR) A/D conversion result register (ADCR) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) (1) ANI0 to ANI7 pins These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification register (ADS) can be used as input port pins. (2) Sample & hold circuit The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled analog input voltage value during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with www..com the analog input signal. (4) Voltage comparator The voltage comparator compares the sampled analog input voltage and the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). (6) A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its higher 10 bits (the lower 6 bits are fixed to 0). (7) Controller When A/D conversion has been completed or when the power-fail detection function is used, this controller compares the result of A/D conversion (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). It generates the interrupt INTAD only if a specified comparison condition is satisfied as a result. 278 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER (8) AVREF pin This pin inputs an analog power/reference voltage to the A/D converter. Always use this pin at the same potential as that of the VDD pin even when the A/D converter is not used. The signal input to ANI0 to ANI7 is converted into a digital signal, based on the voltage applied across AVREF and AVSS. In the standby mode, the current flowing through the series resistor string can be reduced by lowering the voltage input to the AVREF pin to the AVSS level. (9) AVSS pin This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS pin even when the A/D converter is not used. (10) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (11) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (12) Power-fail comparison mode register (PFM) This register is used to set the power-fail monitor mode. (13) Power-fail comparison threshold register (PFT) This register is used to set the threshold value that is to be compared with the value of the A/D conversion result www..com register (ADCR). User's Manual U15947EJ2V0UD 279 CHAPTER 13 A/D CONVERTER 13.3 Registers Used in A/D Converter The A/D converter uses the following five registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * A/D conversion result register (ADCR) * Power-fail comparison mode register (PFM) * Power-fail comparison threshold register (PFT) www..com 280 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-2. Format of A/D Converter Mode Register (ADM) Address: FF28H Symbol ADM <7> ADCS After reset: 00H 6 0 5 FR2 R/W 4 FR1 3 FR0 2 0 1 0 <0> ADCE ADCS 0 1 A/D conversion operation control Stops conversion operation Enables conversion operation FR2 FR1 FR0 Conversion time selectionNote 1 fX = 2 MHz fX = 8.38 MHz fX = 10 MHz 144 s 120 s 96 s 72 s 60 s 48 s 0 0 0 1 1 1 www..com 0 0 1 0 0 1 0 1 0 0 1 0 288/fX 240/fX 192/fX 144/fX 120/fX 96/fX 34.3 s 28.6 s 22.9 s 17.2 s 14.3 s 11.5 s 28.8 s 24.0 s 19.2 s 14.4 s 12.0 s 9.6 s Other than above Setting prohibited ADCE 0 1 Boost reference voltage generator operation controlNote 2 Stops operation of reference voltage generator Enables operation of reference voltage generator Notes 1. Set so that the A/D conversion time is as follows. * Standard products, (A) grade products: 14 s or longer but less than 100 s * (A1) grade products: * (A2) grade products: 14 s or longer but less than 60 s 16 s or longer but less than 48 s 2. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that generates the reference voltage for boosting is controlled by ADCE, and it takes 14 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 14 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. Remark fX: X1 input clock oscillation frequency User's Manual U15947EJ2V0UD 281 CHAPTER 13 A/D CONVERTER Table 13-2. Settings of ADCS and ADCE ADCS 0 0 1 1 ADCE 0 1 0 1 A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates) Note ) Note Data of first conversion cannot be used. Figure 13-3. Timing Chart When Boost Reference Voltage Generator Is Used Boost reference voltage generator: operating ADCE Boost reference voltage Conversion operation ADCS Note Conversion waiting Conversion operation Conversion stopped Note The time from the rising of the ADCE bit to the falling of the ADCS bit must be 14 s or longer to stabilize the reference voltage. www..com Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the identical data. 2. For the sampling time of the A/D converter and the A/D conversion start delay time, see (11) in 13.6 Cautions for A/D Converter. 3. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. CHAPTER 35 CAUTIONS FOR WAIT. Remark fX: X1 input clock oscillation frequency For details, see 282 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-4. Format of Analog Input Channel Specification Register (ADS) Address: FF29H Symbol ADS 7 0 After reset: 00H 6 0 5 0 R/W 4 0 3 0 2 ADS2 1 ADS1 0 ADS0 ADS2 0 0 0 0 1 1 1 1 ADS1 0 0 1 1 0 0 1 1 ADS0 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Analog input channel specification Cautions 1. Be sure to clear bits 3 to 7 of ADS to 0. 2. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is www..com operating on the subsystem clock and the X1 input clock is stopped. CHAPTER 35 CAUTIONS FOR WAIT. For details, see User's Manual U15947EJ2V0UD 283 CHAPTER 13 A/D CONVERTER (3) A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from the most significant bit (MSB). FF09H indicates the higher 8 bits of the conversion result, and FF08H indicates the lower 2 bits of the conversion result. ADCR can be read by a 16-bit memory manipulation instruction. RESET input makes ADCR undefined. Figure 13-5. Format of A/D Conversion Result Register (ADCR) Address: FF08H, FF09H Symbol ADCR After reset: Undefined FF09H R FF08H 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT. www..com Read the conversion result following conversion completion before writing to ADM and ADS. Using 284 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER (4) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-6. Format of Power-Fail Comparison Mode Register (PFM) Address: FF2AH Symbol PFM <7> PFEN After reset: 00H <6> PFCM 5 0 R/W 4 0 3 0 2 0 1 0 0 0 PFEN 0 1 Power-fail comparison enable Stops power-fail comparison (used as a normal A/D converter) Enables power-fail comparison (used for power-fail detection) PFCM Higher 8 bits of ADCR PFT Higher 8 bits of ADCR < PFT Higher 8 bits of ADCR PFT Higher 8 bits of ADCR < PFT Power-fail comparison mode selection Interrupt request signal (INTAD) generation No INTAD generation No INTAD generation INTAD generation 0 1 www..com Caution If data is written to PFM, a wait cycle is generated. Do not write data to PFM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT. (5) Power-fail comparison threshold register (PFT) The power-fail comparison threshold register (PFT) is a register that sets the threshold value when comparing the values with the A/D conversion result. 8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result. PFT can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-7. Format of Power-Fail Comparison Threshold Register (PFT) Address: FF2BH Symbol PFT 7 PFT7 After reset: 00H 6 PFT6 5 PFT5 R/W 4 PFT4 3 PFT3 2 PFT2 1 PFT1 0 PFT0 Caution If data is written to PFT, a wait cycle is generated. Do not write data to PFT when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT. User's Manual U15947EJ2V0UD 285 CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). <2> Set ADCE to 1 and wait for 14 s or longer. <3> Set ADCS to 1 and start the conversion operation. (<4> to <10> are operations performed by hardware.) <4> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <5> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation has ended. <6> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <7> The voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <8> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <9> Comparison is continued in this way up to bit 0 of SAR. www..com <10> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <11> Repeat steps <4> to <10>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the status of ADCE = 0, however, start from <2>. 286 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER Figure 13-8. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined Conversion result ADCR Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to one of the ADM, analog input channel specification register (ADS), power-fail comparison mode register (PFM), or power-fail comparison threshold register (PFT) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. www..com RESET input makes the A/D conversion result register (ADCR) undefined. User's Manual U15947EJ2V0UD 287 CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or (ADCR - 0.5) x where, INT( ): VAIN: AVREF: SAR: AVREF 1024 VAIN < (ADCR + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses Analog input voltage AVREF pin voltage Successive approximation register ADCR: A/D conversion result register (ADCR) value Figure 13-9 shows the relationship between the analog input voltage and the A/D conversion result. Figure 13-9. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR www..com 1023 FFC0H 1022 FF80H 1021 A/D conversion result (ADCR) 3 FF40H 00C0H 2 0080H 1 0040H 0 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 0000H Input voltage/AVREF 288 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison mode register (PFM). * Normal 10-bit A/D converter (PFEN = 0) * Power-fail detection function (PFEN = 1) (1) A/D conversion operation (when PFEN = 0) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 0, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has started and when one A/D conversion has been completed, the next A/D conversion operation is immediately started. The A/D conversion operations are repeated until new data is written to ADS. If ADM, ADS, the power-fail comparison mode register (PFM), and the power-fail comparison threshold register (PFT) are rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. conversion result is undefined. Figure 13-10. A/D Conversion Operation www..com At this time, the Rewriting ADM ADCS = 1 Rewriting ADS ADCS = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion is stopped Conversion result is not retained Stopped ADCR ANIn ANIn ANIm INTAD (PFEN = 0) Remarks 1. n = 0 to 7 2. m = 0 to 7 User's Manual U15947EJ2V0UD 289 CHAPTER 13 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started. When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM. <1> When PFEN = 1 and PFCM = 0 The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when the higher 8 bits of ADCR PFT. <2> When PFEN = 1 and PFCM = 1 The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when the higher 8 bits of ADCR < PFT. Figure 13-11. Power-Fail Detection (When PFEN = 1 and PFCM = 0) A/D conversion ANIn ANIn ANIn ANIn Higher 8 bits of ADCR www..com 80H 7FH 80H PFT 80H INTAD (PFEN = 1) Note First conversion Condition match Note If the conversion result is not read before the end of the next conversion after INTAD is output, the result is replaced by the next conversion result. Remark n = 0 to 7 290 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER The setting methods are described below. * When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <3> Set bit 7 (ADCS) of ADM to 1. <4> An interrupt request signal (INTAD) is generated. <5> Transfer the A/D conversion data to the A/D conversion result register (ADCR). www..com <1> Set bit 7 (PFEN) of the power-fail comparison mode register (PFM). <2> Set power-fail comparison condition using bit 6 (PFCM) of PFM. <3> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <4> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <5> Set a threshold value to the power-fail comparison threshold register (PFT). <6> Set bit 7 (ADCS) of ADM to 1. <7> Transfer the A/D conversion data to the A/D conversion result register (ADCR). <8> The higher 8 bits of ADCR and PFT are compared and an interrupt request signal (INTAD) is generated if the conditions match. User's Manual U15947EJ2V0UD 291 CHAPTER 13 A/D CONVERTER 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot www..com be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 13-12. Overall Error 1......1 Figure 13-13. Quantization Error 1......1 Ideal line Digital output Overall error Digital output 1/2LSB Quantization error 1/2LSB 0......0 0 Analog input AVREF 0......0 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. 292 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 13-14. Zero-Scale Error 111 Digital output (Lower 3 bits) Full-scale error Figure 13-15. Full-Scale Error Ideal line 011 Digital output (Lower 3 bits) 111 010 001 000 110 Zero-scale error 0 1 2 3 AVREF 101 Ideal line 000 0 AVREF-3 AVREF-2 AVREF-1 AVREF www..com Analog input (LSB) Analog input (LSB) Figure 13-16. Integral Linearity Error 1......1 Ideal line Digital output Figure 13-17. Differential Linearity Error 1......1 Ideal 1LSB width Digital output 0......0 0 Integral linearity error Analog input AVREF Differential linearity error 0......0 0 Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time User's Manual U15947EJ2V0UD 293 CHAPTER 13 A/D CONVERTER 13.6 Cautions for A/D Converter (1) Operating current in standby mode The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0. Figure 13-18 shows the circuit configuration of the series resistor string. Figure 13-18. Circuit Configuration of Series Resistor String AVREF P-ch ADCS Series resistor string AVSS (2) Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. www..com (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end of conversion ADCR read has priority. After the read operation, the new conversion result is written to ADCR. <2> Conflict between ADCR write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal (INTAD) generated. 294 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 13-19, to reduce noise. Figure 13-19. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI7 C = 100 to 1,000 pF AVSS VSS www..com (5) ANI0/P20 to ANI7/P27 <1> The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI7 pins In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 13-19). (7) AVREF pin input impedance A series resistor string of several tens of 10 k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. User's Manual U15947EJ2V0UD 295 CHAPTER 13 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 13-20. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) ADS rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended. A/D conversion ANIn ANIn ANIm ANIm ADCR ANIn ANIn ANIm ANIm www..com ADIF Remarks 1. n = 0 to 7 2. m = 0 to 7 (9) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 14 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR) read operation When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. 296 User's Manual U15947EJ2V0UD CHAPTER 13 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 13-21 and Table 13-3. Figure 13-21. Timing of A/D Converter Sampling and A/D Conversion Start Delay ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait period A/D Sampling conversion time start delay time Sampling time Conversion time Conversion time www..com Table 13-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) FR2 FR1 FR0 Conversion Time Sampling Time A/D Conversion Start Delay Time MIN. 0 0 0 1 1 1 0 0 1 0 0 1 Other than above 0 1 0 0 1 0 288/fX 240/fX 192/fX 144/fX 120/fX 96/fX Setting prohibited 40/fX 32/fX 24/fX 20/fX 16/fX 12/fX - 32/fX 28/fX 24/fX 16/fX 14/fX 12/fX - 36/fX 32/fX 28/fX 18/fX 16/fX 14/fX - MAX. Note Note The A/D conversion start delay time is the time after wait period. For the wait function, see CHAPTER 35 CAUTIONS FOR WAIT. Remark fX: X1 clock oscillation frequency (12) Register generating wait cycle Do not read data from the ADCR register and do not write data to the ADM, ADS, PFM, and PFT registers while the CPU is operating on the subsystem clock and while oscillation of the clock input to X1 is stopped. User's Manual U15947EJ2V0UD 297 CHAPTER 13 A/D CONVERTER (13) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-22. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 C3 R2 Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF 2.7 V 4.5 V R1 12 k 4 k R2 8 k 2.7 k C1 8 pF 8 pF C2 3 pF 1.4 pF C3 2 pF 2 pF Remarks 1. The resistance and capacitance values shown in Table 13-4 are not guaranteed values. 2. n = 0 to 7 www..com 298 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 14.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode The functions of this mode are outlined below. For details, see 14.4.2 generator. * Two-pin configuration TXD0: Transmit data output pin Asynchronous serial interface (UART) mode and 14.4.3 Dedicated baud rate RXB0: Receive data input pin * Length of communication data can be selected from 7 or 8 bits. * Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Four operating clock inputs selectable * Fixed to LSB-first communication www..com Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. 2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. 3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. User's Manual U15947EJ2V0UD 299 CHAPTER 14 SERIAL INTERFACE UART0 14.2 Configuration of Serial Interface UART0 Serial interface UART0 consists of the following hardware. Table 14-1. Configuration of Serial Interface UART0 Item Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Port mode register 1 (PM1) Port register 1 (P1) Configuration www..com 300 User's Manual U15947EJ2V0UD Figure 14-1. Block Diagram of Serial Interface UART0 www..com Filter RxD0/ SI10/P11 Receive shift register 0 (RXS0) fX/2 Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator Reception unit Internal bus INTSR0 Reception control Receive buffer register 0 (RXB0) fX/2 5 Selector fX/23 CHAPTER 14 SERIAL INTERFACE UART0 8-bit timer/ event counter 50 output Baud rate generator control register 0 (BRGC0) 7 7 Baud rate generator User's Manual U15947EJ2V0UD INTST0 Transmission control Transmit shift register 0 (TXS0) Output latch (P10) PM10 TxD0/ SCK10/P10 Registers Transmission unit 301 CHAPTER 14 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0). If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is always 0. If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0. RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. RESET input or POWER0 = 0 sets this register to FFH. (2) Receive shift register 0 (RXS0) This register converts the serial data input to the RXD0 pin into parallel data. RXS0 cannot be directly manipulated by a program. (3) Transmit shift register 0 (TXS0) This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is transmitted from the TXD0 pins. TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read. RESET input, POWER0 = 0, or TXE0 = 0 sets this register to FFH. Caution Do not write the next transmit data to TXS0 before the transmission completion interrupt signal (INTST0) is generated. www..com 302 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 14.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 0 (ASIM0) This 8-bit register controls the serial communication operations of serial interface UART0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2) Address: FF70H After reset: 01H R/W Symbol ASIM0 <7> POWER0 <6> TXE0 <5> RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1 POWER0 0 www..com Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . 1 Enables operation of the internal operation clock. TXE0 0 1 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission. RXE0 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception. Notes 1. 2. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. User's Manual U15947EJ2V0UD 303 CHAPTER 14 SERIAL INTERFACE UART0 Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 0 0 1 1 PS00 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parity Note Judges as odd parity. Judges as even parity. CL0 0 1 Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits SL0 0 1 Number of stop bits = 1 Number of stop bits = 2 Specifies number of stop bits of transmit data Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear TXE0 to 0, and then clear POWER0 to 0. 2. At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear RXE0 to 0, www..com and then clear POWER0 to 0. 3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. 4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 5. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. 6. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. 7. Be sure to set bit 0 to 1. 304 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when this register is read. Figure 14-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) Address: FF73H After reset: 00H R Symbol ASIS0 7 0 6 0 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0 PE0 0 1 Status flag indicating parity error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If the parity of transmit data does not match the parity bit on completion of reception. FE0 0 1 Status flag indicating framing error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If the stop bit is not detected on completion of reception. OVE0 www..com Status flag indicating overrun error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If receive data is set to the RXB register and the next reception operation is completed before the data is read. 0 1 Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). 2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. 4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT. User's Manual U15947EJ2V0UD 305 CHAPTER 14 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH. Figure 14-4. Format of Baud Rate Generator Control Register 0 (BRGC0) Address: FF71H After reset: 1FH R/W Symbol BRGC0 7 TPS01 6 TPS00 5 0 4 MDL04 3 MDL03 2 MDL02 1 MDL01 0 MDL00 TPS01 0 0 1 1 TPS00 0 1 0 1 TM50 output fX/2 (5 MHz) fX/2 (1.25 MHz) fX/2 (312.5 kHz) 5 3 Note Base clock (fXCLK0) selection MDL04 MDL03 MDL02 x 0 0 0 * * * * * 0 0 1 1 1 MDL01 x 0 0 1 * * * * * 1 1 0 1 1 MDL00 x 0 1 0 * * * * * 0 1 0 0 1 k x 8 9 10 * * * * * 26 27 28 30 31 Selection of 5-bit counter output clock 0 0 0 www..com 0 1 1 1 * * * * * 1 1 1 1 1 Setting prohibited fXCLK0/8 fXCLK0/9 fXCLK0/10 * * * * * fXCLK0/26 fXCLK0/27 fXCLK0/28 fXCLK0/30 fXCLK0/31 0 * * * * * 1 1 1 1 1 Note To select the TM50 output as the base clock, start an operation by setting 8-bit timer/event counter 50 so that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then clear TPS01 and TPS00 to 0. It is not necessary to enable the TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1). Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the RingOSC clock, the operation of serial interface UART0 is not guaranteed. 2. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 3. The baud rate value is the output clock of the 5-bit counter divided by 2. 306 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits 2. fX: 3. k: 4. x: X1 input clock oscillation frequency Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) Don't care 5. Figures in parentheses apply to operation at fX = 10 MHz (4) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of P10 to 1. When using the P11/RxD0/SI10 pin for serial interface data input, set PM11 to 1. The output latch of P11 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 14-5. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 www..com P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 1 User's Manual U15947EJ2V0UD 307 CHAPTER 14 SERIAL INTERFACE UART0 14.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0, TXE0, and RXE0) of ASIM0 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0). ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Address: FF70H After reset: 01H R/W Symbol ASIM0 <7> POWER0 <6> TXE0 <5> RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1 POWER0 0 www..com Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . TXE0 0 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). RXE0 0 Enables/disables reception Disables reception (synchronously resets the reception circuit). Notes 1. 2. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode. To start the operation, set POWER0 to 1, and then set TXE0 and RXE0 to 1. Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS. 308 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 14.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the BRGC0 register (see Figure 14-4). <2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 14-2). <3> Set bit 7 (POWER0) of the ASIM0 register to 1. <4> Set bit 6 (TXE0) of the ASIM0 register to 1. Transmission is enabled. Set bit 5 (RXE0) of the ASIM0 register to 1. Reception is enabled. <5> Write data to the TXS0 register. Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. www..com The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins POWER0 TXE0 RXE0 PM10 P10 PM11 P11 UART0 Operation 0 1 0 0 1 1 0 1 0 1 x x Note Pin Function TxD0/SCK10/P10 SCK10/P10 SCK10/P10 TxD0 TxD0 RxD0/SI10/P11 SI10/P11 RxD0 SI10/P11 RxD0 x x Note x Note x Note Stop Reception Transmission Transmission/ reception Note Note 1 x Note x x Note 0 0 1 1 1 x Note Can be set as port function. Remark x: TXE0: RXE0: PM1x: P1x: don't care Bit 6 of ASIM0 Bit 5 of ASIM0 Port mode register Port output latch POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) User's Manual U15947EJ2V0UD 309 CHAPTER 14 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. Figure 14-6. Format of Normal UART Transmit/Receive Data 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits (LSB first) * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (ASIM0). Figure 14-7. Example of Normal UART Transmit/Receive Data Waveform www..com 1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Stop 310 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 www..com * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. User's Manual U15947EJ2V0UD 311 CHAPTER 14 SERIAL INTERFACE UART0 (c) Transmission The TXD0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the start bit is output from the TXD0 pin, followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is generated. Transmission is stopped until the data to be transmitted next is written to TXS0. Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt occurs as soon as the last stop bit has been output. Caution After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. Figure 14-8. Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST0 www..com 2. Stop bit length: 2 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST0 312 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the RXD0 pin input is sampled again ( as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an overrun error (OVE0) occurs, however, the receive data is not written to RXB0. Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR0) is generated after completion of reception. Figure 14-9. Reception Completion Interrupt Request Timing in Figure 14-9). If the RXD0 pin is low level at this time, it is recognized RXD0 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR0 RXB0 www..com Cautions 1. Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 0 (ASIS0) before reading RXB0. User's Manual U15947EJ2V0UD 313 CHAPTER 14 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception error interrupt servicing (INTSR0) (see Figure 14-3). The contents of ASIS0 are reset to 0 when ASIS0 is read. Table 14-3. Cause of Reception Error Reception Error Parity error Framing error Overrun error Cause The parity specified for transmission does not match the parity of the receive data. Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 0 (RXB0). (f) Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-10. Noise Filter Circuit www..com Base clock RXD0/SI10/P11 In Q Internal signal A In Q Internal signal B Match detector LD_EN 314 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed to low level when POWER0 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when POWER0 = 1 and TXE0 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0). * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. www..com Figure 14-11. Configuration of Baud Rate Generator POWER0 Baud rate generator fX/2 POWER0, TXE0 (or RXE0) fX/23 Selector fX/25 8-bit timer/ event counter 50 output fXCLK0 5-bit counter Match detector 1/2 Baud rate BRGC0: TPS01, TPS00 BRGC0: MDL04 to MDL00 Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: RXE0: BRGC0: Bit 6 of ASIM0 Bit 5 of ASIM0 Baud rate generator control register 0 User's Manual U15947EJ2V0UD 315 CHAPTER 14 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK0 [bps] 2xk fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz www..com Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16) Target baud rate = 76,800 bps Baud rate = 2.5 M/(2 x 16) = 2,500,000/(2 x 16) = 78,125 [bps] Error = (78,125/76,800 - 1) x 100 = 1.725 [%] 316 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 14-4. Set Data of Baud Rate Generator Baud Rate [bps] TPS01, TPS00 2400 4800 9600 10400 19200 31250 38400 76800 115200 153600 230400 - - 3 3 3 2 2 2 1 1 1 - - 16 15 8 20 16 8 22 16 11 fX = 10.0 MHz k Calculated ERR[%] Value - - 9766 10417 19531 31250 39063 78125 113636 156250 227273 - - 1.73 0.16 1.73 0 1.73 1.73 -1.36 1.73 -1.36 TPS01, TPS00 - 3 3 3 2 2 2 1 1 1 1 - 27 14 13 27 17 14 27 18 14 9 fX = 8.38 MHz k Calculated ERR[%] Value - 4850 9353 10072 19398 30809 38796 77593 116389 149643 232778 - 1.03 -2.58 -3.15 1.03 -1.41 -2.58 1.03 1.03 -2.58 1.03 TPS01, TPS00 3 3 2 2 2 - 2 1 1 - - 27 14 27 25 14 - 27 14 9 - - fX = 4.19 MHz k Calculated ERR[%] Value 2425 4676 9699 10475 18705 - 38796 74821 116389 - - 1.03 -2.58 1.03 0.72 -2.58 - 1.03 -2.58 1.03 - - Remark TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock (fXCLK0)) k: fX: Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31) X1 input clock oscillation frequency Baud rate error www..com ERR: User's Manual U15947EJ2V0UD 317 CHAPTER 14 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 14-12. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART0 Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax www..com As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART0 k: FL: Set value of BRGC0 1-bit data length Margin of latch timing: 2 clocks 318 User's Manual U15947EJ2V0UD CHAPTER 14 SERIAL INTERFACE UART0 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. -1 BRmax = (FLmin/11) = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - k+2 2xk x FL = 21k - 2 2xk FL FLmax = 21k - 2 20k FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k Brate 21k - 2 The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. www..com Table 14-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) 8 16 24 31 Maximum Permissible Baud Rate Error +3.53% +4.14% +4.34% +4.44% Minimum Permissible Baud Rate Error -3.61% -4.19% -4.38% -4.47% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC0 User's Manual U15947EJ2V0UD 319 CHAPTER 15 SERIAL INTERFACE UART6 15.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 15.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 15.4.2 generator. * Two-pin configuration TXD6: Transmit data output pin RXB6: Receive data input pin * Data length of communication data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Twelve operating clock inputs selectable * MSB- or LSB-first communication selectable www..com Asynchronous serial interface (UART) mode and 15.4.3 Dedicated baud rate * Inverted transmission operation * Synchronous break field transmission from 13 to 20 bits * More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided). Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. 2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 3. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is incorporated in LIN. 320 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 15-1 and 15-2 outline the transmission and reception operations of LIN. Figure 15-1. LIN Transmission Operation Wakeup signal frame Synchronous break field Synchronous field Indent field Data field Data field Checksum field Sleep bus 8 bits www..com Note 1 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission TX6 Note 3 INTST6 Notes 1. 2. 3. Remark The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The synchronous break field is output by hardware. The output width is adjusted by baud rate generator control register 6 (BRGC6) (see 15.4.2 (h) SBF transmission). INTST6 is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. User's Manual U15947EJ2V0UD 321 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-2. LIN Reception Operation Wakeup signal frame Sleep bus 13 bitsNote 2 SBF reception Note 3 Reception interrupt (INTSR6) SF reception ID reception Data reception Data Data reception receptionNote 5 Synchronous break field Synchronous field Indent field Data field Data field Checksum field RX6 Disable Enable Edge detection Note 1 (INTP0) Note 4 Capture timer Disable Enable Notes 1. 2. www..com The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored. 3. If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH. 4. 5. Calculate the baud rate error from the bit length of the synchronous field, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again. To perform a LIN receive operation, use a configuration like the one shown in Figure 15-3. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally. 322 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0 INTP0 input Port mode (PM120) Output latch (P120) www..com Port input switch control (ISC0) Selector P00/TI000 TI000 input Port mode (PM00) Output latch (P00) Port input switch control (ISC1) Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 15-11) The peripheral functions used in the LIN communication operation are shown below. User's Manual U15947EJ2V0UD 323 CHAPTER 15 SERIAL INTERFACE UART6 15.2 Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 15-1. Configuration of Serial Interface UART6 Item Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Port mode register 1 (PM1) Port register 1 (P1) Configuration www..com 324 User's Manual U15947EJ2V0UD Figure 15-4. Block Diagram of Serial Interface UART6 TI000, INTP0Note INTSR6 INTSRE6 www..com Filter Reception control Receive shift register 6 (RXS6) Asynchronous serial interface control register 6 (ASICL6) Receive buffer register 6 (RXB6) RXD6/ P14 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 8-bit timer/ event counter 50 output Selector Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Baud rate generator Reception unit Internal bus CHAPTER 15 SERIAL INTERFACE UART6 User's Manual U15947EJ2V0UD Baud rate generator control register 6 (BRGC6) 8 Asynchronous serial Clock selection interface transmission register 6 (CKSR6) status register 6 (ASIF6) 8 Baud rate generator Asynchronous serial interface control register 6 (ASICL6) Transmit buffer register 6 (TXB6) INTST6 Transmission control Transmit shift register 6 (TXS6) TXD6/ P13 Registers Output latch (P13) Transmission unit PM13 Note Selectable with input switch control register (ISC). 325 CHAPTER 15 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. RESET input sets this register to FFH. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. This register can be read or written by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 2. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). www..com (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the base clock. TXS6 cannot be directly manipulated by a program. 326 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 15.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) www..com Address: FF50H After reset: 01H R/W Symbol ASIM6 <7> POWER6 <6> TXE6 <5> RXE6 4 PS61 3 PS60 2 CL6 1 SL6 0 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . 1 Note 3 Enables operation of the internal operation clock TXE6 0 1 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission Notes 1. 2. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when POWER6 = 0. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. 3. Operation of the 8-bit counter output is enabled at the second base clock after 1 is written to the POWER6 bit. User's Manual U15947EJ2V0UD 327 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 0 0 1 1 PS60 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parity Note Judges as odd parity. Judges as even parity. CL6 0 1 Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits SL6 0 1 Number of stop bits = 1 Number of stop bits = 2 Specifies number of stop bits of transmit data ISRM6 www..com Enables/disables occurrence of reception completion interrupt in case of error "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur). 0 1 Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0, and then clear POWER6 to 0. 2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0, and then clear POWER6 to 0. 3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. 4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 5. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN. 6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. 328 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this register is read. Figure 15-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Address: FF53H After reset: 00H R Symbol ASIS6 7 0 6 0 5 0 4 0 3 0 2 PE6 1 FE6 0 OVE6 PE6 0 1 Status flag indicating parity error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If the parity of transmit data does not match the parity bit on completion of reception FE6 0 1 Status flag indicating framing error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If the stop bit is not detected on completion of reception OVE6 www..com Status flag indicating overrun error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If receive data is set to the RXB register and the next reception operation is completed before the data is read. 0 1 Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT. User's Manual U15947EJ2V0UD 329 CHAPTER 15 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0. Figure 15-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Address: FF55H After reset: 00H R Symbol ASIF6 7 0 6 0 5 0 4 0 3 0 2 0 1 TXBF6 0 TXSF6 TXBF6 0 1 Transmit buffer data flag If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6) TXSF6 0 Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer 1 www..com If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 330 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-8. Format of Clock Selection Register 6 (CKSR6) Address: FF56H After reset: 00H R/W Symbol CKSR6 7 0 6 0 5 0 4 0 3 TPS63 2 TPS62 1 TPS61 0 TPS60 TPS63 0 0 0 0 0 0 www..com TPS62 0 0 0 0 1 1 1 1 0 0 0 0 TPS61 0 0 1 1 0 0 1 1 0 0 1 1 TPS60 0 1 0 1 0 1 0 1 0 1 0 1 fX (10 MHz) fX/2 (5 MHz) Base clock (fXCLK6) selection fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (312.5 kHz) fX/2 (156.25 kHz) fX/2 (78.13 kHz) fX/2 (39.06 kHz) fX/2 (19.53 kHz) fX/2 (9.77 kHz) TM50 output Note 10 9 8 7 6 5 4 3 2 0 0 1 1 1 1 Other than above Setting prohibited Note To select the output of TM50 as the base clock, start the operation by setting 8-bit timer/event counter 50 so that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then set TPS63, TPS62, TPS61, and TPS60 to 1, 0, 1, and 1, respectively. It is not necessary to enable the TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1). Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the RingOSC clock, the operation of serial interface UART6 is not guaranteed. 2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. Figures in parentheses are for operation with fX = 10 MHz 2. fX: X1 input clock oscillation frequency User's Manual U15947EJ2V0UD 331 CHAPTER 15 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-9. Format of Baud Rate Generator Control Register 6 (BRGC6) Address: FF57H After reset: FFH R/W Symbol BRGC6 7 MDL67 6 MDL66 5 MDL65 4 MDL64 3 MDL63 2 MDL62 1 MDL61 0 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 x 0 0 0 * * * * * 1 1 1 1 MDL61 x 0 0 1 * * * * * 0 0 1 1 MDL60 x 0 1 0 * * * * * 0 1 0 1 k x 8 9 10 * * * * * 252 253 254 255 Output clock selection of 8-bit counter 0 0 0 0 * * www..com 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 1 1 1 * * * * * 1 1 1 1 Setting prohibited fXCLK6/8 fXCLK6/9 fXCLK6/10 * * * * * fXCLK6/252 fXCLK6/253 fXCLK6/254 fXCLK6/255 * * * 1 1 1 1 Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255) 3. x: Don't care 332 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh operation because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is completed (when an interrupt signal is generated). Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) Address: FF58H After reset: 16H R/W Symbol ASICL6 <7> SBRF6 <6> SBRT6 Note 5 0 4 1 3 0 2 1 1 DIR6 0 TXDLV6 SBRF6 0 1 SBF reception status flag If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly SBF reception in progress SBRT6 www..com SBF reception trigger - SBF reception trigger 0 1 DIR6 0 1 MSB LSB First bit specification TXDLV6 0 1 Normal output of TXD6 Inverted output of TXD6 Enables/disables inverting TXD6 output Note Bits 2 to 5 and 7 are read-only. Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode and hold the status of the SBRF6 flag. 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. User's Manual U15947EJ2V0UD 333 CHAPTER 15 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 15-11. Format of Input Switch Control Register (ISC) Address: FF4FH Symbol ISC After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 0 2 0 1 ISC1 0 ISC0 ISC1 0 1 TI000 (P00) RxD6 (P14) TI000 input source selection ISC0 0 1 INTP0 (P120) RxD6 (P14) INTP0 input source selection (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. www..com When using the P13/TxD3 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1. When using the P14/RxD6 pin for serial interface data input, set PM14 to 1. The output latch of P14 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 15-12. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 334 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 15.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 15.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Address: FF50H After reset: 01H R/W Symbol ASIM6 <7> POWER6 <6> TXE6 <5> RXE6 4 PS61 3 PS60 2 CL6 1 SL6 0 ISRM6 POWER6 0 www..com Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . TXE6 0 Enables/disables transmission Disables transmission operation (synchronously resets the transmission circuit). RXE6 0 Enables/disables reception Disables reception (synchronously resets the reception circuit). Notes 1. 2. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when POWER6 = 0. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode. To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1. Remark To use the RxD6/P14 and TxD6/P13 pins as general-purpose port pins, see CHAPTER 4 FUNCTIONS. PORT User's Manual U15947EJ2V0UD 335 CHAPTER 15 SERIAL INTERFACE UART6 15.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6 register (see Figure 15-8). <2> Set the BRGC6 register (see Figure 15-9). <3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 15-5). <4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 15-10). www..com <5> Set bit 7 (POWER6) of the ASIM6 register to 1. <6> Set bit 6 (TXE6) of the ASIM6 register to 1. Transmission is enabled. Set bit 5 (RXE6) of the ASIM6 register to 1. Reception is enabled. <7> Write data to transmit buffer register 6 (TXB6). Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. 336 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 P13 PM14 P14 UART6 Operation 0 1 0 0 1 1 0 1 0 1 x x Note Pin Function TxD6/P13 P13 P13 TxD6 TxD6 RxD6/P14 P14 RxD6 P14 RxD6 x x Note x Note x Note Stop Reception Transmission Transmission/ reception Note Note 1 x Note x x Note 0 0 1 1 1 x Note Can be set as port function. Remark x: TXE6: RXE6: PM1x: P1x: don't care Bit 6 of ASIM6 Bit 5 of ASIM6 Port mode register Port output latch POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) www..com User's Manual U15947EJ2V0UD 337 CHAPTER 15 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. Figure 15-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity bit Stop bit Character bits www..com One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6. 338 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin inverted output 1 data frame Start www..com D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Stop User's Manual U15947EJ2V0UD 339 CHAPTER 15 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. www..com If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. 340 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 (c) Normal transmission The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 15-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 15-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST6 2. Stop bit length: 2 www..com TXD6 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST6 User's Manual U15947EJ2V0UD 341 CHAPTER 15 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written, and then write the data. Cautions 1. The TXBF6 and TXSF6 flags of the ASIS register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. 2. When the device is incorporated in a LIN, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 0 1 Writing enabled Writing disabled Writing to TXB6 Register Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. www..com Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6 flag. TXSF6 0 1 Transmission is completed. Transmission is in progress. Transmission Status Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 2. During continuous transmission, an overrun error may occur, which means that the next transmission was completed before execution of INTST6 interrupt servicing after transmission of one data frame. An overrun error can be detected by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. 342 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-16 shows an example of the continuous transmission processing flow. Figure 15-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? No Yes Read ASIF6 TXBF6 = 0? Yes No Write TXB6. www..com Transmission completion interrupt occurs? Yes No Transfer executed necessary number of times? No Yes Read ASIF6 TXSF6 = 0? Yes Yes Completion of transmission processing No Remark TXB6: Transmit buffer register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag) User's Manual U15947EJ2V0UD 343 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of ending continuous transmission. Figure 15-17. Timing of Starting Continuous Transmission TXD6 INTST6 Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXB6 FF Data (1) Data (2) Data (3) TXS6 TXBF6 TXSF6 FF Data (1) Data (2) Data (3) Note Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXB6: www..com TXD6 pin (output) Transmit buffer register 6 Transmit shift register 6 Asynchronous serial interface transmission status register 6 INTST6: Interrupt request signal TXS6: ASIF6: TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 344 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-18. Timing of Ending Continuous Transmission TXD6 INTST6 Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop TXB6 Data (n - 1) Data (n) TXS6 Data (n - 1) Data (n) FF TXBF6 TXSF6 POWER6 or TXE6 Remark TXD6: INTST6: TXB6: TXS6: ASIF6: TXBF6: TXSF6: TXD6 pin (output) Interrupt request signal Transmit buffer register 6 Transmit shift register 6 Asynchronous serial interface transmission status register 6 Bit 1 of ASIF6 Bit 0 of ASIF6 Bit 6 of asynchronous serial interface operation mode register (ASIM6) www..com POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6) TXE6: User's Manual U15947EJ2V0UD 345 CHAPTER 15 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 15-19. Reception Completion Interrupt Request Timing in Figure 15-19). If the RXD6 pin is low level at this time, it is recognized RXD6 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6 RXB6 www..com Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. 346 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt servicing (INTSR6/INTSRE6) (see Figure 15-6). The contents of ASIS6 are reset to 0 when ASIS6 is read. Table 15-3. Cause of Reception Error Reception Error Parity error Framing error Overrun error Cause The parity specified for transmission does not match the parity of the receive data. Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 6 (RXB6). The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 15-20. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are separated) www..com (a) No error during reception INTSR6 (b) Error during reception INTSR6 INTSRE6 INTSRE6 2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception (b) Error during reception INTSR6 INTSRE6 INTSR6 INTSRE6 User's Manual U15947EJ2V0UD 347 CHAPTER 15 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 15-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 15-21. Noise Filter Circuit Base clock RXD6/P14 In Q Internal signal A In Q Internal signal B Match detector LD_EN (h) SBF transmission When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is used for transmission. Operation. www..com For the transmission operation of LIN, see Figure 15-1 LIN Transmission SBF transmission is used to transmit an SBF length that is a low-level width of 13 bits or more by adjusting the baud rate value of the ordinary UART transmission function. [Setting method] Transmit 00H by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even parity. This enables a low-level transmission of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits (character bits) + 1 bit (parity bit)). Adjust the baud rate value to adjust this 10-bit low level to the targeted SBF length. Example If LIN is to be transmitted under the following conditions * Base clock of UART6 = 5 MHz (set by clock selection register 6 (CKSR6)) * Target baud rate value = 19200 bps To realize the above baud rate value, the length of a 13-bit SBF is as follows if the baud rate generator control register 6 (BRGC6) is set to 130. * 13-bit SBF length = 0.2 s x 130 x 2 x 13 = 676 s To realize a 13-bit SBF length in 10 bits, set a value 1.3 times the targeted baud rate to BRGC6. In this example, set 169 to BRGC6. The transmission length of a 10-bit low level in this case is as follows, and matches the 13-bit SBF length. * 10-bit low-level transmission length = 0.2 s x 169 x 2 x 10 = 676 s 348 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of UART6. Figure 15-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to generalpurpose register. Clear TXE6 and RXE6 bits of ASIM6 register to 0 (to disable transmission/ reception). Set value to BRGC6 register to realize desired SBF length. Clear TXE6 and RXE6 bits of ASIM6 register to 0. Set character length of data to 8 bits and parity to 0 or even using ASIM6 register. Rewrite saved BRGC6 value to BRGC6 register. www..com Set TXE6 bit of ASIM6 register to 1 to enable transmission. Re-set PS61 bit, PS60 bit, and CL6 bit of ASIM6 register to desired value. Set TXB6 register to "00H" and start transmission. Set TXE6 bit of ASIM6 register to 1 to enable transmission. End No INTST6 occurred? Yes Figure 15-23. SBF Transmission TXD6 1 2 3 4 5 6 7 8 9 10 11 12 13 Stop INTST6 Remark TXD6: TXD6 pin (output) INTST6: Transmission completion interrupt request User's Manual U15947EJ2V0UD 349 CHAPTER 15 SERIAL INTERFACE UART6 (i) SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 15-24. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) RXD6 1 2 3 4 5 6 7 8 9 10 11 www..com SBRT6 /SBRF6 INTSR6 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) RXD6 1 2 3 4 5 6 7 8 9 10 SBRT6 /SBRF6 INTSR6 "0" Remark RXD6: RXD6 pin (input) SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request 350 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 15.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial www..com interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. User's Manual U15947EJ2V0UD 351 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-25. Configuration of Baud Rate Generator POWER6 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 8-bit timer/ event counter 50 output Baud rate generator POWER6, TXE6 (or RXE6) Selector fXCLK6 8-bit counter Match detector 1/2 Baud rate CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: RXE6: CKSR6: BRGC6: Bit 6 of ASIM6 Bit 5 of ASIM6 Clock selection register 6 Baud rate generator control register 6 www..com 352 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 [bps] 2xk fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. www..com Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M/(2 x 33) = 10000000/(2 x 33) = 151,515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] User's Manual U15947EJ2V0UD 353 CHAPTER 15 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 15-4. Set Data of Baud Rate Generator Baud Rate [bps] TPS63 to TPS60 600 1200 2400 4800 9600 10400 19200 31250 38400 76800 115200 153600 230400 6H 5H 4H 3H 2H 2H 1H 1H 0H 0H 0H 0H 0H 130 130 130 130 130 120 130 80 130 65 43 33 22 fX = 10.0 MHz k Calculated ERR[%] TPS63 to Value TPS60 601 1202 2404 4808 9615 10417 19231 31250 38462 76923 116279 151515 227272 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 0.16 0.94 -1.36 -1.36 6H 5H 4H 3H 2H 2H 1H 0H 0H 0H 0H 0H 0H fX = 8.38 MHz k Calculated ERR[%] TPS63 to Value TPS60 601 1201 2403 4805 9610 10371 19200 31268 38440 76182 116388 155185 232777 0.11 0.11 0.11 0.11 0.11 0.28 0.11 0.06 0.11 -0.80 1.03 1.03 1.03 5H 4H 3H 2H 1H 1H 0H 0H 0H 0H 0H 0H 0H fX = 4.19 MHz k Calculated ERR[%] Value 601 1201 2403 4805 9610 10475 19220 31268 38090 77593 116389 149643 232778 0.11 0.11 0.11 0.11 0.11 -0.28 0.11 0.06 -0.80 1.03 1.03 -2.58 1.03 109 109 109 109 109 101 109 134 109 55 36 27 18 109 109 109 109 109 101 109 67 55 27 18 14 9 Remark www..com TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6)) k: fX: ERR: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 8, 9, 10, ..., 255) X1 input clock oscillation frequency Baud rate error 354 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 15-26. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART6 Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax www..com As shown in Figure 15-26, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART6 k: FL: Set value of BRGC6 1-bit data length Margin of latch timing: 2 clocks User's Manual U15947EJ2V0UD 355 CHAPTER 15 SERIAL INTERFACE UART6 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. -1 BRmax = (FLmin/11) = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - k+2 2xk x FL = 21k - 2 2xk FL FLmax = 21k - 2 20k FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k Brate 21k - 2 The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. www..com Table 15-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) 8 20 50 100 255 Maximum Permissible Baud Rate Error +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Permissible Baud Rate Error -3.61% -4.31% -4.58% -4.67% -4.73% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC6 356 User's Manual U15947EJ2V0UD CHAPTER 15 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 15-27. Data Frame Length During Continuous Transmission 1 data frame Start bit of second byte Bit 7 FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Start bit FL Bit 0 FL Bit 1 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 www..com User's Manual U15947EJ2V0UD 357 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The PD780143 and 780144 incorporate serial interface CSI10, and the PD780146, 780148, and 78F0148 incorporate serial interfaces CSI10 and CSI11. 16.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 16.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK1n) and two serial data lines (SI1n and SO1n). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can be connected to any device. www..com The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. For details, see 16.4.2 3-wire serial I/O mode. 358 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 consist of the following hardware. Table 16-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Registers Configuration Transmit buffer register 1n (SOTB1n) Serial I/O shift register 1n (SIO1n) Transmit controller Clock start/stop controller & clock phase controller Control registers Serial operation mode register 1n (CSIM1n) Serial clock selection register 1n (CSIC1n) Port mode register 0 (PM0) or port mode register 1 (PM1) Port register 0 (P0) or port register 1 (P1) Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: Figure 16-1. Block Diagram of Serial Interface CSI10 Internal bus 8 8 Transmit buffer register 10 (SOTB10) Output selector SO10/P12 SI10/P11/RXD0 www..com Serial I/O shift register 10 (SIO10) Transmit data controller Output latch Output latch (P12) PM12 Transmit controller fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 SCK10/P10/TxD0 Selector Clock start/stop controller & clock phase controller INTCSI10 User's Manual U15947EJ2V0UD 359 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-2. Block Diagram of Serial Interface CSI11 (PD780146, 780148, and 78F0148 Only) Internal bus 8 SI11/P03 Serial I/O shift register 11 (SIO11) 8 Transmit buffer register 11 (SOTB11) Output selector SO11/P02 Transmit data controller Output latch Output latch (P02) SSI11 Transmit controller fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 SCK11/P04 PM02 Selector Clock start/stop controller & clock phase controller INTCSI11 (1) Transmit buffer register 1n (SOTB1n) This register sets the transmit data. Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and output to the serial output pin (SO1n). www..com SOTB1n can be written or read by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication). 2. The SSI11 pin can be used in the slave mode. For details of the transmission/reception operation, see 16.4.2 (2) Communication operation. (2) Serial I/O shift register 1n (SIO1n) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. During reception, the data is read from the serial input pin (SI1n) to SIO1n. RESET input clears this register to 00H. Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication). 2. The SSI11 pin can be used in the slave mode. For details of the reception operation, see 16.4.2 (2) Communication operation. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 360 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) (1) Serial operation mode register 1n (CSIM1n) CSIM1n is used to select the operation mode and enable or disable operation. CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 Figure 16-3. Format of Serial Operation Mode Register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol CSIM10 <7> CSIE10 6 TRMD10 Note 1 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10 CSIE10 0 www..com Operation control in 3-wire serial I/O mode Disables operation Enables operation Note 2 and asynchronously resets the internal circuit Note 3 . 1 TRMD10 0 Note 5 Note 4 Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode 1 DIR10 0 1 Note 6 First bit specification MSB LSB CSOT10 0 1 Communication is stopped. Communication is in progress. Communication status flag Notes 1. 2. 3. 4. 5. 6. Bit 0 is a read-only bit. When using as a general-purpose port, see Caution 3 of Figure 16-5 and Table 16-2. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). The SO10 output is fixed to the low level when TRMD10 is 0. Reception is started when data is read from SIO10. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). Caution Be sure to clear bit 5 to 0. User's Manual U15947EJ2V0UD 361 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11) Address: FF88H After reset: 00H R/W Symbol CSIM11 <7> CSIE11 6 TRMD11 Note 1 5 SSE11 4 DIR11 3 0 2 0 1 0 0 CSOT11 CSIE11 0 1 Disables operation Enables operation Note 2 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 3 . TRMD11 0 Note 5 Note 4 Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode 1 SSE11 0 1 Notes 6, 7 SSI11 pin use selection SSI11 pin is not used SSI11 pin is used DIR11 0 1 www..com Note 8 First bit specification MSB LSB CSOT11 0 1 Communication is stopped. Communication is in progress. Communication status flag Notes 1. 2. 3. 4. 5. 6. 7. 8. Bit 0 is a read-only bit. When using as a general-purpose port, see Caution 3 of Figure 16-6 and Table 16-2. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. Do not rewrite TRMD11 when CSOT11 = 1 (during serial communication). The SO11 output is fixed to the low level when TRMD11 is 0. Reception is started when data is read from SIO11. Do not rewrite SSE11 when CSOT11 = 1 (during serial communication). Before setting this bit to 1, fix the SSI11 pin input level to 0 or 1. Do not rewrite DIR11 when CSOT11 = 1 (during serial communication). 362 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10) Address: FF81H After reset: 00H R/W Symbol CSIC10 7 0 6 0 5 0 4 CKP10 3 DAP10 2 CKS102 1 CKS101 0 CKS100 CKP10 0 DAP10 0 Specification of data transmission/reception timing Type 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 0 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 2 www..com 1 0 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 3 1 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 4 CKS102 0 0 0 0 1 1 1 1 CKS101 0 0 1 1 0 0 1 1 CKS100 0 1 0 1 0 1 0 1 fX/2 (5 MHz) CSI10 serial clock selection Mode Master mode Master mode Master mode Master mode Master mode Master mode Master mode Slave mode fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (312.5 kHz) fX/2 (156.25 kHz) fX/2 (78.13 kHz) External clock input to SCK10 7 6 5 4 3 2 User's Manual U15947EJ2V0UD 363 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the RingOSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI10 is not guaranteed. 2. Do not write to CSIC10 while CSIE10 = 1 (operation enabled). 3. Clear CKP10 to 0 to use P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 as general-purpose port pins. 4. The phase type of the data clock is type 1 after reset. Remarks 1. Figures in parentheses are for operation with fx = 10 MHz 2. fX: X1 input clock oscillation frequency www..com 364 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol CSIC11 7 0 6 0 5 0 4 CKP11 3 DAP11 2 CKS112 1 CKS111 0 CKS110 CKP11 0 DAP11 0 Specification of data transmission/reception timing SCK11 SO11 SI11 input timing D7 D6 D5 D4 D3 D2 D1 D0 Type 1 0 1 SCK11 SO11 SI11 input timing D7 D6 D5 D4 D3 D2 D1 D0 2 1 0 SCK11 SO11 SI11 input timing D7 D6 D5 D4 D3 D2 D1 D0 3 1 1 SCK11 SO11 SI11 input timing D7 D6 D5 D4 D3 D2 D1 D0 4 www..com CKS112 0 0 0 0 1 1 1 1 CKS111 0 0 1 1 0 0 1 1 CKS110 0 1 0 1 0 1 0 1 fX/2 (5 MHz) CSI11 serial clock selection Mode Master mode Master mode Master mode Master mode Master mode Master mode Master mode Slave mode fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (312.5 kHz) fX/2 (156.25 kHz) fX/2 (78.13 kHz) External clock input to SCK11 7 6 5 4 3 2 Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the RingOSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI11 is not guaranteed. 2. Do not write to CSIC11 while CSIE11 = 1 (operation enabled). 3. Clear CKP11 to 0 to use P02/SO11, P03/SI11, and P04/SCK11 as general-purpose port pins. 4. The phase type of the data clock is type 1 after reset. Remarks 1. Figures in parentheses are for operation with fx = 10 MHz 2. fX: X1 input clock oscillation frequency User's Manual U15947EJ2V0UD 365 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Port mode registers 0 and 1 (PM0, PM1) These registers set port 0 and 1 input/output in 1-bit units. When using P10/SCK10 and P04/SCK11Note as the clock output pins of the serial interface, and P12/SO10 and P02/SO11Note as the data output pins, clear PM10, PM04, PM12, PM02, and the output latches of P10, P04, P12, and P02 to 0. When using P10/SCK10 and P04/SCK11Note as the clock input pins of the serial interface, P11/SI10/RxD0 and P03/SI11Note as the data input pins, and P05/SSI11/TI001 as the chip select input pin, set PM10, PM04, PM11, PM03, and PM05 to 1. At this time, the output latches of P10, P04, P11, P03, and P05 may be 0 or 1. PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Note PD780146, 780148, 78F0148 only. Figure 16-7. Format of Port Mode Register 0 (PM0) Address: FF20H Symbol PM0 7 1 6 After reset: FFH 5 4 R/W 3 2 1 0 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n 0 1 www..com P0n pin I/O mode selection (n = 0 to 6) Output mode (output buffer on) Input mode (output buffer off) Figure 16-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol 7 6 After reset: FFH 5 4 R/W 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 366 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/TXD0, P11/SI10/RXD0, P12/SO10, P02/SO11Note, P03/SI11Note, and P04/SCK11Note pins can be used as ordinary I/O port pins in this mode. Note PD780146, 780148, and 78F0148 only (1) Register used The operation stop mode is set by serial operation mode register 1n (CSIM1n). To set the operation stop mode, clear bit 7 (CSIE1n) of CSIM1n to 0. (a) Serial operation mode register 1n (CSIM1n) CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM1n to 00H. Remark PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 n = 0: * Serial operation mode register 10 (CSIM10) www..com Address: FF80H After reset: 00H R/W Symbol CSIM10 <7> CSIE10 6 TRMD10 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10 CSIE10 0 Disables operation Note 1 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 2 . Notes 1. 2. To use the SI10/RxD0/P11, SO10/P12, and SCK10/TxD0/P10 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. * Serial operation mode register 11 (CSIM11) Address: FF88H After reset: 00H R/W Symbol CSIM11 <7> CSIE11 6 TRMD11 5 SSE11 4 DIR11 3 0 2 0 1 0 0 CSOT11 CSIE11 0 Disables operation Note 1 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 2 . Notes 1. 2. To use the SI11/P03, SO11/P02, SCK11/P04, and SSI11/TI001/P05 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. User's Manual U15947EJ2V0UD 367 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines. (1) Registers used * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the CSIC1n register (see Figures 16-5 and 16-6). <2> Set bits 0 and 4 to 6 (CSOT1n, DIR1n, SSE11 (serial interface CSI11 only), and TRMD1n) of the CSIM1n register (see Figures 16-3 and 16-4). <3> Set bit 7 (CSIE1n) of the CSIM1n register to 1. Transmission/reception is enabled. <4> Write data to transmit buffer register 1n (SOTB1n). Data transmission/reception is started. Read data from serial I/O shift register 1n (SIO1n). Data reception is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. www..com Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 368 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 16-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 P10 CSI10 Operation Pin Function SI10/RxD0/ SO10/P12 P11 0 x x Note 1 SCK10/ TxD0/P10 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Stop RxD0/P11 P12 TxD0/ P10 Note 2 1 0 1 Note 1 x Note 1 x Note 1 x Note 1 1 x Slave reception Note 3 SI10 P12 SCK10 (input) Note 3 1 1 x x 0 0 1 x Slave transmission Note 3 RxD0/P11 SO10 SCK10 (input) Note 3 1 1 1 x 0 0 1 x Slave transmission/ reception Note 3 SI10 SO10 SCK10 (input) Note 3 1 0 1 Note 1 x Note 1 x Note 1 x Note 1 0 1 Master reception SI10 P12 SCK10 (output) 1 1 x x 0 0 0 1 Master transmission RxD0/P11 SO10 SCK10 (output) 1 1 1 x 0 0 0 1 Master transmission/ reception SI10 SO10 SCK10 (output) www..com Notes 1. Can be set as port function. 2. To use P10/SCK10/TxD0 as port pins, clear CKP10 to 0. 3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1. Remark x: CSIE10: TRMD10: CKP10: PM1x: P1x: don't care Bit 7 of serial operation mode register 10 (CSIM10) Bit 6 of CSIM10 Bit 4 of serial clock selection register 10 (CSIC10) Port mode register Port output latch CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10 User's Manual U15947EJ2V0UD 369 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2. Relationship Between Register Settings and Pins (2/2) (b) Serial interface CSI11 (PD780146, 780148, 78F0148 only) CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 CSI11 Operation SI11/ P03 0 x x x Note 1 Pin Function SO11/ P02 P02 SCK11/ P04 P04 Note 2 SSI11/ TI001/P05 TI001/ P05 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Stop P03 1 0 0 1 x x Note 1 x Note 1 1 x x Note 1 x Note 1 Slave reception Note 3 SI11 P02 SCK11 (input) Note 3 TI001/ P05 SSI11 1 1 1 0 x Note 1 1 x Note 1 x x Note 1 0 0 1 x x Note 1 Slave transmission Note 3 P03 SO11 SCK11 (input) Note 3 TI001/ P05 SSI11 1 1 1 0 1 x 0 0 1 x x 1 Note 1 x x Note 1 Slave transmission/ reception Note 3 SI11 SO11 SCK11 (input) Note 3 TI001/ P05 SSI11 1 1 0 0 1 Note 1 1 x Note 1 x x Note 1 x Note 1 x Note 1 0 1 x Note 1 Master reception SI11 P02 SCK11 (output) TI001/ P05 TI001/ P05 TI001/ P05 1 1 0 x x 0 0 0 1 x Note 1 x Note 1 Master transmission P03 SO11 SCK11 (output) 1 1 0 1 x 0 0 0 1 x Note 1 x Note 1 Master transmission/ reception SI11 SO11 SCK11 (output) www..com Notes 1. Can be set as port function. 2. To use P04/SCK11 as port pins, clear CKP11 to 0. 3. To use the slave mode, set CKS112, CKS111, and CKS110 to 1, 1, 1. Remark x: CSIE11: TRMD11: CKP11: PM0x: P0x: don't care Bit 7 of serial operation mode register 11 (CSIM11) Bit 6 of CSIM11 Bit 4 of serial clock selection register 11 (CSIC11) Port mode register Port output latch CKS112, CKS111, CKS110: Bits 2 to 0 of CSIC11 370 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n). In addition, data can be received when bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. Reception is started when data is read from serial I/O shift register 1n (SIO1n). However, communication is performed as follows if bit 5 (SSE11) of CSIM11 is 1 when serial interface CSI11 is in the slave mode. <1> Low level input to the SSI11 pin Transmission/reception is started when SOTB11 is written, or reception is started when SIO11 is read. <2> High level input to the SSI11 pin Transmission/reception or reception is held, therefore, even if SOTB11 is written or SIO11 is read, transmission/reception or reception will not be started. <3> Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin, then a low level is input to the SSI11 pin Transmission/reception or reception is started. <4> A high level is input to the SSI11 pin during transmission/reception or reception Transmission/reception or reception is suspended. After communication has been started, bit 0 (CSOT1n) of CSIM1n is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt request flag (CSIIF1n) is set, and CSOT1n is cleared to 0. Then the next communication is enabled. www..com Cautions 1. Do not access the control register and data register when CSOT1n = 1 (during serial communication). 2. When using serial interface CSI11, wait for the duration of at least one clock before the clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise, malfunctioning may occur. Remark n = 0, 1 User's Manual U15947EJ2V0UD 371 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (1/2) (1) Transmission/reception timing (Type 1; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n 55H (communication data) SIO1n ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (receive AAH) www..com SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 372 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n 55H (communication data) SIO1n ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (input AAH) www..com SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 373 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-10. Timing of Clock/Data Phase (a) Type 1; CKP1n = 0, DAP1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n D7 D6 D5 D4 D3 D2 D1 D0 (b) Type 2; CKP1n = 0, DAP1n = 1 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n D7 D6 D5 D4 D3 D2 D1 D0 (c) Type 3; CKP1n = 1, DAP1n = 0 www..com SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n D7 D6 D5 D4 D3 D2 D1 D0 (d) Type 4; CKP1n = 1, DAP1n = 1 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n D7 D6 D5 D4 D3 D2 D1 D0 Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 374 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 16-11. Output Operation of First Bit (1) When CKP1n = 0, DAP1n = 0 (or CKP1n = 1, DAP1n = 0) SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising) www..com edge of SCK1n, and the data is output from the SO1n pin. (2) When CKP1n = 0, DAP1n = 1 (or CKP1n = 1, DAP1n = 1) SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling) edge of SCK1n, and the data is output from the SO1n pin. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 User's Manual U15947EJ2V0UD 375 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 16-12. Output Value of SO1n Pin (Last Bit) (1) Type 1; when CKP1n = 0 and DAP1n = 0 (or CKP1n = 1, DAP1n = 0) SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n Last bit ( Next request is issued.) (2) Type 2; when CKP1n = 0 and DAP1n = 1 (or CKP1n = 1, DAP1n = 1) SCK1n Writing to SOTB1n or reading from SIO1n www..com ( Next request is issued.) SOTB1n SIO1n Output latch SO1n Last bit Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 376 User's Manual U15947EJ2V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is cleared to 0. Table 16-3. SO1n Output Status TRMD1n TRMD1n = 0 TRMD1n = 1 Note DAP1n - DAP1n = 0 DIR1n - - SO1n Output Outputs low level Note . Value of SO1n latch (low-level output) DAP1n = 1 DIR1n = 0 DIR1n = 1 Value of bit 7 of SOTB1n Value of bit 0 of SOTB1n Note Status after reset Caution If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes. Remark n = 0: PD780143, 780144 n = 0, 1: PD780146, 780148, 78F0148 www..com User's Manual U15947EJ2V0UD 377 CHAPTER 17 SERIAL INTERFACE CSIA0 17.1 Functions of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 17.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCKA0) and two serial data lines (SIA0 and SOA0). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated MSB or LSB first can be specified, so this interface can be connected to any device. For details, see 17.4.2 3-wire serial I/O mode. (3) 3-wire serial I/O mode with automatic transmit/receive function (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCKA0) and two serial www..com data lines (SIA0 and SOA0). The processing time of data communication can be shortened in the 3-wire serial I/O mode with automatic transmit/receive function because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated MSB or LSB first can be specified, so this interface can be connected to any device. Data can be communicated to/from a display driver etc. without using software since a 32-byte transfer buffer RAM is incorporated. Also, the incorporation of handshake pins (STB0, BUSY0) has made connection to peripheral LSIs easy. For details, see 17.4.3 3-wire serial I/O mode with automatic transmit/receive function. * Master mode/slave mode selectable * Communication data length: 8 bits * MSB/LSB-first selectable for communication data * Automatic transmit/receive function: Number of transfer bytes can be specified between 1 and 32 Transfer interval can be specified (0 to 63 clocks) Single communication/repeat communication selectable * On-chip dedicated baud rate generator (6/8/16/32 divisions) * 3-wire SOA0: Serial data output SIA0: Serial data input Strobe output SCKA0: Serial clock I/O * Handshake function incorporated STB0: BUSY0: Busy input * Transmission/reception completion interrupt: INTACSI * Internal 32-byte buffer RAM 378 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 17.2 Configuration of Serial Interface CSIA0 Serial interface CSIA0 consists of the following hardware. Table 17-1. Configuration of Serial Interface CSIA0 Item Registers Configuration Serial I/O shift register 0 (SIOA0) Automatic data transfer address count register 0 (ADTC0) Control registers Serial operation mode specification register 0 (CSIMA0) Serial status register 0 (CSIS0) Serial trigger register 0 (CSIT0) Divisor selection register 0 (BRGCA0) Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer interval specification register 0 (ADTI0) Port mode register 14 (PM14) Port register 14 (P14) www..com User's Manual U15947EJ2V0UD 379 www..com 380 Buffer RAM ATE0 DIR0 RXAE SIA0/P143 User's Manual U15947EJ2V0UD Serial I/O shift register 0 (SIOA0) Figure 17-1. Block Diagram of Serial Interface CSIA0 Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer address count register 0 (ADTC0) Internal bus Serial trigger register 0 (CSIT0) ATM0 TXAE CHAPTER 17 SERIAL INTERFACE CSIA0 Divisor selection register 0 (BRGCA0) ATSTP0 ATSTA0 Serial status register 0 (CSIS0) STBE0 BUSYE0 BUSYLV0 ERRE0 ERRF0 TSF0 2 SOA0/P144 PM144 P144 STB0/P145 PM145 BUSY0/P141 P145 Serial transfer controller Serial clock counter Interrupt generator INTACSI 4 3 SCKA0/P142 PM142 P142 Selector fX/6 to fX/32 Automatic data transfer interval specification register 0 (ADTI0) Baud rate generator fX 6-bit counter MASTER0 CHAPTER 17 SERIAL INTERFACE CSIA0 (1) Serial I/O shift register 0 (SIOA0) This is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 0). Writing transmit data to SIOA0 starts the communication. In addition, after a communication completion interrupt request (INTACSI) is output (bit 0 (TSF0) of serial status register 0 (CSIS0) = 0), data can be received by reading data from SIOA0. This register can be written or read by an 8-bit memory manipulation instruction. However, writing to SIOA0 is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1. RESET input clears this register to 00H. Cautions 1. A communication operation is started by writing to SIOA0. Consequently, when transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the SIOA0 register to start the communication operation, and then perform a receive operation. 2. Do not write data to SIOA0 while the automatic transmit/receive function is operating. (2) Automatic data transfer address count register 0 (ADTC0) This is a register used to indicate buffer RAM addresses during automatic transfer. When automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading ADTC0 register value. This register can be read by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. However, reading from ADTC0 is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1. Figure 17-2. Format of Automatic Data Transfer Address Count Register 0 (ADTC0) Address: FF97H www..com After reset: 00H 7 0 6 0 R 5 0 4 ADTC04 3 ADTC03 2 ADTC02 1 ADTC01 0 ADTP00 Symbol ADTC0 17.3 Registers Controlling Serial Interface CSIA0 Serial interface CSIA0 is controlled by the following eight registers. * Serial operation mode specification register 0 (CSIMA0) * Serial status register 0 (CSIS0) * Serial trigger register 0 (CSIT0) * Divisor selection register 0 (BRGCA0) * Automatic data transfer address point specification register 0 (ADTP0) * Automatic data transfer interval specification register 0 (ADTI0) * Port mode register 14 (PM14) * Port register 14 (P14) User's Manual U15947EJ2V0UD 381 CHAPTER 17 SERIAL INTERFACE CSIA0 (1) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 17-3. Format of Serial Operation Mode Specification Register 0 (CSIMA0) Address: FF90H Symbol CSIMA0 <> CSIAE0 CSIAE0 0 1 ATE0 ATM0 MASTER0 After reset: 00H R/W <> TXEA0 <> RXEA0 DIR0 0 Control of CSIA0 operation enable/disable CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and asynchronously resets the internal circuitNote. CSIA0 operation enabled ATE0 0 1 ATM0 0 1 MASTER0 0 1 Control of automatic communication operation enable/disable 1-byte communication mode Automatic communication mode Automatic communication mode specification Single transfer mode (stops at the address specified by the ADTP0 register) Repeat transfer mode (after transfer is complete, clear the ADTC0 register to 00H to resume transfer) CSIA0 master/slave mode specification Slave mode (synchronous with SCKA0 input clock) Master mode (synchronous with internal clock) Control of transmit operation enable/disable Transmit operation disabled (SOA0: Low level) Transmit operation enabled Control of receive operation enable/disable Receive operation disabled Receive operation enabled First bit specification MSB LSB www..com TXEA0 0 1 RXEA0 0 1 DIR0 0 1 Note Automatic data transfer address count register 0 (ADTC0), serial trigger register 0 (CSIT0), serial I/O shift register 0 (SIOA0), and bit 0 (TSF0) of serial status register 0 (CSIS0) are reset. Cautions 1. When CSIAE0 = 0, the buffer RAM cannot be accessed. 2. When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set the initialized registers. 3. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that the value of the buffer RAM will be retained. 382 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (2) Serial status register 0 (CSIS0) This is an 8-bit register used to control the communication operation and indicate status of CSIA0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. However, rewriting CSIS0 is prohibited when bit 0 (TSF0) is 1. Figure 17-4. Format of Serial Status Register 0 (CSIS0) (1/2) Address: FF91H Symbol CSIS0 After reset: 00H 7 0 STBE0Notes 2, 3 0 1 BUSYE0 0 1 BUSYLV0Note 4 0 1 www..com R/WNote 1 5 STBE0 4 BUSYE0 3 BUSYLV0 2 ERRE0 1 ERRF0 0 TSF0 6 0 Strobe output enable/disable Strobe output disabled Strobe output enabled Busy signal detection enable/disable Busy signal detection disabled (input via BUSY0 pin is ignored) Busy signal detection enabled and communication wait by busy signal is executed Busy signal active level setting Low level High level Notes 1. 2. 3. Bits 0 and 1 are read-only. STBE0 is valid only in master mode. When STBE0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the setting of automatic data transfer interval specification register 0 (ADTI0). That is, 10 transfer clocks are used for 1-byte transfer if ADTI0 = 00H is set. 4. Caution In bit error detection by busy input, the active level specified by BUSYLV0 is detected. Be sure to clear bits 6 and 7 to 0. User's Manual U15947EJ2V0UD 383 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-4. Format of Serial Status Register 0 (CSIS0) (2/2) ERRE0Note 0 1 ERRF0 0 Error detection disabled Error detection enabled Bit error detection flag * Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 * At reset input * When communication is started by setting bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1 or writing to SIOA0. Bit error detected (when ERRE0 = 1, the level specified by BUSYLV0 during the data bit transfer period is detected via BUSY0 pin input). Bit error detection enable/disable 1 TSF0 0 * * * * Transfer status detection flag Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 At reset input At the end of the specified transfer When transfer is stopped by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1 1 From the transfer start to the end of the specified transfer Note The ERRE0 setting is valid even when BUSYE0 = 0. Caution When TSF0 is 1, rewriting serial operation mode specification register 0 (CSIMA0), serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address point www..com specification register 0 (ADTP0), automatic data transfer interval specification register 0 (ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can be read and re-written to the same value. In addition, the buffer RAM can be rewritten during transfer. 384 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (3) Serial trigger register 0 (CSIT0) This is an 8-bit register used to control execution/stop of automatic data transfer between buffer RAM and serial I/O shift register 0 (SIOA0). This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. However, manipulate only when bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is 1 (manipulation prohibited when ATE0 = 0). Figure 17-5. Format of Serial Trigger Register 0 (CSIT0) Address: FF92H Symbol CSIT0 After reset: 00H 7 0 ATSTP0 0 1 ATSTA0 0 1 Automatic data transfer started Automatic data transfer stopped Automatic data transfer start - 6 0 R/W 5 0 4 0 3 0 2 0 <1> ATSTP0 <0> ATSTA0 Automatic data transfer stop - Cautions 1. Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be started/stopped until 1byte transfer is complete. www..com 2. ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI is generated. 3. After automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (ADTC0). However, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting ATSTP0 = 1, start automatic data transfer by ATSTA0 after re-setting the registers. User's Manual U15947EJ2V0UD 385 CHAPTER 17 SERIAL INTERFACE CSIA0 (4) Divisor selection register 0 (BRGCA0) This is an 8-bit register used to select the serial clock. This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting BRGCA0 is prohibited. Figure 17-6. Format of Divisor Selection Register 0 (BRGCA0) Address: FF93H Symbol BRGCA0 After reset: 03H 7 0 BRGCA01 0 0 1 1 6 0 BRGCA00 0 1 0 1 fX/6 (1.67 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (312.5 kHz) R/W 5 0 4 0 3 0 2 0 1 BRGCA01 0 BRGCA00 CSIA0 serial clock selection Remarks 1. Figures in parentheses apply to operation with fX = 10 MHz 2. fX: X1 input clock oscillation frequency (5) Automatic data transfer address point specification register 0 (ADTP0) This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 = 1). www..com This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting ADTP0 is prohibited. In the 78K0/KF1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When ADTP0 is set to 07H 8 bytes of FA00H to FA07H are transferred. In repeat transfer mode (bit 5 (ATM0) of CSIMA0 = 1), transfer is performed repeatedly up to the address specified with ADTP0. Example When ADTP0 is set to 07H (repeat transfer mode) Transfer is repeated as FA00H to FA07H, FA00H to FA07H, ... . Figure 17-7. Format of Automatic Data Transfer Address Point Specification Register 0 (ADTP0) Address: FF94H Symbol ADTP0 After reset: 00H 7 0 6 0 R/W 5 0 4 ADTP04 3 ADTP03 2 ADTP02 1 ADTP01 0 ADTP00 Caution Be sure to clear bits 7 to 5 to 0. 386 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 The relationship between buffer RAM address values and ADTP0 setting values is shown below. Table 17-2. Relationship Between Buffer RAM Address Values and ADTP0 Setting Values Buffer RAM Address Value FA00H FA01H FA02H FA03H FA04H FA05H FA06H FA07H FA08H FA09H FA0AH FA0BH FA0CH FA0DH FA0EH FA0FH www..com ADTP0 Setting Value 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Buffer RAM Address Value FA10H FA11H FA12H FA13H FA14H FA15H FA16H FA17H FA18H FA19H FA1AH FA1BH FA1CH FA1DH FA1EH FA1FH ADTP0 Setting Value 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH User's Manual U15947EJ2V0UD 387 CHAPTER 17 SERIAL INTERFACE CSIA0 (6) Automatic data transfer interval specification register 0 (ADTI0) This is an 8-bit register used to specify the interval time between 1-byte communications during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1). Set this register when in master mode (bit 4 (MASTER0) of CSIMA0 = 1) (setting is unnecessary in slave mode). Setting in 1-byte communication mode (bit 6 (ATE0) of CSIMA0 = 0) is also valid. When the interval time specified by ADTI0 after the end of 1-byte communication has elapsed, an interrupt request signal (INTACSI) is output. The number of clocks for the interval can be set to between 0 and 63 clocks. This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting ADTI0 is prohibited. Figure 17-8. Format of Automatic Data Transfer Interval Specification Register 0 (ADTI0) Address: FF95H Symbol ADTI0 After reset: 00H 7 0 6 0 R/W 5 ADTI05 4 ADTI04 3 ADTI03 2 ADTI02 1 ADTI01 0 ADTI00 Caution Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register 0 (CSIS0) takes priority over the ADTI0 setting, the interval time based on the setting of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H. Example Interval time when busy signal is not generated <1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated <2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated www..com <3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated Therefore, clearing STBE0 and BUSYE0 to 0 is required to perform no-wait transfer. The specified interval time is the serial clock (specified by divisor selection register 0 (BRGCA0)) multiplied by an integer value. Example When ADTI0 = 03H SCKA0 Interval time of 3 clocks 388 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (7) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using P142/SCKA0, P144/SOA0, and P145/STB0 pins as the clock output, data output, or strobe output of the serial interface, clear PM142, PM144, PM145, and the output latches of P142, P144, and P145 to 0. When using P141/BUSY0, P142/SCKA0, and P143/SIA0 pins as the busy input, clock input, or data input of the serial interface, set PM141, PM142, and PM143 to 1. At this time, the output latches of P141, P142, and P143 may be 0 or 1. PM14 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 17-9. Format of Port Mode Register 14 (PM14) Address: FF2EH Symbol PM14 7 1 After reset: FFH 6 1 R/W 5 PM145 4 PM144 3 PM143 2 PM142 1 PM141 0 PM140 PM14n 0 1 P14n pin I/O mode selection (n = 0 to 5) Output mode (output buffer on) Input mode (output buffer off) www..com User's Manual U15947EJ2V0UD 389 CHAPTER 17 SERIAL INTERFACE CSIA0 17.4 Operation of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P142/SCKA0, P143/SIA0, and P144/SOA0 pins can be used as ordinary I/O port pins in this mode. (1) Register used The operation stop mode is set by serial operation mode specification register 0 (CSIMA0). To set the operation stop mode, clear bit 7 (CSIAE0) of CSIMA0 to 0. (a) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Address: FF90H <> CSIMA0 www..com After reset: 00H R/W <> <> RXEA0 DIR0 0 CSIAE0 ATE0 ATM0 MASTER0 TXEA0 CSIAE0 0 Control of CSIA0 operation enable/disable CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and asynchronously resets the internal circuit 390 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 17.4.2 3-wire serial I/O mode The one-byte data transmission/reception is executed in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is cleared to 0. The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: serial clock (SCKA0), serial output (SOA0), and serial input (SIA0) lines. (1) Registers used * Serial operation mode specification register 0 (CSIMA0)Note 1 * Serial status register 0 (CSIS0)Note 2 * Divisor selection register 0 (BRGCA0) * Port mode register 14 (PM14) * Port register 14 (P14) Notes 1. Bits 7, 6, and 4 to 1 (CSIAE0, ATE0, MASTER0, TXEA0, RXEA0, and DIR0) are used. Setting of bit 5 (ATM0) is invalid. 2. Only bit 0 (TSF0) is used. The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the BRGCA0 register (see Figure 17-6)Note 1. <2> Set bits 4 to 1 (MASTER0, TXEA0, RXEA0, and DIR0) of the CSIMA0 register (see Figure 17-3). www..com <3> Set bit 7 (CSIAE0) of the CSIMA0 register to 1 and clear bit 6 (ATE0) to 0. <4> Write data to serial I/O shift register 0 (SIOA0). Data transmission/reception is startedNote 2. Notes 1. This register does not have to be set when the slave mode is specified (MASTER0 = 0). 2. Write dummy data to SIOA0 only for reception. Caution Take relationship with the other party of communication when setting the port mode register and port register. User's Manual U15947EJ2V0UD 391 CHAPTER 17 SERIAL INTERFACE CSIA0 The relationship between the register settings and pins is shown below. Table 17-3. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 PM143 P143 PM144 P144 PM142 P142 Serial I/O Shift Register 0 Operation 0 x x xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 Operation stopped 1 0 0 1Note 2 xNote 2 0Note 3 0Note 3 1 x Operation enabled 1 0 1 Count operation SIA0Note 2 SOA0Note 3 SCKA0 (input) SCKA0 (output) Serial Clock Counter Operation Control Clear P143 P144 P142 SIA0/ P143 Pin Function SOA0/ P144 SCKA0/ P142 Notes 1. Can be set as port function. 2. Can be used as P143 when only transmission is performed. Clear bit 2 (RXEA0) of CSIMA0 to 0. 3. Can be used as P144 when only reception is performed. Clear bit 3 (TXEA0) of CSIMA0 to 0. Remark x: CSIAE0: ATE0: MASTER0: PM14x: P14x: don't care Bit 7 of serial operation mode specification register 0 (CSIMA0) Bit 6 of CSIMA0 Bit 4 of CSIMA0 Port mode register Port output latch www..com 392 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (2) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When bit 7 (CSIAE0) and bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1, 0, respectively, if communication data is written to serial I/O shift register 0 (SIOA0), the data is output via the SOA0 pin in synchronization with the SCKA0 falling edge, and then input via the SIA0 pin in synchronization with SCKA0 falling edge, and stored in the SIOA0 register in synchronization with the rising edge 1 clock later. Data transmission and data reception can be performed simultaneously. If only reception is to be performed, communication can only be started by writing a dummy value to the SIOA0 register. When communication of 1 byte is complete, an interrupt request signal (INTACSI) is generated. In 1-byte transmission/reception, the setting of bit 5 (ATM0) of CSIMA0 is invalid. Be sure to read data after confirming that bit 0 (TSF0) of serial status register 0 (CSIS0) = 0. Figure 17-10. 3-Wire Serial I/O Mode Timing SCKA0 1 2 3 4 5 6 7 8 SIA0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOA0 www..com DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 TSF0 ACSIIF Transfer starts at falling edge of SCKA0 SIOA0 write End of transfer Caution The SOA0 pin becomes low level by an SIOA0 write. User's Manual U15947EJ2V0UD 393 CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Data format In the data format, data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data communication direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-11. Format of Transmit/Receive Data (a) MSB-first (DIR0 bit = 0) SCKA0 SIA0 SOA0 DO7 DI7 DO6 DI6 DO5 DI5 DO4 DI4 DO3 DI3 DO2 DI2 DO1 DI1 DO0 DI0 (b) LSB-first (DIR0 bit = 1) SCKA0 SIA0 SOA0 DO0 DI0 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 DO6 DI6 DO7 DI7 www..com 394 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Switching MSB/LSB as start bit Figure 17-12 shows the configuration of serial I/O shift register 0 (SIOA0) and the internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. Switching MSB/LSB as the start bit can be specified using bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-12. Transfer Bit Order Switching Circuit 7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate SOA0 latch SIA0 Shift register 0 (SIOA0) D Q SOA0 www..com SCKA0 Start bit switching is realized by switching the bit order for data written to SIOA0. The SIOA0 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (d) Communication start Serial communication is started by setting communication data to serial I/O shift register 0 (SIOA0) when the following two conditions are satisfied. * Serial interface CSIA0 operation control bit (CSIAE0) = 1 * Serial communication is not in progress Caution If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start. Upon termination of 8-bit communication, serial communication automatically stops and the interrupt request flag (ACSIIF) is set. User's Manual U15947EJ2V0UD 395 CHAPTER 17 SERIAL INTERFACE CSIA0 17.4.3 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. After communication is started, only data of the set number of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and stored in RAM. In addition, to transmit/receive data continuously, handshake signals (STB0 and BUSY0) generated by hardware are supported. Therefore, connection to peripheral LSIs such as OSD (On Screen Display) LSIs and LCD controller/drivers can be easily realized. (1) Registers used * Serial operation mode specification register 0 (CSIMA0) * Serial status register 0 (CSIS0) * Serial trigger register 0 (CSIT0) * Divisor selection register 0 (BRGCA0) * Automatic data transfer address point specification register 0 (ADTP0) * Automatic data transfer interval specification register 0 (ADTI0) * Port mode register 14 (PM14) * Port register 14 (P14) The relationship between the register settings and pins is shown below. www..com 396 User's Manual U15947EJ2V0UD Table 17-4. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 STBE0 BUSYE0 ERRE0 PM143 P143 PM144 P144 PM142 P142 PM145 P145 PM141 P141 Serial I/O Shift Register 0 Operation Pin Function Serial Clock Counter SIA0/ SOA10/ SCKA0/ STB0/ BUSY0/ Operation Control P143 P144 P142 P145 P141 P143 SIA0 Note 2 www..com 0 1 x 1 x 0 1 x x Note 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 Operation stopped Clear x Note 1 P144 P142 P145 P141 P141 0/1 0/1 0/1 1 x 0 0 1 0 x 1 x Note 1 x Note 1 x Note 1 x Note 1 Operation enabled Count operation SOA10 SCKA0 P145 (input) 0 1 0 1 xNote 1 xNote 1 xNote 1 xNote 1 0 0 1 x SCKA0 P145 P141 (output) STB0 BUSY0 Notes 1. 2. Remark User's Manual U15947EJ2V0UD Can be set as port function. CHAPTER 17 SERIAL INTERFACE CSIA0 Can be used as P143 when only transmission is performed. Clear bit 2 (RXEA0) of CSIMA0 to 0. x: CSIAE0: ATE0: STBE0: BUSYE0: ERRE0: PM14x: P14x: don't care Bit 7 of serial operation mode specification register 0 (CSIMA0) Bit 6 of CSIMA0 Bit 5 of serial status register 0 (CSIS0) Bit 4 of CSIS0 Bit 2 of CSIS0 Port mode register Port output latch MASTER0: Bit 4 of CSIMA0 397 CHAPTER 17 SERIAL INTERFACE CSIA0 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FA00H of buffer RAM (up to FA1FH at maximum). The transmit data should be in the order from lower address to higher address. <2> Set the automatic data transfer address point specification register 0 (ADTP0) to the value obtained by subtracting 1 from the number of transmit data bytes. (b) Setting example of automatic transmission/reception mode <1> Set bit 7 (CSIAE0) and bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) to 1. <2> Set bit 2 (RXEA0) and bit 3 (TXEA0) of CSIMA0 to 1. <3> Set a data transfer interval in automatic data transfer interval specification register 0 (ADTI0). <4> Set bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1. Caution Take relationship with the other party of communication when setting the port mode register and port register. The following operations are automatically carried out when (a) and (b) are carried out. * After the buffer RAM data indicated by automatic data transfer address count register 0 (ADTC0) is transferred to SIOA0, transmission is carried out (start of automatic transmission/reception). * The received data is written to the buffer RAM address indicated by ADTC0. * ADTC0 is incremented and the next data transmission/reception is carried out. www..com Data transmission/reception continues until the ADTC0 incremental output matches the set value of automatic data transfer address point specification register 0 (ADTP0) (end of automatic transmission/reception). However, if bit 5 (ATM0) of CSIMA0 is set to 1 (repeat mode), ADTC0 is cleared after a match between ADTP0 and ADTC0, and then repeated transmission/reception is started. * When automatic transmission/reception is terminated, TSF0 is cleared to 0. (3) Automatic transmission/reception communication operation (a) Automatic transmission/reception mode Automatic transmission/reception can be performed using buffer RAM. The data stored in the buffer RAM is output from the SOA0 pin via the SIOA0 register in synchronization with the SCKA0 falling edge by performing (a) and (b) in (2) Automatic transmit/receive data setting. The data is then input from the SIA0 pin via the SIOA0 register in synchronization with the SCKA0 falling edge and the receive data is stored in the buffer RAM in synchronization with the rising edge 1 clock later. Data transfer ends if bit 0 (TSF0) of serial status register 0 (CSIS0) is set to 1 when any of the following conditions is met. * Reset by clearing bit 7 (CSIAE0) of the CSIMA0 register to 0 * Transfer of 1 byte is complete by setting bit 1 (ATSTP0) of the CSIT0 register to 1 * Transfer of 1 byte is complete when bit 1 (ERRF0) of the CSIS0 register becomes 1 while bit 2 (ERRE0) = 1 * Transfer of the range specified by the ADTP0 register is complete 398 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 At this time, an interrupt request signal (INTACSI) is generated except when the CSIAE0 bit = 0. If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read automatic data transfer address count register 0 (ADTC0) to confirm how much of the data has already been transferred and re-execute transfer by performing (a) and (b) in (2) Automatic transmit/receive data setting. In addition, when busy control and strobe control are not performed, the BUSY0/BUZ/INTP7/P141 and STB0/P145 pins can be used as ordinary I/O port pins. Figure 17-13 shows the operation timing in automatic transmission/reception mode and Figure 17-14 shows the operation flowchart. Figure 17-15 shows the operation of internal buffer RAM when 6 bytes of data are transmitted/received. Figure 17-13. Automatic Transmission/Reception Mode Operation Timings Interval SCKA0 SOA0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF TSF0 www..com Cautions 1. Because, byte in the automatic transmission/reception an interval is mode, the until automatic the next transmit/receive function writes/reads data to/from the internal buffer RAM after 1transmission/reception, inserted transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Remark ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) Automatic User's Manual U15947EJ2V0UD 399 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-14. Automatic Transmission/Reception Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the automatic transmission/reception mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Transmission/reception operation Increment pointer value Hardware execution www..com Write receive data from SIOA0 to internal buffer RAM ADTP0 = ADTC0 No Yes TSF0 = 0 No Software execution Yes End ADTP0: ADTI0: ATSTA0: SIOA0: ADTC0: TSF0: Automatic data transfer address point specification register 0 Automatic data transfer interval specification register 0 Bit 0 of serial trigger register 0 (CSIT0) Serial I/O shift register 0 Automatic data transfer address count register 0 Bit 0 of serial status register 0 (CSIS0) 400 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission/reception (ATM0 = 0, RXEA0 = 1, TXEA0 = 1) in automatic transmission/reception mode, internal buffer RAM operates as follows. (i) Starting transmission/reception (see Figure 17-15 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0. When transmission of the first byte is completed, receive data 1 (R1) is transferred from SIOA0 to the buffer RAM, and automatic data transfer address count register 0 (ADTC0) is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIOA0. (ii) 4th byte transmission/reception point (see Figure 17-15 (b).) Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the internal buffer RAM to SIOA0. When transmission of the fourth byte is completed, the receive data 4 (R4) is transferred from SIOA0 to the internal buffer RAM, and ADTC0 is incremented. (iii) Completion of transmission/reception (see Figure 17-15 (c).) When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIOA0 to the internal buffer RAM, and the interrupt request flag (ACSIIF) is set (INTACSI generation). Bit 0 (TSF0) of serial status register 0 (CSIS0) is cleared. Figure 17-15. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (1/2) (a) Starting transmission/reception www..com FA1FH FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 Receive data 1 (R1) SIOA0 5 ADTP0 0 ADTC0 FA00H Transmit data 1 (T1) 0 ACSIIF User's Manual U15947EJ2V0UD 401 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-15. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (2/2) (b) 4th byte transmission/reception FA1FH FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Receive data 3 (R3) Receive data 2 (R2) +1 Receive data 4 (R4) SIOA0 5 ADTP0 3 ADTC0 FA00H Receive data 1 (R1) 0 ACSIIF (c) Completion of transmission/reception FA1FH FA05H www..com Receive data 6 (R6) Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) Receive data 2 (R2) 5 SIOA0 ADTP0 5 ADTC0 FA00H Receive data 1 (R1) 1 ACSIIF 402 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Automatic transmission mode In this mode, the specified number of 8-bit unit data is transmitted. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1. When the final byte has been transmitted, an interrupt request flag (ACSIIF) is set. The termination of automatic transmission and reception can also be judged by bit 0 (TSF0) of serial status register 0 (CSIS0). If a receive operation, busy control and strobe control are not executed, the SIA0/P143, BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as normal I/O port pins. Figure 17-16 shows the automatic transmission mode operation timing, and Figure 17-17 shows the operation flowchart. Figure 17-18 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted. Figure 17-16. Automatic Transmission Mode Operation Timing Interval SCKA0 SOA0 ACSIIF TSF0 www..com D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Cautions 1. Because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Remark ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) User's Manual U15947EJ2V0UD 403 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-17. Automatic Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the automatic transmission mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Increment pointer value Transmission operation Hardware execution www..com ADTP0 = ADTC0 No Yes TSF0 = 0 No Software execution Yes End ADTP0: ADTI0: ATSTA0: SIOA0: ADTC0: TSF0: Automatic data transfer address point specification register 0 Automatic data transfer interval specification register 0 Bit 0 of serial trigger register 0 (CSIT0) Serial I/O shift register 0 Automatic data transfer address count register 0 Bit 0 of serial status register 0 (CSIS0) 404 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission (ATM0 = 0, RXEA0 = 0, TXEA0 = 1, ATE0 = 1) in automatic transmission mode, internal buffer RAM operates as follows. (i) Starting transmission (see Figure 17-18 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0. When transmission of the first byte is completed, automatic data transfer address count register 0 (ADTC0) is incremented. transferred from the internal buffer RAM to SIOA0. (ii) 4th byte transmission point (see Figure 17-18 (b).) Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the internal buffer RAM to SIOA0. When transmission of the fourth byte is completed, ADTC0 is incremented. (iii) Completion of transmission (see Figure 17-18 (c).) When transmission of the sixth byte is completed, the interrupt request flag (ACSIIF) is set (INTACSI generation). Bit 0 (TSF0) of serial status register 0 (CSIS0) is cleared. Figure 17-18. Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (1/2) (a) Starting transmission Then transmit data 2 (T2) is FA1FH www..com FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5 SIOA0 ADTP0 0 ADTC0 FA00H Transmit data 1 (T1) 0 ACSIIF User's Manual U15947EJ2V0UD 405 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-18. Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (2/2) (b) 4th byte transmission point FA1FH FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5 SIOA0 ADTP0 3 ADTC0 FA00H Transmit data 1 (T1) 0 ACSIIF (c) Completion of transmission FA1FH FA05H www..com Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) 5 SIOA0 ADTP0 5 ADTC0 FA00H Transmit data 1 (T1) 1 ACSIIF 406 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), bit 5 (ATM0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1. Unlike the basic transmission mode, after the number of setting bytes has been transmitted, the interrupt request flag (ACSIIF) is not set, automatic data transfer address count register 0 (ADTC0) is reset to 0, and the internal buffer RAM contents are transmitted again. When a reception operation, busy control and strobe control are not performed, the SIA0/P143, BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as ordinary I/O port pins. The repeat transmission mode operation timing is shown in Figure 17-19, and the operation flowchart in Figure 17-20. Figure 17-21 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode. Figure 17-19. Repeat Transmission Mode Operation Timing Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Interval Cautions 1. Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the www..com next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. User's Manual U15947EJ2V0UD 407 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-20. Repeat Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (point value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the repeat transmission mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Increment pointer value Transmission operation Hardware execution www..com ADTP0 = ADTC0 No Yes Reset ADTC0 to 0 ADTP0: ADTI0: ATSTA0: SIOA0: ADTC0: Automatic data transfer address point specification register 0 Automatic data transfer interval specification register 0 Bit 0 of serial trigger register 0 (CSIT0) Serial I/O shift register 0 Automatic data transfer address count register 0 408 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission (ATM0 = 1, RXEA0 = 0, TXEA0 = 1, ATE0 = 1) in repeat transmission mode, internal buffer RAM operates as follows. (i) Starting transmission (see Figure 17-21 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0. When transmission of the first byte is completed, automatic data transfer address count register 0 (ADTC0) is incremented. transferred from the internal buffer RAM to SIOA0. (ii) Upon completion of transmission of 6 bytes (see Figure 17-21 (b).) When transmission of the sixth byte is completed, the interrupt request flag (ACSIIF) is not set. ADTC0 is reset to 0. (iii) 7th byte transmission point (see Figure 17-21 (c).) Transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0 again. When transmission of the first byte is completed, ADTC0 is incremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIOA0. Figure 17-21. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (1/2) (a) Starting transmission Then transmit data 2 (T2) is www..com FA1FH FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5 SIOA0 ADTP0 0 ADTC0 FA00H Transmit data 1 (T1) 0 ACSIIF User's Manual U15947EJ2V0UD 409 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-21. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (2/2) (b) Upon completion of transmission of 6 bytes FA1FH FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) 5 SIOA0 ADTP0 5 ADTC0 FA00H Transmit data 1 (T1) 0 ACSIIF (c) 7th byte transmission point FA1FH FA05H www..com Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5 SIOA0 ADTP0 0 ADTC0 FA00H Transmit data 1 (T1) 0 ACSIIF 410 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (d) Data format In the data format, data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-22. Format of CSIA0 Transmit/Receive Data (a) MSB-first (DIR0 bit = 0) SCKA0 SIA0 SOA0 DO7 DI7 DO6 DI6 DO5 DI5 DO4 DI4 DO3 DI3 DO2 DI2 DO1 DI1 DO0 DI0 (b) LSB-first (DIR0 bit = 1) SCKA0 SIA0 SOA0 DO0 DI0 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 DO6 DI6 DO7 DI7 www..com User's Manual U15947EJ2V0UD 411 CHAPTER 17 SERIAL INTERFACE CSIA0 (e) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1. During 8-bit data communication, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data communication. When suspended, bit 0 (TSF0) of serial status register 0 (CSIS0) is cleared to 0 after transfer of the 8th bit. Cautions 1. If the HALT instruction is executed during automatic transmission/reception, communication is suspended and the HALT mode is set if during 8-bit data communication. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while TSF0 = 1. Figure 17-23. Automatic Transmission/Reception Suspension and Restart ATSTP0 = 1 (Suspend command) Suspend Restart command ATSTA0 = 1 SCKA0 SOA0 SIA0 www..com D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ATSTP0: Bit 1 of serial trigger register 0 (CSIT0) ATSTA0: Bit 0 of CSIT0 412 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (4) Synchronization control Busy control and strobe control are functions used to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. When using this busy control option, the following conditions must be satisfied. * Bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. * Bit 4 (BUSYE0) of serial status register 0 (CSIS0) is set to 1. Figure 17-24 shows the system configuration of the master device and slave device when the busy control option is used. Figure 17-24. System Configuration When Busy Control Option Is Used Master device (78K0/KF1) SCKA0 SOA0 SIA0 www..com Slave device SCKA SIA SOA Busy output BUSY0 The master device inputs the busy signal output by the slave device to the BUSY0/BUZ/INTP7/P141 pin. The master device samples the input busy signal in synchronization with the falling of the serial clock. Even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. If the busy signal is active at the rising edge of the serial clock one clock after completion of transmission/reception of the 8-bit data, the busy input becomes valid. After that, the master transmission/reception is kept waiting while the busy signal is active. The active level of the busy signal is set by bit 3 (BUSYLV0) of CSIS0. BUSYLV0 = 1: Active-high BUSYLV0 = 0: Active-low When using the busy control option, select the internal clock as the serial clock. Control with the busy signal cannot be implemented with the external clock. Figure 17-25 shows the operation timing when the busy control option is used. Caution Busy control cannot be used simultaneously with the interval time control function of automatic data transfer interval specification register 0 (ADTI0). User's Manual U15947EJ2V0UD 413 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-25. Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 Wait ACSIIF Busy input released Busy input valid TSF0 Remark ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock. www..com Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the busy signal was sampled. To accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5 clock. Figure 17-26 shows the timing of the busy signal and releasing the waiting. This figure shows an example in which the busy signal is active as soon as transmission/reception has been started. Figure 17-26. Busy Signal and Wait Release (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 (active-high) 1.5 clocks (min.) If made inactive immediately after sampled Wait Busy input released Busy input valid 414 User's Manual U15947EJ2V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Busy & strobe control option Strobe control is a function used to synchronize data transmission/reception between the master and slave devices. The master device outputs the strobe signal from the STB0/P145 pin when 8-bit transmission/reception has been completed. By this signal, the slave device can determine the timing of the end of data transmission. Therefore, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift. To use the strobe control option, the following conditions must be satisfied: * Bit 6 (ATE0) of the serial operation mode specification register 0 (CSIMA0) is set to 1. * Bit 5 (STBE0) of serial status register 0 (CSIS0) is set to 1. Usually, the busy control and strobe control options are simultaneously used as handshake signals. In this case, the strobe signal is output from the STB0/P145 pin, the BUSY0/BUZ/INTP7/P141 pin can be sampled to keep transmission/reception waiting while the busy signal is input. A high level lasting for one transfer clock is output from the STB0/P145 pin in synchronization with the falling edge of the ninth serial clock as the strobe signal. The busy signal is detected at the rising edge of the serial clock two clocks after 8-bit data transmission/reception completion. When the strobe control option is not used, the P145/STB0 pin can be used as a normal I/O port pin. Figure 17-27 shows the operation timing when the busy & strobe control options are used. When the strobe control option is used, the interrupt request flag (ACSIIF) that is set on completion of transmission/reception is set after the strobe signal is output. Figure 17-27. Operation Timing When Busy & Strobe Control Options Are Used (When BUSYLV0 = 1) www..com SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB0 BUSY0 ACSIIF Busy input released Busy input valid TSF0 Caution Remark When TSF0 is cleared, the SOA0 pin goes low. ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) User's Manual U15947EJ2V0UD 415 CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. In this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. A bit shift is detected by using the busy signal as follows: The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). The master samples the busy signal in synchronization with the falling edge of the serial clock if bit 2 (ERRE0) of serial status register 0 (CSIS0) is set to 1. If a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. If the sampled serial clocks are active, it is assumed that a bit shift has occurred, error processing is executed (by setting bit 1 (ERRF0) of serial status register 0 (CSIS0) to 1, and communication is suspended and an interrupt request signal (INTACSI) is output). Although communication is suspended after completion of 1-byte data communication, slave signal output, wait due to the busy signal, and wait due to the interval time specified by ADTI0 are not executed. If ERRE0 = 0, ERRF0 cannot become 1 even if a bit shift occurs. Figure 17-28 shows the operation timing of the bit shift detection function by the busy signal. Remark The bit error function is valid both in the master mode and slave mode. The setting of ERRE0 is valid even when BUSYE0 = 0. Figure 17-28. Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 0) www..com SCKA0 (Master) Bit shift due to noise SCKA0 (Slave) SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 ACSIIF CSIAE0 ERRF0 Busy not detected Error interrupt request generated Error detected ACSIIF: ERRF0: Interrupt request flag Bit 1 of serial status register 0 (CSIS0) User's Manual U15947EJ2V0UD CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) 416 CHAPTER 17 SERIAL INTERFACE CSIA0 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. transmit/receive operation. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in automatic data transfer interval specification register 0 (ADTI0) and bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0). When ADTI0 is cleared to 00H, an interval time based on the to STBE0 and BUSYE0 settings is generated. For example, when ADTI0 = 00H and STBE0 = BUSYE0 = 1, an interval time of two clocks is generated. If an interval time of two clocks or more is set by ADTI0, the interval time set by ADTI0 is generated regardless of the STBE0 and BUSYE0 settings. Example Interval time when busy signal is not generated <1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated <2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated <3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated Figure 17-29. Automatic Transmit/Receive Interval Time Interval SCKA0 SOA0 www..com Therefore, an interval is inserted before the next D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 ACSIIF ACSIIF: Interrupt request flag User's Manual U15947EJ2V0UD 417 CHAPTER 18 MULTIPLIER/DIVIDER 18.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. * 16 bits x 16 bits = 32 bits (multiplication) * 32 bits / 16 bits = 32 bits, 16-bit remainder (division) 18.2 Configuration of Multiplier/Divider The multiplier/divider consists of the following hardware. Table 18-1. Configuration of Multiplier/Divider Item Registers Configuration Remainder data register 0 (SDR0) Multiplication/division data registers A0 (MDA0H, MDA0L) Multiplication/division data registers B0 (MDB0) Control register Multiplier/divider control register 0 (DMUC0) Figure 18-1 shows the block diagram of the multiplier/divider. www..com 418 User's Manual U15947EJ2V0UD Figure 18-1. Block Diagram of Multiplier/Divider Internal bus Multiplication/division data register B0 (MDB0 (MDB0H+MDB0L) Multiplication/division data register A0 Remainder data register 0 (SDR0 (SDR0H+SDR0L) (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL)) MDA000 www..com Multiplier/divider control register 0 (DMUC0) DMUSEL0 DMUE Start INTDMU Clear Controller User's Manual U15947EJ2V0UD Controller 6-bit counter CPU clock CHAPTER 18 MULTIPLIER/DIVIDER 17-bit adder Controller 419 CHAPTER 18 MULTIPLIER/DIVIDER (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. This register can be read by an 8-bit or 16-bit memory manipulation instruction. RESET input clears this register to 0000H. Figure 18-2. Format of Remainder Data Register 0 (SDR0) Address: FF60H, FF61H Symbol After reset: 0000H FF61H (SDR0H) R FF60H (SDR0L) SDR0 SDR 015 SDR 014 SDR 013 SDR 012 SDR 011 SDR 010 SDR 009 SDR 008 SDR 007 SDR 006 SDR 005 SDR 004 SDR 003 SDR 002 SDR 001 SDR 000 Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. 2. SDR0 is reset when the operation is started (when DMUE is set to 1). www..com 420 User's Manual U15947EJ2V0UD CHAPTER 18 MULTIPLIER/DIVIDER (2) Multiplication/division data register A0 (MDA0H, MDA0L) MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L). Figure 18-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L) Address: FF62H, FF63H, FF64H, FF65H Symbol After reset: 0000H, 0000H R/W FF64H (MDA0HL) FF65H (MDA0HH) MDA0H MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 031 030 029 028 027 026 025 024 023 022 021 020 019 018 017 016 Symbol FF63H (MDA0LH) FF62H (MDA0LL) MDA0L MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (DMUC0) is set to 81H). 2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of www..com multiplier/divider control register 0 (DMUC0) is 1). executed, but the result is undefined. Even in this case, the operation is 3. The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed. User's Manual U15947EJ2V0UD 421 CHAPTER 18 MULTIPLIER/DIVIDER The functions of MDA0 when an operation is executed are shown in the table below. Table 18-2. Functions of MDA0 During Operation Execution DMUSEL0 0 1 Operation Mode Division mode Multiplication mode Dividend Higher 16 bits: 0, Lower 16 bits: Multiplier A Setting Operation Result Division result (quotient) Multiplication result (product) The register configuration differs between when multiplication is executed and when division is executed, as follows. * Register configuration during multiplication www..com (3) Multiplication/division data register B0 (MDB0) MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the division mode. This register can be set by an 8-bit or 16-bit memory manipulation instruction. RESET input clears this register to 0000H. Figure 18-4. Format of Multiplication/Division Data Register B0 (MDB0) Address: FF66H, FF67H Symbol After reset: 0000H FF67H (MDB0H) R/W FF66H (MDB0L) MDB0 MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). executed, but the result is undefined. 2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored in MDA0 and SDR0. Even in this case, the operation is 422 User's Manual U15947EJ2V0UD CHAPTER 18 MULTIPLIER/DIVIDER 18.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 18-5. Format of Multiplier/Divider Control Register 0 (DMUC0) Address: FF68H Symbol DMUC0 After reset: 00H <7> DMUE DMUENote 0 1 DMUSEL0 0 1 Division mode Multiplication mode Stops operation Starts operation Operation mode (multiplication/division) selection 6 0 R/W 5 0 4 0 3 0 Operation start/stop 2 0 1 0 0 DMUSEL0 www..com Note When DMUE is set to 1, the operation is started. DMUE is automatically cleared to 0 after the operation is complete. Cautions 1. If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result is not guaranteed. If the operation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. Do not change the value of DMUSEL0 during operation processing (while DMUE is 1). If it is changed, undefined operation results are stored in multiplication/division data register A0 (MDA0) and remainder data register 0 (SDR0). 3. If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation processing is stopped. To execute the operation again, set multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the operation (by setting DMUE to 1). User's Manual U15947EJ2V0UD 423 CHAPTER 18 MULTIPLIER/DIVIDER 18.4 Operations of Multiplier/Divider 18.4.1 Multiplication operation * Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. * During operation 3. The operation will be completed when 16 internal clocks have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The operation result data is stored in the MDA0L and MDA0H registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 18.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 18.4.2 Division operation. www..com 424 User's Manual U15947EJ2V0UD Figure 18-6. Timing Chart of Multiplication Operation (00DAH x 0093H) www..com Operation clock DMUE DMUSEL0 Internal clock Counter SDR0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 0 CHAPTER 18 MULTIPLIER/DIVIDER XXXX XXXX XXXX XXXX 00DA 0000 0000 00DA 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0049 0024 005B 0077 003B 0067 007D 003E 001F 000F 0007 0003 0001 0000 0000 006D 8036 C01B E00D 7006 B803 5C01 2E00 9700 4B80 A5C0 D2E0 E970 F4B8 FA5C 7D2E User's Manual U15947EJ2V0UD MDA0 MDB0 XXXX 0093 INTDMU 425 CHAPTER 18 MULTIPLIER/DIVIDER 18.4.2 Division operation * Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start. * During operation 3. The operation will be completed when 32 internal clocks have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 (SDR0) during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The result data is stored in the MDA0L, MDA0H, and SDR0 registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 18.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 18.4.2 Division operation. www..com 426 User's Manual U15947EJ2V0UD Figure 18-7. Timing Chart of Division Operation (DCBA2586H / 0018H) www..com Operation clock DMUE DMUSEL0 "0" Internal clock Counter SDR0 User's Manual U15947EJ2V0UD 0 1 2 3 4 5 6 7 8 19 1A 1B 1C 1D 1E 1F 20 0 CHAPTER 18 MULTIPLIER/DIVIDER XXXX XXXX XXXX DCBA 2586 0000 0001 0003 0006 000D 0003 0007 000E 0004 B974 72E8 E5D1 CBA2 A744 2E89 6D12 BA25 4B0C A618 2C30 6860 BAC1 6182 C304 8609 000B 0016 0014 0010 0008 0011 000B 0016 0C12 1824 3049 6093 C126 824C 0499 0932 64D8 C9B0 9361 26C3 4D87 9B0E 361D 6C3A MDA0 MDB0 XXXX 0018 INTDMU 427 CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupts with the same priority are generated simultaneously, each interrupt is serviced according to its predetermined priority (see Table 19-1). A standby release signal is generated and STOP and HALT modes are released. Nine external interrupt requests and 20 (17 in the PD780143 and 780144) internal interrupt requests are provided as maskable interrupts. (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control. 19.2 Interrupt Sources and Configuration A total of 30 (27 in the PD780143 and 780144) interrupt sources exist for maskable and software interrupts (see www..com Table 19-1). 428 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (1/2) Interrupt Type Default Priority Note 1 Interrupt Source Name INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10/ INTST0 UART6 reception error generation End of UART6 reception End of UART6 transmission End of CSI10 communication/end of UART0 transmission Match between TMH1 and CRH1 (when compare register is specified) Trigger Low-voltage detection Note 3 Internal/ External Vector Table Address Basic Configuration Type Note 2 Maskable 0 1 2 3 4 5 6 7 8 9 10 Internal External 0004H 0006H 0008H 000AH 000CH 000EH 0010H (A) (B) Pin input edge detection Internal 0012H 0014H 0016H 0018H (A) 11 INTTMH1 001AH 12 INTTMH0 Match between TMH0 and CRH0 (when compare register is specified) 001CH 13 INTTM50 Match between TM50 and CR50 (when compare register is specified) 001EH www..com 14 INTTM000 Match between TM00 and CR000 (when compare register is specified), TI010 pin valid edge detection (when capture register is specified) 0020H 15 INTTM010 Match between TM00 and CR010 (when compare register is specified), TI000 pin valid edge detection (when capture register is specified) 0022H 16 17 INTAD INTSR0 End of A/D conversion End of UART0 reception or reception error generation 0024H 0026H 18 19 INTWTI INTTM51 Watch timer reference time interval signal Match between TM51 and CR51 (when compare register is specified) 0028H 002AH Notes 1. 2. 3. The default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 28 is the lowest. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 0. User's Manual U15947EJ2V0UD 429 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (2/2) Interrupt Type Default Priority Note 1 Interrupt Source Name INTKR INTWT INTP6 INTP7 INTDMU INTCSI11 Note 3 Internal/ External Vector Table Address Basic Configuration Type Note 2 Trigger Key interrupt detection Watch timer overflow Pin input edge detection Maskable 20 21 22 23 24 25 26 External Internal External 002CH 002EH 0030H 0032H (C) (A) (B) End of multiply/divide operation End of CSI11 communication Match between TM01 and CR001 (when compare register is specified), TI011 pin valid edge detection (when capture register is specified) Note 3 Internal 0034H 0036H 0038H (A) INTTM001 Note 3 27 INTTM011 Match between TM01 and CR011 (when compare register is specified), TI001 pin valid edge detection (when capture register is specified) 003AH 28 Software Reset - - INTACSI BRK RESET POC LVI End of CSIA0 communication BRK instruction execution Reset input Power-on-clear Note 4 003CH - - 003EH 0000H (D) - Low-voltage detection Note 5 www..com Clock monitor X1 oscillation stop detection WDT WDT overflow Notes 1. 2. 3. 4. 5. The default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 28 is the lowest. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1. The interrupt sources INTCSI11, INTTM001, and INTTM011 are available only in the PD780146, 780148, and 78F0148. When "POC used" is selected by a mask option. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1. 430 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus MK IE PR ISP Interrupt request IF Priority controller Vector table address generator Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) MK IE PR ISP www..com Interrupt request Edge detector IF Priority controller Vector table address generator Standby release signal IF: IE: ISP: MK: PR: Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag User's Manual U15947EJ2V0UD 431 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus MK IE PR ISP Interrupt request Key interrupt detector IF Priority controller Vector table address generator 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus www..com Interrupt request Priority controller Vector table address generator IF: IE: ISP: MK: PR: Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag KRM: Key return mode register 19.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) * Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) * Priority specification flag register (PR0L, PR0H, PR1L, PR1H) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) * Program status word (PSW) Table 19-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. 432 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS Table 19-2. Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Register INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10 INTST0 INTTMH1 INTTMH0 INTTM50 INTTM000 www..com Interrupt Mask Flag Register LVIMK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 SREMK6 MK0L Priority Specification Flag Register LVIPR PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 SREPR6 PR0L LVIIF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 SREIF6 SRIF6 STIF6 DUALIF0 Note 1 IF0L IF0H SRMK6 STMK6 DUALMK0 Note 2 MK0H SRPR6 STPR6 DUALPR0 Note 2 PR0H TMIFH1 TMIFH0 TMIF50 TMIF000 TMIF010 ADIF SRIF0 WTIIF TMIF51 KRIF WTIF PIF6 PIF7 DMUIF Note 3 TMMKH1 TMMKH0 TMMK50 TMMK000 TMMK010 IF1L ADMK SRMK0 WTIMK TMMK51 KRMK WTMK PMK6 PMK7 IF1H Note 3 TMPRH1 TMPRH0 TMPR50 TMPR000 TMPR010 MK1L ADPR SRPR0 WTIPR TMPR51 KRPR WTPR PPR6 PPR7 MK1H Note 3 INTTM010 INTAD INTSR0 INTWTI INTTM51 INTKR INTWT INTP6 INTP7 INTDMU INTCSI11 PR1L DMUMK CSIMK11 DMUPR CSIPR11 Note 3 PR1H CSIIF11 INTTM001 INTTM011 INTACSI Note 3 TMIF001 TMIF011 ACSIIF Note 3 TMMK001 TMMK011 ACSIMK Note 3 TMPR001 TMPR011 ACSIPR Note 3 Note 3 Note 3 Note 3 Note 3 Notes 1. 2. 3. If either of the two types of interrupt sources is generated, these flags are set (1). Both types of interrupt sources are supported. PD780146, 780148, and 78F0148 only. User's Manual U15947EJ2V0UD 433 CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 19-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> SREIF6 <6> PIF5 <5> PIF4 <4> PIF3 <3> PIF2 <2> PIF1 <1> PIF0 <0> LVIIF Address: FFE1H Symbol IF0H After reset: 00H <7> <6> TMIF000 R/W <5> TMIF50 <4> TMIFH0 <3> TMIFH1 <2> DUALIF0 <1> STIF6 <0> SRIF6 TMIF010 Address: FFE2H Symbol www..com After reset: 00H <7> PIF7 <6> PIF6 R/W <5> WTIF <4> KRIF <3> TMIF51 <2> WTIIF <1> SRIF0 <0> ADIF IF1L Address: FFE3H Symbol IF1H 0 After reset: 00H 7 Note 1 R/W 5 0 Note 1 6 0 Note 1 <4> ACSIIF <3> TMIF011 Note 2 <2> TMIF001 Note2 <1> CSIIF11 Note 2 <0> DMUIF XXIFX 0 1 Interrupt request flag No interrupt request signal is generated Interrupt request is generated, interrupt request status Notes 1. 2. Be sure to clear bits 5 to 7 of IF1H to 0. PD780146, 780148, and 78F0148 only. Be sure to clear these bits to 0 in the PD780143 and 780144. Cautions 1. When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. 2. If an interrupt request corresponding to a flag of the interrupt request flag register is generated while the interrupt request flag register is being manipulated (including by 1-bit memory manipulation), the flag corresponding to the interrupt request may not be set to 1. 434 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction. RESET input sets MK0L, MK0H, and MK1L to FFH and MK1H to DFH. Figure 19-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) Address: FFE4H Symbol MK0L After reset: FFH <7> SREMK6 <6> PMK5 R/W <5> PMK4 <4> PMK3 <3> PMK2 <2> PMK1 <1> PMK0 <0> LVIMK Address: FFE5H Symbol MK0H After reset: FFH <7> <6> TMMK000 R/W <5> TMMK50 <4> TMMKH0 <3> TMMKH1 <2> DUALMK0 <1> STMK6 <0> SRMK6 TMMK010 Address: FFE6H Symbol MK1L After reset: FFH <7> PMK7 <6> PMK6 R/W <5> WTMK <4> KRMK <3> TMMK51 <2> WTIMK <1> SRMK0 <0> ADMK Address: FFE7H Symbol www..com After reset: DFH 7 1 Note 1 R/W 5 0 Note 1 6 1 Note 1 <4> ACSIMK <3> TMMK011 Note 2 <2> TMMK001 Note2 <1> CSIMK11 Note 2 <0> DMUMK MK1H XXMKX 0 1 Interrupt servicing enabled Interrupt servicing disabled Interrupt servicing control Notes 1. 2. Be sure to set bits 6 and 7 of MK1H to 1 and clear bit 5 to 0. PD780146, 780148, and 78F0148 only. Be sure to set these bits to 1 in the PD780143 and 780144. User's Manual U15947EJ2V0UD 435 CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 19-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) Address: FFE8H Symbol PR0L After reset: FFH <7> SREPR6 <6> PPR5 R/W <5> PPR4 <4> PPR3 <3> PPR2 <2> PPR1 <1> PPR0 <0> LVIPR Address: FFE9H Symbol PR0H After reset: FFH <7> <6> TMPR000 R/W <5> TMPR50 <4> TMPRH0 <3> TMPRH1 <2> DUALPRO <1> STPR6 <0> SRPR6 TMPR010 Address: FFEAH Symbol PR1L After reset: FFH <7> <6> PPR6 R/W <5> WTPR <4> KRPR <3> TMPR51 <2> WTIPR <1> SRPR0 <0> ADPR PPR7 Address: FFEBH Symbol www..com After reset: FFH 7 1 Note 1 R/W 5 1 Note 1 6 1 Note 1 <4> ACSIPR <3> TMPR011 Note 2 <2> TMPR001 Note2 <1> CSIPR11 Note 2 <0> DMUPR PR1H XXPRX 0 1 High priority level Low priority level Priority level selection Notes 1. 2. Be sure to set bits 5 to 7 of PR1H to 1. PD780146, 780148, and 78F0148 only. Be sure to set these bits to 1 in the PD780143 and 780144. 436 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 19-5. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) Address: FF48H Symbol EGP After reset: 00H 7 EGP7 6 EPG6 R/W 5 EGP5 4 EGP4 3 EGP3 2 EGP2 1 EGP1 0 EGP0 Address: FF49H Symbol EGN After reset: 00H 7 EGN7 6 EGN6 R/W 5 EGN5 4 EGN4 3 EGN3 2 EGN2 1 EGN1 0 EGN0 EGPn 0 0 1 1 EGNn 0 1 0 1 INTPn pin valid edge selection (n = 0 to 7) Edge detection disabled Falling edge Rising edge Both rising and falling edges www..com Table 19-3 shows the ports corresponding to EGPn and EGNn. Table 19-3. Ports Corresponding to EGPn and EGNn Detection Enable Register EGP0 EGP1 EGP2 EGP3 EGP4 EGP5 EGP6 EGP7 EGN0 EGN1 EGN2 EGN3 EGN4 EGN5 EGN6 EGN7 P120 P30 P31 P32 P33 P16 P140 P141 Edge Detection Port Interrupt Request Signal INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when the external interrupt function is switched to the port function. Remark n = 0 to 7 User's Manual U15947EJ2V0UD 437 CHAPTER 19 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets PSW to 02H. Figure 19-6. Format of Program Status Word <7> PSW IE <6> Z <5> RBS1 <4> AC <3> RBS0 2 0 <1> ISP 0 CY After reset 02H Used when normal instruction is executed ISP 0 Priority of interrupt currently being serviced High-priority interrupt servicing (low-priority interrupt disabled) Interrupt request not acknowledged, or lowpriority interrupt servicing (all maskable interrupts enabled) 1 www..com IE 0 1 Interrupt request acknowledgment enable/disable Disabled Enabled 438 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Maskable interrupt request acknowledgement A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 19-4 below. For the interrupt request acknowledgment timing, see Figures 19-8 and 19-9. Table 19-4. Time from Generation of Maskable Interrupt Request Until Servicing Minimum Time When xxPR = 0 When xxPR = 1 7 clocks 8 clocks Maximum Time 32 clocks 33 clocks Note Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. www..com An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 19-7 shows the interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction. User's Manual U15947EJ2V0UD 439 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-7. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (interrupt request generation) No xxMK = 0? Yes Interrupt request held pending Yes (High priority) xxPR = 0? No (Low priority) Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Interrupt request held pending No No IE = 1? Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Yes No Any high-priority interrupt request among those simultaneously generated? Interrupt request held pending Yes Interrupt request held pending No Vectored interrupt servicing IE = 1? Yes www..com Interrupt request held pending No Interrupt request held pending No ISP = 1? Yes Interrupt request held pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag xxPR: Priority specification flag IE: ISP: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable) Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing) 440 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks Instruction Instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 19-9. Interrupt Request Acknowledgment Timing (Maximum Time) 25 clocks 6 clocks PSW and PC saved, jump to interrupt servicing CPU processing xxIF (xxPR = 1) Instruction Divide instruction Interrupt servicing program 33 clocks www..com xxIF (xxPR = 0) 32 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) 19.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Do not use the RETI instruction for restoring from the software interrupt. Software interrupts cannot be User's Manual U15947EJ2V0UD 441 CHAPTER 19 INTERRUPT FUNCTIONS 19.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). Also, when an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of one main processing instruction execution. Table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 19-10 shows multiple interrupt servicing examples. Table 19-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request PR = 0 Interrupt Being Serviced www..com Software Interrupt Request IE = 0 x x x PR = 1 IE = 0 x x x IE = 1 x IE = 1 ISP = 0 ISP = 1 Maskable interrupt Software interrupt Remarks 1. : Multiple interrupt servicing enabled 2. x: Multiple interrupt servicing disabled 3. ISP and IE are flags contained in the PSW. ISP = 0: An interrupt with higher priority is being serviced. ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0: IE = 1: Interrupt request acknowledgment is disabled. Interrupt request acknowledgment is enabled. 4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H. PR = 0: Higher priority level PR = 1: Lower priority level 442 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing EI IE = 0 EI INTyy (PR = 0) IE = 0 EI INTzz (PR = 0) IE = 0 INTxx (PR = 1) RETI IE = 1 IE = 1 RETI IE = 1 RETI During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing www..com INTxx servicing INTyy servicing EI IE = 0 EI INTxx (PR = 0) INTyy (PR = 1) IE = 1 RETI 1 instruction execution IE = 0 RETI IE = 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: Interrupt request acknowledgment disabled User's Manual U15947EJ2V0UD 443 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing IE = 0 EI INTyy (PR = 0) RETI IE = 1 INTxx servicing INTyy servicing INTxx (PR = 0) 1 instruction execution IE = 0 RETI IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request www..com is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level IE = 0: Interrupt request acknowledgment disabled 444 User's Manual U15947EJ2V0UD CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW.bit, CY * MOV1 CY, PSW.bit * AND1 CY, PSW.bit * OR1 CY, PSW.bit * XOR1 CY, PSW.bit * SET1 PSW.bit * CLR1 PSW.bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW.bit, $addr16 * BF PSW.bit, $addr16 * BTCLR PSW.bit, $addr16 * EI * DI www..com These * Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, and PR1H registers Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. Figure 19-11 shows the timing at which interrupt requests are held pending. Figure 19-11. Interrupt Request Hold PSW and PC saved, jump to interrupt servicing Interrupt servicing program CPU processing Instruction N Instruction M xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request). User's Manual U15947EJ2V0UD 445 CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 20-1. Assignment of Key Interrupt Detection Pins Flag KRM0 KRM1 KRM2 KRM3 KRM4 KRM5 KRM6 KRM7 Description Controls KR0 signal in 1-bit units. Controls KR1 signal in 1-bit units. Controls KR2 signal in 1-bit units. Controls KR3 signal in 1-bit units. Controls KR4 signal in 1-bit units. Controls KR5 signal in 1-bit units. Controls KR6 signal in 1-bit units. Controls KR7 signal in 1-bit units. 20.2 Configuration of Key Interrupt The key interrupt consists of the following hardware. Table 20-2. Configuration of Key Interrupt Item Control register Configuration Key return mode register (KRM) www..com Figure 20-1. Block Diagram of Key Interrupt KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0 Edge detector INTKR KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) 446 User's Manual U15947EJ2V0UD CHAPTER 20 KEY INTERRUPT FUNCTION 20.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 20-2. Format of Key Return Mode Register (KRM) Address: FF6EH Symbol KRM 7 KRM7 After reset: 00H 6 KRM6 5 KRM5 R/W 4 KRM4 3 KRM3 2 KRM2 KRM1 0 KRM0 KRMn 0 1 Key interrupt mode control Does not detect key interrupt signal Detects key interrupt signal Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the corresponding pull-up resistor register 7 (PU7) to 1. 2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and then change the KRM register. Clear the interrupt request flag and enable interrupts. 3. The bits not used in the key interrupt mode can be used as normal ports. www..com User's Manual U15947EJ2V0UD 447 CHAPTER 21 STANDBY FUNCTION 21.1 Standby Function and Configuration 21.1.1 Standby function Table 21-1. Relationship Between Operation Clocks in Each Operation Status Status X1 Oscillator Ring-OSC Oscillator Subsystem CPU Clock Clock Operation Mode Reset STOP HALT Oscillating Stopped MSTOP = 0 MSTOP = 1 MCC = 0 Stopped MCC = 1 Stopped Oscillating Oscillating Stopped Note 1 Note 2 RSTOP = 0 RSTOP = 1 Oscillating Ring-OSC Note 3 Note 4 Stopped Stopped Ring-OSC X1 Oscillator After Release Prescaler Clock Supplied to Peripherals MCM0 = 0 MCM0 = 1 Notes 1. 2. 3. 4. When "Cannot be stopped" is selected for Ring-OSC by a mask option. When "Can be stopped by software" is selected for Ring-OSC by a mask option. Operates using the CPU clock at STOP instruction execution. Operates using the CPU clock at HALT instruction execution. Caution The RSTOP setting is valid only when "Can be stopped by software" is set for Ring-OSC by a mask option. www..com Remark MSTOP: Bit 7 of the main OSC control register (MOC) MCC: MCM0: Bit 7 of the processor clock control register (PCC) Bit 0 of the main clock mode register (MCM) RSTOP: Bit 0 of the Ring-OSC mode register (RCM) The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the X1 oscillator, Ring-OSC oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. 448 User's Manual U15947EJ2V0UD CHAPTER 21 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the X1 oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. STOP mode can be used only when CPU is operating on the X1 input clock or Ring-OSC clock. HALT mode can be used when CPU is operating on the X1 input clock, Ring-OSC clock, or subsystem clock. However, when the STOP instruction is executed during RingOSC clock operation, the X1 oscillator stops, but Ring-OSC oscillator does not stop. 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction. 3. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 4. If the Ring-OSC oscillator is operating before the STOP mode is set, oscillation of the RingOSC clock cannot be stopped in the STOP mode. However, when the Ring-OSC clock is used as the CPU clock, the CPU operation is stopped for 17/fR (s) after STOP mode is released. www..com User's Manual U15947EJ2V0UD 449 CHAPTER 21 STANDBY FUNCTION 21.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. Reset release (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, MSTOP (bit 7 of MOC register) = 1, and MCC (bit 7 of PCC register) = 1 clear OSTC to 00H. Figure 21-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H Symbol OSTC After reset: 00H 7 0 6 0 R 5 0 4 MOST11 3 MOST13 2 MOST14 1 MOST15 0 MOST16 MOST11 1 1 www..com MOST13 0 1 1 1 1 MOST14 0 0 1 1 1 MOST15 0 0 0 1 1 MOST16 0 0 0 0 1 Oscillation stabilization time status 2 /fX min. (204.8 s min.) 11 2 /fX min. (819.2 s min.) 13 1 1 1 2 /fX min. (1.64 ms min.) 2 /fX min. (3.27 ms min.) 2 /fX min. (6.55 ms min.) 16 15 14 Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. 3. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. Values in parentheses are reference value for operation with fX = 10 MHz. 2. fX: X1 input clock oscillation frequency 450 User's Manual U15947EJ2V0UD CHAPTER 21 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU clock. After STOP mode is released when the Ring-OSC clock is selected, check the oscillation stabilization time using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 05H. Figure 21-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H Symbol OSTS After reset: 05H 7 0 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS2 0 0 0 1 1 OSTS1 0 1 1 0 0 Other than above OSTS0 1 0 1 0 1 11 Oscillation stabilization time selection 2 /fX (204.8 s) 2 /fX (819.2 s) 13 2 /fX (1.64 ms) 2 /fX (3.27 ms) 2 /fX (6.55 ms) Setting prohibited 16 15 14 www..com Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. 2. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. Values in parentheses are reference value for operation with fX = 10 MHz. 2. fX: X1 input clock oscillation frequency User's Manual U15947EJ2V0UD 451 CHAPTER 21 STANDBY FUNCTION 21.2 Standby Function Operation 21.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the X1 input clock, Ring-OSC clock, or subsystem clock. The operating statuses in the HALT mode are shown below. Table 21-2. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on X1 Input Clock When Ring-OSC Oscillation Continues When Subsystem Clock Used Item System clock CPU Port (latch) 16-bit timer/event counter 00 16-bit timer/event counter 01Note 2 8-bit timer/event counter 50 8-bit timer/event counter 51 8-bit timer H0 www..com When HALT Instruction Is Executed While CPU Is Operating on Ring-OSC Clock When X1 Input Clock Oscillation Continues When Subsystem Clock Used When Subsystem Clock Not Used When X1 Input Clock Oscillation Stopped When Subsystem Clock Used When Subsystem Clock Not Used When Ring-OSC Oscillation StoppedNote 1 When Subsystem Clock Used When Subsystem Clock Not Used When Subsystem Clock Not Used Clock supply to the CPU is stopped. Operation stopped Status before HALT mode was set is retained Operable Operable Operable Operable Operable Operation not guaranteed Operation not guaranteed Operation not guaranteed when count clock other than TI50 is selected Operation not guaranteed when count clock other than TI51 is selected Operation not guaranteed when count clock other than TM50 output is selected during 8-bit timer/event counter 50 operation Operation not guaranteed when count clock other than fR/27 is selected OperableNote 3 Operable OperableNote 3 OperableNote 4 Operation not guaranteed - Operable OperableNote 4 Operation not guaranteed 8-bit timer H1 Watch timer Operable Operable Watchdog timer Ring-OSC cannot be stoppedNote 5 Ring-OSC can be stoppedNote 5 Operable Operation stopped Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable A/D converter Serial interface UART0 UART6 CSI10 CSI11Note 2 CSIA0 Clock monitor Multiplier/divider Power-on-clear functionNote 6 Low-voltage detection function External interrupt Operation not guaranteed Operation not guaranteed when serial clock other than TM50 output is selected during TM50 operation Operation not guaranteed when serial clock other than external SCK10 is selected Operation not guaranteed when serial clock other than external SCK11 is selected Operation not guaranteed Operation stopped Operable Operation not guaranteed Operation stopped Notes 1. 2. 3. 4. 5. 6. When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by software (for mask options, see CHAPTER 27 MASK OPTIONS). PD780146, 780148, and 78F0148 only. Operable when the X1 input clock is selected. Operation not guaranteed when other than subsystem clock is selected. "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask option. When "POC used" is selected by a mask option. User's Manual U15947EJ2V0UD 452 CHAPTER 21 STANDBY FUNCTION Table 21-2. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When X1 Input Clock Oscillation Continues Item System clock CPU Port (latch) 16-bit timer/event counter 00 16-bit timer/event counter 01 8-bit timer/event counter 50 8-bit timer/event counter 51 8-bit timer H0 Note 2 When X1 Input Clock Oscillation Stopped When Ring-OSC Oscillation Continues When Ring-OSC Oscillation StoppedNote 1 When Ring-OSC Oscillation Continues When Ring-OSC Oscillation StoppedNote 1 Clock supply to the CPU is stopped. Operation stopped Status before HALT mode was set is retained Operable Operable Operable Operable Operable Operation stopped Operation stopped Operable only when TI50 is selected as the count clock Operable only when TI51 is selected as the count clock Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter 50 operation Operable only when the X1 input clock is selected as the count clock Operable only when fR/27 is selected as the count clock Operation stopped 8-bit timer H1 Operable Watch timer Watchdog timer Ring-OSC cannot be stoppedNote 3 Ring-OSC can be stoppedNote 3 A/D converter Serial interface www..com Operable Operable Operation stopped Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operation stopped - Operable only when subsystem clock is selected Operable - Not operable Operable only when TM50 output is selected as the serial clock during TM50 operation Operable only when external clock is selected as the serial clock Operable only when external clock is selected as the serial clock Operation stopped UART0 UART6 CSI10 CSI11Note 2 CSIA0 Clock monitor Multiplier/divider Power-on-clear functionNote 4 Low-voltage detection function External interrupt Operation stopped Notes 1. 2. 3. 4. When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by software (for mask options, see CHAPTER 27 MASK OPTIONS). PD780146, 780148, and 78F0148 only. "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask option. When "POC used" is selected by a mask option. User's Manual U15947EJ2V0UD 453 CHAPTER 21 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 21-3. HALT Mode Release by Interrupt Request Generation Interrupt request Wait HALT instruction Standby release signal Operating mode Status of CPU X1 input clock, Ring-OSC clock, or subsystem clock HALT mode Oscillation Wait Operating mode Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. The wait time is as follows: www..com * When vectored interrupt servicing is carried out: 8 or 9 clocks * When vectored interrupt servicing is not carried out: 2 or 3 clocks 454 User's Manual U15947EJ2V0UD CHAPTER 21 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 21-4. HALT Mode Release by RESET Input (1/2) (1) When X1 input clock is used as CPU clock HALT instruction RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Reset period Oscillation stabilization time (211/fXP to 216/fXP) Status of CPU Operating mode (X1 input clock) HALT mode Oscillates X1 input clock (2) When Ring-OSC clock is used as CPU clock HALT instruction www..com RESET signal Operation Operating mode stopped (Ring-OSC clock) Oscillation (17/fR) Oscillates stopped Reset period Status of CPU Operating mode (Ring-OSC clock) HALT mode Oscillates Ring-OSC clock Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency User's Manual U15947EJ2V0UD 455 CHAPTER 21 STANDBY FUNCTION Figure 21-4. HALT Mode Release by RESET Input (2/2) (3) When subsystem clock is used as CPU clock HALT instruction RESET signal Operating mode Subsystem clock Subsystem clock Oscillates Reset period Operation stopped (17/fR) Status of CPU HALT mode Operating mode (Ring-OSC clock) Remark fR: Ring-OSC clock oscillation frequency Table 21-3. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt request 0 0 1 x MKxx 0 PRxx 0 IE 0 ISP x Operation Next address instruction execution Interrupt servicing execution 0 www..com 1 1 1 x - 0 x 1 x x 1 0 1 x x Next address instruction execution Interrupt servicing execution 0 0 1 RESET input - HALT mode held Reset processing x: don't care 456 User's Manual U15947EJ2V0UD CHAPTER 21 STANDBY FUNCTION 21.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set when the CPU clock before the setting was the X1 input clock or Ring-OSC clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. The operating statuses in the STOP mode are shown below. Table 21-4. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on X1 Input Clock When Ring-OSC Oscillation Continues Item System clock CPU Port (latch) 16-bit timer/event counter 00 16-bit timer/event counter 01Note 2 8-bit timer/event counter 50 8-bit timer/event counter 51 www..com When Ring-OSC Oscillation StoppedNote 1 When STOP Instruction Is Executed While CPU Is Operating on RingOSC Clock When Subsystem When Subsystem When Subsystem When Subsystem When Subsystem When Subsystem Clock Used Clock Not Used Clock Used Clock Not Used Clock Used Clock Not Used Only X1 oscillator oscillation is stopped. Clock supply to the CPU is stopped. Operation stopped Status before STOP mode was set is retained Operation stopped Operation stopped Operable only when TI50 is selected as the count clock Operable only when TI51 is selected as the count clock Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter 50 operation OperableNote 3 Operable Ring-OSC cannot be stoppedNote 5 Ring-OSC can be stoppedNote 5 Note 4 8-bit timer H0 8-bit timer H1 Watch timer Watchdog timer Operation stopped Operation stopped Operable Note 4 OperableNote 3 Note 4 Operation stopped Operable Operation stopped Operable Operation stopped Operation stopped - Operable A/D converter Serial interface UART0 UART6 CSI10 CSI11Note 2 CSIA0 Clock monitor Multiplier/divider Power-on-clear functionNote 6 Low-voltage detection function External interrupt Operable only when TM50 output is selected as the serial clock during TM50 operation Operable only when external SCK10 is selected as the serial clock Operable only when external SCK11 is selected as the serial clock Operation stopped Operation stopped Operation stopped Operable Operable Operable Notes 1. 2. 3. 4. 5. 6. When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by software (for mask options, see CHAPTER 27 MASK OPTIONS). PD780146, 780148, and 78F0148 only. 7 Operable only when fR/2 is selected as the count clock. Operable when the subsystem clock is selected. "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask option. When "POC used" is selected by a mask option. User's Manual U15947EJ2V0UD 457 CHAPTER 21 STANDBY FUNCTION (2) STOP mode release Figure 21-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode X1 input clock Ring-OSC clock X1 input clock is selected as CPU clock when STOP instruction is executed Ring-OSC clock is selected as CPU clock when STOP instruction is executed Operation stopped (17/fR) HALT status (oscillation stabilization time set by OSTS) X1 input clock Ring-OSC clock X1 input clock Clock switched by software The STOP mode can be released by the following two sources. www..com 458 User's Manual U15947EJ2V0UD CHAPTER 21 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 21-6. STOP Mode Release by Interrupt Request Generation (1) When X1 input clock is used as CPU clock STOP instruction Wait (set by OSTS) After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried Standby release signal Status of CPU Operating mode (X1 input clock) Oscillates STOP mode Oscillation stopped Oscillation stabilization wait (HALT mode status) Oscillates Operating mode (X1 input clock) X1 input clock Oscillation stabilization time (set by OSTS) (2) When Ring-OSC clock is used as CPU clock STOP instruction www..com Standby release signal Operation stopped (17/fR) Oscillates Status of CPU Ring-OSC clock Operating mode (Ring-OSC clock) STOP mode Operating mode (Ring-OSC clock) Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 2. fR: Ring-OSC clock oscillation frequency User's Manual U15947EJ2V0UD 459 CHAPTER 21 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 21-7. STOP Mode Release by RESET Input (1) When X1 input clock is used as CPU clock STOP instruction RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Oscillation stabilization time (211/fXP to 216/fXP) Reset period Status of CPU Operating mode (X1 input clock) Oscillates STOP mode Oscillation stopped X1 input clock (2) When Ring-OSC clock is used as CPU clock STOP instruction RESET signal www..com Status of CPU Operating mode (Ring-OSC clock) Ring-OSC clock STOP mode Oscillates Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Reset period Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency Table 21-5. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt request 0 0 1 x MKxx 0 PRxx 0 IE 0 ISP x Operation Next address instruction execution Interrupt servicing execution 0 0 0 1 1 1 x - 0 x 1 x x 1 0 1 x x Next address instruction execution Interrupt servicing execution 1 RESET input - STOP mode held Reset processing x: don't care 460 User's Manual U15947EJ2V0UD CHAPTER 22 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor X1 clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H when the reset signal is input. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, X1 clock oscillation stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Table 22-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset release, except for P130, which is low-level output. When a high level is input to the RESET pin, the reset is released and program execution starts using the RingOSC clock after the CPU clock operation has stopped for 17/fR (s). A reset generated by the watchdog timer and clock monitor sources is automatically released after the reset, and program execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/fR (s) (see Figures 22-2 to 22-4). Reset by POC and LVI circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and program execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/fR (s) (see CHAPTER 24 POWER-ON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR). www..com Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, the X1 input clock and Ring-OSC clock stop oscillating. 3. When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130, which is set to lowlevel output. User's Manual U15947EJ2V0UD 461 www..com 462 Watchdog timer reset signal Clock monitor reset signal User's Manual U15947EJ2V0UD Figure 22-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Set Clear CLMRF Set Clear LVIRF Set Clear CHAPTER 22 RESET FUNCTION Reset signal RESET Power-on-clear circuit reset signal Reset signal to LVIM/LVIS register Low-voltage detector reset signal Reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2. LVIS: Low-voltage detection level selection register CHAPTER 22 RESET FUNCTION Figure 22-2. Timing of Reset by RESET Input Ring-OSC clock X1 input clock Reset period (Oscillation stop) Operation stop (17/fR) Normal operation (Reset processing, Ring-OSC clock) CPU clock RESET Normal operation Internal reset signal Delay Port pin Delay Hi-ZNote Note The port pins become high impedance, except for P130, which is set to low-level output. Figure 22-3. Timing of Reset Due to Watchdog Timer Overflow Ring-OSC clock www..com X1 input clock CPU clock Watchdog timer overflow Normal operation Reset period (Oscillation stop) Operation stop (17/fR) Normal operation (Reset processing, Ring-OSC clock) Internal reset signal Port pin Hi-ZNote Note The port pins become high impedance, except for P130, which is set to low-level output. Caution A watchdog timer internal reset resets the watchdog timer. User's Manual U15947EJ2V0UD 463 CHAPTER 22 RESET FUNCTION Figure 22-4. Timing of Reset in STOP Mode by RESET Input Ring-OSC clock X1 input clock STOP instruction execution Operation stop Normal Reset period Stop status operation (Oscillation stop) (Oscillation stop) (17/fR) CPU clock RESET Normal operation (Reset processing, Ring-OSC clock) Internal reset signal Delay Port pin Delay Hi-ZNote Note The port pins become high impedance, except for P130, which is set to low-level output. Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 24 POWERON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR. www..com 464 User's Manual U15947EJ2V0UD CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (1/3) Hardware Program counter (PC) Status After Reset Note 1 Acknowledgment The contents of the reset vector table (0000H, 0001H) are set. Undefined 02H Undefined Undefined Note 2 Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose registers Port registers (P0 to P7, P12 to P14) (output latches) Port mode registers (PM0, PM1, PM3 to PM7, PM12, PM14) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14) Input switch control register (ISC) Internal memory size switching register (IMS) Internal expansion RAM size switching register (IXS) Memory expansion mode register (MEM) Memory expansion wait setting register (MM) Processor clock control register (PCC) Ring-OSC mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) www..com Note 2 00H (undefined only for P2) FFH 00H 00H CFH 0CH 00H 10H 00H 00H 00H 00H 05H 00H 0000H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Oscillation stabilization time select register (OSTS) Oscillation stabilization time counter status register (OSTC) 16-bit timer/event Note 3 counters 00, 01 Timer counters 00, 01 (TM00, TM01) Capture/compare registers 000, 010, 001, 011 (CR000, CR010, CR001, CR011) Mode control registers 00, 01 (TMC00, TMC01) Prescaler mode registers 00, 01 (PRM00, PRM01) Capture/compare control registers 00, 01 (CRC00, CRC01) Timer output control registers 00, 01 (TOC00, TOC01) 8-bit timer/event counters 50, 51 Timer counters 50, 51 (TM50, TM51) Compare registers 50, 51 (CR50, CR51) Timer clock selection registers 50, 51 (TCL50, TCL51) Mode control registers 50, 51 (TMC50, TMC51) 8-bit timers H0, H1 Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) Mode registers (TMHMD0, TMHMD1) Carrier control register 1 (TMCYC1) Watch timer Clock output/buzzer output controller Operation mode register (WTM) Clock output selection register (CKS) Note 4 Notes 1. 2. 3. 4. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. When a reset is executed in the standby mode, the pre-reset status is held even after reset. 16-bit timer/event counter 01 is available only for the PD780146, 780148, and 78F0148. 8-bit timer H1 only. User's Manual U15947EJ2V0UD 465 CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Watchdog timer Mode register (WDTM) Enable register (WDTE) A/D converter Conversion result register (ADCR) Mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) Serial interface UART0 Receive buffer register 0 (RXB0) Transmit shift register 0 (TXS0) Asynchronous serial interface operation mode register 0 (ASIM0) Baud rate generator control register 0 (BRGC0) Serial interface UART6 Receive buffer register 6 (RXB6) Transmit buffer register 6 (TXB6) Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) www..com Status After Reset Acknowledgment 67H 9AH Undefined 00H 00H 00H 00H FFH FFH 01H 1FH FFH FFH 01H 00H 00H 00H FFH 16H Undefined Undefined 00H 00H 00H 00H 00H 00H 03H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H Serial interfaces CSI10, Note CSI11 Transmit buffer registers 10, 11 (SOTB10, SOTB11) Serial I/O shift registers 10, 11 (SIO10, SIO11) Serial operation mode registers 10, 11 (CSIM10, CSIM11) Serial clock selection registers 10, 11 (CSIC10, CSIC11) Serial interface CSIA0 Shift register 0 (SIOA0) Operation mode specification register 0 (CSIMA0) Status register 0 (CSIS0) Trigger register 0 (CSIT0) Divisor selection register 0 (BRGCA0) Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer interval specification register 0 (ADTI0) Automatic data transfer address count register 0 (ADTC0) Multiplier/divider Remainder data register 0 (SDR0) Multiplication/division data register A0 (MDA0H, MDA0L) Multiplication/division data register B0 (MDB0) Multiplier/divider control register 0 (DMUC0) Key interrupt Clock monitor Key return mode register (KRM) Mode register (CLM) Note Serial interface CSI11 is available only for the PD780146, 780148, and 78F0148. 466 User's Manual U15947EJ2V0UD CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Reset function Low-voltage detector Reset control flag register (RESF) Low-voltage detection register (LVIM) Low-voltage detection level selection register (LVIS) Interrupt Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H) Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L) Mask flag register 1H (MK1H) Status After Reset Acknowledgment 00H 00H Note Note 00H 00H Note FFH DFH Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L, PR1H) FFH External interrupt rising edge enable register (EGP) External interrupt falling edge enable register (EGN) 00H 00H Note These values vary depending on the reset source. Reset Source Register RESF LVIM LVIS See Table 22-2. Cleared (00H) Cleared (00H) Cleared (00H) Cleared (00H) Held RESET Input Reset by POC Reset by WDT Reset by CLM Reset by LVI www..com User's Manual U15947EJ2V0UD 467 CHAPTER 22 RESET FUNCTION 22.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KF1. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H. Figure 22-5. Format of Reset Control Flag Register (RESF) Address: FFACH Symbol RESF After reset: 00H 7 0 6 0 Note R 5 0 4 WDTRF 3 0 2 0 1 CLMRF 0 LVIRF WDTRF 0 1 Internal reset request by watchdog timer (WDT) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated. CLMRF 0 1 Internal reset request by clock monitor (CLM) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated. LVIRF www..com Internal reset request by low-voltage detector (LVI) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated. 0 1 Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 22-2. Table 22-2. RESF Status When Reset Request Is Generated Reset Source Flag WDTRF CLMRF LVIRF RESET Input Reset by POC Reset by WDT Reset by CLM Reset by LVI Cleared (0) Cleared (0) Set (1) Held Held Held Set (1) Held Held Held Set (1) 468 User's Manual U15947EJ2V0UD CHAPTER 23 CLOCK MONITOR 23.1 Functions of Clock Monitor The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal when the X1 input clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 22 RESET FUNCTION. The clock monitor automatically stops under the following conditions. * Reset is released and during the oscillation stabilization time * In STOP mode and during the oscillation stabilization time * When the X1 input clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation stabilization time * When the Ring-OSC clock is stopped Remark MSTOP: Bit 7 of main OSC control register (MOC) MCC: Bit 7 of processor clock control register (PCC) 23.2 Configuration of Clock Monitor Clock monitor consists of the following hardware. www..com Table 23-1. Configuration of Clock Monitor Item Control register Clock monitor mode register (CLM) Configuration Figure 23-1. Block Diagram of Clock Monitor Internal bus Clock monitor mode register (CLM) CLME X1 oscillation control signal (MCC, MSTOP) X1 oscillation stabilization status (OSTC overflow) Operation mode controller X1 input clock Ring-OSC clock X1 oscillation monitor circuit Internal reset signal Remark MCC: OSTC: Bit 7 of processor clock control register (PCC) Oscillation stabilization time counter status register (OSTC) MSTOP: Bit 7 of main OSC control register (MOC) User's Manual U15947EJ2V0UD 469 CHAPTER 23 CLOCK MONITOR 23.3 Registers Controlling Clock Monitor Clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 23-2. Format of Clock Monitor Mode Register (CLM) Address: FFA9H Symbol CLM 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 0 1 0 <0> CLME CLME 0 1 Enables/disables clock monitor operation Disables clock monitor operation Enables clock monitor operation Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal reset signal. 2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1. www..com 470 User's Manual U15947EJ2V0UD CHAPTER 23 CLOCK MONITOR 23.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows. CPU Operation Clock X1 input clock Operation Mode STOP mode X1 Input Clock Status Stopped Ring-OSC Clock Status Oscillating Stopped RESET input www..com Note Clock Monitor Status Stopped Oscillating Stopped Note Normal operation mode HALT mode Ring-OSC clock STOP mode RESET input Normal operation mode HALT mode Oscillating Oscillating Stopped Note Operating Stopped Stopped Stopped Oscillating Oscillating Stopped Operating Stopped Note The Ring-OSC clock is stopped only when the "Ring-OSC can be stopped by software" is selected by a mask option. If "Ring-OSC cannot be stopped" is selected, the Ring-OSC clock cannot be stopped. The clock monitor timing is as shown in Figure 23-3. User's Manual U15947EJ2V0UD 471 CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (1/4) (1) When internal reset is executed by oscillation stop of X1 input clock 4 clocks of Ring-OSC clock X1 input clock Ring-OSC clock Internal reset signal CLME CLMRF (2) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time) Normal operation Clock supply stopped CPU operation X1 input clock Reset Normal operation (Ring-OSC clock) Oscillation stopped www..com Oscillation stabilization time Ring-OSC clock Oscillation stopped RESET 17 clocks Set to 1 by software CLME Clock monitor status Monitoring Monitoring stopped Monitoring Waiting for end of oscillation stabilization time RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor operation. Even if CLME is set to 1 by software during the oscillation stabilization time (reset value of OSTS register is 05H (216/fXP)) of the X1 input clock, monitoring is not performed until the oscillation stabilization time of the X1 input clock ends. Monitoring is automatically started at the end of the oscillation stabilization time. 472 User's Manual U15947EJ2V0UD CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (2/4) (3) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time) Normal operation Clock supply stopped CPU operation X1 input clock Reset Normal operation (Ring-OSC clock) Oscillation stabilization time Ring-OSC clock 17 clocks RESET Set to 1 by software CLME Clock monitor status Monitoring Monitoring stopped Monitoring RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (reset value of OSTS register is 05H (216/fXP)) of the X1 input clock, monitoring is started. (4) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode) Normal operation www..com CPU operation X1 input clock (CPU clock) STOP Oscillation stabilization time Normal operation Oscillation stopped Ring-OSC clock Oscillation stabilization time (time set by OSTS register) CLME Clock monitor status Monitoring Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode and during the oscillation stabilization time. User's Manual U15947EJ2V0UD 473 CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (3/4) (5) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode) Normal operation Clock supply stopped CPU operation X1 input clock STOP Normal operation Oscillation stopped Ring-OSC clock (CPU clock) Oscillation stabilization time (time set by OSTS register) 17 clocks CLME Clock monitor status Monitoring Monitoring stopped Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode and during the oscillation stabilization time. (6) Clock monitor status after X1 input clock oscillation is stopped by software CPU operation www..com Normal operation (Ring-OSC clock or subsystem clockNote) X1 input clock Oscillation stopped Ring-OSC clock Oscillation stabilization time (time set by OSTS register) MSTOP or MCCNote CLME Clock monitor status Monitoring Monitoring stopped Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the X1 input clock is stopped, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped when oscillation of the X1 input clock is stopped and during the oscillation stabilization time. Note The register that controls oscillation of the X1 input clock differs depending on the type of the clock supplied to the CPU. * When CPU operates on Ring-OSC clock: Controlled by bit 7 (MSTOP) of the main OSC control register (MOC) * When CPU operates on subsystem clock: Controlled by bit 7 (MCC) of the processor clock control register (PCC) 474 User's Manual U15947EJ2V0UD CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (4/4) (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software CPU operation X1 input clock Normal operation (X1 input clock or subsystem clock) Ring-OSC clock Oscillation stopped RSTOP Note CLME Clock monitor status Monitoring Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the Ring-OSC clock is stopped, monitoring automatically starts after the Ring-OSC clock is stopped. Monitoring is stopped when oscillation of the Ring-OSC clock is stopped. Note If it is specified by a mask option that Ring-OSC cannot be stopped, the setting of bit 0 (RSTOP) of the Ring-OSC mode register (RCM) is invalid. To set RSTOP, be sure to confirm that bit 1 (MCS) of the main www..com clock mode register (MCM) is 1. User's Manual U15947EJ2V0UD 475 CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. * Compares supply voltage (VDD) and detection voltage (VPOC), and generates internal reset signal when VDD < VPOC. * The following can be selected by a mask option. * * * POC disabled POC used (detection voltage: VPOC = 2.85 V 0.15 V)Note POC used (detection voltage: VPOC = 3.5 V 0.2 V) Note (A1) and (A2) grade products cannot be selected because their supply voltage VDD is 3.3 to 5.5 V. Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT), low-voltage-detection (LVI) circuit, or clock monitor. RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT, www..com LVI, or the clock monitor. For details of the RESF, see CHAPTER 22 RESET FUNCTION. 476 User's Manual U15947EJ2V0UD CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 24-1. Figure 24-1. Block Diagram of Power-on-Clear Circuit VDD VDD Mask option + - Internal reset signal Detection voltage source (VPOC) 24.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC) are compared, and when VDD < www..com VPOC, an internal reset signal is generated. Figure 24-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit Supply voltage (VDD) POC detection voltage (VPOC) 2.7 V Time Internal reset signal User's Manual U15947EJ2V0UD 477 CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause of resetNote 2 Power-on-clear ; The cause of reset (power-on-clear, WDT, LVI, or clock monitor) can be identified by the RESF register. Start timer (set to 50 ms) www..com ; 8-bit timer H1 can operate with the Ring-OSC clock. Source: fR (480 kHz (MAX.))/27 x compare value 200 = 53 ms (fR: Ring-OSC clock oscillation frequency) Note 1 Check stabilization of oscillation ; Check the stabilization of oscillation of the X1 input clock by using the OSTC register. Change CPU clock ; Change the CPU clock from the Ring-OSC clock to the X1 input clock. No 50 ms has passed? (TMIFH1 = 1?) ; TMIFH1 = 1: Interrupt request is generated. Yes Initialization processing ; Initialization of ports Notes 1. 2. If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page. 478 User's Manual U15947EJ2V0UD CHAPTER 24 POWER-ON-CLEAR CIRCUIT Figure 24-3. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset cause WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer CLMRF of RESF register = 1? Yes No www..com Reset processing by clock monitor LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated User's Manual U15947EJ2V0UD 479 CHAPTER 25 LOW-VOLTAGE DETECTOR 25.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. * Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. Note * Detection levels (seven levels) of supply voltage can be changed by software. * Interrupt or reset function can be selected by software. * Operable in STOP mode. Note Five levels in the case of (A1) grade products and (A2) grade products. When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, see CHAPTER 22 RESET FUNCTION. 25.2 Configuration of Low-Voltage Detector A block diagram of the low-voltage detector is shown below. Figure 25-1. Block Diagram of Low-Voltage Detector www..com VDD Low-voltage detection level selector VDD N-ch Selector Internal reset signal + - INTLVI Detection voltage source (VLVI) 3 LVIS2 LVIS1 LVIS0 Low-voltage detection level selection register (LVIS) Internal bus LVION LVIE LVIMD LVIF Low-voltage detection register (LVIM) 480 User's Manual U15947EJ2V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR 25.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detection register (LVIM) * Low-voltage detection level selection register (LVIS) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. www..com User's Manual U15947EJ2V0UD 481 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-2. Format of Low-Voltage Detection Register (LVIM) Address: FFBEH Symbol LVIM <7> LVION After reset: 00H 6 0 R/WNote 1 5 0 <4> LVIE 3 0 2 0 <1> LVIMD <0> LVIF LVION 0 1 Notes 2, 3 Enables low-voltage detection operation Disables operation Enables operation LVIE Notes 2, 4, 5 Specifies reference voltage generator Disables operation Enables operation 0 1 LVIMD 0 1 Note 2 Low-voltage detection operation mode selection Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI) Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI) LVIF 0 1 www..com Note 6 Low-voltage detection flag Supply voltage (VDD) > detection voltage (VLVI), or when operation is disabled Supply voltage (VDD) < detection voltage (VLVI) Notes 1. 2. 3. Bit 0 is read-only. LVION, LVIE, and LVIMD are cleared to 0 in the case of a reset other than an LVI reset. These are not cleared to 0 in the case of an LVI reset. When LVION is set to 1, operation of the comparator in the LVI circuit is started. confirmed at LVIF. Use software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is 4. 5. 6. If "POC cannot be used" is selected by a mask option, wait for 2 ms or more by software from when LVIE is set to 1 until LVION is set to 1. If "POC used" is selected by a mask option, setting of LVIE is invalid because the reference voltage generator in the LVI circuit always operates. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0. Caution To stop LVI, follow either of the procedures below. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0 first and then clear LVIE to 0. 482 User's Manual U15947EJ2V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 25-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH Symbol LVIS 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 LVIS2 1 LVIS1 0 LVIS0 LVIS2 0 0 0 0 1 1 1 1 LVIS1 0 0 1 1 0 0 1 1 LVIS0 0 1 0 1 0 1 0 1 VLVI0 (4.3 V 0.2 V) VLVI1 (4.1 V 0.2 V) VLVI2 (3.9 V 0.2 V) VLVI3 (3.7 V 0.2 V) VLVI4 (3.5 V 0.2 V) Note 1 Detection level VLVI5 (3.3 V 0.15 V) VLVI6 (3.1 V 0.15 V) Setting prohibited Notes 1, 2 Notes 1, 2 Notes 1. When the detection voltage of the POC circuit is specified as VPOC = 3.5 V 0.2 V by a mask www..com option, do not select VLVI4 to VLVI6 as the LVI detection voltage. Even if VLVI4 to VLVI6 are selected, the POC circuit has priority. 2. This setting is prohibited in (A1) grade products and (A2) grade products. Caution Be sure to clear bits 3 to 7 to 0. User's Manual U15947EJ2V0UD 483 CHAPTER 25 LOW-VOLTAGE DETECTOR 25.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. * Used as reset Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when VDD < VLVI. * Used as interrupt Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. The operation is set as follows. (1) When used as reset * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator operation). <4> Use software to instigate a wait of at least 2 ms. <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to instigate a wait of at least 0.2 ms. <7> Wait until it is checked that (supply voltage (VDD) > detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. www..com <8> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)). Figure 25-4 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <8> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <5>. 2. If "POC used" is selected by a mask option, procedures <3> and <4> are not required. 3. If supply voltage (VDD) > detection voltage (VLVI) when LVIM is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. When using 1-bit memory manipulation instruction: Clear LVIMD to 0, LVION to 0, and LVIE to 0 in that order. * 484 User's Manual U15947EJ2V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) 2.7 V <2> LVIMK flag (set by software) <1>Note 1 Time LVIE flag (set by software) Not cleared <3> <4> 2 ms or longer Not cleared Clear Not cleared Clear LVION flag (set by software) <5> Not cleared <6> 0.2 ms or longer LVIF flag <7> LVIMD flag (set by software) Note 2 Clear Not cleared Not cleared Clear <8> www..com LVIRF flagNote 3 LVI reset signal Cleared by software POC reset signal Cleared by software Internal reset signal Notes 1. 2. 3. The LVIMK flag is set to "1" by RESET input. The LVIF flag may be set (1). LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET FUNCTION. Remark <1> to <8> in Figure 25-4 above correspond to <1> to <8> in the description of "when starting operation" in 25.4 (1) When used as reset. User's Manual U15947EJ2V0UD 485 CHAPTER 25 LOW-VOLTAGE DETECTOR (2) When used as interrupt * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator operation). <4> Use software to instigate a wait of at least 2 ms. <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to instigate a wait of at least 0.2 ms. <7> Wait until it is checked that (supply voltage (VDD) > detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. <8> Clear the interrupt request flag of LVI (LVIIF) to 0. <9> Release the interrupt mask flag of LVI (LVIMK). <10> Execute the EI instruction (when vectored interrupts are used). Figure 25-5 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <9> above. Caution If "POC used" is selected by a mask option, procedures <3> and <4> are not required. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. When using 1-bit memory manipulation instruction: Clear LVION to 0 first, and then clear LVIE to 0. www..com * 486 User's Manual U15947EJ2V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) 2.7 V <2> LVIMK flag (set by software) <1>Note 1 <9> Cleared by software LVIE flag (set by software) Time <3> <4> 2 ms or longer LVION flag (set by software) <5> <6> 0.2 ms or longer LVIF flag <7> Note 2 INTLVI www..com LVIIF flag Note 2 <8> Cleared by software Internal reset signal Notes 1. 2. Remark The LVIMK flag is set to "1" by RESET input. The LVIF and LVIIF flags may be set (1). <1> to <9> in Figure 25-5 above correspond to <1> to <9> in the description of "when starting operation" in 25.4 (2) When used as interrupt. User's Manual U15947EJ2V0UD 487 CHAPTER 25 LOW-VOLTAGE DETECTOR 25.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take action (2) below. In this system, take the following actions. www..com 488 User's Manual U15947EJ2V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-6. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause of resetNote 2 LVI ; The cause of reset (power-on-clear, WDT, LVI, or clock monitor) can be identified by the RESF register. Start timer (set to 50 ms) ; 8-bit timer H1 can operate with the Ring-OSC clock. Source: fR (480 kHz (MAX.))/27 x compare value 200 = 53 ms (fR: Ring-OSC clock oscillation frequency) Note 1 Check stabilization of oscillation ; Check the stabilization of oscillation of the X1 input clock by using the OSTC register. Change CPU clock ; Change the CPU clock from the Ring-OSC clock to the X1 input clock. www..com No 50 ms has passed? (TMIFH1 = 1?) ; TMIFH1 = 1: Interrupt request is generated. Yes Initialization processing ; Initialization of ports Notes 1. 2. If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page. User's Manual U15947EJ2V0UD 489 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-6. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset cause WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer CLMRF of RESF register = 1? Yes No www..com Reset processing by clock monitor LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector 490 User's Manual U15947EJ2V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR (2) When used as interrupt Check that "supply voltage (VDD) > detection voltage (VLVI)" in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L) to 0 and enable interrupts (EI). In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for the supply voltage fluctuation period, check that "supply voltage (VDD) > detection voltage (VLVI)" using the LVIF flag, and then enable interrupts (EI). www..com User's Manual U15947EJ2V0UD 491 CHAPTER 26 REGULATOR 26.1 Outline of Regulator The 78K0/KF1 includes a circuit to realize constant-voltage operation inside the device. To stabilize the regulator output voltage, connect the REGC pin to VSS via a capacitor (1 F: recommended). The output voltage of the regulator is 3.5 V (TYP.). The supply voltage and oscillation frequency at which the regulator can be used are as follows. * Power supply voltage: VDD = 4.0 to 5.5 V * Oscillation frequency: fX = 2.0 to 8.38 MHz The regulator of the 78K0/KF1 stops operating in the following cases. * During the reset period * In STOP mode * In HALT mode when the CPU is operating on the subsystem clock and when X1 oscillation is stopped Figure 26-1 shows the block diagram of the periphery of the regulator. Figure 26-1. Block Diagram of Regulator Periphery EVDD system I/O buffer www..com Internal digital circuits EVDD A/D converter X1, Ring, sub oscillator AVREF Bidirectional level shifter REGC Flash memory (PD78F0148 only) Regulator VDD VPP 1 F Cautions 1. Directly connect the REGC pin of standard products and (A) grade products to VDD when the regulator is not used. 2. The regulator cannot be used with (A1) and (A2) grade products. Be sure to connect the REGC pin of these products directly to VDD. 492 User's Manual U15947EJ2V0UD CHAPTER 26 REGULATOR Figure 26-2. REGC Pin Connection (a) When REGC = VDD VDD Input voltage = 2.7 to 5.5 V REG REGC Voltage supply to oscillator/internal logic = 2.7 to 5.5 V (b) When connecting REGC pin to VSS via a capacitor www..com VDD Input voltage = 4.0 to 5.5 V REG REGC Voltage supply to oscillator/internal logic = 3.5 V 1 F (recommended) User's Manual U15947EJ2V0UD 493 CHAPTER 27 MASK OPTIONS Mask ROM versions are provided with the following mask options. 1. Power-on-clear (POC) circuit * POC cannot be used * POC used (detection voltage: VPOC = 2.85 V 0.15 V)Note * POC used (detection voltage: VPOC = 3.5 V 0.2 V) 2. Ring-OSC * Cannot be stopped * Can be stopped by software 3. Pull-up resistor of P60 to P63 pins * Pull-up resistor can be incorporated in 1-bit units (Pull-up resistors are not available for the flash memory versions.) Note (A1) and (A2) grade products cannot be selected because their supply voltage VDD is 3.3 to 5.5 V. Flash memory versions that support the mask options of the mask ROM versions are as follows. Table 27-1. Flash Memory Versions Supporting Mask Options of Mask ROM Versions Mask Option POC Circuit www..com Flash Memory Version Ring-OSC POC cannot be used Cannot be stopped Can be stopped by software PD78F0148M1, 78F0148M1(A), 78F0148M1(A1) PD78F0148M2, 78F0148M2(A), 78F0148M2(A1) PD78F0148M3, 78F0148M3(A) PD78F0148M4, 78F0148M4(A) PD78F0148M5, 78F0148M5(A), 78F0148M5(A1) PD78F0148M6, 78F0148M6(A), 78F0148M6(A1) POC used (VPOC = 2.85 V 0.15 V) POC used (VPOC = 3.5 V 0.2 V) Cannot be stopped Can be stopped by software Cannot be stopped Can be stopped by software 494 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 The PD78F0148 is provided as the flash memory version of the 78K0/KF1. The PD78F0148 replaces the internal mask ROM of the PD780148 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. PD78F0148 and the mask ROM versions. Table 28-1 lists the differences between the Table 28-1. Differences Between PD78F0148 and Mask ROM Versions Item Internal ROM configuration Internal ROM capacity PD78F0148 Flash memory 60 KB Note Mask ROM Versions Mask ROM PD780143: 24 KB PD780144: 32 KB PD780146: 48 KB PD780148: 60 KB Note Internal expansion RAM capacity 1024 bytes PD780143: None PD780144: None PD780146: 1024 bytes PD780148: 1024 bytes Available None IC pin VPP pin Electrical specifications, recommended soldering conditions www..com None Available Refer to the description of electrical specifications and recommended soldering conditions. Note The same capacity as the mask ROM versions can be specified by means of the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions. User's Manual U15947EJ2V0UD 495 CHAPTER 28 PD78F0148 28.1 Internal Memory Size Switching Register The PD78F0148 allows users to select the internal memory capacity using the internal memory size switching register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory capacity can be achieved. IMS is set by an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution Be sure to set the value of the relevant mask ROM version at initialization. Figure 28-1. Format of Internal Memory Size Switching Register (IMS) Address: FFF0H Symbol IMS After reset: CFH 7 RAM2 6 RAM1 R/W 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 RAM2 1 RAM1 1 Other than above RAM0 0 Internal high-speed RAM capacity selection 1024 bytes Setting prohibited ROM3 0 1 www..com ROM2 1 0 1 1 ROM1 1 0 0 1 ROM0 0 0 0 1 24 KB 32 KB 48 KB 60 KB Internal ROM capacity selection 1 1 Other than above Setting prohibited The IMS settings required to obtain the same memory map as mask ROM versions are shown in Table 28-2. Table 28-2. Internal Memory Size Switching Register Settings Target Mask ROM Versions IMS Setting C6H C8H CCH CFH PD780143 PD780144 PD780146 PD780148 Caution When using a mask ROM version, be sure to set the value indicated in Table 28-2 to IMS. 496 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 28.2 Internal Expansion RAM Size Switching Register This register is used to set the internal expansion RAM capacity via software. This register is set by an 8-bit memory manipulation instruction. RESET input sets IXS to 0CH. Caution Be sure to set the value of the relevant mask ROM version at initialization. Figure 28-2. Format of Internal Expansion RAM Size Switching Register (IXS) Address: FFF4H Symbol IXS After reset: 0CH 7 0 6 0 R/W 5 0 4 IXRAM4 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 IXRAM4 0 0 IXRAM3 1 1 IXRAM2 1 0 Other than above IXRAM1 0 1 IXRAM0 0 0 Internal expansion RAM capacity selection 0 bytes 1024 bytes Setting prohibited The IXS settings required to obtain the same memory map as mask ROM versions are shown in Table 28-3. Table 28-3. Internal Expansion RAM Size Switching Register Settings www..com Target Mask ROM Versions IXS Setting 0CH 0CH 0AH 0AH PD780143 PD780144 PD780146 PD780148 Caution When using a mask ROM version, be sure to set the value indicated in Table 28-3 to IXS. User's Manual U15947EJ2V0UD 497 CHAPTER 28 PD78F0148 28.3 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the PD78F0148 has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the PD78F0148 is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Table 28-4. Wiring Between PD78F0148 and Dedicated Flash Programmer (1/2) (1) 3-wire serial I/O (CSI10) Pin Configuration of Dedicated Flash Programmer Signal Name SI/RxD SO/TxD SCK CLK www..com With CSI10 Pin Name SO10/P12 SI10/RxD0/P11 SCK10/TxD0/P10 X1 X2 Note 1 With CSI10 + HS Pin No. 20 19 18 12 13 14 8 Pin Name SO10/P12 SI10/RxD0/P11 SCK10/TxD0/P10 X1 X2 Note 1 I/O Input Output Output Output Pin Function Receive signal Transmit signal Transfer clock Clock to PD78F0148 Pin No. 20 19 18 12 13 14 8 23 9 31 1 11 30 2 /RESET VPP H/S VDD Output Output Input I/O Reset signal Write voltage Handshake signal VDD voltage generation/voltage monitor Note 2 RESET VPP Not needed VDD EVDD AVREF RESET VPP HS/P15/TOH0 VDD EVDD AVREF VSS EVSS AVSS Not needed 9 31 1 11 30 2 GND - Ground VSS EVSS AVSS Notes 1. 2. When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Flashpro III only Cautions 1. Be sure to connect the REGC pin in either of the following ways. * To GND via a 1 F capacitor * Directly to VDD 2. When connecting the REGC pin to GND via a 1 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Create an oscillator on the board to supply a clock. 498 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 Table 28-4. Wiring Between PD78F0148 and Dedicated Flash Programmer (2/2) (2) UART (UART0, UART6) Pin Configuration of Dedicated Flash Programmer Signal Name SI/RxD I/O Input Pin Function Receive signal With UART0 Pin Name TxD0/ SCK10/P10 SO/TxD Output Transmit signal RxD0/SI10/ P11 SCK Output Transfer clock Clock to PD78F0148 Not needed Not needed CLK Output X1 X2 /RESET VPP H/S Output Output Input Reset signal Write voltage Handshake signal Note 1 With UART0 + HS Pin Name TxD0/ SCK10/P10 19 RxD0/SI10/ P11 Not needed Not needed X1 X2 Note 1 With UART6 Pin Name TxD6/P13 Pin No. 21 Pin No. 18 Pin No. 18 19 RxD6/P14 22 Not needed Not needed 12 13 14 8 Not needed 12 13 14 8 23 X1 X2 Note 1 12 13 14 8 Not needed RESET VPP Not needed RESET VPP HS/P15/TOH0 RESET VPP Not needed VDD I/O VDD voltage generation/voltage VDD monitor Note 2 9 31 1 11 30 2 VDD EVDD AVREF VSS EVSS AVSS 9 31 1 11 30 2 VDD EVDD AVREF VSS EVSS AVSS 9 31 1 11 30 2 EVDD AVREF GND - Ground VSS EVSS www..com AVSS Notes 1. 2. When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Flashpro III only Cautions 1. Be sure to connect the REGC pin in either of the following ways. * To GND via a 1 F capacitor * Directly to VDD 2. When connecting the REGC pin to GND via a 1 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Create an oscillator on the board to supply a clock. User's Manual U15947EJ2V0UD 499 CHAPTER 28 PD78F0148 Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 28-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www..com SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): Connect directly to VDD 500 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 Figure 28-4. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www..com SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): Connect directly to VDD User's Manual U15947EJ2V0UD 501 CHAPTER 28 PD78F0148 Figure 28-5. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www..com SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): Connect directly to VDD 502 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 Figure 28-6. Example of Wiring Adapter for Flash Memory Writing in UART (UART0 + HS) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www..com SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): Connect directly to VDD User's Manual U15947EJ2V0UD 503 CHAPTER 28 PD78F0148 Figure 28-7. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode VDD (2.7 to 5.5 V)Note 1 GND LVDD (VDD2) VDD GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10Note 2 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www..com SI SO SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE Notes 1. 2. PD78F0148, 78F0148(A): 2.7 to 5.5 V PD78F0148(A1): 3.3 to 5.5 V Connect the REGC pin as follows. PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor PD78F0148(A1): Connect directly to VDD 504 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 28.4 Programming Environment The environment required for writing a program to the flash memory of the PD78F0148 is illustrated below. Figure 28-8. Environment for Writing Program to Flash Memory VPP RS-232C XXXX YYYY XXX YYY Bxxxxx Cxxxxxx XXXX XXXXXX Axxxx VDD PG-FP4 (Flash Pro4) XXXXX STATVE VSS RESET PD78F0148 USB Note Dedicated flash programmer Host machine CSI10/UART0/UART6 Note Flashpro IV only A host machine that controls the dedicated flash programmer is necessary. To interface between the dedicated flash programmer and the PD78F0148, CSI10, UART0, or UART6 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. 28.5 Communication Mode Communication between the dedicated flash programmer and the PD78F0148 is established by serial www..com communication via CSI10, UART0, or UART6 of the PD78F0148. (1) CSI10 Transfer rate: 200 kHz to 2 MHz Figure 28-9. Communication with Dedicated Flash Programmer (CSI10) VPP VDD GND XXXX YYYY VPP VDD/EVDD/AVREF VSS/EVSS/AVSS RESET SO10 SI10 SCK10 X1 X2 Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE /RESET SI/RxD XXXX Dedicated flash programmer SO/TxD SCK CLK PD78F0148 User's Manual U15947EJ2V0UD 505 CHAPTER 28 PD78F0148 (2) CSI communication mode supporting handshake Transfer rate: 200 kHz to 2 MHz Figure 28-10. Communication with Dedicated Flash Programmer (CSI10 + HS) VPP VDD GND XXXX YYYY VPP VDD/EVDD/AVREF VSS/EVSS/AVSS RESET SO10 SI10 SCK10 X1 X2 HS Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE /RESET SI/RxD XXXX Dedicated flash programmer SO/TxD SCK CLK H/S PD78F0148 (3) UART0 Transfer rate: 4800 to 38400 bps Figure 28-11. Communication with Dedicated Flash Programmer (UART0) VPP VDD XXXX YYYY VPP VDD/EVDD/AVREF VSS/EVSS/AVSS RESET RxD0 TxD0 X1 X2 Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx GND /RESET SO/TxD SI/RxD CLK www..com Dedicated flash programmer PD78F0148 506 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 (4) UART communication mode supporting handshake Transfer rate: 4800 to 38400 bps Figure 28-12. Communication with Dedicated Flash Programmer (UART0 + HS) VPP VDD XXXX YYYY VPP VDD/EVDD/AVREF VSS/EVSS/AVSS RESET TxD0 RxD0 X1 X2 HS Bxxxxx Cxxxxxx XXXX XXXXXX Axxxx GND PG-FP4 (Flash Pro4) XXXXX XXX YYY STATVE /RESET SI/RxD Dedicated flash programmer SO/TxD CLK H/S PD78F0148 (5) UART6 Transfer rate: 4800 to 76800 bps Figure 28-13. Communication with Dedicated Flash Programmer (UART6) VPP VDD GND XXXX YYYY VPP VDD VSS RESET TxD6 RxD6 X1 X2 Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE /RESET SI/RxD www..com XXXX Dedicated flash programmer SO/TxD CLK PD78F0148 User's Manual U15947EJ2V0UD 507 CHAPTER 28 PD78F0148 If Flashpro III/Flashpro IV is used as the dedicated flash programmer, Flashpro III/Flashpro IV generates the following signal for the PD78F0148. For details, refer to the Flashpro III/Flashpro IV Manual. Table 28-5. Pin Connection Flashpro III/Flashpro IV Signal Name VPP VDD GND CLK /RESET SI/RxD SO/TxD SCK H/S I/O Output I/O - Output Output Input Output Output Input Write voltage VDD voltage generation/voltage monitor Ground Clock output to PD78F0148 Reset signal Receive signal Transmit signal Transfer clock Handshake signal Note 1 PD78F0148 Pin Name VPP VDD, EVDD, AVREF VSS, EVSS, AVSS X1, X2 Note 2 Connection CSI00 UART0 UART6 Pin Function RESET SO10/TxD0/TxD6 SI10/RxD0/RxD6 SCK10 HS x x x Notes 1. Flashpro III only 2. For off-board writing only: connect the clock output of the flash programmer to X1 and its inverse signal to X2. Remark : Be sure to connect the pin. : The pin does not have to be connected if the signal is generated on the target board. x: The pin does not have to be connected. www..com : In handshake mode 508 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 28.6 Processing of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be processed as described below. 28.6.1 VPP pin In the normal operation mode, the VPP pin is connected to VSS. In addition, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin in the flash memory programming mode. Perform the following pin processing. (1) Connect pull-down resistor RVPP = 10 k to the VPP pin. (2) Switch the input of the VPP pin to the programmer side by using a jumper on the board or to GND directly. Figure 28-14. Example of Connection of VPP Pin PD78F0148 Dedicated flash programmer connection pin VPP Pull-down resistor (RVPP) www..com User's Manual U15947EJ2V0UD 509 CHAPTER 28 PD78F0148 28.6.2 Serial interface pins The pins used by each serial interface are listed below. Table 28-6. Pins Used by Each Serial Interface Serial Interface CSI10 CSI10 + HS UART0 UART0 + HS UART6 Pins Used SO10, SI10, SCK10 SO10, SI10, SCK10, HS/P15 TxD0, RxD0 TxD0, RxD0, HS/P15 TxD6, RxD6 To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. (1) Signal collision If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 28-15. Signal Collision (Input Pin of Serial Interface) PD78F0148 www..com Signal collision Input pin Dedicated flash programmer connection pin Other device Output pin In the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. Therefore, isolate the signal of the other device. 510 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, isolate the connection with the other device. Figure 28-16. Malfunction of Other Device PD78F0148 Dedicated flash programmer connection pin Other device Input pin Pin If the signal output by the PD78F0148 in the flash memory programming mode affects the other device, isolate the signal of the other device. PD78F0148 Dedicated flash programmer connection pin Other device Input pin www..com Pin If the signal output by the dedicated flash programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. User's Manual U15947EJ2V0UD 511 CHAPTER 28 PD78F0148 28.6.3 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash programmer. Figure 28-17. Signal Collision (RESET Pin) PD78F0148 Signal collision RESET Dedicated flash programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer. Therefore, isolate the signal of the reset signal generator. 28.6.4 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port www..com status immediately after reset, the port pin must be connected to VDD or VSS via a resistor. 28.6.5 REGC pin Handle the REGC pin in the same manner as during normal operation. * PD78F0148, 78F0148(A): Connect directly to VDD or connect to GND via a 1 F capacitor * PD78F0148(A1): 28.6.6 Other signal pins Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock. To input the operating clock from the programmer, however, connect the clock out of the programmer to X1, and its inverse signal to X2. 28.6.7 Power supply To use the supply voltage output of the flash programmer, connect the VDD pin to VDD of the flash programmer, and the VSS pin to VSS of the flash programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode. Supply the same other power supplies (EVDD, EVSS, AVREF, and AVSS) as those in the normal operation mode. Caution In the dedicated flash programmer PG-FP3 or FL-PR3, VDD has a power monitor function. Be sure to connect VDD and VSS to VDD and GND of the dedicated flash programmer. Connect directly to VDD 512 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 28.7 Programming Method 28.7.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 28-18. Flash Memory Manipulation Procedure Start VPP pulse supply Flash memory programming mode is set Selecting communication mode Manipulate flash memory End? Yes End www..com No User's Manual U15947EJ2V0UD 513 CHAPTER 28 PD78F0148 28.7.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the PD78F0148 in the flash memory programming mode. To set the mode, set the VPP pin and clear the reset signal. Change the mode by using a jumper when writing the flash memory on-board. Figure 28-19. Flash Memory Programming Mode VPP pulse 10.0 V VPP VDD VSS RESET Flash memory programming mode 1 2 *** n VPP VSS 10.0 V Normal operation mode Operation mode Flash memory programming mode 28.7.3 Selecting communication mode In the PD78F0148 a communication mode is selected by inputting pulses (up to 11 pulses) to the VPP pin after the dedicated flash memory programming mode is entered. These VPP pulses are generated by the flash programmer. The following table shows the relationship between the number of pulses and communication modes. www..com Table 28-7. Communication Modes Communication Mode Port (COMM PORT) 3-wire serial I/O (CSI10) 3-wire serial I/O with handshake supported (CSI10 + HS) UART (UART0) UART (UART6) UART with handshake supported (UART0 + HS) SIO-ch0 (SIO ch-0) SIO-H/S (SIO ch-3 + handshake) UART-ch0 (UART ch-0) UART-ch1 (UART ch-1) UART-ch3 (UART ch-3) 4800 to 38400 bpsNotes 2, 3 TxD0, RxD0, HS/P15 11 4800 to 76800 bpsNotes 2, 3 TxD6, RxD6 9 4800 to 38400 bps Notes 2, 3 Standard (TYPE) SettingNote 1 Speed (SIO CLOCK) 200 k to 2 MHzNote 2 200 k to 2 MHzNote 2 On Target (CPU CLOCK) Optional Frequency (Flashpro Clock) 2 M to 10 MHz Multiply Rate (Multiple Rate) 1.0 Pins Used Number of VPP Pulses SO10, SI10, SCK10 SO10, SI10, SCK10, HS/P15 TxD0, RxD0 0 3 8 Notes 1. Selection items for Standard settings on Flashpro IV (TYPE settings on Flashpro III). 2. The possible setting range differs depending on the voltage. For details, refer to the chapters of electrical specifications. 3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. Caution When UART0 or UART6 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the VPP pulse has been received. Remark Items enclosed in parentheses in the setting item column are the set value and set item when they differ from those of Flashpro IV. 514 User's Manual U15947EJ2V0UD CHAPTER 28 PD78F0148 28.7.4 Communication commands The PD78F0148 communicates with the dedicated flash programmer by using commands. The signals sent from the flash programmer to the PD78F0148 are called commands, and the commands sent from the PD78F0148 to the dedicated flash programmer are called response commands. Figure 28-20. Communication Commands Command XXXX YYYY Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx Dedicated flash programmer Response command PD78F0148 The flash memory control commands of the PD78F0148 are listed in the table below. All these commands are issued from the programmer and the PD78F0148 perform processing corresponding to the respective commands. Table 28-8. Flash Memory Control Commands Classification Verify Command Name Batch verify command Function Compares the contents of the entire memory with the input data. Erase Blank check Data write www..com Batch erase command Batch blank check command High-speed write command Erases the contents of the entire memory. Checks the erasure status of the entire memory. Writes data by specifying the write address and number of bytes to be written, and executes a verify check. Successive write command Writes data from the address following that of the high-speed write command executed immediately before, and executes a verify check. System setting, control Status read command Oscillation frequency setting command Erase time setting command Write time setting command Baud rate setting command Silicon signature command Reset command Obtains the operation status Sets the oscillation frequency Sets the erase time for batch erase Sets the write time for writing data Sets the baud rate when UART is used Reads the silicon signature information Escapes from each status The PD78F0148 return a response command for the command issued by the dedicated flash programmer. The response commands sent from the PD78F0148 are listed below. Table 28-9. Response Commands Command Name ACK NAK Function Acknowledges command/data. Acknowledges illegal command/data. User's Manual U15947EJ2V0UD 515 CHAPTER 29 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KF1 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). 29.1 Conventions Used in Operation List 29.1.1 Operand identifiers and specification methods Operands are written in the "Operand" column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for specification. www..com Table 29-1. Operand Identifiers and Specification Methods Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Specification Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol Note Note Special function register symbol (16-bit manipulatable register even addresses only) FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even address only) 0000H to FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3 Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special function register symbols, see Table 3-5 Special Function Register List. 516 User's Manual U15947EJ2V0UD CHAPTER 29 INSTRUCTION SET 29.1.2 Description of operation column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: RBS: IE: NMIS: ( ): www..com A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non-maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : : Logical sum (OR) Exclusive logical sum (exclusive OR) : Inverted data Signed 8-bit data (displacement value) addr16: 16-bit immediate data or label jdisp8: 29.1.3 Description of flag operation column (Blank): Not affected 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored User's Manual U15947EJ2V0UD 517 CHAPTER 29 INSTRUCTION SET 29.2 Operation List Instruction Group 8-bit data transfer Clocks Note 1 Note 2 Mnemonic MOV Operands r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] Note 3 Bytes 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 Note 3 Operation r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A (HL + B) (HL + B) A A (HL + C) (HL + C) A Ar A (saddr) A (sfr) x x Flag Z AC CY 4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8 - 7 7 - - 5 5 5 5 9+n 9+m 7 5 5 5+n 5+m 5+n 5+m 9+n 9+m 7+n 7+m 7+n 7+m - 6 6 Note 3 x x x x www..com [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A XCH A, r A, saddr A, sfr A, !addr16 A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 1 2 2 3 1 1 2 2 2 10 + n + m A (addr16) 6 + n + m A (DE) 6 + n + m A (HL) 10 + n + m A (HL + byte) 10 + n + m A (HL + B) 10 + n + m A (HL + C) Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. 518 User's Manual U15947EJ2V0UD CHAPTER 29 INSTRUCTION SET Instruction Group 16-bit data transfer Mnemonic MOVW Operands rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX Note 3 Bytes 3 4 4 2 2 2 2 1 1 3 3 Note 3 Clocks Note 1 Note 2 Operation rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX Flag Z AC CY 6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 10 10 8 8 8 8 - - Note 3 12 + 2n AX (addr16) 12 + 2m (addr16) AX - - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x XCHW 8-bit operation ADD AX, rp A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] 1 2 3 Note 4 2 2 2 3 1 2 2 2 2 3 www..com A, [HL + C] ADDC A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 4 2 2 2 3 1 2 2 2 Notes 1. 2. 3. 4. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Only when rp = BC, DE or HL Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. User's Manual U15947EJ2V0UD 519 CHAPTER 29 INSTRUCTION SET Instruction Group 8-bit operation Mnemonic SUB Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Bytes 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 Clocks Note 1 Note 2 Operation A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flag Z AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n SUBC A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 2 2 2 3 1 2 2 2 2 3 AND www..com A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 2 2 2 3 1 2 2 2 Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 520 User's Manual U15947EJ2V0UD CHAPTER 29 INSTRUCTION SET Instruction Group 8-bit operation Mnemonic OR Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Bytes 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 Clocks Note 1 Note 2 Operation A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A - byte (saddr) - byte A-r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flag Z AC CY 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n XOR A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 2 2 2 3 1 2 2 2 2 3 CMP www..com A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 x x x x x x x x x x x x x x x x x x x x 2 2 2 3 1 2 2 2 Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. User's Manual U15947EJ2V0UD 521 CHAPTER 29 INSTRUCTION SET Instruction Group 16-bit operation Mnemonic ADDW SUBW CMPW Operands AX, #word AX, #word AX, #word X C r saddr Bytes 3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2 2 2 6 6 6 16 25 2 4 2 4 4 4 2 2 2 2 Clocks Note 1 Note 2 Operation AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time x x x x x x x Flag Z AC CY x x x x x x - - - - - - 6 - 6 - - - - - - Multiply/ divide Increment/ decrement MULU DIVUW INC x x x x DEC r saddr INCW DECW Rotate ROR ROL RORC ROLC ROR4 ROL4 BCD adjustment www..com rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL] x x x x 10 12 + n + m A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 10 12 + n + m A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 4 4 6 - 4 - 6 6 - 4 - 6 - - 7 7 - 7 7+n 8 8 - 8 Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY x x x x x x x x x x x x x ADJBA ADJBS MOV1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY Bit manipulate 3 3 2 3 2 3 3 2 3 2 8 + n + m (HL).bit CY Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. 522 User's Manual U15947EJ2V0UD CHAPTER 29 INSTRUCTION SET Instruction Group Bit manipulate Mnemonic AND1 Operands CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit Bytes 3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1 6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2 Clocks Note 1 Note 2 Operation CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 CY 1 CY 0 CY CY x x Flag Z AC CY x x x x x x x x x x x x x x x 7 7 - 7 7+n 7 7 - 7 7+n 7 7 - 7 7+n 6 8 - 6 OR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x 8 + n + m (HL).bit 1 6 8 - 6 - - - CLR1 www..com saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x 8 + n + m (HL).bit 0 1 0 x SET1 CLR1 NOT1 CY CY CY Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. User's Manual U15947EJ2V0UD 523 CHAPTER 29 INSTRUCTION SET Instruction Group Call/return Mnemonic CALL CALLF Operands !addr16 !addr11 Bytes 3 2 7 5 Clocks Note 1 Note 2 Operation (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 Flag Z AC CY - - CALLT [addr5] 1 6 - (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 BRK 1 6 - (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 RET RETI RETB Stack manipulate PUSH PSW rp POP www..com 1 1 1 1 1 1 1 4 2 2 3 2 2 2 2 2 2 6 6 6 2 4 2 4 - - - 6 6 8 6 6 6 6 - - - - - - - 10 8 8 - - - - - - - PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 RRR RRR RRR PSW rp MOVW SP, #word SP, AX AX, SP Unconditional BR branch !addr16 $addr16 AX Conditional BC branch BNC BZ BNZ $addr16 $addr16 $addr16 $addr16 Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 524 User's Manual U15947EJ2V0UD CHAPTER 29 INSTRUCTION SET Instruction Group Mnemonic Operands saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 Bytes 3 4 3 3 3 4 4 3 4 3 4 4 3 4 3 2 2 3 2 1 2 2 2 2 8 - 8 - 10 10 - 8 - 10 10 - 8 - 10 6 6 8 4 2 - - 6 6 Clocks Note 1 Note 2 Operation PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit x Flag Z AC CY Conditional BT branch 9 11 - 9 11 + n 11 11 - 11 11 + n 12 12 - 12 BF saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 BTCLR saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 x x 12 + n + m PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit - - 10 - - 6 6 - - B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode DBNZ www..com B, $addr16 C, $addr16 saddr, $addr16 CPU control SEL NOP EI DI HALT STOP RBn Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. User's Manual U15947EJ2V0UD 525 CHAPTER 29 INSTRUCTION SET 29.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 [HL + B] First Operand A [HL + C] 1 None ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD SUB AND OR XOR CMP MOV XCH ADD SUB AND OR XOR CMP MOV MOV XCH MOV XCH ADD SUB AND OR XOR CMP MOV XCH ADD SUB AND OR XOR CMP ROR ROL RORC ROLC ADDC ADDC SUBC SUBC ADDC ADDC SUBC SUBC r MOV MOV ADD ADDC SUB SUBC AND OR INC DEC www..com XOR CMP B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP [DE] [HL] MOV MOV ROR4 ROL4 [HL + byte] [HL + B] [HL + C] X C MULU DIVUW MOV MOV MOV DBNZ INC DEC DBNZ Note Except r = A 526 User's Manual U15947EJ2V0UD CHAPTER 29 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand First Operand AX ADDW SUBW CMPW rp MOVW MOVW Note #word AX rp Note sfrp saddrp !addr16 SP None MOVW XCHW MOVW MOVW MOVW MOVW INCW DECW PUSH POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand www..com A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None First Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 User's Manual U15947EJ2V0UD 527 CHAPTER 29 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ AX !addr16 !addr11 [addr5] $addr16 (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP www..com 528 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Target products: PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A) Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD EVDD REGC VSS EVSS AVREF AVSS VPP Input voltage VI1 Conditions Ratings -0.3 to +6.5 -0.3 to +6.5 -0.3 to +6.5 -0.3 to +0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 Note 1 Unit V V V V V V V V Note 1 PD78F0148, 78F0148(A) only, Note 2 P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, X1, X2, XT1, XT2, RESET -0.3 to +10.5 -0.3 to VDD + 0.3 V VI2 www..com P62, P63 N-ch open drain On-chip pull-up resistor -0.3 to +13 -0.3 to VDD + 0.3 -0.3 to +10.5 -0.3 to VDD + 0.3 Note 1 Note 1 V V V VI3 VPP in flash programming mode (PD78F0148, 78F0148(A) only) Output voltage Analog input voltage VO VAN V Note 1 AVSS - 0.3 to AVREF + 0.3 and -0.3 to VDD + 0.3 -10 P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 P10 to P17, P30 to P33, P120, P130, P140, P141 -30 -30 V Note 1 Output current, high IOH Per pin Total of all pins -60 mA mA mA mA Note 1. Must be 6.5 V or lower. (See Note 2 on the next page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 529 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Per pin Conditions P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 Total of all pins 70 mA P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Operating ambient temperature Storage temperature Tstg TA In normal operation mode In flash memory programming mode -40 to +85 -10 to +85 -65 to +150 -40 to +125 C C 35 mA 30 35 mA mA Ratings 20 Unit mA PD780143, 780144, 780146, 780148, 780143(A), 780144(A), 780146(A), 780148(A) PD78F0148, 78F0148(A) Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (2.7 V) of the operating voltage range (15 s if the supply voltage is dropped by the regulator) (see a in the figure below). www..com * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.7 V) of the operating voltage range of VDD (see b in the figure below). 2.7 V 0V a b VDD VPP 2.7 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 530 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) X1 Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fXP) Note 1 Conditions When a capacitor is connected to the REGC pin Note 2 MIN. 2.0 TYP. MAX. 8.38 Unit MHz VSS X1 X2 4.0 V VDD < 5.5 V C1 C2 When the REGC pin is connected directly to VDD 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V 4.0 V VDD < 5.5 V 2.0 2.0 2.0 2.0 10 8.38 5.0 8.38 MHz Crystal resonator VSS X1 X2 Oscillation frequency (fXP) Note 1 When a capacitor is connected to the REGC pin Note 2 MHz C1 C2 When the REGC pin is connected directly to VDD 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V 2.0 2.0 2.0 2.0 2.0 2.0 46 56 96 10 8.38 5.0 10 8.38 5.0 500 500 500 MHz External clock Note 3 X1 input X1 X2 4.0 V VDD 5.5 V Note 1 MHz frequency (fXP) 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V X1 input high/low-level width (tXPH, tXPL) 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V ns www..com Notes 1. 2. 3. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Connect the REGC pin directly to VDD. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the Ring-OSC after reset is released, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. User's Manual U15947EJ2V0UD 531 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Ring-OSC Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator On-chip Ring-OSC oscillator Parameter Oscillation frequency (fR) Conditions MIN. 120 TYP. 240 MAX. 480 Unit kHz Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT) Note Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz VSS XT2 Rd C4 XT1 C3 External clock XT2 XT1 XT1 input frequency (fXT) Note 32 38.5 kHz XT1 input high-/low-level width (tXTH, tXTL) 12 15 s Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken www..com lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 532 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Recommended Oscillator Constants Caution For the resonator selection of the PD780143(A), 780144(A), 780146(A), 780148(A), and 78F0148(A) and oscillator constants, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (a) PD780143, 780144, 780146, 780148 X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Part Number SMD/ Lead Frequency (MHz) Recommended Circuit Constants Oscillation Voltage Range When Capacitor Is Connected to Note REGC Pin MIN. (V) 4.0 MAX. (V) 5.5 REGC Pin Is Connected Directly to VDD MIN. (V) 2.7 MAX. (V) 5.5 C1 (pF) Murata Mfg. CSTCC2M00G56-R0 CSTCR4M00G53-R0 CSTCR4M00G53U-R0 CSTLS4M00G53-B0 CSTLS4M00G53U-B0 CSTCR4M19G53-R0 CSTCR4M19G53U-R0 CSTLS4M19G53-B0 CSTLS4M19G53U-B0 CSTCR4M91G53-R0 CSTCR4M91G53U-R0 www..com C2 (pF) Internal (47) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (10) Internal (15) Internal (10) Internal (15) SMD SMD Lead SMD Lead SMD Lead SMD Lead SMD Lead SMD Lead SMD Lead 2.00 4.00 Internal (47) Internal (15) Internal (15) 4.194 Internal (15) Internal (15) 4.915 Internal (15) Internal (15) CSTLS4M91G53-B0 CSTLS4M91G53U-B0 CSTCR5M00G53-R0 CSTCR5M00G53U-R0 CSTLS5M00G53-B0 CSTLS5M00G53U-B0 CSTCR6M00G53-R0 CSTCR6M00G53U-R0 CSTLS6M00G53-B0 CSTLS6M00G53U-B0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 CSTLS8M00G53U-B0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTLS10M0G53U-B0 5.00 Internal (15) Internal (15) 6.00 Internal (15) Internal (15) 8.00 Internal (10) Internal (15) 10.0 Internal (10) Internal (15) - - Note When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User's Manual U15947EJ2V0UD 533 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (b) PD78F0148 X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Part Number SMD/ Lead Frequency (MHz) Recommended Circuit Constants Oscillation Voltage Range When Capacitor Is Connected to Note REGC Pin MIN. (V) 4.0 MAX. (V) 5.5 REGC Pin Is Connected Directly to VDD MIN. (V) 2.7 MAX. (V) 5.5 C1 (pF) Murata Mfg. CSTCC2M00G56-R0 CSTCR4M00G55-R0 CSTCR4M00G55U-R0 CSTLS4M00G56-B0 CSTLS4M00G56U-B0 CSTCR4M19G55-R0 CSTCR4M19G55U-R0 CSTLS4M19G56-B0 CSTLS4M19G56U-B0 CSTCR4M91G53-R0 CSTCR4M91G53U-R0 CSTLS4M91G53-B0 CSTLS4M91G53U-B0 CSTCR5M00G53-R0 www..com C2 (pF) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) Internal (10) Internal (15) Internal (10) Internal (15) SMD SMD 2.00 4.00 Internal (47) Internal (39) Internal (47) Lead SMD 4.194 Internal (39) Internal (47) Lead SMD 4.915 Internal (15) Internal (15) Lead SMD 5.00 CSTCR5M00G53U-R0 CSTLS5M00G53-B0 CSTLS5M00G53U-B0 CSTCR6M00G53-R0 CSTCR6M00G53U-R0 CSTLS6M00G53-B0 CSTLS6M00G53U-B0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 CSTLS8M00G53U-B0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTLS10M0G53U-B0 SMD Lead 10.0 SMD Lead 8.00 Lead SMD 6.00 Lead Internal (15) Internal (15) Internal (15) Internal (15) Internal (10) Internal (15) Internal (10) Internal (15) - - Note When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. 534 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (1/4) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Per pin Total of P10 to P17, P30 to P33, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 All pins Output current, low IOL Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Per pin for P60 to P63 Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, www..com Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V MIN. TYP. MAX. -5 -25 Unit mA mA 4.0 V VDD 5.5 V -25 mA 2.7 V VDD < 4.0 V 4.0 V VDD 5.5 V -10 10 mA mA 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 15 30 mA mA 4.0 V VDD 5.5 V 30 mA P142 to P145 All pins Input voltage, high VIH1 2.7 V VDD < 4.0 V 0.7VDD 10 VDD mA V P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIH2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note 0.8VDD VDD V VIH3 VIH4 VIH5 P20 to P27 P60, P61 P62, P63 0.7AVREF 0.7VDD N-ch open drain On-chip pull-up resistor (mask ROM version only) 0.7VDD 0.7VDD VDD - 0.5 0 AVREF VDD 12 VDD V V V V VIH6 Input voltage, low VIL1 X1, X2, XT1, XT2 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VDD 0.3VDD V V VIL2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note 0 0.2VDD V VIL3 VIL4 VIL5 VIL6 P20 to P27 P60, P61 P62, P63 0 0 0 0 0.3AVREF 0.3VDD 0.3VDD 0.4 V V V V X1, X2, XT1, XT2 Note When used as digital input ports, set AVREF = VDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 535 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (2/4) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Symbol VOH Conditions Total of P10 to P17, P30 to P33, P120, P130, P140, P141 IOH = -25 mA Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 IOH = -25 mA IOH = -100 A Output voltage, low VOL1 Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 IOL = 30 mA Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 IOL = 30 mA IOL = 400 A VOL2 Input leakage current, high www..com MIN. TYP. MAX. Unit V 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -5 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -5 mA V 2.7 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 10 mA VDD - 0.5 1.3 V V 4.0 V VDD 5.5 V, IOL = 10 mA 1.3 V 2.7 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 15 mA P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET P20 to P27 X1, X2 Note 1 0.4 2.0 3 V V P60 to P63 VI = VDD ILIH1 A VI = AVREF ILIH2 ILIH3 Input leakage current, low ILIL1 VI = VDD VI = 12 V VI = 0 V 3 Note 1 A A A A , XT1, XT2 20 3 -3 P62, P63 (N-ch open drain) P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET X1, X2 Note 1 ILIL2 ILIL3 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value VPP supply voltage (PD78F0148, 78F0148(A) only) ILOL RL VPP1 VO = VDD VO = 0 V VI = 0 V , XT1, XT2 Note 1 -20 -3 Note 2 A A A A k V P62, P63 (N-ch open drain) 3 -3 10 0 30 100 0.2VDD In normal operation mode Notes 1. 2. When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If there is no on-chip pull-up resistor for P62 and P63 (specified by a mask option) and if port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -45 A flows during only one cycle. At all other times, the maximum leakage current is -3 A. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 536 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (3/4): PD78F0148, 78F0148(A) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply Note 1 current Symbol IDD1 X1 crystal oscillation operating Note 2 mode Conditions fXP = 10 MHz When A/D converter is stopped Notes 3, 7 VDD = 5.0 V 10% When A/D converter is Note 9 operating fXP = 8.38 MHz When A/D converter is stopped Notes 3, 8 VDD = 5.0 V 10% When A/D converter is Note 9 operating fXP = 5 MHz Note 3 VDD = 3.0 V 10% When A/D converter is stopped When A/D converter is Note 9 operating When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating MIN. TYP. MAX. Unit 14.0 15.0 8.4 9.4 4.6 5.2 2.0 26.2 28.2 15.8 17.8 8.2 9.4 4.0 9.9 1 2 6.85 0.44 0.88 2.6 0.53 0.40 130 98 2.12 1.60 260 196 mA mA mA mA mA mA mA mA mA mA mA mA mA mA IDD2 X1 crystal oscillation HALT mode fXP = 10 MHz Note 7 VDD = 5.0 V 10% fXP = 8.38 MHz Note 8 VDD = 5.0 V 10% fXP = 5 MHz VDD = 3.0 V 10% IDD3 Ring-OSC operating Note 4 mode VDD = 5.0 V 10% VDD = 3.0 V 10% IDD4 www..com VDD = 5.0 V 10% 32.768 kHz crystal oscillation VDD = 3.0 V 10% operating Notes 4, 6 mode VDD = 5.0 V 10% 32.768 kHz crystal oscillation VDD = 3.0 V 10% Notes 4, 6 HALT mode STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 5 A A A A A A A A A A A A IDD5 20 6 0.1 14 3.5 17.5 0.05 7.5 3.5 11 40 12 30 58 35.5 63.5 10 25 15.5 30.5 IDD6 , RING: OFF , RING: ON POC: ON VDD = 3.0 V 10% Note 5 POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 5 , RING: OFF , RING: ON POC: ON Note 5 Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 in the PD78F0148M1, 78F0148M2, 78F0148M1(A), and 78F0148M2(A). When the PD78F0148M1, 78F0148M2, 78F0148M1(A), and 78F0148M2(A) (including LVIE = 0) are selected and Ring-OSC oscillation is stopped. When the REGC pin is connected directly to VDD. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Including the current that flows through the AVREF pin. User's Manual U15947EJ2V0UD 537 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (4/4): PD780143, 780144, 780146, 780148, 780143(A), 780144(A), 780146(A), 780148(A) (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal oscillation operating mode Note 2 Conditions fXP = 10 MHz When A/D converter is stopped Notes 3, 7 VDD = 5.0 V 10% When A/D converter is operating Note 9 MIN. TYP. MAX. Unit 7.7 8.7 15.4 17.4 mA mA fXP = 8.38 MHz When A/D converter is stopped Notes 3, 8 VDD = 5.0 V 10% When A/D converter is operating fXP = 5 MHz Note 3 VDD = 3.0 V 10% Note 9 4.3 5.3 9.5 11.5 mA mA When A/D converter is stopped When A/D converter is operating Note 9 2.2 2.8 4.4 5.6 mA mA IDD2 X1 crystal oscillation HALT mode fXP = 10 MHz Note 7 VDD = 5.0 V 10% fXP = 8.38 MHz Note 8 VDD = 5.0 V 10% fXP = 5 MHz VDD = 3.0 V 10% When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating 1.7 3.4 8.1 mA mA mA mA mA mA mA mA 0.85 1.71 5.59 0.33 0.66 2 IDD3 Ring-OSC operating mode Note 4 VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% 0.28 0.17 38 17 1.12 0.68 76 34 IDD4 www..com 32.768 kHz A A crystal oscillation VDD = 3.0 V 10% operating mode IDD5 Notes 4, 6 32.768 kHz VDD = 5.0 V 10% 20 6 POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON POC: ON Note 5 40 12 30 58 35.5 63.5 10 25 15.5 30.5 A A A A A A A A A A crystal oscillation VDD = 3.0 V 10% Notes 4, 6 HALT mode IDD6 STOP mode VDD = 5.0 V 10% 0.1 14 3.5 17.5 0.05 7.5 3.5 11 , RING: OFF , RING: ON Note 5 VDD = 3.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON POC: ON Note 5 , RING: OFF , RING: ON Note 5 Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. When POC-OFF (including LVIE = 0) is selected by a mask option and Ring-OSC oscillation is stopped. When the REGC pin is connected directly to VDD. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). Including the current that flows through the AVREF pin. User's Manual U15947EJ2V0UD 538 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Main system clock operation Ring-OSC clock Subsystem clock operation TI000, TI010, TI001 TI011 Note 3 Note 3 Conditions X1 input clock Note 1 Note 2 MIN. 4.0 V VDD 5.5 V 0.238 4.0 V VDD 5.5 V 0.2 TYP. MAX. 16 16 16 16 Unit s s s s s s s s 3.3 V VDD < 4.0 V 0.238 2.7 V VDD < 3.3 V 0.4 4.17 114 2/fsam + 0.1 Note 4 8.33 122 16.67 125 , tTIH0, 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V input high-level width, tTIL0 low-level width 2/fsam + 0.2 Note 4 TI50, TI51 input frequency fTI5 10 5 50 100 1 MHz MHz ns ns TI50, TI51 input high-level width, tTIH5, low-level width Interrupt input high-level width, low-level width Key return input low-level width www..com 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V tTIL5 tINTH, tINTL tKR s ns ns 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 50 100 10 RESET low-level width tRSL s Notes 1. 2. 3. 4. When the REGC pin is connected to VSS via a capacitor (1 F: recommended). When the REGC pin is connected directly to VDD. PD780146, 780148, 78F0148, 780146(A), 780148(A), and 78F0148(A) only. Selection of fsam = fXP, fXP/4, fXP/256, or fXP, fXP/16, fXP/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fXP. User's Manual U15947EJ2V0UD 539 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) TCY vs. VDD (X1 Input Clock Operation) (a) When REGC pin is connected to VSS via capacitor (1 F: recommended) 20.0 16.0 10.0 Cycle time TCY [ s] 5.0 2.0 1.0 Guaranteed operation range 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD [V] www..com (b) When REGC pin is connected directly to VDD 20.0 16.0 10.0 Cycle time TCY [ s] 5.0 2.0 1.0 Guaranteed operation range 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 2.7 3.3 4.0 5.0 5.5 6.0 Supply voltage VDD [V] 540 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Read/write operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1/2) Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Address output time from RD Data input time from RD tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width www..com Conditions MIN. 0.3tCY 20 6 MAX. Unit ns ns ns (2 + 2n)tCY - 54 (3 + 2n)tCY - 60 0 100 (2 + 2n)tCY - 87 (3 + 2n)tCY - 93 0 (1.5 + 2n)tCY - 33 (2.5 + 2n)tCY - 33 tCY - 43 tCY - 43 tCY - 25 (0.5 + 2n)tCY + 10 60 6 (1.5 + 2n)tCY - 15 6 2tCY - 15 0.8tCY - 15 0.8tCY - 15 1.2tCY (2 + 2n)tCY ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR Delay time from WAIT to RD Delay time from WAIT to WR tRDADH 1.2tCY + 30 ns tRDWD tWRWD tWRADH tWTRD tWTWR 40 10 0.8tCY - 15 0.8tCY 0.8tCY 60 1.2tCY + 30 2.5tCY + 25 2.5tCY + 25 ns ns ns ns ns Caution TCY can only be used at 0.238 s (MIN). Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) User's Manual U15947EJ2V0UD 541 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Read/write operation (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (2/2) Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width www..com Conditions MIN. 0.3tCY 30 10 MAX. Unit ns ns ns (2 + 2n)tCY - 108 (3 + 2n)tCY - 120 0 200 (2 + 2n)tCY - 148 (3 + 2n)tCY - 162 0 (1.5 + 2n)tCY - 40 (2.5 + 2n)tCY - 40 tCY - 75 tCY - 60 tCY - 50 (0.5 + 2n)tCY + 10 60 10 (1.5 + 2n)tCY - 30 10 2tCY - 30 0.8tCY - 30 0.8tCY - 30 1.2tCY (2 + 2n)tCY ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Hold time from RD to address at external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDADH 1.2tCY + 60 ns tRDWD tWRWD tWRADH tWTRD tWTWR 40 20 0.8tCY - 30 0.5tCY 0.5tCY 120 1.2tCY + 60 2.5tCY + 50 2.5tCY + 50 ns ns ns ns ns Caution TCY can only be used at 0.4 s (MIN). Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) 542 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (3) Serial interface (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps (b) UART mode (UART0, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps (c) 3-wire serial I/O mode (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V SCK1n high-/low-level width SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to www..com MIN. 200 240 400 tKCY1/2 - 10 TYP. MAX. Unit ns ns ns ns tKH1, tKL1 tSIK1 tKSI1 tKSO1 C = 100 pF Note 30 30 30 ns ns ns SO1n output Note C is the load capacitance of the SCK1n and SO1n output lines. (d) 3-wire serial I/O mode (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 C = 100 pF Note Conditions MIN. 400 tKCY2/2 TYP. MAX. Unit ns ns 80 50 120 ns ns ns Note C is the load capacitance of the SO1n output line. Remark PD780143, 780144, 780143(A), 780144(A) n = 0, 1: PD780146, 780148, 78F0148, 780146(A), 780148(A), 78F0148(A) n = 0: User's Manual U15947EJ2V0UD 543 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter SCKA0 cycle time Symbol tKCY3 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V SCKA0 high-/low-level width tTH3, tTL3 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V SIA0 setup time (to SCKA0) SIA0 hold time (from SCKA0) Delay time from SCKA0 to SOA0 output Time from SCKA0 to STB0 Strobe signal high-level width tSBD tSBW 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) Time from busy inactive to SCKA0 tSPS tBYH 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 100 150 2tKCY3 ns ns ns tBYS tSIK3 tKSI3 tKSO3 C = 100 pF Note MIN. 600 1200 tKCY3/2 - 50 tKCY3/2 - 100 100 300 TYP. MAX. Unit ns ns ns ns ns ns 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V tKCY3/2 - 100 tKCY3 - 30 tKCY3 - 60 100 200 300 ns ns ns ns ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. (f) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0 ... external clock input) Parameter SCKA0 cycle time Symbol tKCY4 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V SCKA0 high-/low-level width tKH4, tKL4 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V SIA0 setup time (to SCKA0) SIA0 hold time (from SCKA0) Delay time from SCKA0 to SOA0 output SCKA0 rise/fall time tR4, tF4 tSIK4 tKSI4 tKSO4 C = 100 pF Note www..com MIN. 600 1200 300 600 100 300 TYP. MAX. Unit ns ns ns ns ns ns 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 200 300 120 ns ns ns When external device expansion function is used When external device expansion function is not used 1000 ns Note C is the load capacitance of the SOA0 output line. 544 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD 0.2VDD Test points Clock Timing 1/fXP tXPL tXPH X1 input VIH6 (MIN.) VIL6 (MAX.) 1/fXT tXTL tXTH VIH6 (MIN.) VIL6 (MAX.) XT1 input TI Timing www..com tTIL0 tTIH0 TI00, TI010, TI001Note, TI011Note 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Note PD780146, 780148, 78F0148, 780146(A), 780148(A), and 78F0148(A) only. User's Manual U15947EJ2V0UD 545 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) RESET Input Timing tRSL RESET Read/Write Operation External fetch (no wait): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Lower 8-bit address tADS tASTH ASTB tADH Hi-Z tRDAD tRDD1 Instruction code tRDADH tRDAST RD tASTRD www..com tRDL1 tRDH External fetch (wait insertion): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Lower 8-bit address tADS tASTH ASTB tADH tRDAD Hi-Z tRDD1 Instruction code tRDADH tRDAST RD tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH 546 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) External data access (no wait): A8 to A15 tADD2 AD0 to AD7 Lower 8-bit address tADS tASTH ASTB tADH Hi-Z tRDAD tRDD2 Read data Write data Hi-Z Higher 8-bit address tRDH RD tASTRD WR tASTWR tWRL1 tRDL2 tRDWD tWRWD tWDS tWDH tWRADH External data access (wait insertion): A8 to A15 tADD2 AD0 to AD7 www..com Higher 8-bit address Lower 8-bit address Hi-Z Read data tRDH Write data Hi-Z tADS tADH tASTH ASTB tRDAD tRDD2 tASTRD RD tRDL2 tRDWD tWRWD tWDS tWDH WR tASTWR WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR tWRL1 tWRADH User's Manual U15947EJ2V0UD 547 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK1n tSIKm tKSIm SI1n Input data tKSOm SO1n Output data Remark www..com m = 1, 2 n = 0: PD780143, 780144, 780143(A), 780144(A) n = 0, 1: PD780146, 780148, 78F0148, 780146(A), 780148(A), 78F0148(A) 548 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 D2 D1 D0 D7 SIA0 D2 tSIK3, 4 tKSO3, 4 D1 tKSI3, 4 tKH3, 4 tF4 D0 D7 SCKA0 tR4 tKL3, 4 tKCY3, 4 STB0 tSBD tSBW 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCKA0 7 8 9Note 10Note tBYH 10+nNote tSPS 1 tBYS www..com BUSY0 (active-high) Note The signal is not actually driven low here; it is shown as such to indicate the timing. User's Manual U15947EJ2V0UD 549 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) A/D Converter Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.4 0.6 100 100 0.4 0.6 0.4 0.6 2.5 4.5 1.5 2.0 Unit bit %FSR %FSR 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Conversion time tCONV 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 14 17 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V Zero-scale error Notes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Full-scale error Notes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Integral non-linearity error Note 1 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Differential non-linearity error Note 1 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Analog input voltage VIAN AVSS AVREF Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +85C) Parameter www..com Symbol VPOC0 VPOC1 Conditions Mask option = 3.5 V Note 1 MIN. 3.3 2.7 0.0015 0.002 TYP. 3.5 2.85 MAX. 3.7 3.0 Unit V V ms ms Detection voltage Mask option = 2.85 V VDD: 0 V 2.7 V VDD: 0 V 3.3 V Note 2 Power supply rise time tPTH Response delay time 1 Response delay time 2 Minimum pulse width Note 3 tPTHD tPD tPW When power supply rises, after reaching detection voltage (MAX.) When VDD falls 0.2 3.0 1.0 ms ms ms Note 3 Notes 1. When flash memory version PD78F0148M5, 78F0148M6, 78F0148M5(A), or 78F0148M6(A) is used 2. When flash memory version PD78F0148M3, 78F0148M4, 78F0148M3(A), or 78F0148M4(A) is used 3. Time required from voltage detection to reset release. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time 550 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) LVI Circuit Characteristics (TA = -40 to +85C) Parameter Detection voltage Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 Response time Note 1 Conditions MIN. 4.1 3.9 3.7 3.5 3.3 3.15 2.95 TYP. 4.3 4.1 3.9 3.7 3.5 3.3 3.1 0.2 MAX. 4.5 4.3 4.1 3.9 3.7 3.45 3.25 2.0 Unit V V V V V V V ms ms tLD tLW 0.2 Minimum pulse width Note 2 Reference voltage stabilization wait tLWAIT0 time Note 3 0.5 2.0 ms Operation stabilization wait time tLWAIT1 0.1 0.2 ms Notes 1. 2. Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by the POC mask option (when flash memory version PD78F0148M1, 78F0148M2, 78F0148M1(A), or 78F0148M2(A) is used). Time required from setting LVION to 1 to operation stabilization. 3. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 www..com 2. VPOCn < VLVIm (n = 0 and 1, m = 0 to 6) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tWAIT0 tWAIT1 tLD LVIE 1 LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol VDDDR Note Conditions When POC-OFF is selected by mask option MIN. 1.6 TYP. MAX. 5.5 Unit V Release signal set time tSREL 0 s Note When flash memory version PD78F0148M1, 78F0148M2, 78F0148M1(A), or 78F0148M2(A) is used User's Manual U15947EJ2V0UD 551 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Flash Memory Programming Characteristics: PD78F0148, 78F0148(A) (TA = +10 to +60C, 2.7 V VDD = EVDD 5.5 V, 2.7 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1) Write erase characteristics Parameter VPP supply voltage VDD supply current VPP supply current Step erase time Note 1 Symbol VPP2 IDD IPP Ter Tera Twb Cwb Conditions During flash memory programming When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V VPP = VPP2 MIN. 9.7 TYP. 10.0 MAX. 10.3 37 100 Unit V mA mA s s/chip ms Times 0.199 When step erase time = 0.2 s 49.4 When writeback time = 50 ms 0.2 0.201 20 Overall erase time Writeback time Note 2 Note 3 50 50.6 60 Number of writebacks per 1 writeback command Note 4 Number of erases/writebacks Step write time Note 5 Cerwb Twr 48 When step write time = 50 s (1 word = 1 byte) 1 erase + 1 write after erase = 1 rewrite 48 50 16 52 520 Times s s Times/ area Overall write time per word Note 6 Twrw Number of rewrites per chip Note 7 Cerwr 20 Notes 1. 2. www..com The recommended setting value of the step erase time is 0.2 s. The prewrite time before erasure and the erase verify time (writeback time) are not included. The recommended setting value of the writeback time is 50 ms. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries must be the maximum value minus the number of commands issued. The recommended setting value of the step write time is 50 s. The actual write time per word is 100 s longer. The internal verify time during or after a write is not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P: 3 rewrites 3. 4. 5. 6. 7. Shipped product E P E P E P: 3 rewrites Remark The range of the operating clock during flash memory programming is the same as the range during normal operation. 552 User's Manual U15947EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Set time from VDD to VPP Symbol tDP Conditions MIN. 10 10 2 TYP. MAX. Unit s s ms Release time from VPP to RESET tPR VPP pulse input start time from RESET VPP pulse high-/low-level width VPP pulse input end time from RESET VPP pulse low-level input voltage VPP pulse high-level input voltage tRP tPW tRPE 8 14 s ms VPPL VPPH 0.8VDD 9.7 10.0 1.2VDD 10.3 V V Flash Write Mode Setting Timing VDD VDD 0V VPPH VPP VPPL 0V www..com tDP tRP tPW tPW tPR tRPE VDD RESET (input) 0V User's Manual U15947EJ2V0UD 553 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Target products: PD780143(A1), 780144(A1), 780146(A1), 780148(A1), 78F0148(A1) Cautions 1. Be sure to connect the REGC pin of (A1) grade products directly to VDD. 2. The external bus interface function cannot be used with (A1) grade products. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD EVDD REGC VSS EVSS AVREF AVSS VPP Input voltage VI1 Conditions Ratings -0.3 to +6.5 -0.3 to +6.5 -0.3 to +6.5 -0.3 to +0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 Note 1 Unit V V V V V V V V Note 1 PD78F0148(A1) only, Note 2 P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, X1, X2, XT1, XT2, RESET -0.3 to +10.5 -0.3 to VDD + 0.3 V www..com VI2 P62, P63 N-ch open drain On-chip pull-up resistor -0.3 to +13 -0.3 to VDD + 0.3 -0.3 to +10.5 -0.3 to VDD + 0.3 Note 1 Note 1 V V V VI3 VPP in flash programming mode (PD78F0148(A1) only) Output voltage Analog input voltage VO VAN V Note 1 AVSS - 0.3 to AVREF + 0.3 and -0.3 to VDD + 0.3 -8 P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 P10 to P17, P30 to P33, P120, P130, P140, P141 -24 -24 V Note 1 Output current, high IOH Per pin Total of all pins -48 mA mA mA mA Note 1. Must be 6.5 V or lower. (Refer to Note 2 on the next page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 554 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Per pin Conditions P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 Total of all pins 56 mA P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Operating ambient temperature TA 28 -40 to +110 -40 to +105 -10 to +85 -65 to +150 -40 to +125 C mA C 24 28 mA mA Ratings 16 Unit mA PD780143(A1), 780144(A1), 780146(A1), 780148(A1) PD78F0148(A1) In normal operation mode In flash memory programming mode Storage temperature Tstg PD780143(A1), 780144(A1), 780146(A1), 780148(A1) PD78F0148(A1) Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash www..com memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (3.3 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (3.3 V) of the operating voltage range of VDD (see b in the figure below). 3.3 V 0V a b VDD VPP 3.3 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 555 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) X1 Oscillator Characteristics Note 1 , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (TA = -40 to +110C Resonator Ceramic resonator Note 2 Recommended Circuit Parameter Oscillation frequency (fXP) Note 3 Conditions 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V MIN. 2.0 2.0 2.0 TYP. MAX. 10 8.38 5.0 Unit MHz VSS X1 X2 C1 C2 3.3 V VDD < 4.0 V Crystal resonator Note 2 VSS X1 X2 Oscillation frequency (fXP) Note 3 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 2.0 2.0 2.0 10 8.38 5.0 MHz C1 C2 3.3 V VDD < 4.0 V External clock Note 2 X1 input frequency (fXP) X1 X2 Note 3 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V 2.0 2.0 2.0 46 56 96 10 8.38 5.0 500 500 500 MHz X1 input high-/low-level width (tXPH, tXPL) 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V ns Notes 1. www..com TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) Connect the REGC pin directly to VDD. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. 3. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the Ring-OSC after reset is released, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 556 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Ring-OSC Oscillator Characteristics Note (TA = -40 to +110C , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator On-chip Ring-OSC oscillator Parameter Oscillation frequency (fR) Conditions MIN. 120 TYP. 240 MAX. 490 Unit kHz Note TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) Subsystem Clock Oscillator Characteristics Note 1 , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (TA = -40 to +110C Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT) Note 2 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz VSS XT2 Rd C4 XT1 C3 External clock XT2 XT1 XT1 input frequency (fXT) Note 2 32 38.5 kHz XT1 input high-/low-level width (tXTH, tXTL) 12 15 s Notes 1. www..com TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U15947EJ2V0UD 557 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (1/6): PD78F0148(A1) (TA = -40 to +105C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Per pin Total of P10 to P17, P30 to P33, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 All pins 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Output current, low IOL Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Per pin for P60 to P63 Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, www..com Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V MIN. TYP. MAX. -4 -20 Unit mA mA 4.0 V VDD 5.5 V -20 mA -25 -8 8 mA mA mA 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 12 24 mA mA 4.0 V VDD 5.5 V 24 mA P64 to P67, P70 to P77, P142 to P145 All pins 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Input voltage, high VIH1 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIH2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET VIH3 VIH4 VIH5 VIH6 Input voltage, low VIL1 P20 to P27 P60, P61 P62, P63 X1, X2, XT1, XT2 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIL2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET VIL3 VIL4 VIL5 VIL6 P20 to P27 P60, P61 P62, P63 X1, X2, XT1, XT2 Note Note 30 8 0.7VDD VDD mA mA V 0.8VDD VDD V 0.7AVREF 0.7VDD N-ch open drain 0.7VDD VDD - 0.5 0 AVREF VDD 12 VDD 0.3VDD V V V V V 0 0.2VDD V 0 0 0 0 0.3AVREF 0.3VDD 0.3VDD 0.4 V V V V Note When used as digital input ports, set AVREF = VDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 558 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (2/6): PD78F0148(A1) (TA = -40 to +105C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Symbol VOH Conditions Total of P10 to P17, P30 to P33, P120, P130, P140, P141 IOH = -20 mA Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 IOH = -20 mA IOH = -100 A Output voltage, low VOL1 Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 IOL = 24 mA Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 IOL = 24 mA IOL = 400 A VOL2 www..com MIN. TYP. MAX. Unit V 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -4 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -4 mA V 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 8 mA VDD - 0.5 1.3 V V 4.0 V VDD 5.5 V, IOL = 8 mA 1.3 V 3.3 V VDD < 4.0 V IOL = 12 mA P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET 0.4 2.0 10 V V P60 to P63 VI = VDD Input leakage current, high ILIH1 A VI = AVREF ILIH2 ILIH3 Input leakage current, low ILIL1 VI = VDD VI = 12 V VI = 0 V P20 to P27 X1, X2 Note 1 10 Note 1 A A A A , XT1, XT2 20 20 -10 P62, P63 (N-ch open drain) P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET Note 1 Note 1 ILIL2 ILIL3 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value VPP supply voltage (PD78F0148 only) ILOL RL VPP1 VO = VDD VO = 0 V VI = 0 V X1, X2 , XT1, XT2 -20 -10 Note 2 A A A A k V P62, P63 (N-ch open drain) 10 -10 10 0 30 120 0.2VDD In normal operation mode Notes 1. 2. When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -55 A flows during only one cycle. At all other times, the maximum leakage current is -10 A. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 559 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (3/6): PD78F0148(A1) (TA = -40 to +105C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal oscillation operating mode IDD2 Note 2 Conditions fXP = 10 MHz Note 3 VDD = 5.0 V 10% When A/D converter is stopped When A/D converter is operating fXP = 10 MHz VDD = 5.0 V 10% Note 7 MIN. TYP. MAX. Unit 14.0 15.0 27.6 29.6 mA mA X1 crystal oscillation HALT mode When peripheral functions are stopped When peripheral functions are operating 2.0 5.4 mA 11.3 mA IDD3 Ring-OSC operating mode Note 4 VDD = 5.0 V 10% 0.53 3.52 mA IDD4 32.768 kHz crystal oscillation operating mode Notes 4, 6 VDD = 5.0 V 10% 130 1700 A IDD5 32.768 kHz crystal oscillation HALT mode Notes 4, 6 VDD = 5.0 V 10% 20 1400 A IDD6 STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 5 0.1 14 3.5 1400 1500 1400 A A A A , RING: OFF , RING: ON www..com POC: ON Note 5 17.5 1500 Notes 1. 2. 3. 4. 5. 6. 7. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 in the PD78F0148M1(A1) and 78F0148M2(A1). When the PD78F0148M1(A1) and 78F0148M2(A1) (including LVIE = 0) are selected and Ring-OSC oscillation is stopped. Including the current that flows through the AVREF pin. 560 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (4/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) (TA = -40 to +110C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Per pin Total of P10 to P17, P30 to P33, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 All pins Output current, low IOL Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Per pin for P60 to P63 Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, www..com Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V MIN. TYP. MAX. -4 -20 Unit mA mA 4.0 V VDD 5.5 V -20 mA 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V -8 8 mA mA 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 12 24 mA mA 4.0 V VDD 5.5 V 24 mA P142 to P145 All pins Input voltage, high VIH1 3.3 V VDD < 4.0 V 0.7VDD 8 VDD mA V P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIH2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note 0.8VDD VDD V VIH3 VIH4 VIH5 P20 to P27 P60, P61 P62, P63 0.7AVREF 0.7VDD N-ch open drain On-chip pull-up resistor 0.7VDD 0.7VDD VDD - 0.5 0 AVREF VDD 12 VDD VDD 0.3VDD V V V V V V VIH6 Input voltage, low VIL1 X1, X2, XT1, XT2 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIL2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note 0 0.2VDD V VIL3 VIL4 VIL5 VIL6 P20 to P27 P60, P61 P62, P63 0 0 0 0 0.3AVREF 0.3VDD 0.3VDD 0.4 V V V V X1, X2, XT1, XT2 Note When used as digital input ports, set AVREF = VDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 561 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (5/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) (TA = -40 to +110C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Symbol VOH Conditions Total of P10 to P17, P30 to P33, P120, P130, P140, P141 IOH = -20 mA Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 IOH = -20 mA IOH = -100 A Output voltage, low VOL1 Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 IOL = 24 mA Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 IOL = 24 mA IOL = 400 A VOL2 www..com MIN. TYP. MAX. Unit V 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -4 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -4 mA V 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 8 mA VDD - 0.5 1.3 V V 4.0 V VDD 5.5 V, IOL = 8 mA 1.3 V 3.3 V VDD < 4.0 V IOL = 12 mA P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET 0.4 2.0 10 V V P60 to P63 VI = VDD Input leakage current, high ILIH1 A VI = AVREF ILIH2 ILIH3 Input leakage current, low ILIL1 VI = VDD VI = 12 V VI = 0 V P20 to P27 X1, X2 Note 1 10 Note 1 A A A A , XT1, XT2 20 10 -10 P62, P63 (N-ch open drain) P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET Note 1 Note 1 ILIL2 ILIL3 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value ILOL RL VO = VDD VO = 0 V VI = 0 V X1, X2 , XT1, XT2 -20 -10 Note 2 A A A A k P62, P63 (N-ch open drain) 10 -10 10 30 120 Notes 1. 2. When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -55 A flows during only one cycle. At all other times, the maximum leakage current is -10 A. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 562 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (6/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) (TA = -40 to +110C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal oscillation operating mode IDD2 Note 2 Conditions fXP = 10 MHz Note 3 VDD = 5.0 V 10% When A/D converter is stopped When A/D converter is operating fXP = 10 MHz VDD = 5.0 V 10% Note 7 MIN. TYP. MAX. Unit 7.7 8.7 16.5 18.5 mA mA X1 crystal oscillation HALT mode When peripheral functions are stopped When peripheral functions are operating 1.7 4.5 mA 9.2 mA IDD3 Ring-OSC operating mode Note 4 VDD = 5.0 V 10% 0.28 2.22 mA IDD4 32.768 kHz crystal oscillation operating mode Notes 4, 6 VDD = 5.0 V 10% 38 1200 A IDD5 32.768 kHz crystal oscillation HALT mode Notes 4, 6 VDD = 5.0 V 10% 20 1100 A IDD6 STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 5 0.1 14 3.5 1100 1200 1100 A A A A , RING: OFF , RING: ON www..com POC: ON Note 5 17.5 1200 Notes 1. 2. 3. 4. 5. 6. 7. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. When POC-OFF (including LVIE = 0) is selected by a mask option and Ring-OSC oscillation is stopped. Including the current that flows through the AVREF pin. User's Manual U15947EJ2V0UD 563 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +110CNote 1, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Main system clock operation X1 input clock Conditions 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V Ring-OSC clock Subsystem clock operation TI000, TI010, TI001 TI011 Note 2 Note 2 MIN. 0.2 0.238 0.4 4.09 114 2/fsam + 0.1 Note 3 TYP. MAX. 16 16 16 Unit s s s s s s s 8.33 122 16.67 125 , tTIH0, 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V input high-level width, tTIL0 low-level width 2/fsam + 0.2 Note 3 TI50, TI51 input frequency fTI5 10 5 50 100 1 MHz MHz ns ns TI50, TI51 input high-level width, tTIH5, low-level width Interrupt input high-level width, low-level width Key return input low-level width tTIL5 tINTH, tINTL tKR 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V s ns ns 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 50 100 10 www..com RESET low-level width tRSL s Notes 1. 2. 3. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) PD780146(A1), 780148(A1), and 78F0148(A1) only. Selection of fsam = fXP, fXP/4, fXP/256, or fXP, fXP/16, fXP/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fXP. 564 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) TCY vs. VDD (X1 Input Clock Operation) 20.0 16.0 10.0 Cycle time TCY [ s] 5.0 2.0 1.0 Guaranteed operation range 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 3.3 4.0 4.5 5.0 5.5 6.0 Supply voltage VDD [V] www..com User's Manual U15947EJ2V0UD 565 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial interface Note (TA = -40 to +110C , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Note TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps (b) UART mode (UART0, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps (c) 3-wire serial I/O mode (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V SCK1n high-/low-level width SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output tKH1, tKL1 www..com MIN. 200 240 400 tKCY1/2 - 10 TYP. MAX. Unit ns ns ns ns tSIK1 tKSI1 tKSO1 C = 100 pF Note 30 30 30 ns ns ns Note C is the load capacitance of the SCK1n and SO1n output lines. (d) 3-wire serial I/O mode (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 C = 100 pF Note Conditions MIN. 400 tKCY2/2 TYP. MAX. Unit ns ns 80 50 120 ns ns ns Note C is the load capacitance of the SO1n output line. Remark n = 0: PD780143(A1), 780144(A1) n = 0, 1: PD780146(A1), 780148(A1), 78F0148(A1) 566 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter SCKA0 cycle time Symbol tKCY3 Conditions 4.5 V VDD 5.5 V 3.3 V VDD < 4.5 V SCKA0 high-/low-level width tTH3, tTL3 4.5 V VDD 5.5 V 3.3 V VDD < 4.5 V SIA0 setup time (to SCKA0) SIA0 hold time (from SCKA0) Delay time from SCKA0 to SOA0 output Time from SCKA0 to STB0 Strobe signal high-level width tSBD tSBW 4.5 V VDD 5.5 V 3.3 V VDD < 4.5 V Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) Time from busy inactive to SCKA0 tSPS tBYH 4.5 V VDD 5.5 V 3.3 V VDD < 4.5 V 100 150 2tKCY3 ns ns ns tBYS tSIK3 tKSI3 tKSO3 C = 100 pF Note MIN. 600 1200 tKCY3/2 - 50 tKCY3/2 - 100 100 300 TYP. MAX. Unit ns ns ns ns ns ns 4.5 V VDD 5.5 V 3.3 V VDD < 4.5 V tKCY3/2 - 100 tKCY3 - 30 tKCY3 - 60 100 200 300 ns ns ns ns ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. (f) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0 ... external clock input) Parameter SCKA0 cycle time Symbol tKCY4 Conditions 4.5 V VDD 5.5 V 3.3 V VDD < 4.5 V SCKA0 high-/low-level width tKH4, tKL4 4.5 V VDD 5.5 V 3.3 V VDD < 4.5 V SIA0 setup time (to SCKA0) SIA0 hold time (from SCKA0) Delay time from SCKA0 to SOA0 output SCKA0 rise/fall time tR4, tF4 tSIK4 tKSI4 tKSO4 C = 100 pF Note www..com MIN. 600 1200 300 600 100 300 TYP. MAX. Unit ns ns ns ns ns ns 4.5 V VDD 5.5 V 3.3 V VDD < 4.5 V 200 300 1000 ns ns ns Note C is the load capacitance of the SOA0 output line. User's Manual U15947EJ2V0UD 567 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD 0.2VDD Test points Clock Timing 1/fXP tXPL tXPH X1 input VIH6 (MIN.) VIL6 (MAX.) 1/fXT tXTL tXTH VIH6 (MIN.) VIL6 (MAX.) XT1 input TI Timing www..com tTIL0 tTIH0 TI00, TI010, TI001Note, TI011Note 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Note PD780146(A1), 780148(A1), and 78F0148(A1) only. 568 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) RESET Input Timing tRSL RESET Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK1n tSIKm tKSIm SI1n Input data tKSOm www..com SO1n Output data Remark m = 1, 2 n = 0: PD780143(A1), 780144(A1) n = 0, 1: PD780146(A1), 780148(A1), 78F0148(A1) User's Manual U15947EJ2V0UD 569 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 D2 D1 D0 D7 SIA0 D2 tSIK3, 4 tKSO3, 4 D1 tKSI3, 4 tKH3, 4 tF4 D0 D7 SCKA0 tR4 tKL3, 4 tKCY3, 4 STB0 tSBD tSBW 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCKA0 7 8 9Note 10Note tBYH 10+nNote tSPS 1 tBYS BUSY0 (active-high) www..com Note The signal is not actually driven low here; it is shown as such to indicate the timing. 570 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) A/D Converter Characteristics Note 1 (TA = -40 to +110C , 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 2, 3 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.6 0.8 60 60 0.6 0.8 0.6 0.8 4.5 6.5 2.0 2.5 Unit bit %FSR %FSR 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Conversion time tCONV 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V 14 19 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V Zero-scale error Notes 2, 3 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Full-scale error Notes 2, 3 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Integral non-linearity error Note 2 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Differential non-linearity error Note 2 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Analog input voltage VAIN AVSS AVREF Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. 3. www..com Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +110CNote 1) Parameter Detection voltage Power supply rise time Response delay time 1 Response delay time 2 Minimum pulse width Note 3 Symbol VPOC0 tPTH tPTHD tPD tPW Conditions Mask option = 3.5 V VDD: 0 V 3.3 V When power supply rises, after reaching detection voltage (MAX.) When VDD falls Note 2 MIN. 3.3 0.002 TYP. 3.5 MAX. 3.72 Unit V ms 3.0 1.0 0.2 ms ms ms Note 3 Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. When flash memory version PD78F0148M5(A1) or 78F0148M6(A1) is used 3. Time required from voltage detection to reset release. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time User's Manual U15947EJ2V0UD 571 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) LVI Circuit Characteristics (TA = -40 to +110CNote 1) Parameter Detection voltage Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 Response time Note 2 Conditions MIN. 4.1 3.9 3.7 3.5 3.3 TYP. 4.3 4.1 3.9 3.7 3.5 0.2 MAX. 4.52 4.32 4.12 3.92 3.72 2.0 Unit V V V V V ms ms tLD tLW 0.2 Minimum pulse width Reference voltage stabilization wait tLWAIT0 Note 3 time Operation stabilization wait time Note 4 0.5 2.0 ms tLWAIT1 0.1 0.2 ms Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. 3. 4. Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by mask option (when flash memory version PD78F0148M1(A1) or 78F0148M2(A1) is used). Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 2. VPOCn < VLVIm (n = 0 and 1, m = 0 to 4) www..com LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tWAIT0 tWAIT1 tLD LVIE 1 LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +110CNote 1) Parameter Data retention supply voltage Symbol VDDDR Note 2 Conditions When POC-OFF is selected by mask option MIN. 2.0 TYP. MAX. 5.5 Unit V Release signal set time tSREL 0 s Notes 1. TA = -40 to +110C: PD780143(A1), 780144(A1), 780146(A1), 780148(A1) TA = -40 to +105C: PD78F0148(A1) 2. When flash memory version PD78F0148M1(A1) or 78F0148M2(A1) is used 572 User's Manual U15947EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Flash Memory Programming Characteristics: PD78F0148(A1) (TA = +10 to +60C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (1) Write erase characteristics Parameter VPP supply voltage VDD supply current VPP supply current Step erase time Note 1 Symbol VPP2 IDD IPP Ter Tera Twb Cwb Conditions During flash memory programming When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V VPP = VPP2 MIN. 9.7 TYP. 10.0 MAX. 10.3 37 100 Unit V mA mA s s/chip ms Times 0.199 When step erase time = 0.2 s 49.4 When writeback time = 50 ms 0.2 0.201 20 Overall erase time Writeback time Note 2 Note 3 50 50.6 60 Number of writebacks per 1 writeback command Note 4 Number of erases/writebacks Step write time Note 5 Cerwb Twr 48 When step write time = 50 s (1 word = 1 byte) 1 erase + 1 write after erase = 1 rewrite 48 50 16 52 520 Times s s Times/ area Overall write time per word Note 6 Twrw Number of rewrites per chip Note 7 Cerwr 20 Notes 1. 2. www..com The recommended setting value of the step erase time is 0.2 s. The prewrite time before erasure and the erase verify time (writeback time) are not included. The recommended setting value of the writeback time is 50 ms. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries must be the maximum value minus the number of commands issued. The recommended setting value of the step write time is 50 s. The actual write time per word is 100 s longer. The internal verify time during or after a write is not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P: 3 rewrites 3. 4. 5. 6. 7. Shipped product E P E P E P: 3 rewrites Remark The range of the operating clock during flash memory programming is the same as the range during normal operation. User's Manual U15947EJ2V0UD 573 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Set time from VDD to VPP Symbol tDP Conditions MIN. 10 10 2 TYP. MAX. Unit s s ms Release time from VPP to RESET tPR VPP pulse input start time from RESET VPP pulse high-/low-level width VPP pulse input end time from RESET VPP pulse low-level input voltage VPP pulse high-level input voltage tRP tPW tRPE 8 14 s ms VPPL VPPH 0.8VDD 9.7 10.0 1.2VDD 10.3 V V Flash Write Mode Setting Timing VDD VDD 0V VPPH VPP VPPL 0V www..com tDP tRP tPW tPW tPR tRPE VDD RESET (input) 0V 574 User's Manual U15947EJ2V0UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Target products: PD780143(A2), 780144(A2), 780146(A2), 780148(A2) Cautions 1. Be sure to connect the REGC pin of (A2) grade products directly to VDD. 2. The external bus interface function cannot be used with (A2) grade products. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD EVDD REGC VSS EVSS AVREF AVSS Input voltage VI1 P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, X1, X2, XT1, XT2, RESET VI2 www..com Conditions Ratings -0.3 to +6.5 -0.3 to +6.5 -0.3 to +6.5 -0.3 to +0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 Note Note Unit V V V V V V V V P62, P63 N-ch open drain On-chip pull-up resistor -0.3 to +13 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Note V V V Note Output voltage Analog input voltage VO VAN Note AVSS - 0.3 to AVREF + 0.3 and -0.3 to VDD + 0.3 -7 P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 P10 to P17, P30 to P33, P120, P130, P140, P141 -21 -21 V Note Output current, high IOH Per pin Total of all pins -42 mA mA mA mA Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 575 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Per pin Conditions P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 Total of all pins 49 mA P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Operating ambient temperature Storage temperature Tstg -65 to +150 C TA In normal operation mode -40 to +125 C 24.5 mA 21 24.5 mA mA Ratings 14 Unit mA Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. www..com 576 User's Manual U15947EJ2V0UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) X1 Oscillator Characteristics (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Ceramic resonator Note 2 Recommended Circuit Parameter Oscillation frequency (fXP) Note 1 Conditions 4.0 V VDD < 5.5 V 3.3 V VDD < 4.0 V MIN. 2.0 2.0 TYP. MAX. 8.38 5.0 Unit MHz VSS X1 X2 C1 C2 Crystal resonator Note 2 VSS X1 X2 Oscillation frequency (fXP) Note 1 4.0 V VDD < 5.5 V 3.3 V VDD < 4.0 V 2.0 2.0 8.38 5.0 MHz C1 C2 External clock Note 2 X1 X2 X1 input frequency (fXP) Note 1 4.0 V VDD < 5.5 V 3.3 V VDD < 4.0 V 4.0 V VDD < 5.5 V 3.3 V VDD < 4.0 V 2.0 2.0 56 96 8.38 5.0 500 500 MHz X1 input high-/lowlevel width (tXPH, tXPL) ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Connect the REGC pin directly to VDD. www..com Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the Ring-OSC after reset is released, check the oscillation stabilization time of the X1 input clock using the oscillation stabilization time status register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U15947EJ2V0UD 577 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Ring-OSC Oscillator Characteristics (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator On-chip Ring-OSC oscillator Parameter Oscillation frequency (fR) Conditions MIN. 120 TYP. 240 MAX. 495 Unit kHz Subsystem Clock Oscillator Characteristics (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT) Note Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz VSS XT2 Rd C4 XT1 C3 External clock XT2 XT1 XT1 input frequency (fXT) Note 32 38.5 kHz XT1 input high-/low-level width (tXTH, tXTL) 12 15 s Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken www..com lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 578 User's Manual U15947EJ2V0UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (1/3) (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Per pin Total of P10 to P17, P30 to P33, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 All pins Output current, low IOL Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Per pin for P60 to P63 Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, www..com Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V MIN. TYP. MAX. -3.5 -17.5 Unit mA mA 4.0 V VDD 5.5 V -17.5 mA 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V -7 7 mA mA 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 10.5 21 mA mA 4.0 V VDD 5.5 V 21 mA P142 to P145 All pins Input voltage, high VIH1 3.3 V VDD < 4.0 V 0.7VDD 7 VDD mA V P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIH2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note 0.8VDD VDD V VIH3 VIH4 VIH5 P20 to P27 P60, P61 P62, P63 0.7AVREF 0.75VDD N-ch open drain On-chip pull-up resistor 0.7VDD 0.7VDD VDD - 0.5 0 AVREF VDD 12 VDD VDD 0.3VDD V V V V V V VIH6 Input voltage, low VIL1 X1, X2, XT1, XT2 P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P144, P145 VIL2 P00 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET Note 0 0.2VDD V VIL3 VIL4 VIL5 VIL6 P20 to P27 P60, P61 P62, P63 0 0 0 0 0.3AVREF 0.25VDD 0.3VDD 0.4 V V V V X1, X2, XT1, XT2 Note When used as digital input ports, set AVREF = VDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 579 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (2/3) (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, high Symbol VOH Conditions Total of P10 to P17, P30 to P33, P120, P130, P140, P141 IOH = -17.5 mA Total of P00 to P06, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P142 to P145 IOH = -17.5 mA IOH = -100 A Output voltage, low VOL1 Total of P10 to P17, P30 to P33, P62, P63, P120, P130, P140, P141 IOL = 21 mA Total of P00 to P06, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P142 to P145 IOL = 21 mA IOL = 400 A VOL2 www..com MIN. TYP. MAX. Unit V 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -3.5 mA 4.0 V VDD 5.5 V, VDD - 1.0 IOH = -3.5 mA V 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 7 mA VDD - 0.5 1.3 V V 4.0 V VDD 5.5 V, IOL = 7 mA 1.3 V 3.3 V VDD < 4.0 V IOL = 10.5 mA P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET 0.4 2.0 10 V V P60 to P63 VI = VDD Input leakage current, high ILIH1 A VI = AVREF ILIH2 ILIH3 Input leakage current, low ILIL1 VI = VDD VI = 12 V VI = 0 V P20 to P27 X1, X2 Note 1 10 Note 1 A A A A , XT1, XT2 20 40 -10 P62, P63 (N-ch open drain) P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P60, P61, P64 to P67, P70 to P77, P120, P140 to P145, RESET Note 1 Note 1 ILIL2 ILIL3 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value ILOL RL VO = VDD VO = 0 V VI = 0 V X1, X2 , XT1, XT2 -20 -10 Note 2 A A A A k P62, P63 (N-ch open drain) 10 -10 10 30 120 Notes 1. 2. When the inverse level of X1 is input to X2 and the inverse level of XT1 is input to XT2. If there is no on-chip pull-up resistor for P62 and P63 (specified by a mask option) and if port 6 has been set to input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to -55 A flows during only one cycle. At all other times, the maximum leakage current is -10 A. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15947EJ2V0UD 580 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (3/3) (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal oscillation operating mode IDD2 Note 2 Conditions fXP = 8.38 MHz Note 3 VDD = 5.0 V 10% When A/D converter is stopped When A/D converter is operating fXP = 8.38 MHz Note 3 VDD = 5.0 V 10% Note 7 MIN. TYP. MAX. Unit 6.7 7.7 15.0 17.0 mA mA X1 crystal oscillation HALT mode When peripheral functions are stopped When peripheral functions are operating 1.5 4.7 mA 8.7 mA IDD3 Ring-OSC operating mode Note 4 VDD = 5.0 V 10% 0.28 2.82 mA IDD4 32.768 kHz crystal oscillation operating mode Notes 4, 6 VDD = 5.0 V 10% 38 1800 A IDD5 32.768 kHz crystal oscillation HALT mode Notes 4, 6 VDD = 5.0 V 10% 20 1700 A IDD6 STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 5 0.1 14 3.5 1700 1800 1700 A A A A , RING: OFF , RING: ON www..com POC: ON Note 5 17.5 1800 Notes 1. 2. 3. 4. 5. 6. 7. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. When POC-OFF (including LVIE = 0) is selected by a mask option and Ring-OSC oscillation is stopped. Including the current that flows through the AVREF pin. User's Manual U15947EJ2V0UD 581 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Main system clock operation X1 input clock Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V MIN. 0.238 0.4 4.04 114 2/fsam + 0.1 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V TI50, TI51 input high-level width, tTIH5, low-level width Interrupt input high-level width, low-level width Key return input low-level width tTIL5 tINTH, tINTL tKR 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V RESET low-level width www..com Note 2 TYP. MAX. 16 16 Unit s s s s s s Ring-OSC clock 8.33 122 16.67 125 Subsystem clock operation TI000, TI010, TI001 TI011 Note 1 Note 1 , tTIH0, 4.0 V VDD 5.5 V input high-level width, tTIL0 low-level width 2/fsam + 0.2 Note 2 TI50, TI51 input frequency fTI5 8.38 5 59.6 100 1 MHz MHz ns ns 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V s ns ns 59.6 100 10 tRSL s Notes 1. 2. PD780146(A2) and 780148(A2) only. Selection of fsam = fXP, fXP/4, fXP/256, or fXP, fXP/16, fXP/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fXP. 582 User's Manual U15947EJ2V0UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) TCY vs. VDD (X1 Input Clock Operation) 20.0 16.0 10.0 Cycle time TCY [ s] 5.0 2.0 1.0 Guaranteed operation range 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 3.3 4.0 5.0 5.5 6.0 Supply voltage VDD [V] www..com User's Manual U15947EJ2V0UD 583 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (2) Serial interface (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 261.9 Unit kbps (b) UART mode (UART0, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 261.9 Unit kbps (c) 3-wire serial I/O mode (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time Symbol tKCY1 Conditions 4.0 V VDD < 5.5 V 3.3 V VDD < 4.0 V SCK1n high-/low-level width SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output www..com MIN. 240 400 tKCY1/2 - 10 TYP. MAX. Unit ns ns ns tKH1, tKL1 tSIK1 tKSI1 tKSO1 C = 100 pF Note 30 30 30 ns ns ns Note C is the load capacitance of the SCK1n and SO1n output lines. (d) 3-wire serial I/O mode (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 C = 100 pF Note Conditions MIN. 400 tKCY2/2 TYP. MAX. Unit ns ns 80 50 120 ns ns ns Note C is the load capacitance of the SO1n output line. Remark n = 0: PD780143(A2), 780144(A2) n = 0, 1: PD780146(A2), 780148(A2) 584 User's Manual U15947EJ2V0UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter SCKA0 cycle time SCKA0 high-/low-level width SIA0 setup time (to SCKA0) SIA0 hold time (from SCKA0) Delay time from SCKA0 to SOA0 output Time from SCKA0 to STB0 Strobe signal high-level width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) Time from busy inactive to SCKA0 tSPS 2tKCY3 ns tBYH 150 ns Symbol tKCY3 tTH3, tTL3 tSIK3 tKSI3 tKSO3 tSBD tSBW tBYS C = 100 pF Note Conditions MIN. 1200 tKCY3/2 - 100 100 300 TYP. MAX. Unit ns ns ns ns 300 tKCY3/2 - 100 tKCY3 - 60 100 ns ns ns ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. (f) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0 ... external clock input) Parameter SCKA0 cycle time SCKA0 high-/low-level width www..com Symbol tKCY4 tKH4, tKL4 tSIK4 tKSI4 tKSO4 tR4, tF4 Conditions MIN. 1200 600 100 300 TYP. MAX. Unit ns ns ns ns SIA0 setup time (to SCKA0) SIA0 hold time (from SCKA0) Delay time from SCKA0 to SOA0 output SCKA0 rise/fall time C = 100 pF Note 300 1000 ns ns Note C is the load capacitance of the SOA0 output line. User's Manual U15947EJ2V0UD 585 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD 0.2VDD Test points Clock Timing 1/fXP tXPL tXPH X1 input VIH6 (MIN.) VIL6 (MAX.) 1/fXT tXTL tXTH VIH6 (MIN.) VIL6 (MAX.) XT1 input TI Timing www..com tTIL0 tTIH0 TI00, TI010, TI001Note, TI011Note 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Note PD780146(A2) and 780148(A2) only. 586 User's Manual U15947EJ2V0UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) RESET Input Timing tRSL RESET Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK1n tSIKm tKSIm SI1n Input data tKSOm www..com SO1n Output data Remark m = 1, 2 n = 0: PD780143(A2), 780144(A2) n = 0, 1: PD780146(A2), 780148(A2) User's Manual U15947EJ2V0UD 587 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 D2 D1 D0 D7 SIA0 D2 tSIK3, 4 tKSO3, 4 D1 tKSI3, 4 tKH3, 4 tF4 D0 D7 SCKA0 tR4 tKL3, 4 tKCY3, 4 STB0 tSBD tSBW 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCKA0 7 8 9Note 10Note tBYH 10+nNote tSPS 1 tBYS BUSY0 (active-high) www..com Note The signal is not actually driven low here; it is shown as such to indicate the timing. 588 User's Manual U15947EJ2V0UD CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) A/D Converter Characteristics (TA = -40 to +125C, 3.3 V VDD = EVDD 5.5 V, 3.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.7 0.9 48 48 0.7 0.9 0.7 0.9 5.5 7.5 2.5 3.0 Unit bit %FSR %FSR 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Conversion time tCONV 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V 16 19 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V Zero-scale error Notes 1, 2 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Full-scale error Notes 1, 2 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Integral non-linearity error Note 1 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Differential non-linearity error Note 1 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Analog input voltage VIAN AVSS AVREF Notes 1. 2. Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +125C) www..com Parameter Detection voltage Power supply rise time Response delay time 1 Note Symbol VPOC0 tPTH tPTHD Conditions Mask option = 3.5 V VDD: 0 V 3.3 V When power supply rises, after reaching detection voltage (MAX.) MIN. 3.3 0.002 TYP. 3.5 MAX. 3.76 Unit V ms 3.0 ms Response delay time 2 Minimum pulse width Note tPD tPW When VDD falls 0.2 1.0 ms ms Note Time required from voltage detection to reset release. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time User's Manual U15947EJ2V0UD 589 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) LVI Circuit Characteristics (TA = -40 to +125C) Parameter Detection voltage Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 Response time Note 1 Conditions MIN. 4.1 3.9 3.7 3.5 3.3 TYP. 4.3 4.1 3.9 3.7 3.5 0.2 MAX. 4.56 4.36 4.16 3.96 3.76 2.0 Unit V V V V V ms ms tLD tLW 0.2 Minimum pulse width Reference voltage stabilization wait tLWAIT0 Note 2 time Operation stabilization wait time Note 3 0.5 2.0 ms tLWAIT1 0.1 0.2 ms Notes 1. 2. 3. Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by the mask option. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 2. VPOCn < VLVIm (n = 0 and 1, m = 0 to 4) LVI Circuit Timing www..com Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tWAIT0 tWAIT1 tLD LVIE 1 LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +125C) Parameter Data retention supply voltage Symbol VDDDR Conditions When POC-OFF is selected by mask option Release signal set time tSREL 0 MIN. 2.0 TYP. MAX. 5.5 Unit V s 590 User's Manual U15947EJ2V0UD CHAPTER 33 PACKAGE DRAWINGS 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 61 41 40 detail of lead end S C D P T 80 1 F G www..com 21 20 Q H I M R L U J K S N NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. S M ITEM A B C D F G H I J K L M N P Q R S T U MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.1450.05 0.08 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P80GK-50-9EU-1 User's Manual U15947EJ2V0UD 591 CHAPTER 33 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G P www..com H I M K S N S L M ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 +7 3 -3 1.70 MAX. P80GC-65-8BT-1 NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 592 User's Manual U15947EJ2V0UD CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 34-1. Surface Mounting Type Soldering Conditions (1/3) (1) 80-pin plastic QFP (14 x 14) PD780143GC-xxx-8BT, 780144GC-xxx-8BT, 780146GC-xxx-8BT, 780148GC-xxx-8BT, PD780143GC(A)-xxx-8BT, 780144GC(A)-xxx-8BT, 780146GC(A)-xxx-8BT, 780148GC(A)-xxx-8BT, PD780143GC(A1)-xxx-8BT, 780144GC(A1)-xxx-8BT, 780146GC(A1)-xxx-8BT, 780148GC(A1)-xxx-8BT, PD780143GC(A2)-xxx-8BT, 780144GC(A2)-xxx-8BT, 780146GC(A2)-xxx-8BT, 780148GC(A2)-xxx-8BT, PD78F0148M1GC-8BT, 78F0148M2GC-8BT, 78F0148M3GC-8BT, 78F0148M4GC-8BT, 78F0148M5GC-8BT, PD78F0148M6GC-8BT, 78F0148M1GC(A)-8BT, 78F0148M2GC(A)-8BT, 78F0148M3GC(A)-8BT, PD78F0148M4GC(A)-8BT, 78F0148M5GC(A)-8BT, 78F0148M6GC(A)-8BT, 78F0148M1GC(A1)-8BT, PD78F0148M2GC(A1)-8BT, 78F0148M5GC(A1)-8BT, 78F0148M6GC(A1)-8BT Soldering Method www..com Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: 2 times or less, Exposure limit: 7 days 10 hours) Note IR35-107-2 (after that, prebake at 125C for VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: 2 times or less, Exposure limit: 7 days 10 hours) Note VP15-107-2 (after that, prebake at 125C for Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Exposure Note limit: 7 days (after that, prebake at 125C for 10 hours) WS60-107-1 Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U15947EJ2V0UD 593 CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Table 34-1. Surface Mounting Type Soldering Conditions (2/3) (2) 80-pin plastic TQFP (fine pitch) (12 x 12) PD780143GK-xxx-9EU, 780144GK-xxx-9EU, 780146GK-xxx-9EU, 780148GK-xxx-9EU, 780143GK(A)-xxx-9EU, PD780144GK(A)-xxx-9EU, 780146GK(A)-xxx-9EU, 780148GK(A)-xxx-9EU, 780143GK(A1)-xxx-9EU, PD780144GK(A1)-xxx-9EU, 780146GK(A1)-xxx-9EU, 780148GK(A1)-xxx-9EU, 780143GK(A2)-xxx-9EU, PD780144GK(A2)-xxx-9EU, 780146GK(A2)-xxx-9EU, 780148GK(A2)-xxx-9EU Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2 Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: 2 times or less, Exposure limit: 7 days 10 hours) Note (after that, prebake at 125C for VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: 2 times or less, Exposure limit: 7 days 10 hours) Note VP15-107-2 (after that, prebake at 125C for - Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). www..com 594 User's Manual U15947EJ2V0UD CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Table 34-1. Surface Mounting Type Soldering Conditions (3/3) (3) 80-pin plastic TQFP (fine pitch) (12 x 12) PD78F0148M1GK-9EU, 78F0148M2GK-9EU, 78F0148M3GK-9EU, 78F0148M4GK-9EU, 78F0148M5GK-9EU, PD78F0148M6GK-9EU, 78F0148M1GK(A)-9EU, 78F0148M2GK(A)-9EU, 78F0148M3GK(A)-9EU, PD78F0148M4GK(A)-9EU, 78F0148M5GK(A)-9EU, 78F0148M6GK(A)-9EU, 78F0148M1GK(A1)-9EU, PD78F0148M2GK(A1)-9EU, 78F0148M5GK(A1)-9EU, 78F0148M6GK(A1)-9EU Soldering Method Soldering Conditions Recommended Condition Symbol IR35-103-2 Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: 2 times or less, Exposure limit: 3 days 10 hours) Note (after that, prebake at 125C for VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: 2 times or less, Exposure limit: 3 days 10 hours) Note VP15-103-2 (after that, prebake at 125C for - Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). www..com User's Manual U15947EJ2V0UD 595 CHAPTER 35 CAUTIONS FOR WAIT 35.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware. When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing, until the correct data is passed. As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Table 351). This must be noted when real-time processing is performed. www..com 596 User's Manual U15947EJ2V0UD CHAPTER 35 CAUTIONS FOR WAIT 35.2 Peripheral Hardware That Generates Wait Table 35-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 35-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Watchdog timer Serial interface UART0 Serial interface UART6 A/D converter WDTM ASIS0 ASIS6 ADM ADS PFM PFT ADCR Register Write Read Read Write Write Write Write Read 1 to 5 clocks (when ADM.5 flag = "1") 1 to 9 clocks (when ADM.5 flag = "0") www..com Access Number of Wait Clocks 3 clocks (fixed) 1 clock (fixed) 1 clock (fixed) 2 to 5 clocks 2 to 9 clocks Note (when ADM.5 flag = "1") Note (when ADM.5 flag = "0") Macro operating frequency (When bit 5 (FR2) of ADM = "1": fX/2, when bit 5 (FR2) of ADM = "0": fX/2 ) 2 fCPU: tCPUL: CPU clock frequency Low-level width of CPU clock Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1. Caution When the CPU is operating on the subsystem clock and the X1 input clock is stopped (MCC = 1), do not access the registers listed above using an access method in which a wait request is issued. Remark The clock is the CPU clock (fCPU). User's Manual U15947EJ2V0UD 597 CHAPTER 35 CAUTIONS FOR WAIT 35.3 Example of Wait Occurrence <1> Watchdog timer Value of Bit 5 (FR2) of ADM Register www..com fCPU fX fX/2 fX/2 fX/2 fX/2 2 Number of Wait Clocks 9 clocks 5 clocks 3 clocks 2 clocks 0 clocks (1 clock 5 clocks 3 clocks 2 clocks 0 clocks (1 clock 0 clocks (1 clock Note Note Number of Execution Clocks 14 clocks 10 clocks 8 clocks 7 clocks 0 3 4 ) 5 clocks (6 clocks 10 clocks 8 clocks 7 clocks Note ) 1 fX fX/2 fX/2 fX/2 fX/2 2 3 ) ) 5 clocks (6 clocks 5 clocks (6 clocks Note ) ) 4 Note Note Note On execution of MOV A, ADCR Remark The clock is the CPU clock (fCPU). fX: X1 input clock frequency tCPUL: Low-level width of CPU clock 598 User's Manual U15947EJ2V0UD APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/KF1. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * Windows Unless otherwise specified, "Windows" means the following OSs. * Windows 3.1 * Windows 95, 98, 2000 * Windows NT TM Ver 4.0 www..com User's Manual U15947EJ2V0UD 599 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulators IE-78K0-NS, IE-78K0-NS-A Software package * Software package Language processing software * Assembler package * C compiler package * Device file * C library source fileNote 1 Debugging software * Integrated debugger * System simulator Control software * Project manager (Windows only)Note 2 Embedded software * Real-time OS Host machine (PC or EWS) Interface adapter, PC card interface, etc. www..com Power supply unit Flash memory write environment Flash programmer In-circuit emulatorNote 3 Emulation board Flash memory write adapter Performance board Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. 2. 3. The C library source file is not included in the software package. The project manager is included in the assembler package. The project manager is only used for Windows. Products other than in-circuit emulators IE-78K0-NS and IE-78K0-NS-A are all sold separately. 600 User's Manual U15947EJ2V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the in-circuit emulator IE-78K0K1-ET Software package * Software package Language processing software * Assembler package * C compiler package * Device file * C library source fileNote 1 Debugging software * Integrated debugger * System simulator Control software * Project manager (Windows only)Note 2 Embedded software * Real-time OS Host machine (PC or EWS) Interface adapter, PC card interface, etc. www..com Flash memory write environment Flash programmer Power supply unit In-circuit emulatorNote 3 Flash memory write adapter Emulation probe Flash memory Conversion socket or conversion adapter Target system Notes 1. 2. 3. The C library source file is not included in the software package. The project manager is included in the assembler package. The project manager is only used for Windows. In-circuit emulator IE-78K0K1-ET is supplied with integrated debugger ID78K0-NS, a device file, power supply unit, and PCI bus interface adapter IE-70000-PCI-IF-A. Any other products are sold separately. User's Manual U15947EJ2V0UD 601 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 78K/0 Series software package Development tools (software) common to the 78K/0 Series are combined in this package. Part number: SxxxxSP78K0 Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSP78K0 xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM www..com 602 User's Manual U15947EJ2V0UD APPENDIX A DEVELOPMENT TOOLS A.2 Language Processing Software RA78K0 Assembler package This assembler converts programs written in mnemonics into object codes executable with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780148) (sold separately). Note 1 This file contains information peculiar to the device. This device file should be used in combination with a tool (RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0) (all sold separately). The corresponding OS and host machine differ depending on the tool to be used. Part number: SxxxxDF780148 www..com CC78K0-L Note 2 This is a source file of the functions that configure the object library included in the C compiler package. This file is required to match the object library included in the C compiler package to the user's specifications. Since this is a source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0-L C library source file Notes 1. 2. The DF780148 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0. The CC78K0-L is not included in the software package (SP78K0). User's Manual U15947EJ2V0UD 603 APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxRA78K0 SxxxxCC78K0 xxxx AB13 BB13 AB17 BB17 3P17 3K17 HP9000 series 700 SPARCstation TM TM Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) HP-UX TM Supply Medium 3.5-inch 2HD FD CD-ROM (Rel. 10.10) (Rel. 4.1.4), (Rel. 2.5.1) SunOS Solaris TM TM SxxxxDF780148 SxxxxCC78K0-L xxxx AB13 BB13 3P16 3K13 www..com Host Machine PC-9800 series, IBM PC/AT compatibles HP9000 series 700 SPARCstation OS Windows (Japanese version) Windows (English version) HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1) DAT Supply Medium 3.5-inch 2HD FD 3.5-inch 2HD FD 1/4-inch CGMT 3K15 A.3 Control Software Project manager This is control software designed to enable efficient user program development in the Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. A.4 Flash Memory Writing Tools Flashpro III (part number: FL-PR3, PG-FP3) Flashpro IV (part number: FL-PR4, PG-FP4) Flash programmer FA-80GK-9EU FA-80GC-8BT Flash memory writing adapter Flash memory writing adapter used connected to the Flashpro III/Flashpro IV. * FA-80GK-9EU: For 80-pin plastic TQFP (GK-9EU type) * FA-80GC-8BT: For 80-pin plastic QFP (GC-8BT type) Flash programmer dedicated to microcontrollers with on-chip flash memory. Remark FL-PR3, FL-PR4, FA-80GK-9EU, and FA-80GC-8BT are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 604 User's Manual U15947EJ2V0UD APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. IE-78K0-NS-PA Performance board This board is connected to the IE-78K0-NS to expand its functions. Adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. IE-78K0-NS-A In-circuit emulator IE-70000-MC-PS-B Power supply unit IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-780148-NS-EM1 www..com IE-78K0-NS In-circuit emulator Product that combines the IE-78K0-NS and IE-78K0-NS-PA This adapter is used for supplying power from a 100 V to 240 V AC outlet. This adapter is required when using a PC-9800 series computer (except notebook type) as the host machine (C bus compatible). This is PC card and interface cable required when using a notebook-type computer as the host machine (PCMCIA socket compatible). This adapter is required when using an IBM PC/AT compatible computer as the host machine (ISA bus compatible). This adapter is required when using a computer with a PCI bus as the host machine. This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic TQFP (GK-9EU type). TGK-080SDW Conversion adapter This conversion adapter is used to connect the NP-80GK and target system board on which an 80-pin plastic TQFP (GK-9EU type) can be mounted. Emulation board NP-80GK NP-H80GK-TQ Emulation probe NP-80GC Emulation probe EV-9200GC-80 Conversion socket NP-80GC-TQ NP-H80GC-TQ Emulation probe TGC-080SBP Conversion adapter This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic QFP (GC-8BT type). This conversion socket is used to connect the NP-80GC and target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic QFP (GC-8BT type). This conversion adapter is used to connect the NP-80GC-TQ or NP-H80GC-TQ and a target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. Remarks 1. NP-80GK, NP-H80GK-TQ, NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. TGK-080SDW and TGC-080SBP are products of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) 3. EV-9200GC-80 is sold in five-device units. 4. TGK-080SDW and TGC-080SBP are sold in individual units. User's Manual U15947EJ2V0UD 605 APPENDIX A DEVELOPMENT TOOLS A.5.2 When using in-circuit emulator IE-78K0K1-ET Notes 1, 2 IE-78K0K1-ET The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K0/Kx1 product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. In-circuit emulator IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter NP-80GK NP-H80GK-TQ Emulation probe TGK-080SDW Conversion adapter NP-80GC Emulation probe EV-9200GC-80 Conversion socket www..com This adapter is required when using a PC-9800 series computer (except notebook type) as the host machine (C bus compatible). This is PC card and interface cable required when using a notebook-type computer as the host machine (PCMCIA socket compatible). This adapter is required when using an IBM PC/AT compatible computer as the host machine (ISA bus compatible). This adapter is required when using a computer with a PCI bus as the host machine. This is supplied with IE-78K0K1-ET. This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic TQFP (GK-9EU type). This conversion adapter is used to connect the NP-80GK and target system board on which an 80-pin plastic TQFP (GK-9EU type) can be mounted. This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic QFP (GC-8BT type). This conversion socket is used to connect the NP-80GC and target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. NP-80GC-TQ NP-H80GC-TQ Emulation probe TGC-080SBP Conversion adapter This probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic QFP (GC-8BT type). This conversion adapter is used to connect the NP-80GC-TQ or NP-H80GC-TQ and a target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. Notes 1. 2. IE-78K0K1-ET is supplied with a power supply unit and PCI bus interface adapter IE-70000-PCI-IF-A. It is also supplied with integrated debugger ID78K0-NS and a device file as control software. Under development Remarks 1. NP-80GK, NP-H80GK-TQ, NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. TGK-080SDW and TGC-080SBP are products of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) 3. EV-9200GC-80 is sold in five-device units. 4. TGK-080SDW and TGC-080SBP are sold in individual units. 606 User's Manual U15947EJ2V0UD APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) SM78K0 System simulator This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with the device file (DF780148) (sold separately). Part number: SxxxxSM78K0 ID78K0-NS Integrated debugger (supporting in-circuit emulators IE-78K0-NS, IE-78K0-NS-A, and IE-78K0K1-ET) This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (sold separately). Part number: SxxxxID78K0-NS Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSM78K0 SxxxxID78K0-NS xxxx www..com Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) Supply Medium 3.5-inch 2HD FD AB13 BB13 AB17 BB17 CD-ROM User's Manual U15947EJ2V0UD 607 APPENDIX A DEVELOPMENT TOOLS A.7 Embedded Software RX78K0 Real-time OS The RX78K0 is a real-time OS conforming to the ITRON specifications. A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780148) (both sold separately). Caution To purchase the RX78K0, first fill in the purchase application form and sign the user agreement. Remark xxxx and in the part number differ depending on the host machine and OS used. SxxxxRX78013- 001 100K 001M 010M S01 www..com Product Outline Evaluation object Mass-production object Maximum Number for Use in Mass Production Do not use for mass-produced product. 0.1 million units 1 million units 10 million units Source program Object source program for mass production xxxx AA13 AB13 BB13 Host Machine PC-9800 series IBM PC/AT compatibles OS Windows (Japanese version) Windows (Japanese version) Windows (English version) Supply Medium 3.5-inch 2HD FD 608 User's Manual U15947EJ2V0UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the emulation probe and conversion adapter. Design your system making allowances for conditions such as the shape of parts mounted on the target system, as shown below. Table B-1. Distance Between IE System and Conversion Adapter Emulation Probe Conversion Adapter EV-9200GC-80 TGC-080SBP Distance Between IE System and Conversion Adapter NP-80GC NP-80GC-TQ NP-H80GC-TQ NP-80GK NP-H80GK-TQ TGK-080SDW 170 mm 170 mm 370 mm 170 mm 370 mm Figure B-1. Distance Between IE System and Conversion Adapter In-circuit emulator IE-78K0-NS, IE-78K0-NS-A, or IE-78K0K1-ET Target system Emulation board IE-780148-NS-EM1 170 mmNote www..com CN6 Emulation probe NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, NP-80GK, NP-H80GK-TQ Conversion adapter EV-9200GC-80, TGC-080SBP, TGK-080SDW Note Distance when using NP-80GC, NP-80GC-TQ, and NP-80GK. This is 370 mm when using NP-H80GC-TQ and NP-H80GK-TQ. Remark The NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, NP-80GK, and NP-H80GK-TQ are products of Naito Densei Machida Mfg. Co., Ltd. The TGC-080SBP and TGK-080SDW are products of TOKYO ELETECH CORPORATION. User's Manual U15947EJ2V0UD 609 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System (When Using NP-80GC-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-80GC-TQ 24.8 mm Conversion adapter TGC-080SBP 25 mm 21 mm 40 mm 21 mm 11 mm 34 mm www..com Target system 610 User's Manual U15947EJ2V0UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-3. Connection Conditions of Target System (When Using NP-H80GC-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-H80GC-TQ 25.3 mm Conversion adapter TGC-080SBP 25 mm 21 mm 42 mm 21 mm 11 mm 45 mm www..com Target system User's Manual U15947EJ2V0UD 611 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-4. Connection Conditions of Target System (When Using NP-80GK) Emulation board IE-780148-NS-EM1 Emulation probe NP-80GK 23 mm Conversion adapter TGK-080SDW 11 mm 18 mm 40 mm www..com 18 mm 34 mm Target system 612 User's Manual U15947EJ2V0UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-5. Connection Conditions of Target System (When Using NP-H80GK-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-H80GK-TQ 23 mm Conversion adapter TGK-080SDW 11 mm 18 mm 42 mm www..com 18 mm 45 mm Target system User's Manual U15947EJ2V0UD 613 APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) [A] A/D conversion result register (ADCR)........................................................................................................................284 A/D converter mode register (ADM) ............................................................................................................................281 Analog input channel specification register (ADS) ......................................................................................................283 Asynchronous serial interface control register 6 (ASICL6) ..........................................................................................333 Asynchronous serial interface operation mode register 0 (ASIM0) .............................................................................303 Asynchronous serial interface operation mode register 6 (ASIM6) .............................................................................327 Asynchronous serial interface reception error status register 0 (ASIS0) .....................................................................305 Asynchronous serial interface reception error status register 6 (ASIS6) .....................................................................329 Asynchronous serial interface transmission status register 6 (ASIF6) ........................................................................330 Automatic data transfer address count register 0 (ADTC0).........................................................................................381 Automatic data transfer address point specification register 0 (ADTP0) .....................................................................386 Automatic data transfer interval specification register 0 (ADTI0).................................................................................388 [B] Baud rate generator control register 0 (BRGC0) .........................................................................................................306 Baud rate generator control register 6 (BRGC6) .........................................................................................................332 www..com [C] Capture/compare control register 00 (CRC00)............................................................................................................177 Capture/compare control register 01 (CRC01)............................................................................................................177 Clock monitor mode register (CLM) ............................................................................................................................470 Clock output selection register (CKS) .........................................................................................................................273 Clock selection register 6 (CKSR6).............................................................................................................................331 [D] Divisor selection register 0 (BRGCA0) ........................................................................................................................386 [E] 8-bit timer compare register 50 (CR50) .......................................................................................................................215 8-bit timer compare register 51 (CR51) .......................................................................................................................215 8-bit timer counter 50 (TM50)......................................................................................................................................214 8-bit timer counter 51 (TM51)......................................................................................................................................214 8-bit timer H carrier control register 1 (TMCYC1)........................................................................................................238 8-bit timer H compare register 00 (CMP00).................................................................................................................233 8-bit timer H compare register 01 (CMP01).................................................................................................................233 8-bit timer H compare register 10 (CMP10).................................................................................................................233 8-bit timer H compare register 11 (CMP11).................................................................................................................233 8-bit timer H mode register 0 (TMHMD0) ....................................................................................................................234 8-bit timer H mode register 1 (TMHMD1) ....................................................................................................................234 8-bit timer mode control register 50 (TMC50)..............................................................................................................218 8-bit timer mode control register 51 (TMC51)..............................................................................................................218 External interrupt falling edge enable register (EGN)..................................................................................................437 614 User's Manual U15947EJ2V0UD APPENDIX C REGISTER INDEX External interrupt rising edge enable register (EGP)...................................................................................................437 [I] Input switch control register (ISC) ...............................................................................................................................334 Internal expansion RAM size switching register (IXS).................................................................................................497 Internal memory size switching register (IMS) ............................................................................................................496 Interrupt mask flag register 0H (MK0H) ......................................................................................................................435 Interrupt mask flag register 0L (MK0L)........................................................................................................................435 Interrupt mask flag register 1H (MK1H) ......................................................................................................................435 Interrupt mask flag register 1L (MK1L)........................................................................................................................435 Interrupt request flag register 0H (IF0H) .....................................................................................................................434 Interrupt request flag register 0L (IF0L) ......................................................................................................................434 Interrupt request flag register 1H (IF1H) .....................................................................................................................434 Interrupt request flag register 1L (IF1L) ......................................................................................................................434 [K] Key return mode register (KRM) .................................................................................................................................447 [L] Low-voltage detection level selection register (LVIS)..................................................................................................483 Low-voltage detection register (LVIM) ........................................................................................................................481 [M] Main clock mode register (MCM) ................................................................................................................................146 www..com Main OSC control register (MOC) ...............................................................................................................................147 Memory expansion mode register (MEM) ...................................................................................................................132 Memory expansion wait setting register (MM) ............................................................................................................134 Multiplication/division data register A0 (MDA0H, MDA0L) ..........................................................................................421 Multiplication/division data register B0 (MDB0)...........................................................................................................422 Multiplier/divider control register 0 (DMUC0) ..............................................................................................................423 [O] Oscillation stabilization time counter status register (OSTC) ..............................................................................148, 450 Oscillation stabilization time select register (OSTS)............................................................................................149, 451 [P] Port mode register 0 (PM0)......................................................................................................................... 123, 184, 366 Port mode register 1 (PM1)................................................................................................. 123, 220, 238, 307, 334, 366 Port mode register 12 (PM12).....................................................................................................................................123 Port mode register 14 (PM14)..................................................................................................................... 123, 275, 389 Port mode register 3 (PM3).................................................................................................................................123, 220 Port mode register 4 (PM4).........................................................................................................................................123 Port mode register 5 (PM5).........................................................................................................................................123 Port mode register 6 (PM6).........................................................................................................................................123 Port mode register 7 (PM7).........................................................................................................................................123 Port register 0 (P0)......................................................................................................................................................126 Port register 1 (P1)......................................................................................................................................................126 Port register 12 (P12)..................................................................................................................................................126 Port register 13 (P13)..................................................................................................................................................126 User's Manual U15947EJ2V0UD 615 APPENDIX C REGISTER INDEX Port register 14 (P14) ..................................................................................................................................................126 Port register 2 (P2)......................................................................................................................................................126 Port register 3 (P3)......................................................................................................................................................126 Port register 4 (P4)......................................................................................................................................................126 Port register 5 (P5)......................................................................................................................................................126 Port register 6 (P6)......................................................................................................................................................126 Port register 7 (P7)......................................................................................................................................................126 Power-fail comparison mode register (PFM) ...............................................................................................................285 Power-fail comparison threshold register (PFT) ..........................................................................................................285 Prescaler mode register 00 (PRM00) ..........................................................................................................................181 Prescaler mode register 01 (PRM01) ..........................................................................................................................181 Priority specification flag register 0H (PR0H) ..............................................................................................................436 Priority specification flag register 0L (PR0L) ...............................................................................................................436 Priority specification flag register 1H (PR1H) ..............................................................................................................436 Priority specification flag register 1L (PR1L) ...............................................................................................................436 Processor clock control register (PCC) .......................................................................................................................143 Pull-up resistor option register 0 (PU0) .......................................................................................................................127 Pull-up resistor option register 1 (PU1) .......................................................................................................................127 Pull-up resistor option register 12 (PU12) ...................................................................................................................127 Pull-up resistor option register 14 (PU14) ...................................................................................................................127 Pull-up resistor option register 3 (PU3) .......................................................................................................................127 Pull-up resistor option register 4 (PU4) .......................................................................................................................127 Pull-up resistor option register 5 (PU5) .......................................................................................................................127 Pull-up resistor option register 6 (PU6) .......................................................................................................................127 www..com Pull-up resistor option register 7 (PU7) .......................................................................................................................127 [R] Receive buffer register 0 (RXB0) ................................................................................................................................302 Receive buffer register 6 (RXB6) ................................................................................................................................326 Remainder data register 0 (SDR0)..............................................................................................................................420 Reset control flag register (RESF) ..............................................................................................................................468 Ring-OSC mode register (RCM) .................................................................................................................................145 [S] Serial clock selection register 10 (CSIC10) .................................................................................................................363 Serial clock selection register 11 (CSIC11) .................................................................................................................363 Serial I/O shift register 0 (SIOA0)................................................................................................................................381 Serial I/O shift register 10 (SIO10) ..............................................................................................................................360 Serial I/O shift register 11 (SIO11) ..............................................................................................................................360 Serial operation mode register 10 (CSIM10) ...............................................................................................................361 Serial operation mode register 11 (CSIM11) ...............................................................................................................361 Serial operation mode specification register 0 (CSIMA0) ............................................................................................382 Serial status register 0 (CSIS0)...................................................................................................................................383 Serial trigger register 0 (CSIT0) ..................................................................................................................................385 16-bit timer capture/compare register 000 (CR000) ....................................................................................................171 16-bit timer capture/compare register 001 (CR001) ....................................................................................................171 16-bit timer capture/compare register 010 (CR010) ....................................................................................................173 16-bit timer capture/compare register 011 (CR011) ....................................................................................................173 616 User's Manual U15947EJ2V0UD APPENDIX C REGISTER INDEX 16-bit timer counter 00 (TM00)....................................................................................................................................171 16-bit timer counter 01 (TM01)....................................................................................................................................171 16-bit timer mode control register 00 (TMC00) ...........................................................................................................174 16-bit timer mode control register 01 (TMC01) ...........................................................................................................174 16-bit timer output control register 00 (TOC00)...........................................................................................................178 16-bit timer output control register 01 (TOC01)...........................................................................................................178 [T] Timer clock selection register 50 (TCL50) ..................................................................................................................216 Timer clock selection register 51 (TCL51) ..................................................................................................................216 Transmit buffer register 10 (SOTB10).........................................................................................................................360 Transmit buffer register 11 (SOTB11).........................................................................................................................360 Transmit buffer register 6 (TXB6)................................................................................................................................326 Transmit shift register 0 (TXS0) ..................................................................................................................................302 [W] Watch timer operation mode register (WTM) ..............................................................................................................257 Watchdog timer enable register (WDTE) ....................................................................................................................266 Watchdog timer mode register (WDTM) .....................................................................................................................265 www..com User's Manual U15947EJ2V0UD 617 APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) [A] ADCR: ADM: ADS: ADTC0: ADTI0: ADTP0: ASICL6: ASIF6: ASIM0: ASIM6: ASIS0: ASIS6: A/D conversion result register...............................................................................................................284 A/D converter mode register.................................................................................................................281 Analog input channel specification register...........................................................................................283 Automatic data transfer address count register 0 .................................................................................381 Automatic data transfer interval specification register 0........................................................................388 Automatic data transfer address point specification register 0..............................................................386 Asynchronous serial interface control register 6 ...................................................................................333 Asynchronous serial interface transmission status register 6 ...............................................................330 Asynchronous serial interface operation mode register 0 .....................................................................303 Asynchronous serial interface operation mode register 6 .....................................................................327 Asynchronous serial interface reception error status register 0 ............................................................305 Asynchronous serial interface reception error status register 6 ............................................................329 [B] BRGCA0: BRGC0: BRGC6: Divisor selection register 0....................................................................................................................386 Baud rate generator control register 0 ..................................................................................................306 Baud rate generator control register 6 ..................................................................................................332 [C] CKS: www..com Clock output selection register..............................................................................................................273 Clock selection register 6......................................................................................................................331 Clock monitor mode register .................................................................................................................470 8-bit timer H compare register 00 .........................................................................................................233 8-bit timer H compare register 01 .........................................................................................................233 8-bit timer H compare register 10 .........................................................................................................233 8-bit timer H compare register 11 .........................................................................................................233 16-bit timer capture/compare register 000 ............................................................................................171 16-bit timer capture/compare register 001 ............................................................................................171 16-bit timer capture/compare register 010 ............................................................................................173 16-bit timer capture/compare register 011 ............................................................................................173 8-bit timer compare register 50 .............................................................................................................215 8-bit timer compare register 51 .............................................................................................................215 Capture/compare control register 00 ....................................................................................................177 Capture/compare control register 01 ....................................................................................................177 Serial clock selection register 10 ..........................................................................................................363 Serial clock selection register 11 ..........................................................................................................363 Serial operation mode register 10.........................................................................................................361 Serial operation mode register 11.........................................................................................................361 Serial operation mode specification register 0 ......................................................................................382 Serial status register 0 ..........................................................................................................................383 Serial trigger register 0 .........................................................................................................................385 CKSR6: CLM: CMP00: CMP01: CMP10: CMP11: CR000: CR001: CR010: CR011: CR50: CR51: CRC00: CRC01: CSIC10: CSIC11: CSIM10: CSIM11: CSIMA0: CSIS0: CSIT0: [D] DMUC0: Multiplier/divider control register 0 ........................................................................................................423 618 User's Manual U15947EJ2V0UD APPENDIX C REGISTER INDEX [E] EGN: EGP: External interrupt falling edge enable register ......................................................................................437 External interrupt rising edge enable register .......................................................................................437 [I] IF0H: IF0L: IF1H: IF1L: IMS: ISC: IXS: Interrupt request flag register 0H..........................................................................................................434 Interrupt request flag register 0L ..........................................................................................................434 Interrupt request flag register 1H..........................................................................................................434 Interrupt request flag register 1L ..........................................................................................................434 Internal memory size switching register................................................................................................496 Input switch control register..................................................................................................................334 Internal expansion RAM size switching register ...................................................................................497 [K] KRM: Key return mode register ......................................................................................................................447 [L] LVIM: LVIS: Low-voltage detection register..............................................................................................................481 Low-voltage detection level selection register ......................................................................................483 [M] MCM: MDA0H: MDA0L: www..com Main clock mode register......................................................................................................................146 Multiplication/division data register A0..................................................................................................421 Multiplication/division data register A0..................................................................................................421 Multiplication/division data register B0..................................................................................................422 Memory expansion mode register ........................................................................................................132 Interrupt mask flag register 0H .............................................................................................................435 Interrupt mask flag register 0L..............................................................................................................435 Interrupt mask flag register 1H .............................................................................................................435 Interrupt mask flag register 1L..............................................................................................................435 Memory expansion wait setting register ...............................................................................................134 Main OSC control register ....................................................................................................................147 MDB0: MEM: MK0H: MK0L: MK1H: MK1L: MM: MOC: [O] OSTC: OSTS: Oscillation stabilization time counter status register .....................................................................148, 450 Oscillation stabilization time select register ..................................................................................149, 451 [P] P0: P1: P12: P13: P14: P2: P3: P4: P5: P6: Port register 0.......................................................................................................................................126 Port register 1.......................................................................................................................................126 Port register 12.....................................................................................................................................126 Port register 13.....................................................................................................................................126 Port register 14.....................................................................................................................................126 Port register 2.......................................................................................................................................126 Port register 3.......................................................................................................................................126 Port register 4.......................................................................................................................................126 Port register 5.......................................................................................................................................126 Port register 6.......................................................................................................................................126 User's Manual U15947EJ2V0UD 619 APPENDIX C REGISTER INDEX P7: PCC: PFM: PFT: PM0: PM1: PM12: PM14: PM3: PM4: PM5: PM6: PM7: PR0H: PR0L: PR1H: PR1L: PRM00: PRM01: PU0: PU1: PU12: PU14: PU3: www..com Port register 7 .......................................................................................................................................126 Processor clock control register............................................................................................................143 Power-fail comparison mode register ...................................................................................................285 Power-fail comparison threshold register..............................................................................................285 Port mode register 0 .............................................................................................................123, 184, 366 Port mode register 1 .....................................................................................123, 220, 238, 307, 334, 366 Port mode register 12 ...........................................................................................................................123 Port mode register 14 ...........................................................................................................123, 275, 389 Port mode register 3 .....................................................................................................................123, 220 Port mode register 4 .............................................................................................................................123 Port mode register 5 .............................................................................................................................123 Port mode register 6 .............................................................................................................................123 Port mode register 7 .............................................................................................................................123 Priority specification flag register 0H.....................................................................................................436 Priority specification flag register 0L .....................................................................................................436 Priority specification flag register 1H.....................................................................................................436 Priority specification flag register 1L .....................................................................................................436 Prescaler mode register 00...................................................................................................................181 Prescaler mode register 01...................................................................................................................181 Pull-up resistor option register 0 ...........................................................................................................127 Pull-up resistor option register 1 ...........................................................................................................127 Pull-up resistor option register 12 .........................................................................................................127 Pull-up resistor option register 14 .........................................................................................................127 Pull-up resistor option register 3 ...........................................................................................................127 Pull-up resistor option register 4 ...........................................................................................................127 Pull-up resistor option register 5 ...........................................................................................................127 Pull-up resistor option register 6 ...........................................................................................................127 Pull-up resistor option register 7 ...........................................................................................................127 PU4: PU5: PU6: PU7: [R] RCM: RESF: RXB0: RXB6: Ring-OSC mode register ......................................................................................................................145 Reset control flag register.....................................................................................................................468 Receive buffer register 0.......................................................................................................................302 Receive buffer register 6.......................................................................................................................326 [S] SDR0: SIO10: SIO11: SIOA0: SOTB10: SOTB11: Remainder data register 0 ....................................................................................................................420 Serial I/O shift register 10 .....................................................................................................................360 Serial I/O shift register 11 .....................................................................................................................360 Serial I/O shift register 0 .......................................................................................................................381 Transmit buffer register 10....................................................................................................................360 Transmit buffer register 11....................................................................................................................360 [T] TCL50: TCL51: TM00: TM01: Timer clock selection register 50 ..........................................................................................................216 Timer clock selection register 51 ..........................................................................................................216 16-bit timer counter 00..........................................................................................................................171 16-bit timer counter 01..........................................................................................................................171 620 User's Manual U15947EJ2V0UD APPENDIX C REGISTER INDEX TM50: TM51: TMC00: TMC01: TMC50: TMC51: TMCYC1: TMHMD0: TMHMD1: TOC00: TOC01: TXB6: TXS0: 8-bit timer counter 50............................................................................................................................214 8-bit timer counter 51............................................................................................................................214 16-bit timer mode control register 00 ....................................................................................................174 16-bit timer mode control register 01 ....................................................................................................174 8-bit timer mode control register 50 ......................................................................................................218 8-bit timer mode control register 51 ......................................................................................................218 8-bit timer H carrier control register 1 ...................................................................................................238 8-bit timer H mode register 0 ................................................................................................................234 8-bit timer H mode register 1 ................................................................................................................234 16-bit timer output control register 00 ...................................................................................................178 16-bit timer output control register 01 ...................................................................................................178 Transmit buffer register 6 .....................................................................................................................326 Transmit shift register 0 ........................................................................................................................302 [W] WDTE: WDTM: WTM: Watchdog timer enable register............................................................................................................266 Watchdog timer mode register .............................................................................................................265 Watch timer operation mode register ...................................................................................................257 www..com User's Manual U15947EJ2V0UD 621 APPENDIX D REVISION HISTORY The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/5) Edition 1st edition (Modified version) Description Modification of reset value of the following registers in Table 3-5 Special Function Register List * Serial I/O shift register 10 (SIO10) * Serial I/O shift register 11 (SIO11) * Interrupt mask flag register 1H (MK1H) Modification of manipulatable bit unit of the following register in Table 3-5 Special Function Register List * Oscillation stabilization time counter status register (OSTC) Modification of manipulatable bit unit and clear condition in 6.3 (5) Oscillation stabilization time counter status register (OSTC) Modification of Figure 6-13 Status Transition Diagram Modification of Table 6-4 Oscillation Control Flags and Clock Oscillation Status Modification of reset value in 7.2 (2) 16-bit timer capture/compare register 00n (CR00n) and (3) 16-bit timer capture/compare register 01n (CR01n) Modification of manipulatable bit unit in 7.3 (4) Prescaler mode register 0n (PRM0n) Addition of caution description in 13.6 (10) A/D conversion result register (ADCR) read operation www..com Applied to: CHAPTER 3 CPU ARCHITECTURE CHAPTER 6 CLOCK GENERATOR CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 CHAPTER 13 A/D CONVERTER CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Modification of reset value in 16.2 (2) Serial I/O shift register 1n (SIO1n) Modification of reset value in 19.3 (2) Interrupt mask flag register (MK1H) CHAPTER 19 INTERRUPT FUNCTIONS Modification of manipulatable bit unit and clear condition in 21.1.2 (1) Oscillation stabilization time counter status register (OSTC) Modification of A/D converter item in Table 21-2 Operating Statuses in HALT Mode Modification of stop condition of clock monitor in 23.1 Functions of Clock Monitor and 23.4 Operation of Clock Monitor Addition of 24.4 Cautions for Power-on-Clear Circuit CHAPTER 21 STANDBY FUNCTION CHAPTER 23 CLOCK MONITOR CHAPTER 24 POWERON-CLEAR CIRCUIT Modification of Figure 25-3 Format of Low-Voltage Detection Level Selection Register (LVIS) Addition of 25.5 Cautions for Low-Voltage Detector Modification of description in 26.1 Outline of Regulator CHAPTER 25 LOWVOLTAGE DETECTOR CHAPTER 26 REGULATOR 622 User's Manual U15947EJ2V0UD APPENDIX D REVISION HISTORY (2/5) Edition 1st edition (Modified version) Description Modification of the following contents in CHAPTER 30 ELECTRICAL SPECIFICATIONS (TARGET VALUES) * Absolute Maximum Ratings * X1 Oscillator Characteristics * Subsystem Clock Oscillator Characteristics * DC Characteristics * A/D Converter Characteristics * POC Circuit Characteristics * LVI Circuit Characteristics * Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (deletion of data retention supply current) * Deletion of Ring-OSC Characteristics * Flash Memory Programming Characteristics Modification from CHAPTER 32 RETRY to CHAPTER 32 CAUTIONS FOR WAIT CHAPTER 32 CAUTIONS FOR WAIT 2nd edition Addition of products PD78F0148(A1), 780143(A2), 780144(A2), 780146(A2), 780148(A2) Under development Under mass production Throughout Applied to: CHAPTER 30 ELECTRICAL SPECIFICATIONS (TARGET VALUES) PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A), 780143(A1), 780144(A1), 780146(A1), 780148(A1) Modification of names of the following special function registers (SFRs) * Ports 0 to 7, and 12 to 14 Port registers 0 to 7, and 12 to 14 Addition of Cautions 3 and 4 to 1.4 Pin Configuration (Top View) www..com CHAPTER 1 OUTLINE Modification of 1.5 K1 Family Lineup Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions Addition of Table 2-1 Pin I/O Buffer Power Supplies Modification of descriptions in 2.2.12 AVREF, 2.2.15 REGC, and 2.2.20 VPP (flash memory versions only) Modification of the following contents in Table 2-2 Pin I/O Circuit Types * Modification of recommended connection when P60 to P63 are not used * Modification of I/O circuit type of P62 and P63 * Addition of Note to AVREF * Modification of recommended connection when VPP is not used Modification of Figure 3-1 Memory Map (PD780143) to Figure 3-5 Memory Map (PD78F0148) Modification of Figure 3-14 Data to Be Saved to Stack Memory Modification of Figure 3-15 Data to Be Restored from Stack Memory Modification of [Description example] in 3.4.4 Short direct addressing Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing, and 3.4.9 Stack addressing Addition of Table 4-1 Pin I/O Buffer Power Supplies Modification of Table 4-3 Port Configuration Modification of Figure 4-11 Block Diagram of P20 to P27, Figure 4-14 Block Diagram of P40 to P47, Figure 4-15 Block Diagram of P50 to P57, Figure 4-17 Block Diagram of P64, P65, and P67, and Figure 4-18 Block Diagram of P66 Addition of Remark to Figure 4-21 Block Diagram of P130 CHAPTER 4 PORT FUNCTIONS CHAPTER 3 CPU ARCHITECTURE CHAPTER 2 PIN FUNCTIONS User's Manual U15947EJ2V0UD 623 APPENDIX D REVISION HISTORY (3/5) Edition 2nd edition Description Applied to: Deletion of input switch control register (ISC) from and addition of port registers (P0 to P7, CHAPTER 4 PORT P12 to P14) to 4.3 Registers Controlling Port Function Modification of setting of output latch of P40 to P47, P50 to P57, P64, P65, and P67 in and addition of Note 2 to Table 4-5 Settings of Port Mode Register and Output Latch When Using Alternate Function Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode, and (2) Input mode Addition of Caution to 5.1 External Bus Interface Addition of Note to Figure 5-2 Format of Memory Expansion Mode Register (MEM) Addition of Caution 2 to Figure 5-4 Format of Memory Expansion Wait Setting Register (MM) Addition of Remark to Figure 5-8 External Memory Read Modify Write Timing Modification of Figure 6-1 Block Diagram of Clock Generator Addition of Note to 6.3 (1) Processor clock control register (PCC) Addition of Cautions 2 and 3 to Figure 6-6 Format of Oscillation Stabilization Time Counter Status Register (OSTC) Modification of Figure 6-8 Examples of External Circuit of X1 Oscillator, Figure 6-9 Examples of External Circuit of Subsystem Clock Oscillator, and Figure 6-10 Examples of Incorrect Resonator Connection Modification of Notes 4 and 5 in Figure 6-13 Status Transition Diagram (2) Modification of Note 4 and illustration in Figure 6-13 Status Transition Diagram (4) CHAPTER 6 CLOCK GENERATOR CHAPTER 5 EXTERNAL BUS INTERFACE FUNCTIONS www..com Modification of Table 6-3 Relationship Between Operation Clocks in Each Operation Status Modification of Note in Figure 6-14 Switching from Ring-OSC Clock to X1 Input Clock (Flowchart) Addition of Note to Figure 6-16 Switching from X1 Input Clock to Subsystem Clock (Flowchart) Revision of CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Revision of CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Revision of CHAPTER 9 8-BIT TIMERS H0 AND H1 CHAPTER 9 8-BIT TIMERS H0 AND H1 Modification of Figure 10-1 Watch Timer Block Diagram Addition of Figure 10-4 Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) Modification of Figure 12-1 Block Diagram of Clock Output/Buzzer Output Controller CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Revision of CHAPTER 13 A/D CONVERTER CHAPTER 13 A/D CONVERTER Revision of CHAPTER 14 SERIAL INTERFACE UART0 CHAPTER 14 SERIAL INTERFACE UART0 CHAPTER 10 WATCH TIMER 624 User's Manual U15947EJ2V0UD APPENDIX D REVISION HISTORY (4/5) Edition 2nd edition Description Revision of CHAPTER 15 SERIAL INTERFACE UART6 Applied to: CHAPTER 15 SERIAL INTERFACE UART6 Revision of CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Revision of CHAPTER 17 SERIAL INTERFACE CSIA0 CHAPTER 17 SERIAL INTERFACE CSIA0 Revision of CHAPTER 18 MULTIPLIER/DIVIDER CHAPTER 18 MULTIPLIER/DIVIDER Addition of Note to INTVLI, POC, and LVI in Table 19-1 Interrupt Source List Addition of Note 2 to Table 19-2 Flags Corresponding to Interrupt Request Sources Addition of Caution 2 to Figure 19-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) Addition of Caution to Table 19-3 Ports Corresponding to EGPn and EGNn Addition of software interrupt request item to Table 19-5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Modification of Figure 20-1 Block Diagram of Key Interrupt CHAPTER 20 KEY INTERRUPT FUNCTION Modification of Table 21-1 Relationship Between HALT Mode, STOP Mode, and Clock in old edition to Table 21-1 Relationship Between Operation Clocks in Each www..com CHAPTER 19 INTERRUPT FUNCTIONS CHAPTER 21 STANDBY FUNCTION Operation Status Addition of Cautions 2 and 3 to Figure 21-1 Format of Oscillation Stabilization Time Counter Status Register (OSTC) Modification of Table 21-1 Operating Statuses in HALT Mode Addition of (3) When subsystem clock is used as CPU clock to Figure 21-4 HALT Mode Release by RESET Input Modification of the following items in Table 21-4 Operating Statuses in STOP Mode * 8-bit timer H0 * Serial interfaces UART0 and UART6 Modification of Figure 22-1 Block Diagram of Reset Function to Figure 22-4 Timing of Reset in STOP Mode by RESET Input Modification of mask flag register 1H (MK1H) in Table 22-1 Hardware Statuses After Reset Acknowledgment Modification of Figure 23-1 Block Diagram of Clock Monitor Addition of operation mode to Table 23-2 Operation Status of Clock Monitor (When CLME = 1) Addition of (6) Clock monitor status after X1 input clock oscillation is stopped by software and (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software to Figure 23-3 Timing of Clock Monitor Addition of Note to description in 24.1 Functions of Power-on-Clear Circuit Modification of Figure 24-1 Block Diagram of Power-on-Clear Circuit Addition of Note to description in 25.1 Functions of Low-Voltage Detector Modification of Figure 25-1 Block Diagram of Low-Voltage Detector CHAPTER 24 POWERON-CLEAR CIRCUIT CHAPTER 25 LOWVOLTAGE DETECTOR CHAPTER 23 CLOCK MONITOR CHAPTER 22 RESET FUNCTION User's Manual U15947EJ2V0UD 625 APPENDIX D REVISION HISTORY (5/5) Edition 2nd edition Description Modification of Note 5 in Figure 25-2 Format of Low-Voltage Detection Register (LVIM) Addition of Note 2 and Caution to Figure 25-3 Format of Low-Voltage Detection Level Selection Register (LVIS) Modification of Figure 25-4 Timing of Low-Voltage Detector Internal Reset Signal Generation and Figure 25-5 Timing of Low-Voltage Detector Interrupt Signal Generation Partial modification of description of (2) When used as interrupt under PD78F0148 CHAPTER 29 INSTRUCTION SET Revision of CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) www..com Addition of CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Addition of CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Addition of CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Addition of A.3 Control Software Addition of in-circuit emulator "IE-78K0K1-ET" to A.5 Debugging Tools (Hardware) Modification of part number of RX78K0 in A.7 Embedded Software Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX A DEVELOPMENT TOOLS APPENDIX B NOTES ON TARGET SYSTEM DESIGN Addition of APPENDIX D REVISION HISTORY APPENDIX D REVISION HISTORY 626 User's Manual U15947EJ2V0UD |
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