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W2465 8K x 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W2465 is a slow-speed, low-power CMOS static RAM organized as 8192 x 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology.
FEATURES
*
* * *
Low power consumption: - Active: 250 mW (max.) - Standby: 100 W (max.)(LL-version) 250 W (max.)(L-version) Access time: 70/100 nS (max.) Single +5V power supply Fully static operation
* * * * *
All inputs and outputs directly TTL compatible Three-state outputs Battery back-up operation capability Data retention voltage: 2V (min.) Available packages: 28-pin 600 mil DIP, 330 mil SOP and 300 mil skinny DIP
PIN CONFIGURATION
BLOCK DIAGRAM
V DD V SS
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD WE CS A8 A9 A11
A0 . . A12
DECODER
CORE ARRAY
CS2 CS1 OE WE
CONTROL
DATA I/O
I/O1 . . I/O8
OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
PIN DESCRIPTION
SYMBOL A0-A12 I/O1-I/O8 CS1, CS2
WE OE VDD VSS NC
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection
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Publication Release Date: April 1997 Revision A8
W2465
TRUTH TABLE
CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L MODE Not Selected Not Selected Output Disable Read Write I/O1-I/O8 High Z High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 ISB, ISB1 IDD IDD IDD
DC CHARACTERISTICS Absolute Maximum Ratings
PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 0 to +70 UNIT V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD = 5V 10%, VSS = 0V, TA = 0 to 70 C)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current
SYM. VIL VIH ILI ILO
Output Low Voltage Output High Voltage Operating Power Supply Current
VOL VOH IDD
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD CS1 = VIH (min.) or CS2 = VIL (max.) or OE = VIH (min.) or WE = VIL (max.) IOL = +4.0 mA IOH = -1.0 mA 70 CS1 = VIL (max.), CS2 = VIH (min.) I/O = 0 mA, 100 Cycle = min. Duty = 100%
CS1 = VIH (min.) or CS2 = VIL (max.), Cycle = min. Duty = 100% LL CS1 VDD -0.2V
MIN. -0.5 +2.2 -2 -2
TYP. -
MAX. +0.8 VDD +0.5 +2 +2
UNIT V V A A
2.4 -
-
0.4 70 60
V V mA mA
Standby Power Supply Current
ISB
-
-
3
mA
ISB1
-
-
20 50
A A
or CS2 0.2V
Note: Typical characteristics are at VDD = 5 V, TA = 25 C.
L
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W2465
CAPACITANCE
(VDD = 5V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 8
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0.6V to 2.4V 5 nS 1.5V CL = 100 pF, IOH/IOL = -1 mA/4 mA CONDITIONS
AC Test Loads and Waveform
R1 1000 ohm 5V OUTPUT 100 pF Including Jig and Scope R2 660 ohm 5V OUTPUT
R1 1000 ohm
5 pF Including Jig and Scope R2 660 ohm
(For TCLZ1,TCLZ2, TOLZ, TCHZ1,T OHZ, TWHZ,T ) CHZ2, T OW
2.4V
90% 10% 5 nS 10%
90%
0.6V
5 nS
-3-
Publication Release Date: April 1997 Revision A8
W2465
AC Characteristics, continued (VDD = 5V 10%, VSS = 0V, TA = 0 to 70 C)
Read Cycle
PARAMETER Read Cycle Time Address Access Time Chip Select Access Time
CS1
SYM. TRC TAA TACS1 TACS2 TAOE
CS1
W2465-70 MIN. 70 5 5 5 10 MAX. 70 70 70 35 30 30 30 -
W2465-10 MIN. 100 10 10 5 10 MAX. 100 100 100 50 35 35 35 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS
CS2 Output Enable to Output Valid Chip Selection to Output in Low Z
TCLZ1* TCLZ2* TOLZ* TCHZ1* TCHZ2* TOHZ* TOH
CS2 Output Enable to Output in Low Z Chip Deselection to Output in High Z
CS1
CS2 Output Disable to Output in High Z Output Hold from Address Change
* These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write
* These parameters are sampled but not 100% tested.
SYM. TWC TCW1 TCW2 TAW TAS TWP TWR1 TWR2 TDW TDH TWHZ* TOHZ* TOW
CS1 CS2
W2465-70 MIN. MAX. 70 60 60 60 0 45 0 0 30 0 0 30 30 -
W2465-10 MIN. MAX. 100 80 80 80 0 60 0 0 40 0 0 30 30 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS
CS1 , WE
CS2
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W2465
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
TRC Address TOH D OUT TAA TOH
Read Cycle 2
(Chip Select Controlled)
CS1
TACS1 TCHZ1
CS2
TACS2 TCHZ2
TCLZ1 D OUT TCLZ2
Read Cycle 3
(Output Enable Controlled)
TRC
Address
TAA
OE
TAOE TOLZ TOH
CS1
TACS1 TCLZ1 TCHZ1
CS2
TACS2 TCLZ2 TCHZ2 TOHZ
DOUT
-5-
Publication Release Date: April 1997 Revision A8
W2465
Timing Waveforms, continued
Write Cycle 1
TWC
Address
TWR1
OE
TCW1
CS1
CS2
TAW
TCW2 TWR2 TWP
WE
TAS TOHZ
(1, 4)
TDW TDH
D OUT
D IN
Write Cycle 2
(OE = VIL Fixed)
TWC Address TCW1 CS1 TWR1
CS2 TAW WE TAS
TCW2 TWR2 TWP TWHZ(1, 4) TOH TOW (2) (3)
DOUT TDW D IN TDH
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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W2465
DATA RETENTION CHARACTERISTICS
(TA = 0 to 70 C)
PARAMETER VDD for Data Retention Data Retention Current
SYM. VDR IDDDR
TEST CONDITIONS
CS1 VDD -0.2V, or CS2 0.2V CS1 VDD -0.2V, or CS2 0.2V VDD = 3V
MIN. 2.0 0 TRC*
TYP. -
MAX. 10 20 -
UNIT V A A nS nS
LL L
Chip Deselect to Data Retention Time Operation Recovery Time
TRC* = Read Cycle Time
TCDR TR
See data retention waveforms
DATA RETENTION WAVEFORMS
DATA RETENTION MODE VDD 4.5V TCDR CS1 VIH VDR > 2V =
4.5V TR VIH
CS1 > VDD - 0.2V =
CS2
VIL
CS2 < 0.2V =
VIL
ORDERING INFORMATION
PART NO. W2465-70LL W2465-10L W2465S-70LL W2465S-10L W2465K-70LL W2465K-10L ACCESS TIME (nS) 70 100 70 100 70 100 OPERATING CURRENT MAX. (mA) 70 60 70 60 70 60 STANDBY CURRENT MAX. (A) 20 50 20 50 20 50 PACKAGE 600 mil DIP 600 mil DIP 330 mil SOP 330 mil SOP 300 mil Skinny 300 mil Skinny
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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Publication Release Date: April 1997 Revision A8
W2465
BONDING PAD DIAGRAM
PAD NO.
5 A4 6 A3 4 A5 3 A6 2 A7 1 A12
27S-2 27S-1
X -226.95 -350.95 -484.10 -608.10 -739.75 -741.75 -741.75 -741.75 -610.60 -481.50 -343.80 -206.10 -73.00 -8.35 60.10 193.30 332.40 465.60 603.30 738.15 740.15 740.15 738.15 606.50 482.50 349.35 225.35 94.20 -50.40
Y 1526.15 1526.15 1526.15 1526.15 1526.15 1315.10 -1231.85 -1456.30 -1456.30 -1466.30 -1466.30 -1466.30 -1401.10 -1212.80 -1466.30 -1466.30 -1466.30 -1466.30 -1466.30 -1456.30 -1221.45 1310.80 1526.15 1526.15 1526.15 1526.15 1526.15 1526.15 1456.10
26
25
24 A8
23 A9
22 A11
21
VDD
VDD
WE CS2
OE
Y
X
7 A2 8 A1 9 A0 10 O0 11 O1 12
13S-2
20 A10
VSS
13S-1
14
VSS
03
15 O4
16 O5
17 O6
18
19 CS1
1 2 3 4 5 6 7 8 9 10 11 12 13S-1 13S-2 14 15 16 17 18 19 20 21 22 23 24 25 26 27S-1 27S-2
O2
O7
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.
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W2465
PACKAGE DIMENSIONS
28-pin P-DIP
Symbol
Dimension in Inches
Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.058 0.008 0.155 0.018 0.060 0.010 1.460 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.064 0.014 1.470 0.610 0.550 0.110 0.140 15 0.670 0.090 14.99 13.72 2.29 3.05 0 16.00 16.51 0.25 3.81 0.41 1.47 0.20 3.94 0.46 1.52 0.25 37.08 15.24 13.84 2.54 3.30 4.06 0.56 1.63 0.36 37.34 15.49 13.97 2.79 3.56 15 17.02 2.29 5.33
D
28 15
A A1 A2 B B1 c D E E1 e1 L
a
E1
eA S Notes:
1 14
S
E c
A A2
A1
Base Plane Seating Plane
L B B1
e1
a
eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
28-pin P-DIP Skinny
Symbol
Dimension in Inches
Dimension in mm
Min. Nom.
0.010 0.125 0.016 0.058 0.008 0.130 0.018 0.060 0.010 1.388 0.300 0.283 0.090 0.120 0 0.330 0.350 0.310 0.288 0.100 0.130
Max.
0.175
Min. Nom.
0.25
Max.
4.45
D
28 15
E1
1
14
A A1 A2 B B1 c D E E1 e1 L
a
0.135 0.022 0.064 0.014 1.400 0.320 0.293 0.110 0.140 15 0.370 0.055
3.18 0.41 1.47 0.20
3.30 0.46 1.52 0.25 35.26
3.43 0.56 1.63 0.36 35.56 8.13 7.44 2.79 3.56 15
7.62 7.19 2.29 3.05 0 8.38
7.87 7.32 2.54 3.30
eA S Notes:
S E
8.89
9.40 1.40
Base Plane
A A2 L B B1 e1 A1
c
Mounting Plane
a eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
-9-
Publication Release Date: April 1997 Revision A8
W2465
Package Dimensions, continued
28-pin SO Wide Body
Symbol
Dimension in Inches
Dimension in mm
Min. Nom. Max.
0.112 0.004 0.093 0.014 0.008 0.098 0.016 0.010 0.713 0.326 0.044 0.453 0.028 0.059 0.331 0.050 0.465 0.036 0.067 0.103 0.020 0.014 0.733 0.336 0.056 0.477 0.044 0.075 0.047 0.004 0 10
Min. Nom. Max.
2.85 0.10 2.36 0.36 0.20 2.49 0.41 0.25 18.11 8.28 1.12 11.51 0.71 1.50 8.41 1.27 11.81 0.91 1.70 2.62 0.51 0.36 18.62 8.53 1.42 12.12 1.12 1.91 1.19 0.10 0 10
28
15
e1
E
HE
L
Detail F
1 b 14
A A1 A2 b c D E e HE L LE S y Notes:
D
e1 c
A2 A
S
e
y
A1
LE
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec.
See Detail F Seating Plane
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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