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 Features
* * * * * * * * * *
Low-noise Low Drop Out Voltage Regulator Programmable at 2.8V or 2.9V Output Voltages 3V to 5.5V Supply Operation 30 mA Maximum Load Current Power-down Mode Consumption Less Than 1 A Macrocell for Integration into System-on-chip Products More Than 70 dB (Typical) PSRR at 1 kHz 32 VRMS Output Noise 0.35 m CMOS Technology Typical Application: Radio Section Supply in Mobile Terminals
Description
RE025 is a Low Drop Out (LDO) voltage regulator macrocell with programmable 2.8V or 2.9V output voltages, rated for loads of up to 30 mA. It is designed to be integrated with other analog cells, digital logic, microcontrollers, DSP cores and memory blocks into system-on-chip products. The circuit consists of a PMOS pass device, an error amplifier and a feedback resistive network, sized to achieve the required closed loop gain. These blocks make up the regulating loop. An over-current and short circuit protection circuit has been included to limit the output current delivered by the regulator, thus avoiding destruction in case of a short circuit. An external reference voltage (bandgap voltage) is necessary for correct functionality. The target reference voltage is 1.231V, delivered, for example, by BG019. Double pads on the supply voltage VBAT3A/VBAT3AA and output voltage VPLLA/VPLLAA are used to reduce the total output resistance. Current reference is generated inside the cell through a circuit supplied by a 2.5V 0.1V regulated input voltage on VSAUVC. Remote sense terminal VPLLS provides regulation at the load by connecting it to the output terminal near a critical point to improve performance of the regulator (e.g., connecting them at the package pin by double-bonding thus avoiding the bonding resistance influence). A ceramic capacitor of 2.2 F connected from VPLLA/VPLLAA to ground is needed as external compensation. Figure 1. Symbol(1)
vsauvc vbg vbat3a vbat3aa
Embedded ASIC Macrocell: Power Management for Mobile Terminals (PM) RE025 Programmable 2.8V or 2.9V 30 mA Low-noise LDO Voltage Regulator
vplla vpllaa on3 vplls trimldo3
vpllc
gnd3
Note:
1. Pin names are written as they appear on the user screen when the symbol is opened in the design tool environment.
Rev. 2700B-PMGMT-02/03
1
Functional Diagram
Figure 2. Functional Diagram
VBAT3A VSAUVC IREF ON3 IBIAS VBG ON3 FCOTA ON3 Pass Device VPLLC VPLLAA GND3 GND3 Current Sensing and Limiter R1 GND3 VPLLA VPLLS VBAT3AA
ON3
R21
R22
ON3
TRIMLDO3
GND3
Pin Description
Pin Name VBAT3A VBAT3AA VPLLA VPLLAA VPLLS VPLLC GND3 VSAUVC VBG ON3 TRIMLDO3 I/O Power supply Power supply Analog output Analog output Analog input Analog output Ground Power supply Analog input Digital input Digital input Type External pad External pad External pad External pad External pad Internal pin Internal pin Internal pin Internal pin Internal pin Internal pin Function Power supply Power supply Output voltage Output voltage Sense voltage Output voltage Ground Power supply Voltage reference Enable command Output voltage selection Value 3V to 5.5V 3V to 5.5V 2.75V to 2.935V 2.75V to 2.935V 2.75V to 2.935V 2.75V to 2.935V 0V 2.5V 0.1V 1.231V 0V or VBAT3A/VBAT3AA 0V or VBAT3A/VBAT3AA
2
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
2700B-PMGMT-02/03
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
Absolute Maximum Ratings*
VIN .......................................................... -0.3V to 6.5V Digital Signals......................................... -0.3V to 5.5V Output Current..................................Internally Limited Junction Temperature ..........................-40C to 150C
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Specifications(1)
TJ = -20C to 125C, VBAT3A/VBAT3AA = 3V to 5.5V unless otherwise specified, output capacitance = 2.2 F. Table 1. Electrical Specifications
Symbol VBAT3A/VBAT3AA VSAUVC Parameter Operating Supply Voltage Auxiliary Operating Supply Voltage Junction Temperature Range Output Voltage TRIMLDO3 = 0 TRIMLDO3 = VBAT3A/VBAT3AA IPLLA/IPLLAA ICC VDC VTRAN VDC VTRAN VDC VTRAN VDC VTRAN Output Current Quiescent Current Line Regulation @2.8V Transient Line Regulation @2.8V Load Regulation @2.8V Transient Load Regulation @2.8V Line Regulation @2.9V Transient Line Regulation @2.9V Load Regulation @2.9V Transient Load Regulation @2.9V Any condition IPLLA/IPLLAA = 30 mA IPLLA/IPLLAA = 30 mA rise time = fall time = 5 s 10% - 90% of IPLLA/IPLLAA 10% - 90% of IPLLA/IPLLAA rise time = fall time = 5 s IPLLA/IPLLAA = 30 mA IPLLA/IPLLAA = 30 mA rise time = fall time = 5 s 10% - 90% of IPLLA/IPLLAA 10% - 90% of IPLLA/IPLLAA rise time = fall time = 5 s 140 2 2 2 2 2 2 2 3 Condition Min 3 2.4 -20 2.75 2.855 2.8 2.9 2.5 Typ Max 5.5 2.6 125 2.85 2.935 30 250 3 3 3 10 3 6 4 13 Unit V V C V V mA A mV mV mV mV mV mV mV mV
TJ
VPLLA/VPLLAA
3
2700B-PMGMT-02/03
Table 1. Electrical Specifications (Continued)
Symbol Parameter Condition @100 Hz @1 kHz VBAT = 3V @20 kHz @100 kHz @100 Hz PSRR Power Supply Rejection Ratio at Full Load @1 kHz VBAT = 4.25V @20 kHz @100 kHz @100 Hz @1 kHz VBAT = 5.5V @20 kHz @100 kHz VN TR ISD ICC Notes: Output Noise(2) Rise Time Shut Down Current Short-circuit Current Threshold 1. Obtained by considering the parasitics of a TFBGA100 Package. 2. Obtained by using BG019 as reference voltage generator. Bandwidth = 10 Hz to 100 kHz; output current = 30 mA 100% of IPLLA/IPLLAA 10% - 90% of VPLLA/VPLLAA Min Typ -75 -75 -45 -35 -75 -75 -55 -45 -75 -75 -60 -45 32 50 200 1 170 Max Unit dB dB dB dB dB dB dB dB dB dB dB dB VRMS s A mA
4
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
2700B-PMGMT-02/03
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
Control Modes
All digital signals are referred to the supply voltage VBAT3A/BAT3AA. Table 2. Truth Table
ON3 0 1 1 TRIMLDO3 X 0 1 VPLLA/VPLLAA Power down (High-Z) Power on, VPLLA/VPLLAA = 2.8V Power on, VPLLA/VPLLAA = 2.9V
Application Example
A ceramic capacitor of 2.2 F with ESR between 20 m and 250 m connected from VPLLA/VPLLAA to ground is needed for external compensation.
Description Capacitor (CL) Min 1.8 Typ 2.2 Max 2.6 Units F
Figure 3. Application Example
2.5V Regulator (e.g., RE031)
2.5V
VSAUVC
VBAT3A VBAT3AA
1.231V Bandgap (e.g., BG019)
VBG VPLLA VPLLAA ON3 VPLLS
Battery Pack
CL
Digital Core
TRIMLDO3
VPLLC
GND3
5
2700B-PMGMT-02/03
Typical Performance Characteristics (Conditions as specified on page 9)
Static Line Regulation at Full Load and TRIMLDO3 = 0 0.06
Static Line Regulation at Full Load and TRIMLDO3 = V BAT 0.16 Output Voltage Change [mV]
Output Voltage Change [mV]
0.12
0.04
0.08
0.02
0.04
0.00 3 3.5 4 4.5 5 5.5 Battery Voltage [V]
0.00 3 3.5 4 4.5 5 5.5 Battery Voltage [V]
S ta tic L o a d R e g u l a tio n w ith T R IM L DO 3 = 0
S ta tic L o a d Re g u la tio n w ith T R IM L DO 3 = V B AT
2.0
O u tp u t V o lta g e Ch a n g e [m V ]
O u tp u t V o lta g e C h a n g e [m V ]
1.5 V B AT = 5.5V 1.0 V B AT = 4.25V 0.5 V B AT = 3V 0.0
1 .0
V BAT = 5.5V
0 .5
0 .0
V BAT = 4.25V V BAT = 3V
-0 .5
-0.5
-1 .0
-1.0 0 5 10 15 20 25 30
-1 .5 0 5 10 15 20 25 30
O u tp u t C u rre n t [m A ]
O u tp u t C u rre n t [m A ]
6
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
2700B-PMGMT-02/03
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
Typical Performance Characteristics (Conditions as specified on page 9)
Transient Line Regulation at Full Load and TRIMLDO3 = 0 2.805
Transient Line Regulation at Full Load and TRIMLDO3 = V BAT
2.899 2.898
Output Voltage [V]
Output Voltage [V]
2.804
2.897 2.896 2.895 2.894
2.803
2.802 0.35
2.893
0.4 0.45 Time [ms] 0.5 0.55



Time [ms]


T ra n sie n t L o a d R e g u la tio n w ith T RIM L DO 3 = 0
Transient Load Regulation with TRIMLDO3 = VBAT 2.898 VBAT = 5.5V Output Voltage [V] 2.897
2 .80 6
O u tp u t V o lta g e [V ]
2 .80 5
V B A T = 5.5V
2 .80 4
2.896
2 .80 3
V B A T = 4.25V V B A T = 3V
2.895
VBAT = 4.25V VBAT = 3V
2 .80 2 0 .35 0 .4 0 .45
T im e [m s]
0 .5
0 .55
2.894 0.35
0.4
0.45 Time [ms]
0.5
0.55
7
2700B-PMGMT-02/03
Typical Performance Characteristics (Conditions as specified on page 9)
P o w e r S u p p ly R e je ctio n Ra tio a t F u ll L o a d fo r T RIM L DO 3 = 0
Power Supply Rejection Ratio at Full Load for TRIMLDO3 = V BAT
100000
10 -30 -40 -50
P S RR [d B]
100
1000
10000
10 -20 -30 -40 PSRR [dB]
100
1000
10000
100000
-60 -70 -80 V B A T = 3V
V B A T = 4.25V
-50 -60 -70 -80
VBAT = 3V
V BAT = 4.25V
-90 V B A T = 5.5V -100
F re q [H z ]
-90 -100 Freq [Hz]
VBAT = 5.5V
P o w e r S u p p ly Re je cti o n R a tio a t F u l l L o a d ve rsu s Ba tte ry V o lta g e a n d T RI M L DO 3 = V B AT
P o w e r S u p p ly R e je ctio n R a tio a t F u ll L o a d ve rsu s B a tte ry V o lta g e a n d T R IM L D O 3 = 0 5.5
3.0 -20 -30 -40 -50
3.5
4.0
4.5
5.0
3.0 -20 -30 -40 -50
P S R R [d B ]
3.5
4.0
4.5
5.0
5.5
P S RR [d B]
-60 -70 -80 -90 -100 -110
Ba tte ry V o lta g e [V ]
-60 -70 -80 -90 Freq = 1 k Hz Freq = 20 k Hz Freq = 100 k Hz
F req = 1 k Hz F req = 20 k Hz
F req = 100 k Hz
F req = 100 Hz
-100 -110
Freq = 100 Hz
B a tte ry V o lta g e [V ]
L D O S ta rtu p a t F u ll L o a d fo r V B AT = 4.25V
5 4.5 TRIM LDO 3 = V BA T O N3
Output Noise Spectrum at Full Load for TRIMLDO3 = 0, VBAT = 4.25V and CL = 2.2 F 1.0E-11 Output Noise [V/sqrt(Hz)]
4 3.5
V o lta g e [V ]
1.0E-12
Total output noise 32 VRMS
3 2.5 2 1.5
1.0E-13
TRIM LDO 3 = 0 1 0.5 0 0 50 100
T im e [ s]
1.0E-14
1.0E-15
150 200
10
100
1000 Freq [Hz]
10000
100000
8
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
2700B-PMGMT-02/03
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
Terminology
Line Regulation Measures the maximum transient and DC variations of the output voltage of the LDO when the supply changes between two specified values with fixed load current; minimum rise time and fall time is 5 s. Figure 4. Line Regulation
3.4V
VBAT3A/VBAT3AA 3V
5 s
VPLLA/VPLLAA VTRAN
5 s
VDC
Load Regulation
Measures the maximum transient and DC variations of the output voltage of the LDO when the load current changes between two specified values with fixed power supply; minimum rise time and fall time is 5 s. Figure 5. Load Regulation
90% of max IPLLA/IPLLAA IPLLA/IPLLAA 10% of max IPLLA/IPLLAA 5 s
5 s
VTRAN VPLLA/VPLLAA VDC
9
2700B-PMGMT-02/03
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2700B-PMGMT-02/03 0M


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