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ST
ST3010
Audio Decoder/Encoder
Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change.
1. FEATURES
24-bit DSP based voice/audio processor Operation voltage - Core logic: 2.25V~2.7V - I/O pads: 3.0V~3.6V Voltage regulator for core logic Low Voltage Reset (LVR) _ 2.5V low voltage reset One PLL to generate high system frequency from a 3MHz source _ 12M~30MHz PLL output Tow clock sources _ Crystal...........................................................3MHz _ External input..........................................3MHz Low power down current _Typical current: 3uA One 16-bit programmable Timer One clocking output One external interrupt _ Edge/level trigger supported One 16-bit direct-drive DAC - Maximum current: 145mA MCU interfaces _ Parallel mode Two Serial PORT interfaces(SP) _ Programmable data length from 8-bit to 16-bit _ I2S, Left/Right Justified interfaces to external DAC/ADC Function List _LBRC playback (1.2Kbps, 1.6Kbps, 2.4Kbps for 8KHz) (1.6Kbps, 2.2Kbps, 3.3Kbps for 11KHz) 1. AB-Repeat 2. Time stretch (speed up x2, speed down x2) 3. Combine syllable _Audio Playback (CBR, VBR-- all bit rate) 1. Forward/Backward play , AB-Repeat 2. Encryption 3. Spectrum gain 4. Time stretch (speed up x1.5, speed down x1.5) 5. Combine syllable _Wav Playback 1. Forward/Backward play, AB-Repeat _Wav Record {MS-ADPCM(3.8:1)} 1. Software AGC
2. GENERAL DESCRIPTION
The ST3010 is a highly integrated and cost-effective 24-bit DSP based audio processor for various consumer applications. It consists of one powerful DSP for advanced voice decoder and encoder algorithms of natural speech with less memory. It provides low bit rate compression (LBRC) for voice playback and audio playback. System clock comes from 3MHz crystal or external input. ST3010 has 32 I/Os and these can be either GPIO or functional pins. Each pin can be programmed to input or output.
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One external interrupt pin can be requested by external devices. One internal 16-bit DAC can provide significant volume equipping with internal amplifier. For particular application or recorder, two general audio interfaces are supported to interface with external DAC/ADC. Audio interface can be configured to I2S or Left/Right Justified compatible mode. There are serial and parallel interfaces for various connections with different MCUs.
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2.1 Block Diagram
Figure 2-1
ST3010 Block Diagram
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3. SIGNAL DESCRIPTIONS
Table 3-1
Function Group
Signal Function Description
Pin Name RESET PWD PWDA OSCXI OSXO ECLK CMODE[1:0] TEST[2:0] SO[1:0]/ DPA[7,15] CLKO/ DPA[6] DAP[13,14], DPB[0:15] XREQ/DPA[5] TF0/DPA[0] RF0/DPA[1] TX0/DPA[2] RX0/DPA[3] SCLK0/DPA[4] TF1/DPA[8] RF1/DPA[9] TX1/DPA[10] RX1/DPA[11] SCLK1/DPA[12] D[0]/SCL D[1]/SDI D[2]/SDO D[3:7] WR RD CS CMD REQ RDY PMODE
Pin # 1 1 1 1 1 1 2 3 2 1 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1
I/O I I O I O I I I O O I/O I O I O I O O I O I O I/O I/O I/O I/O I I I I O O I
Description System reset, low active Power down, low active Power down acknowledge, high active Crystal input or R-oscillator input Crystal output External clock input Clock source select 01=Crystal 1X=ECLK Test mode SO0/DPA[7], SO1/DPA[15] Clock output/DPA[6] General I/O External interrupt/DPA[5] Transmit frame synchronization/DPA[0] Receive frame synchronization/DPA[1] Serial data transmit/DPA[2] Serial data receive/DPA[3] Serial clock/DPA[4] Transmit frame synchronization/DPA[8] Receive frame synchronization/DPA[9] Serial data transmit/DPA[10] Serial data receive/DPA[11] Serial clock/DPA[12] Parallel : Data bus Parallel : Data bus Parallel : Data bus Parallel : Data bus Parallel : Write enable, low active Parallel : Read enable, low active Parallel : Chip select, low active Parallel : Command/data select "H": Data "L": Command DSP wants to sent command to MCU, low active DSP permit MCU access data, low active Parallel interface select 0: Standard parallel (default) 1: Special parallel
System control
Special I/O
GPIO External Interrupt
Serial Port0/ DPA[4:0]
Serial Port1/ DPA[12:8]
MCU Interface
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P/S VDD25 VSS25 VDD33 VSS33 REGVDD33 REGVSS33 PLLVDD25 PLLVSS25 PLLVDD25A PLLVSS25A DACVDD33A DACVSS33A DACOVDD33A DACOVSS33A VCCOUT VREF DACO DACOB VCM 1 2 2 2 2 1 1 1 1 1 1 1 1 2 2 1 1 2 2 1 I I I I I I I I I I I I I I I O O O O O Parallel/serial interface select 0: Serial 1: Parallel 2.5V power 2.5V power ground 3.3V power 3.3V power ground Digital power input of regulator Digital power ground of regulator Digital power input of PLL Digital power ground of PLL Analog power input of PLL Analog power ground of PLL Analog power input of DAC Analog power ground of DAC Analog power input of DAC output stage Analog power ground of DAC output stage 2.5V output of regulator Voltage reference DAC direct drive pin(+) DAC direct drive pin(-) Common mode voltage reference
Power
Regulator
DAC
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4. ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Rations
DC Supply Voltage: VDD33 ---------------- -0.3V to +4.5V Operating Ambient Temperature --------- -10C to +60C Storage Temperature ------------------------ -10C to +125C
*Note: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. All the ranges are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposed to the absolute maximum rating conditions for extended periods may affect device reliability.
4.2 DC Electrical Characteristics
Table 4-1 DC Electrical Characteristics
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25C, unless otherwise specified Parameter Operating Voltage Operating Voltage Operating Current Power Down Current Output driving Output sinking Input low voltage Input high voltage Pull-up resistor Pull-down resistor Low Voltage Reset Level Symbol VDD33 VDD25 IOP1 IPD Iod Ios VIL VIH RPU RPD VLVR 2.4 Min. 3.0 2.25 2.5 30 3 15 27 0.7 1.3 49 51 2.5 2.6 4.5 Typ. Max. 3.6 2.7 Unit V V mA A mA mA V V K K V Run at 24MHz without speaker Condition
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4.3 AC Electrical Characteristics
Figure 4-1
Serial Interface Timing Diagram
Figure 4-2
Parallel Interface Timing Diagram
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Table 4-2
Timing parameters for 0 Rating Typ.
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25C
Symbol
tCSS tCYC tDS tDH tDD
Characteristic
CS low to 1 SCL rising SCL cycle time Data valid prior SCL falling Data Hold time after SCL rising SDO output delay from SCL falling
st
Min.
100 200 0 10
Max.
Unit
nS nS nS
10
nS nS
Table 4-3
Timing parameters for 0 Rating Typ.
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25C
Symbol
tCH tCS tCYC tCCLW tCCHW tCCLR tCCHR tDS tDH tACC tOH
Characteristic
Cmd pin hold time Cmd pin setup time System cycle time Write pulse width Enable H write width Read pulse width Enable H read width Write data setup time Write data hold time Read access time Read data disable time
Min.
5 5 3.5D 0.5D 3D 0.5D 3D 0.5D 5
Max.
Unit
nS nS nS nS nS nS nS nS
10 4
nS nS nS
Remark: D = time of one DSP system clock
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5. PAD DIAGRAM
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6. DEVICE INFORMATION
1. Substrate: GND PAD Symbol No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DPB7 DPB8 DPB9 DPB10 DPB11 DPB12 DPB13 DPB14 DPB15 VSS33 VDD33 PWDA PWD D7 D6 D5 D4 D3 SDO SDI SCL VDD25 VSS25 CMD PMODE REQ RDY WR RD CS X 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2940 2830 2720 2620 2520 2420 2320 2220 2120 2020 1920 1820 1720 1620 1520 1420 1320 1220 1120 1020 920 820 Y 2036.55 2136.55 2236.55 2336.55 2436.55 2546.55 2656.55 2766.55 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 PAD No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol P/S RESET CMODE0 CMODE1 OSCXI OSXO ECLK VREF VCCOUT REGVDD33 REGVSS33 PLLVSS25 PLLVDD25 PLLVSS25A PLLVDD25A DACVSS33A DACVDD33A VCM DACOB DACOB X 720 620 520 420 320 210 100 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 Y 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 2753.04 2643.04 2533.04 2433.04 2257.04 2157.04 2057.04 1957.04 1781.04 1681.04 1581.04 1481.04 1381.04 1281.04 1081.04 981.04 881.04 781.04 PAD Symbol No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TF0 RF0 TX0 RX0 SCLK0 XREQ CLKO SO0 TF1 RF1 TX1 RX1 SCLK1 DPA13 DPA14 SO1 VDD25 VSS25 TEST2 TEST1 TEST0 VSS33 VDD33 DPB0 DPB1 DPB2 DPB3 DPB4 DPB5 DPB6 X 1616.23 1716.23 1816.23 1916.23 2016.23 2116.23 2216.23 2316.23 2416.23 2516.23 2616.23 2716.23 2826.23 2936.23 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 Y 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 406.55 516.55 626.55 736.55 836.55 936.55 1036.55 1136.55 1236.55 1336.55 1436.55 1536.55 1636.55 1736.55 1836.55 1936.55
81 DACOVSS33A
82 DACOVSS33A 62.51 1181.04 83 DACOVDD33A 62.5 84 DACOVDD33A 62.5 85 86 DACO DACO 62.5 62.5
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7. APPLICATION CIRCUIT
1. ST3010 Part
Figure 7-1
ST3010 Application Circuit Diagram
Note: 1. If any of OSCXI, OSXO, and ECLK is not used, it needs to connect to GND. 2. The cascade resistor and parallel capacitor on CMD, RD, and WR pins can reduce noise interference. In general, resistor is short and capacitor is open. Please preserve the options on PCB.
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2. ADC Part
10K 10K 1.2K 1.5K 2K
Figure 7-2
ADC Application Circuit Diagram
Note:
The capacity and inductance in the left down part is to eliminate the record noise.
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3. DAC Part
Figure 7-3
DAC Application Circuit Diagram
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8. REVISION
REVISION
0.1 0.2 0.3 0.4 0.5 0.6 0.7 First release Revision: Supporting several different digital audio playback Revision together with programming guide Version 0.1 published Remove serial interface Add some new function Modify application circuit Add ADC/DAC Application Circuit
DESCRIPTION
PAGE
DATE
2005/9/16 2005/11/3 2005/11/30 2005/12/8 2006/2/22 2006/4/12 2006/4/24
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice and makes no warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Ver 0.7 13/13 2007-06-14

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