View RT8841_43713.PDF datasheet online --- IC-ON-LINE

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Conceptual
RT8841
4/3/2/1-Phase PWM Controller for High-Density Power Supply
General Description
The RT8841 is a 4/3/2/1-phase synchronous buck controller with 2 integrated MOSFET drivers for VR11 CPU power application. RT8841 uses differential inductor DCR current sense to achieve phase current balance and active voltage positioning. Other features include adjustable operating frequency, adjustable soft start, power good indication, external error-amp compensation, over voltage protection, over current protection and enable/shutdown for various applications. RT8841 comes to a small footprint with WQFN-40L 6x6 package
Features
12V Power Supply Voltage 4/3/2/1-Phase Power Conversion 2 Embedded MOSFET Drivers Internal Regulated 5V Output VID Tables for Intel VRD11/VRD10.x and AMD K8, K8_M2 CPUs Continuous Differential Inductor DCR Current Sense Adjustable Soft Start Adjustable Frequency Power Good Indication Adjustable Over Current Protection Over Voltage Protection Small 40-Lead WQFN Package RoHS Compliant and 100% Lead(Pb)-Free
Applications
Desktop CPU Core Power Low Voltage, High Current DC/ DC Converter
Ordering Information
RT8841 Package Type QW : WQFN-40L 6x6 (W-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
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Pin Configurations
(TOP VIEW)
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 EN/VTT PWRGD
40 39 38 37 36 35 34 33 32 31
Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating.
VIDSEL FBRTN SS/EN ADJ COMP FB OFS RT IMAX GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 41
30 29 28 27
GND
26 25 24 23 22 21
BOOT1 UGATE1 PHASE1 LGATE1 VCC12 LGATE2 PHASE2 UGATE2 BOOT2 PWM3
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ISP4 ISN4 ISN3 ISP3 ISP2 ISN2 ISN1 ISP1 VCC5 PWM4
WQFN-40L 6x6
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RT8841
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12V RT8841 4 ADJ BOOT1 30 UGATE1 29 PHASE1 28 LGATE1 27 L1 19 VCC5 7 OFS 8 RT 9 IMAX 12V 12V NTC
Typical Application Circuit
VCO
12V
BOOT UGATE GND PWM
UGATE2 23 PHASE2 24 LGATE2 25 21 PWM3
VCC
L2
PHASE LGATE
RT9619 14 ISP3 13 ISN3 12V 12V
ISP1 18 ISN1 17 33 to 40 VID[7:0] 32 EN/VTT 1 VIDSEL 31 PWRGD BOOT2 22
Conceptual
L2
ISP2 15 16 ISN2 6 FB COMP 5
BOOT UGATE GND PWM
20
VCC
L2
PHASE LGATE
RT9619
PWM4
LOAD
12V 11 ISP4 12 ISN4 GND 10
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Conceptual
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID2 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID6 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
RT8841
Nominal Output Voltage DACOUT 1.60000V 1.59375V 1.58750V 1.58125V 1.57500V 1.56875V 1.56250V 1.55625V 1.55000V 1.54375V 1.53750V 1.53125V 1.52500V 1.51875V 1.51250V 1.50625V 1.50000V 1.49375V 1.48750V 1.48125V 1.47500V 1.46875V 1.46250V 1.45625V 1.45000V 1.44375V 1.43750V 1.43125V 1.42500V 1.41875V 1.41250V 1.40625V 1.40000V 1.39375V 1.38750V 1.38125V 1.37500V 1.36875V 1.36250V
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To be continued
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Conceptual
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name Nominal Output Voltage DACOUT VID5 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.35625V 1.35000V 1.34375V 1.33750V 1.33125V 1.32500V 1.31875V 1.31250V 1.30625V 1.30000V 1.29375V 1.28750V 1.28125V 1.27500V 1.26875V 1.26250V 1.25625V 1.25000V 1.24375V 1.23750V 1.23125V 1.22500V 1.21875V 1.21250V 1.20625V 1.20000V 1.19375V 1.18750V 1.18125V 1.17500V 1.16875V 1.16250V 1,15625V 1.15000V 1.14375V 1.13750V 1.13125V 1.12500V 1.11875V
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VID1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
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Conceptual
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name VID4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Nominal Output Voltage DACOUT
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
VID0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
VID5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
VID6 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.11250V 1.10625V 1.10000V 1.09375V OFF OFF OFF OFF 1.08750V 1.08125V 1.07500V 1.06875V 1.06250V 1.05625V 1.05000V 1.04375V 1.03750V 1.03125V 1.02500V 1.01875V 1.01250V 1.00625V 1.00000V 0.99375V 0.98750V 0.98125V 0.97500V 0.96875V 0.96250V 0.95625V 0.95000V 0.94375V 0.93750V 0.93125V 0.92500V 0.91875V 0.91250V 0.90625V 0.90000V
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
To be continued
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Conceptual
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name Nominal Output Voltage DACOUT VID5 1 0 0 1 1 0 0 1 1 0 0 VID6 0 1 0 1 0 1 0 1 0 1 0 0.89375V 0.88750V 0.88125V 0.87500V 0.86875V 0.86250V 0.85625V 0.85000V 0.84375V 0.83750V 0.83125V
VID4 0 0 0 0 0 0 0 0 0 0 0
VID3 0 1 1 1 1 1 1 1 1 1 1
VID2 1 0 0 0 0 0 0 0 0 0 0
VID1 1 0 0 0 0 0 0 0 0 1 1
VID0 1 0 0 0 0 1 1 1 1 0 0
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Conceptual
Table 2. Output Voltage Program (VRD11)
Pin Name HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16
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Nominal Output Voltage DACOUT 1.36875V 1.36250V 1.35625V 1.35000V 1.34375V 1.33750V 1.33125V 1.32500V 1.31875V 1.31250V 1.30625V 1.30000V 1.29375V 1.28750V 1.28125V 1.27500V 1.26875V 1.26250V 1.25625V 1.25000V 1.24375V 1.23750V 1.23125V 1.22500V 1.21875V 1.21250V 1.20625V 1.20000V 1.19375V 1.18750V 1.18125V 1.17500V 1.16875V 1.16250V 1.15625V 1.15000V 1.14375V 1.13750V 1.13125V
Nominal Output Voltage DACOUT OFF OFF 1.60000V 1.59375V 1.58750V 1.58125V 1.57500V 1.56875V 1.56250V 1.55625V 1.55000V 1.54375V 1.53750V 1.53125V 1.52500V 1.51875V 1.51250V 1.50625V 1.50000V 1.49375V 1.48750V 1.48125V 1.47500V 1.46875V 1.46250V 1.45625V 1.45000V 1.44375V 1.43750V 1.43125V 1.42500V 1.41875V 1.41250V 1.40625V 1.40000V 1.39375V 1.38750V 1.38125V 1.37500V
Pin Name HEX 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D
17 18 19
1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26
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Pin Name HEX 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64
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Conceptual
Table 2. Output Voltage Program (VRD11)
Nominal Output Voltage DACOUT 1.12500V 1.11875V 1.11250V 1.10625V 1.10000V 1.09375V 1.08750V 1.08125V 1.07500V 1.06875V 1.06250V 1.05625V 1.05000V 1.04375V 1.03750V 1.03125V 1.02500V 1.01875V 1.01250V 1.00625V 1.00000V 0.99375V 0.98750V 0.98125V 0.97500V 0.96875V 0.96250V 0.95625V 0.95000V 0.94375V 0.93750V 0.93125V 0.92500V 0.91875V 0.91250V 0.90625V 0.90000V 0.89375V 0.88750V
Pin Name HEX 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B
Nominal Output Voltage DACOUT 0.88125V 0.87500V 0.86875V 0.86250V 0.85625V 0.85000V 0.84375V 0.83750V 0.83125V 0.82500V 0.81875V 0.81250V 0.80625V 0.80000V 0.79375V 0.78750V 0.78125V 0.77500V 0.76875V 0.76250V 0.75625V 0.75000V 0.74375V 0.73750V 0.73125V 0.72500V 0.71875V 0.71250V 0.70625V 0.70000V 0.69375V 0.68750V 0.68125V 0.67500V 0.66875V 0.66250V 0.65625V 0.65000V 0.64375V
65 66 67 68 69
6A 6B 6C 6D 6E 6F 70 71 72 73 74
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Conceptual
Table 2. Output Voltage Program (VRD11)
Pin Name HEX 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2
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Nominal Output Voltage DACOUT X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Nominal Output Voltage DACOUT 0.63750V 0.63125V 0.62500V 0.61875V 0.61250V 0.60625V 0.60000V 0.59375V 0.58750V 0.58125V 0.57500V 0.56875V 0.56250V 0.55625V 0.55000V 0.54375V 0.53750V 0.53125V 0.52500V 0.51875V 0.51250V 0.50625V 0.50000V X X X X X X X X X X X X X X X X
Pin Name HEX C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9
B3 B4 B5 B6 B7 B8 B9
BA BB BC BD BE BF C0 C1 C2
To be continued
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Pin Name HEX EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Nominal Output Voltage DACOUT X X X X X X X X X X X X X X X X X X X X OFF OFF
Conceptual
Table 2. Output Voltage Program (VRD11)
Note: (1) 0 : Connected to GND (2) 1 : Open www..com (3) X : Don't Care
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Conceptual
Table 3. Output Voltage Program (K8)
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
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Nominal Output Voltage DACOUT 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.200 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown
VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1
Note: (1) 0 : Connected to GND (2) 1 : Open
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Pin Name VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Conceptual
Table 4. Output Voltage Program (K8_M2)
Nominal Output Voltage DACOUT VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.5500 1.5250 1.5000 1.4750 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 1.2500 1.2250 1.2000 1.1750 1.1500 1.1250 1.1000 1.0750 1.0500 1.0250 1.0000 0.9750 0.9500 0.9250 0.9000 0.8750 0.8500 0.8250 0.8000 0.7750 0.7625 0.7500
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
0 0 0 0 0 0 0 0 0 0 1 1
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Conceptual
Table 4. Output Voltage Program (K8_M2)
Pin Name VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Nominal Output Voltage DACOUT 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1
Note: (1) 0 : Connected to GND (2) 1 : Open (3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above correspond to zero load current.
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Functional Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11,14,15,18 12,13,16,17 19 20,21 22,30 23,29 24,28 25,27 26 31 32 33 to 40 Exposed pad(41) www..com Pin Name VIDSEL FBRTN SS/EN ADJ COMP FB OFS RT IMAX GND
Conceptual
Pin Function VID DAC Selection Pin. Negative remote sense pin of output voltage. Connect this pin to GND by a capacitor to adjust soft start time. Pull this pin to GND to disable controller. Connect this pin to GND by a resistor to set loadline. Output of error-amp and input of PWM comparator. Inverting input of error-amp. Connect this pin to GND by a resistor to set no-load offset voltage. Connect this pin to GND by a resistor to adjust frequency. Negative input of OCP comparator. (Positive input of OCP comparator is ADJ). Ground Pin
ISP4, ISP3, ISP2, ISP1 Positive current sense pin of channel 1, 2, 3 and 4. ISN4, ISN3, ISN2, ISN1 Negative current sense pin of channel 1, 2, 3 and 4. VCC5 PWM4, PWM3 BOOT2, BOOT1 UGATE2, UGATE1 PHASE2, PHASE1 LGATE2, LGATE1 VCC12 PWRGD EN/VTT VID7 to VID0 GND Connect this pin to GND by a ceramic cap larger than 1uF. PW M output for channel 4 and channel 3. Bootstrap supply for channel 2 and channel 1. Upper gate driver for channel 2 and channel 1. Switching node of channel 2 and channel 1. Lower gate driver for channel 2 and channel 1. IC power supply. Connect to 12V. Power good indicator. VTT voltage detector input. Voltage identification input for DAC. Exposed pad should be soldered to PCB board and connected to GND.
VID Table Selection
VIDSEL VTT GND VCC5 VCC5 VID [7] X X VTT GND Table VR11 VR10.x K8 K8_M2
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Conceptual Function Block Diagram
Modulator Waveform Generator POR COMP FB EA + Offset
RT8841
RT
VCC12 Power-On Reset 5V Regulator VCC5
BOOT1 OFS + + + 150mV + Transient Response Enhancement + OV OC VIDOFF POR SS/EN EN/VTT + 850mV + I_SEN1 CH3_EN Detector BOOT2 MOSFET Driver UGATE2 PHASE2 LGATE2 PWM3 OV MOSFET Driver UGATE1 PHASE1 LGATE1
Soft Start and Fault Logic
+ -
PWM4 CH4_EN Detector
-
CH1 Current SENSE CH2 Current SENSE CH3 Current SENSE CH4 Current SENSE
ISP1 ISN1
+
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ADJ IMAX
VID Table Generator
I_SEN2
ISP2 ISN2
-
-
+
+
AVG
+
+ OC
I_SEN3
ISP3 ISN3
+
-
I_SEN4
ISP4 ISN4
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Absolute Maximum Ratings
Conceptual
(Note 1)
Supply Input Voltage --------------------------------------------------------------------------------------------------------- -0.3V to 15V BOOTx to PHASEx ---------------------------------------------------------------------------------------------------------- -0.3V to 15V BOOTx to GND ---------------------------------------------------------------------------------------------------------------- -0.3V to 30V PHASEx to GND -------------------------------------------------------------------------------------------------------------- -2V to 15V Input/Output Voltage --------------------------------------------------------------------------------------------------------- -0.3V to 7V Power Dissipation, PD @ TA = 25C WQFN-40L 6x6 --------------------------------------------------------------------------------------------------------------- 2.778W Package Thermal Resistance (Note 4) WQFN-40L 6x6, JA ---------------------------------------------------------------------------------------------------------- 36C/W Junction Temperature -------------------------------------------------------------------------------------------------------- 150C Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------------------- 260C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------------- 2kV MM (Machine Mode) --------------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC12 ---------------------------------------------------------------------------------------------------- 12V 10% Junction Temperature Range ---------------------------------------------------------------------------------------------- -40C to 125C Ambient Temperature Range ---------------------------------------------------------------------------------------------- 0C to 70C
Electrical Characteristics
(VCC12 = 12V, VGND = 0V, TA = 25C, unless otherwise specified)
Parameter VCC12 Supply Input VCC12 Supply Voltage VCC12 Supply Current www..com VCC5 power VCC5 Supply Voltage VCC5 Output Sourcing Power-On Reset VCC12 Rising Threshold VCC12 Hysteresis VCC5 Rising Threshold VCC5 Hysteresis Power Monitor Power Monitor Maximum Output Voltage EN/VTT EN/VTT Rising Threshold Enable Hysteresis
Symbol
Conditions
Min
Typ
Max
Unit
V VCC12 ICC V VCC5 IVCC5 V VCC12TH V VCC12HY V VCC5TH V VCC5HY ILO AD = 10mA
10.8 -4.75 20 9.2 -4.4 --
12 6 5.0 -9.6 0.9 4.6 0.4
13.2 -5.25 -10.0 -4.8 --
V mA V mA V V V V
VCC12 Rising VCC12 Falling VCC5 Rising VCC5 F alling
--
1.15
--
V
V ENVTT V ENVTTHY
EN/VTT Rising EN/VTT Falling 0.8V to 1.6V 0.5V to 0.8V
0.80 --5 -8
0.85 100 ---
0.90 -+5 +8
V mV mV mV
Reference Voltage accuracy DAC Accuracy
To be continued
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Conceptual
Parameter Error Amplifier DC Gain Gain-Bandwidth Slew Rate Output voltage range Max Current Power Sequence PWRGD Low Voltage Soft-Start Delay VBOOT Duration PWRGD Delay Current Sense Amplifier Max Current Input Offset Voltage Running Frequency RT Pin Voltage Ramp Amplitude Soft Start Soft Start Current VID change Current Gate Driver UGATE Drive Source UGATE Drive Sink
www..com Source LGATE Drive
RT8841
Min --10 0.5 300 ----Typ 80 10 ---2 0.8 1.6 Max ---3.6 -0.4 ---Unit dB MHz V/s V A V ms ms ms
Symbol ADC GBW SR VCOMP IEA_SLEW VPGOOD TD1 TD3 TD5
Conditions No Load CLOAD = 10pF CLOAD = 10pF Slew IPWRGD = 4mA
Measured the time form VBOOT change to PWRGD = 1 VCSP = 1.3V Sink Current from CSN RRT = 40k RRT = 40k RRT = 40k Slew Slew BOOT - PHASE = 8V 250mA Source Current BOOT - PHASE = 8V 250mA Sink Current VLGATE = 8V 250mA Sink Current Sweep FB Voltage, VFB,EAP Sweep IMAX Voltage, VIMAX,ADJ
IGMMAX VOSCS fOSC VRT VRAMP ISS1 ISS2
100 -1 280 1.52 -6 60
-0 300 1.60 1.60 8 80
-1 320 1.68 -10 100
A mV kHz V V A A mV mV ns ns ns ns
RUGATEsr RUGATEsk RLGATEsr RLGATEsk VOVP VOCP trUGATE tfUGATE trLGATE tfLGATE
----125 -10 -----
1 1 1 0.8 150 0 15 10 15 10
----175 +10 -----
LGATE Drive Sink Protection Over-Voltage Threshold Over-Current Threshold Dynamic Characteristic UGATE Rise Time UGATE Fall Time LGATE Rise Time LGATE Fall Time
Ciss = 3000p
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Conceptual
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. JA is measured in the natural convection at TA = 25C on a effective single layer thermal conductivity test board of JEDEC thermal measurement standard.
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Conceptual Typical Operating Characteristics
Frequency vs. RRT
1200 1000
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Output Voltage vs. Temperature
1.324 1.323 1.322
Output Voltage (V)
Frequency (kHz)
800 600 400 200 0 0 10 20 30 40 50 60 70
1.321 1.320 1.319 1.318 1.317 1.316 1.315 1.314 -40 -20 0 20 40 60 80 100 120 140
VIN = 12V, IOUT = 0A
RRT (k)
Temperature
Frequency vs. Temperature
380 375
Power On from VTT/EN
RRT = 30.1k
Frequency (kHz)
370 365 360 355 350
VOUT (1V/Div) VTT/EN (1V/Div) PGOOD (1V/Div) PHASE (10V/Div)
0 20 40 60 80 100 120 140
VIN = 12V, VOUT = 1.4V, IOUT = 0A
345 www..com -40 -20
Time (2ms/Div)
Temperature (C)
Power Off from VTT/EN
Power On from VIN
VOUT (1V/Div) VTT/EN (1V/Div) SS (2V/Div) PHASE (10V/Div)
VOUT (1V/Div) VIN (10V/Div) PGOOD (2V/Div) PHASE (10V/Div)
VIN = 12V, VOUT = 1.4V, IOUT = 0A
VIN = 12V, VOUT = 1.4V, IOUT = 0A
Time (40us/Div)
Time (4ms/Div)
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September 2007
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RT8841
Power Off from VIN
Conceptual
ACLL Drop
VOUT (1V/Div) VIN (10V/Div) SS (2V/Div) PHASE (10V/Div)
VOUT (20mV/Div)
IOUT (A)
VIN = 12V, VOUT = 1.4V, IOUT = 0A
67.5 35
IOUT = 35 to 67.5A
Time (4ms/Div)
Time (20us/Div)
ACLL Overshoot
Rising
Dynamic VID
VOUT (20mV/Div)
VOUT (500mV/Div)
IOUT (A)
67.5 35
IOUT = 67.5 to 35A
VID (1V/Div)
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Time (20us/Div)
Time (40us/Div)
Dynamic VID
Falling
Output Short then Power On
VIN = 12V, VOUT = 1.4V
VOUT (1V/Div) VOUT (500mV/Div) PGOOD (1V/Div) SS (2V/Div) VID (1V/Div) PHASE (10V/Div)
Time (40us/Div)
Time (1ms/Div)
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DS8841-02C
September 2007
Conceptual
RT8841
OVP
FB
Power On then Output Short
VIN = 12V, VOUT = 1.4V
VOUT (1V/Div) PGOOD (1V/Div) SS (2V/Div) PHASE (10V/Div)
PGOOD (1V/Div) FB (500mV/Div) SS (2V/Div) PHASE (10V/Div) Time (1ms/Div) Time (40us/Div)
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DS8841-02C
September 2007
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RT8841
Application Information
Conceptual
Phase Switching Frequency The phase switching frequency of the RT8841 is set by an external resistor connected from the RT pin to GND. The frequency follows the graph in Figure 2.
RT8841 is a 4/3/2/1-phase synchronous buck DC/DC converter with 2 embedded MOSFET drivers. The internal VID DAC is designed to interface with the Intel 8-bit VR11 compatible CPUs. Power Ready Detection During start-up, RT8841 will detect VCC12, VCC5 and VTT. When VCC12 > 9.6V, VCC5 > 4.6V and VTT > 0.85V POR will go high. POR (Power On Reset) is the internal signal to indicate all voltage powers are ready to let RT8841 and the companioned MOSFET drivers to work properly. When POR = L, RT8841 will try to turn off both high side and low side MOSFETs.
CMP
Frequency vs. RRT
1000
800
Frequency (kHz)
600
400
200
V CC 12 9.6V V CC 5 4.6V V TT 0.85V
+ + + -
0
CMP POR CMP POR : Power On Reset
0
10
20
30
40
50
60
70
RRT (k ) (k)
Figure 2. RRT vs Phase Switching Frequency
Figure 1. Circuit for Power Ready Detection Phase Detection The number of operational phases is determined by the internal circuitry that monitors the ISNx voltages during start up. Normally, the RT8841 operates as a 4-phase www..com PWM controller. Pull ISN4 and ISP4 to VCC5 programs 3-phase operation, pull ISN3 and ISP3 to VCC5 programs 2-phase operation, and pull ISN2 and ISP2 to VCC5 programs 1-phase operation. RT8841 detects the voltage of ISN4, ISN3 and ISN2 at POR rising edge. At the rising edge, RT8841 detects whether the voltage of ISN4, ISN3 and ISN2 are higher than "VCC5 - 1V" respectively to decide how many phases should be active. Phase detection is only active during start up. When POR = H, the number of operational phases is determined and latched.
VDAC Gnerator
VGB 16V R2 FBRTN R3 1.0V R4 0.8V R5 0.6V R6 0.4V R7 1.2V 0.5V to 1.6V Step = 6.25mV MUX V DAC + R1 1.4V VID[7:0] 1.6V
R8 FBRTN
Figure 3. VDAC Generator Circuit
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DS8841-02C
September 2007
Conceptual
RT8841 builds a precise bandgap reference circuit inside. The output voltage of bandgap reference is 1.6V referred to FBRTN. In Figure 3, RT8841 uses plural resistors to generate precise reference voltages ranging from 0.5V to 1.6V. All the voltages connect to a multiplexer (MUX). According to the VID inputs, multiplexer outputs the selected voltage, VDAC. Please be careful that all the voltage values in Figure 3 are referred to FBRTN. Soft Start
Output current of OPSS (ISS) is limited and variant V DAC OPSS +
-
RT8841
VOUT will trace VEAP which is equal to "VSSQ - VADJ". VADJ is a small voltage signal which is proportional to IOUT. This voltage is used to generate loadline and will be described later. T1 is the delay time from power_on_reset state to the beginning of VOUT rising. T1 = 1600s + 0.6V x CSS/ISS1 (1)
T2 is the soft start time from VOUT = 0 to VOUT = VBOOT. T2 = VBOOT x CSS/ISS1 T3 is the dwelling time for VOUT = VBOOT. T3 = 800s. T4 is the soft start time from VOUT = VBOOT to VOUT = VDAC. T4 ~= |VDAC - VBOOT| x CSS/ISS1 (3) (2)
SSQ SS C SS
+ADJ R ADJ NTC
EAP (ErrorAmp positive input)
T5 is the power good delay time, T5 ~= 1600s. Dynamic VID The RT8841 can accept VID input changing while the controller is running. This allows the output voltage (VOUT) to change while the DC/DC converter is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The CPU changes the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. Theoretically, VOUT should follow VDAC which is a staircase waveform. In RT8841, as mentioned in soft start session, VDAC slew rate is limited by ISS2/CSS when PWRGD = H. This slew rate limiter works as a low pass filter of VDAC and makes the bandwidth of VDAC waveform finite. By smoothening VDAC staircase waveform, VOUT will no longer overshoot or undershoot. On the other hand, CSS will increase the settling time of VOUT during VID OTF. In most cases, 1nF to 30nF ceramic capacitor is suitable for CSS.
Figure 4. Circuit for Soft Start and Dynamic VID The VOUT start-up time is set by a capacitor from the SS pin to GND. In power_on_reset state (POR = L), the SS pin is held at GND. After power_on_reset stae (POR = H) and an extra delay 1600s, VSS and VSSQ begin to rise till VSSQ = VBOOT. When VSSQ = VBOOT, RT8841 stays in this state for 800s waiting for valid VID code sent by CPU. After receiving valid VID code, VOUT continues ramping up or down to the www..com voltage specified by VID code. Before PWRGD = H, output current of OPSS (ISS) is limited to 8A (ISS1). When PWRGD = H, ISS is limited to 80A (ISS2). The soft start waveform is shown in Figure 5.
VTT VCC5 VCC12 VDAC
0.85V 4.6V UVLO THRESHOLD
SS SSQ PWRGD T1 T2 T3 T4 T5
VBOOT
Figure 5. Soft Start Waveforms
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RT8841
Output Voltage Differential Sensing
C2 C FB C1
Conceptual
Load Transient Quick Response
CFB C2 IOUT VOUT RFB FB R1 C1 COMP VOUT FB
R1
R FB V CCP (Positive remote sense pin of CPU)
FB IOFSP
EAP = VQR - VADJ + + EAP - VQR QR FB = VEAP = VEAP - VQR QR
+ (Negative remote sense pin of CPU) V CCN R ADJ ADJ V DAC
-
+EAP
+
EA
COMP
Figure 7. Load Transient Quick Response
IOFSN
FBRTN
Figure 6. Circuit for VOUT Differential Sensing and No Load Offset The RT8841 uses differential sensing by a high gain low offset ErrorAmp. The CPU voltage is sensed between the FB and FBRTN pins. A resistor (RFB) connects FB pin and the positive remote sense pin of the CPU (VCCP). FBRTN pin connects to the negative remote sense pin of CPU (VCCN) directly. The ErrorAmp compares EAP (= VDAC - VADJ) with the VFB to regulate the output voltage. No-Load Offset In Figure 6, IOFSN and IOFSP are used to generate no-load offset. Either IOFSN or IOFSP is active during normal operation. Connect a resistor from OFS pin to GND to activate IOFSN. www..com IOFSN flows through RADJ from ADJ pin to GND. In this case, negative no-load offset voltage (VOFSN) is generated. VOFSN = IOFSN x RADJ = 0.8 x RADJ/ROFS (4)
In steady state, the voltage of VFB is controlled to be very close to VEAP. While a load step transient from light load to heavy load could cause VFB lower than VEAP by several tens of mV. In prior design, owing to limited control bandwidth, controller is hard to prevent VOUT undershoot during quick load transient from light load to heavy load. RT8841 detects load transient by comparing VFB and VEAP. If VFB suddenly drops below "VEAP - VQR", VQR is a predetermined voltage. The quick response indicator QR rises up. When QR = H, RT8841 turns on all high side MOSFETs and turn off all low side MOSFETs. The sensitivity of quick response can be adjusted by the values of CFB and RFB. Smaller RFB and/or larger CFB will make QR easier to be triggered. Figure 7 is the circuit and typical waveforms. Output Current Sensing
L RS CSA: Current Sense Amplifier ISP 235nA IX V OFS_CSA 235nA + R CSP
DCR CS
Connect a resistor from OFS pin to VCC5 to activate IOFSP. IOFSP flows through RFB from the VCCP to FB pin. In this case, positive no-load offset voltage (VOFSP) is generated. VOFSP = IOFSP x RFB = 6.4 x RFB/ROFS (5)
+ -
ISN
R CSN
Figure 8. Circuit for Channel Current Sensing
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DS8841-02C
September 2007
Conceptual
The RT8841 provides low input offset current-sense amplifier (CSA) to monitor the output current of every channel. Output current of CSA (IX[n]) is used for channel current balance and active voltage position. In this inductor current sensing topology, RS and CS must be set according to the equation below : L/DCR = RS x CS (6) Current Balance
COMP
+ CMP -
RT8841
RAMP[1] Interleaved RAMP[n]
+
BUF
PWM[1]
-
IERR [1] x R CB
+
-
+ CMP -
BUF
PWM[n]
Then the output current of CSA will follow the equation below : IX = [IL x DCR - VOFS-CSA + 235n x (RCSP - RCSN)]/RCSN (7) 235nA is typical value of CSA input offset current. VOFS-CSA is the input offset voltage of CSA. VOFS-CSA of RT8841 is smaller than +/- 1mV. Usually, "VOFS-CSA + 235n x (RCSP - RCSN)" is negligible except at very light load and the equation can be simplified as the equation below : IX = IL x DCR/RCSN Loadline Output current of CSA is summed and averaged in RT8841. Then 0.5(IX[n]) is sent to ADJ pin. Because IX[n] is a PTC (Positive Temperature Coefficient) current, an NTC (Negative Temperature Coefficient) resistor is needed to connect ADJ pin to GND. If the NTC resistor is properly selected to compensate the temperature www..com I X[n], the voltage on ADJ pin will be coefficient of proportional to IOUT without temperature effect. In RT8841, the positive input of ErrorAmp is "VDAC - VADJ". VOUT will follow "VDAC - VADJ", too. Thus, the output voltage decreasing linearly with IOUT is obtained. The loadline is defined as LL(loadline) = VOUT/IOUT = VADJ/IOUT = 0.5 x DCR x RADJ/RCSN (9) (8)
IERR [n] x R CB
Figure 9. Circuit for Channel Current Balance In Figure 8, IX[n] is the current signal which is proportional to current flowing through channel n. In Figure 9, the current error signals IERR[n] (= IX[n] - AVG(IX[n])) are used to raise or lower the internal sawtooth waveforms (RAMP[1] to RAMP[n]) which are compared with ErrorAmp output (COMP) to generate PWM signal. The raised sawtooth waveform will decrease the PWM duty of the corresponding channel while the lowered will increase. Eventually, current flowing through each channel will be balanced. Channel Current Adjust If channel current is not balanced due to asymmetric PCB layout of power stage, external resistors can be adjusted to correct current imbalance. Figure 10 shows two types of current imbalance, constant ratio type and constant difference type.
I1 I2
IOUT, total Constant ratio
Briefly, the resistance of RADJ sets the resistance of loadline. The temperature coefficient of RADJ compensates the temperature effect of loadline.
I1 I2
IOUT, total Constant difference
Figure 10. Channel Current vs. Total Current
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RT8841
Conceptual
If the initial current distribution is constant ratio type, according to Equation(8), reduce RCSN[1] can reduce IL[1] and improve current balance. If the initial current distribution is constant difference type, according to Equation(7), increase RCSP[1] can reduce IL[1] and improve current balance. Over Current Protection (OCP)
V CC 5 R1 ADJ IMAX R2
+ CMP -
OCP
Figure 11. Over Current Protection In Figure 11, VIMAX is equal to 5V x R2/(R1 + R2). In RT8841, VADJ is proportional to IOUT and is thermally compensated. Once VADJ is larger than VIMAX, OCP is triggered and latched. RT8841 will turn off both high side MOSFET and low side MOSFET of all channels. A 20uS delay is used in OCP detection circuit to prevent false trigger. Over Voltage Protectiom (OVP) The over voltage protection monitors the output voltage via the FB pin. Once VFB exceeds "VEAP + 150mV", OVP is triggered and latched. RT8841 will try to turn on low side MOSFET and turn off high side MOSFET to protect www..com CPU. A 20s delay is used in OVP detection circuit to prevent false trigger.
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DS8841-02C
September 2007
Conceptual
Datasheet Revision History
Version 00C 01C Data 2007/5/25 Pin Configurations 2007/7/30 Typical Operating Characteristics Application Information 02C 2007/9/14 Pin Configurations Function Block Page No. Item First Edition Modify Add Curve Modify pin10.
RT8841
Description
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DS8841-02C
September 2007
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RT8841
Outline Dimension
D
Conceptual
D2
SEE DETAIL A L 1
E
E2
1
1 2
e A A3 A1
b
2
DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.
Symbol A A1 A3
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Dimensions In Millimeters Min 0.700 0.000 0.175 0.180 5.950 4.000 5.950 4.000 0.500 0.350 0.450 Max 0.800 0.050 0.250 0.300 6.050 4.750 6.050 4.750
Dimensions In Inches Min 0.028 0.000 0.007 0.007 0.234 0.157 0.234 0.157 0.020 0.014 0.018 Max 0.031 0.002 0.010 0.012 0.238 0.187 0.238 0.187
b D D2 E E2 e L
W-Type 40L QFN 6x6 Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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DS8841-02C
September 2007

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