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| Freescale Semiconductor Advance Information MC9328MXL/D Rev. 5, 08/2004 MC9328MXL MC9328MXL Package Information Plastic Package (MAPBGA-225 or 256) Ordering Information See Table 2 on page 5 1 Introduction The i.MX family builds on the DragonBall family of application processors which have demonstrated leadership in the portable handheld market. Continuing this legacy, the i.MX (Media Extensions) series provides a leap in performance with an ARM9TM microprocessor core and highly integrated system functions. The i.MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The new MC9328MXL features the advanced and powerefficient ARM920TTM core that operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller, USB support, and an MMC/SD host controller, support a suite of peripherals to enhance any product seeking to provide a rich multimedia experience. It is packaged in either a 256-pin Mold Array Process-Ball Grid Array (MAPBGA) or 225-pin PBGA package. Figure 1 shows the functional block diagram of the MC9328MXL. Contents 1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Signals and Connections . . . . . . . . . . . . . . . . . . . .6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Pin-Out and Package Information. . . . . . . . . . . . .79 Contact Information . . . . . . . . . . . . . . . . . Last Page (c) Freescale Semiconductor, Inc., 2004. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice. Introduction System Control JTAG/ICE Bootstrap Power Control CGM (PLLx2) Standard System I/O GPIO Connectivity MMC/SD MC9328MXL CPU Complex PWM Timer 1 & 2 RTC Memory Stick(R) Host Controller ARM9TDMITM SPI 1 and SPI 2 UART 1 UART 2 SSI/I2S I2C USB Device AIPI 2 DMAC (11 Chnl) EIM & SDRAMC Bus Control I Cache D Cache Watchdog Multimedia Multimedia Accelerator Video Port AIPI 1 VMMU Interrupt Controller Human Interface LCD Controller Figure 1. MC9328MXL Functional Block Diagram 1.1 Conventions This document uses the following conventions: * * * * * * * * OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. -- Active low signals change from logic level one to logic level zero. -- Active high signals change from logic level zero to logic level one. * Negated means that an asserted discrete signal changes logic state. -- Active low signals change from logic level zero to logic level one. -- Active high signals change from logic level one to logic level zero. * * LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal. MC9328MXL Advance Information, Rev. 5 2 Freescale Semiconductor Introduction 1.2 Features To support a wide variety of applications, the MC9328MXL offers a robust array of features, including the following: * * * * * * * * * * * * * * * * * * * * * * * * * * ARM920TTM Microprocessor Core AHB to IP Bus Interfaces (AIPIs) External Interface Module (EIM) SDRAM Controller (SDRAMC) DPLL Clock and Power Control Module Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2) Two Serial Peripheral Interfaces (SPI1 and SPI2) Two General-Purpose 32-bit Counters/Timers Watchdog Timer Real-Time Clock/Sampling Timer (RTC) LCD Controller (LCDC) Pulse-Width Modulation (PWM) Module Universal Serial Bus (USB) Device Multimedia Card and Secure Digital (MMC/SD) Host Controller Module Memory Stick(R) Host Controller (MSHC) Direct Memory Access Controller (DMAC) Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module Inter-IC (I2C) Bus Module Video Port General-Purpose I/O (GPIO) Ports Bootstrap Mode Multimedia Accelerator (MMA) Power Management Features Operating Voltage Range: 1.7 V to 1.98 V core, 1.7 V to 3.3V I/O 256-pin MAPBGA Package 225-pin MAPBGA Package 1.3 Target Applications The MC9328MXL is targeted for advanced information appliances, smart phones, Web browsers, digital MP3 audio players, handheld computers, and messaging applications. MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 3 Introduction 1.4 Revision History Table 1 provides revision history for this release. This history includes technical content revisions only and not stylistic or grammatical changes. Table 1. MC9328MXL Data Sheet Revision History Rev. 5 Revision Location Throughout Section 3.3, "Power Sequence Requirements" on page 12 Revision Clarified instances where BCLK signal is burst clock. Added reference to AN2537. 1.5 Product Documentation The following documents are required for a complete description of the MC9328MXL and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall products, the following documents are helpful when used in conjunction with this document. ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029) ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E) MC9328MXL Product Brief (order number MC9328MXLP/D) MC9328MXL Reference Manual (order number MC9328MXLRM/D) The Motorola manuals are available on the Motorola Semiconductors Web site at http://www.motorola.com/semiconductors. These documents may be downloaded directly from the Motorola Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com. MC9328MXL Advance Information, Rev. 5 4 Freescale Semiconductor Introduction 1.6 Ordering Information Table 2 provides ordering information for both the 256-lead mold array process ball grid array (MAPBGA) package and the 225-lead BGA package. Table 2. MC9328MXL Ordering Information Package Type 256-lead MAPBGA Frequency 150 MHz Temperature -40OC to 85OC Solderball Type Standard Pb-free 200 MHz 0OC to 70OC Standard Pb-free -30OC to 70OC Standard Pb-free 225-lead MAPBGA 150 MHz -40OC to 85OC Standard Pb-free 200 MHz 0OC to 70OC Standard Pb-free -30OC to 70OC Standard Pb-free Order Number MC9328MXLCVH15(R2) MC9328MXLCVM15(R2) MC9328MXLVH20(R2) MC9328MXLVM20(R2) MC9328MXLDVH20(R2) MC9328MXLDVM20(R2) MC9328MXLCVF15(R2) MC9328MXLCVP15(R2) MC9328MXLVF20(R2) MC9328MXLVP20(R2) MC9328MXLDVF20(R2) MC9328MXLDVP20(R2) MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 5 Signals and Connections 2 Signals and Connections Table 3 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to. Table 3. MC9328MXL Signal Descriptions Signal Name Function/Notes External Bus/Chip-Select (EIM) A[24:0] D[31:0] EB0 EB1 EB2 EB3 OE CS [5:0] ECB LBA BCLK (burst clock) RW DTACK Address bus signals Data bus signals MSB Byte Strobe--Active low external enable byte signal that controls D [31:24]. Byte Strobe--Active low external enable byte signal that controls D [23:16]. Byte Strobe--Active low external enable byte signal that controls D [15:8]. LSB Byte Strobe--Active low external enable byte signal that controls D [7:0]. Memory Output Enable--Active low output enables external data bus. Chip-Select--The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. Active low signal sent by a flash device causing the external burst device to latch the starting burst address. Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal--Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. DTACK signal--The external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed. Bootstrap BOOT [3:0] System Boot Mode Select--The operational system boot mode of the MC9328MXL upon system reset is determined by the settings of these pins. SDRAM Controller SDBA [4:0] SDIBA [3:0] SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles. SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash cycles. SDRAM address signals SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on SDRAM/SyncFlash cycles. SDRAM data enable SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. MA [11:10] MA [9:0] DQM [3:0] CSD0 MC9328MXL Advance Information, Rev. 5 6 Freescale Semiconductor Signals and Connections Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name CSD1 Function/Notes SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as SyncFlash boot chip-select by properly configuring BOOT [3:0] input pins. SDRAM/SyncFlash Row Address Select signal SDRAM/SyncFlash Column Address Select signal SDRAM/SyncFlash Write Enable signal SDRAM/SyncFlash Clock Enable 0 SDRAM/SyncFlash Clock Enable 1 SDRAM/SyncFlash Clock SyncFlash Reset Clocks and Resets EXTAL16M XTAL16M EXTAL32K XTAL32K CLKO RESET_IN RESET_OUT POR Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut down. Crystal output 32 kHz crystal input 32 kHz crystal output Clock Out signal selected from internal clock signals. Master Reset--External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset. Reset Out--Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. Power On Reset--Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. JTAG TRST TDO TDI TCK TMS Test Reset Pin--External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Test Clock to synchronize test logic and control register access through the JTAG port. Test Mode Select to sequence the JTAG test controller's state machine. Sampled on the rising edge of TCK. DMA BIG_ENDIAN Big Endian--Input signal that determines the configuration of the external chip-select space. If it is driven logic-high at reset, the external chip-select space will be configured to little endian. If it is driven logic-low at reset, the external chip-select space will be configured to big endian. External DMA request pin. ETM ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. RAS CAS SDWE SDCKE0 SDCKE1 SDCLK RESET_SF DMA_REQ MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 7 Signals and Connections Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name ETMTRACECLK ETMPIPESTAT [2:0] ETMTRACEPKT [7:0] Function/Notes ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode. ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. CMOS Sensor Interface CSI_D [7:0] CSI_MCLK CSI_VSYNC CSI_HSYNC CSI_PIXCLK Sensor port data Sensor port master clock Sensor port vertical sync Sensor port horizontal sync Sensor port data latch clock LCD Controller LD [15:0] FLM/VSYNC LP/HSYNC LSCLK ACD/OE CONTRAST SPL_SPR PS CLS REV LCD Data Bus--All LCD signals are driven low after reset and when LCD is off. Frame Sync or Vsync--This signal also serves as the clock signal output for the gate driver (dedicated signal SPS for Sharp panel HR-TFT). Line pulse or H sync Shift clock Alternate crystal direction/output enable. This signal is used to control the LCD bias voltage as contrast control. Program horizontal scan direction (Sharp panel dedicated signal). Control signal output for source driver (Sharp panel dedicated signal). Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated signal). Signal for common electrode driving signal preparation (Sharp panel dedicated signal). SPI 1 and 2 SPI1_MOSI SPI1_MISO SPI1_SS SPI1_SCLK SPI1_SPI_RDY SPI2_TXD Master Out/Slave In Slave In/Master Out Slave Select (Selectable polarity) Serial Clock Serial Data Ready SPI2 Master TxData Output--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. SPI2 Master RxData Input--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. SPI2_RXD MC9328MXL Advance Information, Rev. 5 8 Freescale Semiconductor Signals and Connections Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name SPI2_SS Function/Notes SPI2 Slave Select--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. SPI2 Serial Clock--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. General Purpose Timers TIN TMR2OUT Timer Input Capture or Timer Input Clock--The signal on this input is applied to both timers simultaneously. Timer 2 Output USB Device USBD_VMO USBD_VPO USBD_VM USBD_VP USBD_SUSPND USBD_RCV USBD_OE USBD_AFE USB Minus Output USB Plus Output USB Minus Input USB Plus Input USB Suspend Output USB Receive Data USB OE USB Analog Front End Enable Secure Digital Interface SD_CMD SD_CLK SD_DAT [3:0] SD Command--If the system designer does not wish to make use of the internal pull-up, via the Pullup enable register, a 4.7K-69K external pull up resistor must be added. MMC Output Clock Data--If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable register, a 50K-69K external pull up resistor must be added. Memory Stick Interface MS_BS MS_SDIO MS_SCLKO MS_SCLKI MS_PI0 MS_PI1 Memory Stick Bus State (Output)--Serial bus control signal Memory Stick Serial Data (Input/Output) Memory Stick Serial Clock (Input)--Serial protocol clock source for SCLK Divider Memory Stick External Clock (Output)--Test clock input pin for SCLK divider. This pin is only for test purposes, not for use in application mode. General purpose Input0--Can be used for Memory Stick Insertion/Extraction detect General purpose Input1--Can be used for Memory Stick Insertion/Extraction detect UARTs - IrDA/Auto-Bauding UART1_RXD UART1_TXD Receive Data Transmit Data SPI2_SCLK MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 9 Signals and Connections Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name UART1_RTS UART1_CTS UART2_RXD UART2_TXD UART2_RTS UART2_CTS UART2_DSR UART2_RI UART2_DCD UART2_DTR Request to Send Clear to Send Receive Data Transmit Data Request to Send Clear to Send Data Set Ready Ring Indicator Data Carrier Detect Data Terminal Ready Serial Audio Port - SSI (configurable to I2S protocol) SSI_TXDAT SSI_RXDAT SSI_TXCLK SSI_RXCLK SSI_TXFS SSI_RXFS Transmit Data Receive Data Transmit Serial Clock Receive Serial Clock Transmit Frame Sync Receive Frame Sync I2C I2C_SCL I2C_SDA I2C Clock I2C Data PWM PWMO PWM Output Digital Supply Pins NVDD NVSS Digital Supply for the I/O pins Digital Ground for the I/O pins Supply Pins - Analog Modules AVDD AVSS Supply for analog blocks Quiet ground for analog blocks Internal Power Supply QVDD QVSS Power supply pins for silicon internal circuitry Ground pins for silicon internal circuitry Function/Notes MC9328MXL Advance Information, Rev. 5 10 Freescale Semiconductor Specifications Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name Function/Notes Substrate Supply Pins SVDD SGND Supply routed through substrate of package; not to be bonded Ground routed through substrate of package; not to be bonded 3 Specifications This section contains the electrical specifications and timing diagrams for the MC9328MXL processor. 3.1 Maximum Ratings Table 4 provides information on maximum ratings. Table 4. Maximum Ratings Rating Supply voltage Maximum operating temperature range MC9328MXLVH20/MC9328MXLVM20/ MC9328MXLVF20/MC9328MXLVP20 Maximum operating temperature range MC9328MXLDVH20/MC9328MXLDVM20/ MC9328MXLDVF20/MC9328MXLDVP20 Maximum operating temperature range MC9328MXLCVH15/MC9328MXLCVM15/ MC9328MXLCVF15/MC9328MXLCVP15 ESD at human body model (HBM) ESD at machine model (MM) Latch-up current Storage temperature Power Consumption 1. 2. Symbol Vdd TA Minimum -0.3 0 Maximum 3.3 70 Unit V C TA -30 70 C TA -40 85 C VESD_HBM VESD_MM ILatchup Test Pmax - - - -55 8001 2000 100 200 150 13002 V V mA C mW A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS application at 200MHz, and where the whole image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA. MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 11 Specifications 3.2 Recommended Operating Range Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MXL has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/ O pads. This design allows different peripheral supply voltage levels in a system. Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the AVDD pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Table 3 on page 6. Table 5. Recommended Operating Range Rating I/O supply voltage (if using MSHC, SPI, BTA, USBd, LCD and CSI which are only 3 V interfaces) I/O supply voltage (if not using the peripherals listed above) Internal supply voltage (Core = 150 MHz) Internal supply voltage (Core = 200 MHz) Analog supply voltage Symbol NVDD NVDD QVDD QVDD AVDD Minimum 2.70 1.70 1.70 1.80 1.70 Maximum 3.30 3.30 1.90 2.00 3.30 Unit V V V V V 3.3 Power Sequence Requirements For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of application note AN2537 on the i.MX website page. 3.4 DC Electrical Characteristics Table 6 contains both maximum and minimum DC characteristics of the MC9328MXL. Table 6. Maximum and Minimum DC Characteristics Number or Symbol Iop Parameter Full running operating current at 1.8V for QVDD, 3.3V for NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4 decoding playback from external memory card to both external SSI audio decoder and TFT display panel, and OS with MMU enabled memory system is running on external SDRAM). Standby current (Core = 150 MHz, QVDD = 1.8V, temp = 25C) Standby current (Core = 150 MHz, QVDD = 1.8V, temp = 55C) Standby current (Core = 150 MHz, QVDD = 2.0V, temp = 25C) Min - Typical QVDD at 1.8v = 120mA; NVDD+AVDD at 3.0v = 30mA Max - Unit mA Sidd1 Sidd2 Sidd3 - 25 - A A A - 45 - - 35 - MC9328MXL Advance Information, Rev. 5 12 Freescale Semiconductor Specifications Table 6. Maximum and Minimum DC Characteristics (Continued) Number or Symbol Sidd4 VIH VIL VOH VOL IIL IIH IOH IOL IOZ Ci Co Parameter Standby current (Core = 150 MHz, QVDD = 2.0V, temp = 55C) Input high voltage Input low voltage Output high voltage (IOH = 2.0 mA) Output low voltage (IOL = -2.5 mA) Input low leakage current (VIN = GND, no pull-up or pull-down) Input high leakage current (VIN = VDD, no pull-up or pull-down) Output high current (VOH = 0.8VDD, VDD = 1.8V) Output low current (VOL = 0.4V, VDD = 1.8V) Output leakage current (Vout = VDD, output is tri-stated) Input capacitance Output capacitance` Min - Typical 60 Max - Unit A 0.7VDD - 0.7VDD - - - - - - - Vdd+0.2 0.4 Vdd 0.4 1 V V V V A A - - 1 - - 4.0 mA -4.0 - - mA A - - 5 - - - - 5 5 pF pF 3.5 AC Electrical Characteristics The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading. Table 7. Tristate Signal Timing Pin TRISTATE Parameter Time from TRISTATE activate until I/O becomes Hi-Z Minimum - Maximum 20.8 Unit ns Table 8. 32k/16M Oscillator Signal Timing Parameter EXTAL32k input jitter (peak to peak) Minimum - RMS 5 Maximum 20 Unit ns MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 13 Specifications Table 8. 32k/16M Oscillator Signal Timing (Continued) Parameter EXTAL32k startup time EXTAL16M input jitter (peak to peak) EXTAL16M startup time Minimum 800 - TBD RMS - TBD - Maximum - TBD - Unit ms - - 3.6 Embedded Trace Macrocell All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the ARM920T processor's TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprised of the following: * * * 32-bit data field 7-bit address field A read/write bit The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used in Figure 2. 2a 3a TRACECLK 1 2b 3b TRACECLK (Half-Rate Clocking Mode) Output Trace Port Valid Data Valid Data 4a 4b Figure 2. Trace Port Timing Diagram Table 9. Trace Port Timing Diagram Parameter Table Ref No. 1 2a 2b 1.8V 0.10V Parameter Minimum CLK frequency Clock high time Clock low time 0 1.3 3 Maximum 85 - - Minimum 0 2 2 Maximum 100 - - MHz ns ns 3.0V 0.30V Unit MC9328MXL Advance Information, Rev. 5 14 Freescale Semiconductor Specifications Table 9. Trace Port Timing Diagram Parameter Table (Continued) Ref No. 3a 3b 4a 4b 1.8V 0.10V Parameter Minimum Clock rise time Clock fall time Output hold time Output setup time - - 2.28 3.42 Maximum 4 3 - - Minimum - - 2 3 Maximum 3 3 - - ns ns ns ns 3.0V 0.30V Unit MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 15 Specifications 3.7 DPLL Timing Specifications Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the pre-divider and Tdck is the output double clock period. Table 10. DPLL Specifications Parameter Reference clock freq range Pre-divider output clock freq range Double clock freq range Pre-divider factor (PD) Total multiplication factor (MF) Test Conditions Vcc = 1.8V Vcc = 1.8V Minimum 5 5 Typical - - Maximum 100 30 Unit MHz MHz Vcc = 1.8V - Includes both integer and fractional parts - Should be less than the denominator - - FOL mode for non-integer MF (does not include pre-multi lock-in time) FOL mode for non-integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) - 80 1 5 - - - 220 16 15 MHz - - MF integer part MF numerator 5 0 - - 15 1022 - - MF denominator Pre-multiplier lock-in time Freq lock-in time after full reset 1 - 250 - - 280 (56 s) 1023 312.5 300 - sec Tref Freq lock-in time after partial reset 220 250 (50 s) 270 Tref Phase lock-in time after full reset Phase lock-in time after partial reset Freq jitter (p-p) 300 350 (70 s) 320 (64 s) 0.005 (0.01%) 1.0 (10%) - - 400 Tref Tref 2*Tdck ns 270 370 - 0.01 Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V - 1.5 Power supply voltage Power dissipation - FOL mode, integer MF, fdck = 200 MHz, Vcc = 1.8V 1.7 - 2.5 4 V mW MC9328MXL Advance Information, Rev. 5 16 Freescale Semiconductor Specifications 3.8 Reset Module The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4. NOTE: Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent forward biasing. 90% AVDD 1 POR 10% AVDD RESET_POR 2 Exact 300ms RESET_DRAM 3 7 cycles @ CLK32 HRESET RESET_OUT 4 14 cycles @ CLK32 CLK32 HCLK Figure 3. Timing Relationship with POR MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 17 Specifications 5 RESET_IN 14 cycles @ CLK32 HRESET RESET_OUT 4 6 CLK32 HCLK Figure 4. Timing Relationship with RESET_IN Table 11. Reset Module Timing Parameter Table Ref No. 1 2 1.8V 0.10V Parameter Min Width of input POWER_ON_RESET Width of internal POWER_ON_RESET (CLK32 at 32 kHz) 7K to 32K-cycle stretcher for SDRAM reset note1 300 Max - 300 Min note1 300 Max - 300 - ms 3.0V 0.30V Unit 3 7 7 7 7 Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 4 14K to 32K-cycle stretcher for internal system reset HRESERT and output reset at pin RESET_OUT Width of external hard-reset RESET_IN 14 14 14 14 5 4 - 4 - 6 4K to 32K-cycle qualifier 4 4 4 4 1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in calculating timing for the start-up process. MC9328MXL Advance Information, Rev. 5 18 Freescale Semiconductor Specifications 3.9 External Interface Module The External Interface Module (EIM) handles the interface to devices external to the MC9328MXL, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 on page 20 defines the parameters of signals. (HCLK) Bus Clock 1a 1b Address Chip-select 2a 2b 3a 3b Read (Write) OE (rising edge) 4a 4b OE (falling edge) 5a 4c 4d EB (rising edge) 5b EB (falling edge) 6a 5c 5d LBA (negated falling edge) 6b LBA (negated rising edge) 6a 6c 7a 7b Burst Clock (rising edge) 7c 7d Burst Clock (falling edge) 8b Read Data 9a 8a 9b Write Data (negated falling) 9a 9c Write Data (negated rising) DTACK 10a 10a Figure 5. EIM Bus Timing Diagram MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 19 Specifications Table 12. EIM Bus Timing Parameter Table 1.8V 0.10V Ref No. Parameter Min 1a 1b 2a 2b 3a 3b 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 7a 7b 7c 7d 8a 8b 9a 9b 9c 10a 1. Clock fall to address valid Clock fall to address invalid Clock fall to chip-select valid Clock fall to chip-select invalid Clock fall to Read (Write) Valid Clock fall to Read (Write) Invalid Clock1 rise to Output Enable Valid Clock1 rise to Output Enable Invalid Clock1 fall to Output Enable Valid Clock1 fall to Output Enable Invalid Clock1 rise to Enable Bytes Valid Clock1 rise to Enable Bytes Invalid Clock1 fall to Enable Bytes Valid Clock1 fall to Enable Bytes Invalid Clock1 fall to Load Burst Address Valid Clock1 fall to Load Burst Address Invalid Clock1 rise to Load Burst Address Invalid Clock1 rise to Burst Clock rise Clock1rise to Burst Clock fall Clock1 fall to Burst Clock rise Clock1 fall to Burst Clock fall Read Data setup time Read Data hold time Clock1 rise to Write Data Valid Clock1 fall to Write Data Invalid Clock1 rise to Write Data Invalid DTACK setup time 2.48 1.55 2.69 1.55 1.35 1.86 2.32 2.11 2.38 2.17 1.91 1.81 1.97 1.76 2.07 1.97 1.91 1.61 1.61 1.55 1.55 5.54 0 1.81 1.45 1.63 2.52 Typical 3.31 2.48 3.31 2.48 2.79 2.59 2.62 2.52 2.69 2.59 2.52 2.42 2.59 2.48 2.79 2.79 2.62 2.62 2.62 2.48 2.59 - - 2.72 2.48 - - Max 9.11 5.69 7.87 6.31 6.52 6.11 6.85 6.55 7.04 6.73 5.54 5.24 5.69 5.38 6.73 6.83 6.45 5.64 5.84 5.59 5.80 - - 6.85 5.69 - - Min 2.4 1.5 2.6 1.5 1.3 1.8 2.3 2.1 2.3 2.1 1.9 1.8 1.9 1.7 2.0 1.9 1.9 1.6 1.6 1.5 1.5 5.5 0 1.8 1.4 1.62 2.5 Typical 3.2 2.4 3.2 2.4 2.7 2.5 2.6 2.5 2.6 2.5 2.5 2.4 2.5 2.4 2.7 2.7 2.6 2.6 2.6 2.4 2.5 - - 2.7 2.4 - - Max 8.8 5.5 7.6 6.1 6.3 5.9 6.8 6.5 6.8 6.5 5.5 5.2 5.5 5.2 6.5 6.6 6.4 5.6 5.8 5.4 5.6 - - 6.8 5.5 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.0V 0.30V Unit Clock refers to the system clock signal, HCLK, generated from the System PLL MC9328MXL Advance Information, Rev. 5 20 Freescale Semiconductor Specifications 3.9.1 DTACK Signal Description The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only CS5 group is designed to support DTACK signal function when using the external DTACK signal for data acknowledgement. 3.9.2 DTACK Signal Timing Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in Table 13. HCLK CS5 3 RW OE EXT_DTACK 2 INT_DTACK 4 1 5 Figure 6. DTACK Timing, WSC=111111, DTACK_sel=0 Table 13. Access Cycle Timing Parameters Ref No. 1 2 1.8V 0.10V Characteristic Min CS5 asserted to OE asserted External DTACK input setup from CS5 asserted CS5 pulse width External DTACK input hold after CS5 is negated OE negated after CS5 is negated - 0 Max T - Min - 0 Max T - ns ns 3.0V 0.30V Unit 3 4 3T 0 - 1.5T 3T 0 - 1.5T ns ns 5 Note: 0 4.5 0 4 ns 1. n is the number of wait states in the current memory access cycle. The max n is 1022. 2. T is the system clock period (system clock is 96 MHz). 3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 21 Specifications HCLK CS5 RW OE EXT_DTACK (WAIT) 1 INT_DTACK Figure 7. DTACK Timing, WSC=111111, DTACK_sel=1 Table 14. Access Cycle Timing Parameters Ref No. 1 1.8V 0.10V Characteristic Min External DTACK input setup from CS5 asserted 0 Max - Min 0 Max - ns 3.0V 0.30V Unit Note: 1. n is the number of wait states in the current memory access cycle. The max n is 1022. 2. T is the system clock period (system clock is 96 MHz). 3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXL Advance Information, Rev. 5 22 Freescale Semiconductor Specifications 3.9.3 EIM External Bus Timing The timing diagrams in this section show the timing of accesses to memory or a peripheral. hclk hsel_weim_cs[0] htrans hwrite Seq/Nonseq Read haddr hready weim_hrdata weim_hready V1 Last Valid Data V1 weim_bclk weim_addr weim_cs weim_r/w Last Valid Address V1 Read weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in V1 Figure 8. WSC = 1, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 23 Specifications hclk hsel_weim_cs[0] htrans hwrite haddr Nonseq Write V1 hready hwdata weim_hrdata Last Valid Data Write Data (V1) Unknown Last Valid Data weim_hready weim_bclk weim_addr weim_cs[0] weim_r/w weim_lba weim_oe weim_eb Write Last Valid Address V1 weim_data_out Last Valid Data Write Data (V1) Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 24 Freescale Semiconductor Specifications hclk hsel_weim_cs[0] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready weim_bclk weim_addr weim_cs[0] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Read Last Valid Addr Address V1 Address V1 + 2 weim_data_in 1/2 Half Word 2/2 Half Word Figure 10. WSC = 1, OEA = 1, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 25 Specifications hclk hsel_weim_cs[0] htrans hwrite haddr Nonseq Write V1 hready hwdata weim_hrdata Last Valid Data Write Data (V1 Word) Last Valid Data weim_hready weim_bclk weim_addr weim_cs[0] weim_r/w weim_lba weim_oe weim_eb Last Valid Addr Address V1 Address V1 + 2 Write weim_data_out 1/2 Half Word 2/2 Half Word Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 26 Freescale Semiconductor Specifications hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hrdata Nonseq Read V1 Last Valid Data V1 Word weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[3] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Read Address V1 Address V1 + 2 weim_data_in 1/2 Half Word 2/2 Half Word Figure 12. WSC = 3, OEA = 2, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 27 Specifications hclk hsel_weim_cs[3] htrans hwrite haddr hready hwdata Last Valid Data weim_hrdata Nonseq Write V1 Write Data (V1 Word) Last Valid Data weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[3] weim_r/w weim_lba weim_oe Write Address V1 Address V1 + 2 weim_eb weim_data_out] Last Valid Data 1/2 Half Word 2/2 Half Word Figure 13. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 28 Freescale Semiconductor Specifications hclk hsel_weim_cs[2] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w Read Last Valid Addr Address V1 Address V1 + 2 weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in 1/2 Half Word 2/2 Half Word Figure 14. WSC = 3, OEA = 4, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 29 Specifications hclk hsel_weim_cs[2] htrans hwrite haddr Nonseq Write V1 hready hwdata weim_hrdata weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe Last Valid Addr Address V1 Address V1 + 2 Last Valid Data Write Data (V1 Word) Last Valid Data Write weim_eb weim_data_out Last Valid Data 1/2 Half Word 2/2 Half Word Figure 15. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 30 Freescale Semiconductor Specifications hclk hsel_weim_cs[2] htrans Nonseq Read V1 hwrite haddr hready weim_hrdata Last Valid Data V1 Word weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Read Last Valid Addr Address V1 Address V1 + 2 weim_data_in 1/2 Half Word 2/2 Half Word Figure 16. WSC = 3, OEN = 2, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 31 Specifications hclk hsel_weim_cs[2] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Read Last Valid Addr Address V1 Address V1 + 2 weim_data_in 1/2 Half Word 2/2 Half Word Figure 17. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 32 Freescale Semiconductor Specifications hclk hsel_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata Last Valid Data Nonseq Write V1 Write Data (V1 Word) Unknown Last Valid Data weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb Last Valid Addr Address V1 Address V1 + 2 Write weim_data_out Last Valid Data 1/2 Half Word 2/2 Half Word Figure 18. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 33 Specifications hclk hsel_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata Last Valid Data Nonseq Write V1 Write Data (V1 Word) Last Valid Data Unknown weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb Last Valid Addr Address V1 Address V1 + 2 Write weim_data_out Last Valid Data 1/2 Half Word 2/2 Half Word Figure 19. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 34 Freescale Semiconductor Specifications hclk hsel_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata weim_hready Nonseq Read Nonseq Write V1 V8 Last Valid Data Last Valid Data Write Data Read Data weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Last Valid Addr Address V1 Address V8 Read Write weim_data_in weim_data_out Read Data Last Valid Data Write Data Figure 20. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 35 Specifications Read hclk hsel_weim_cs[2] htrans hwrite haddr Idle Write Nonseq Read Nonseq Write V1 V8 hready hwdata weim_hrdata Last Valid Data Write Data Last Valid Data Read Data weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) Read Write Last Valid Addr Address V1 Address V8 weim_eb (EBC=1) weim_data_in weim_data_out Read Data Last Valid Data Write Data Figure 21. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 36 Freescale Semiconductor Specifications hclk hsel_weim_cs[4] htrans hwrite haddr hready hwdata weim_hrdata Last Valid Data Nonseq Write V1 Write Data (Word) Last Valid Data weim_hready weim_bclk weim_addr weim_cs weim_r/w Last Valid Addr Address V1 Address V1 + 2 Write weim_lba weim_oe weim_eb weim_data_out Last Valid Data Write Data (1/2 Half Word) Write Data (2/2 Half Word) Figure 22. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 37 Specifications hclk hsel_weim_cs[4] htrans hwrite haddr Nonseq Read Nonseq Write V1 V8 hready hwdata weim_hrdata weim_hready Last Valid Data Last Valid Data Write Data Read Data weim_bclk weim_addr weim_cs[4] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Last Valid Addr Address V1 Address V8 Read Write weim_data_in weim_data_out Read Data Last Valid Data Write Data Figure 23. WSC = 3, CSA = 1, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 38 Freescale Semiconductor Specifications hclk hsel_weim_cs[4] htrans hwrite haddr Nonseq Read Idle Seq Read V1 V2 hready weim_hrdata weim_hready Last Valid Data Read Data (V1) Read Data (V2) weim_bclk weim_addr Last Valid Address V1 CNC Address V2 weim_cs[4] weim_r/w weim_lba Read weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Read Data (V1) Read Data (V2) Figure 24. WSC = 2, OEA = 2, CNC = 3, BCM = 0, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 39 Specifications hclk hsel_weim_cs[4] htrans hwrite haddr hready hwdata weim_hrdata Nonseq Read Idle Nonseq Write V1 V8 Last Valid Data Last Valid Data Write Data Read Data weim_hready weim_bclk weim_addr Last Valid Addr Address V1 CNC weim_cs[4] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Address V8 Read Write weim_data_in weim_data_out Read Data Last Valid Data Write Data Figure 25. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 40 Freescale Semiconductor Specifications hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hrdata weim_hready weim_bclk weim_addr] Nonseq Read V1 Nonse Read V5 Idle Last Valid Addr Address V1 Address V5 weim_cs[2] weim_r/w weim_lba Read weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in V1 Word V2 Word V5 Word V6 Word Figure 26. WSC = 3, SYNC = 1, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 41 Specifications hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Read Idle Nonseq Read V1 Seq Read V2 Seq Read V3 Seq Read V4 Last Valid Data V1 Word V2 Word V3 Word V4 Word Address V1 weim_ecb weim_data_in V1 Word V2 Word V3 Word V4 Word Figure 27. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD MC9328MXL Advance Information, Rev. 5 42 Freescale Semiconductor Specifications hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word Idle Nonseq Seq Read V1 Read V2 weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe Read Last Valid Address V1 Address V2 weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in V1 1/2 V1 2/2 V2 1/2 V2 2/2 Figure 28. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 43 Specifications hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hrdata Non seq Read Seq Idle Read V1 V2 Last Valid Data V1 Word V2 Word weim_hready weim_bclk weim_addr weim_cs[2] Read Last Address V1 weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in V1 1/2 V1 2/2 V2 1/2 V2 2/2 Figure 29. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 44 Freescale Semiconductor Specifications hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hrdata Non seq Read V1 Seq Idle Read V2 Last Valid Data V1 Word V2 Word weim_hready weim_bclk weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) Last Address V1 Read weim_ecb weim_data_in V1 1/2 V1 2/2 V2 1/2 V2 2/2 Figure 30. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 45 Specifications 3.10 SPI Timing Diagrams To utilize the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the external SPI master's timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data FIFO. Figure 31 through Figure 35 show the timing relationship of the master SPI using different triggering mechanisms. 2 SS 1 SPIRDY 4 3 5 SCLK, MOSI, MISO Figure 31. Master SPI Timing Diagram Using SPI_RDY Edge Trigger SS SPIRDY SCLK, MOSI, MISO Figure 32. Master SPI Timing Diagram Using SPI_RDY Level Trigger SS (output) SCLK, MOSI, MISO Figure 33. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 34. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT MC9328MXL Advance Information, Rev. 5 46 Freescale Semiconductor Specifications SS (input) 6 SCLK, MOSI, MISO 7 Figure 35. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Table 15. Timing Parameter Table for Figure 31 through Figure 35 1.8V 0.10V Ref No. 1 2 Parameter SPI_RDY to SS output low SS output low to first SCLK edge Last SCLK edge to SS output high SS output high to SPI_RDY low SS output pulse width Minimum 2T 1 3 * Tsclk 2 2 * Tsclk Maximum - - 3.0V 0.30V Minimum 2T1 3 * Tsclk2 2 * Tsclk Maximum - - Unit ns ns 3 - - ns 4 0 - 0 - ns 5 Tsclk + WAIT 3 T - Tsclk + WAIT3 T - ns 6 SS input low to first SCLK edge SS input pulse width - - ns 7 1. 2. 3. T - T - ns T = CSPI system clock period (PERCLK2). Tsclk = Period of SCLK. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register. 3.11 LCD Controller This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL Reference Manual. LSCLK LD[15:0] 1 Figure 36. SCLK to LD Timing Diagram MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 47 Specifications Table 16. LCDC SCLK Timing Parameter Table 1.8V 0.10V Ref No. 1 Parameter SCLK to LD valid Minimum - Maximum 2 3.0V 0.30V Minimum - Maximum 2 Unit ns Non-display region T1 T3 Display region T4 VSYN HSYN OE LD[15:0] T2 Line Y Line 1 Line Y T5 HSYN SCLK OE LD[15:0] VSYN T6 XMAX T7 T8 (1,1) (1,2) (1,X) T9 T10 Figure 37. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table 17. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Symbol T1 Description End of OE to beginning of VSYN Minimum T5+T6 +T7+T9 XMAX+5 T2 2 1 1 Corresponding Register Value (VWAIT1*T2)+T5+T6+T7+T9 Unit Ts T2 T3 T4 T5 T6 HSYN period VSYN pulse width End of VSYN to beginning of OE HSYN pulse width End of HSYN to beginning to T9 XMAX+T5+T6+T7+T9+T10 VWIDTH*(T2) VWAIT2*(T2) HWIDTH+1 HWAIT2+1 Ts Ts Ts Ts Ts MC9328MXL Advance Information, Rev. 5 48 Freescale Semiconductor Specifications Table 17. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued) Symbol T7 T8 T9 Description End of OE to beginning of HSYN SCLK to valid LD data End of HSYN idle2 to VSYN edge (for non-display region) End of HSYN idle2 to VSYN edge (for Display region) VSYN to OE active (Sharp = 0) when VWAIT2 = 0 VSYN to OE active (Sharp = 1) when VWAIT2 = 0 Minimum 1 -3 2 Corresponding Register Value HWAIT1+1 3 2 Unit Ts ns Ts T9 1 1 Ts T10 1 1 Ts T10 2 2 Ts Note: * * * * * * Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns. VSYN, HSYN and OE can be programmed as active high or active low. In Figure 37, all 3 signals are active low. The polarity of SCLK and LD[15:0] can also be programmed. SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 37, SCLK is always active. For T9 non-display region, VSYN is non-active. It is used as an reference. XMAX is defined in pixels. MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 49 Specifications 3.12 Multimedia Card/Secure Digital Host Controller The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application (user programming). 3a 3b Bus Clock 1 2 4b 4a 5a CMD_DAT Input Valid Data 5b Valid Data 7 CMD_DAT Output Valid Data Valid Data 6a 6b Figure 38. Chip-Select Read Cycle Timing Diagram Table 18. SDHC Bus Timing Parameter Table Ref No. 1 1.8V 0.10V Parameter Minimum CLK frequency at Data transfer Mode (PP)1--10/30 cards CLK frequency at Identification Mode2 Clock high time1--10/30 cards Clock low time1--10/30 cards Clock fall time1--10/30 cards 0 Maximum 25/5 Minimum 0 Maximum 25/5 MHz 3.0 0.30V Unit 2 3a 3b 4a 0 6/33 15/75 - 400 - - 10/50 (5.00)3 14/67 (6.67)3 - - - - 16 0 10/50 10/50 - 400 - - 10/50 kHz ns ns ns 4b Clock rise time1--10/30 cards - - 10/50 ns 5a 5b 6a 6b 7 1. 2. 3. Input hold time3--10/30 cards Input setup time3--10/30 cards Output hold time3--10/30 cards Output setup time3--10/30 cards Output delay time3 CL 100 pF / 250 pF (10/30 cards) CL 250 pF (21 cards) CL 25 pF (1 card) 5.7/5.7 5.7/5.7 5.7/5.7 5.7/5.7 0 5/5 5/5 5/5 5/5 0 - - - - 14 ns ns ns ns ns MC9328MXL Advance Information, Rev. 5 50 Freescale Semiconductor Specifications 3.12.1 Command Response Timing on MMC/SD Bus The card identification and card operation conditions timing are processed in open-drain mode. The card response to the host command starts after exactly NID clock cycles. For the card address assignment, SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and card response is NCR clock cycles as illustrated in Figure 39. The symbols for Figure 39 through Figure 43 are defined in Table 19. Table 19. State Signal Parameters for Figure 39 through Figure 43 Card Active Symbol Z D Definition High impedance state Data bits Symbol S T Host Active Definition Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1) * CRC Repetition Cyclic redundancy check bits (7 bits) P E NID cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ Identification Timing NCR cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ SET_RCA Timing Figure 39. Timing Diagrams at Identification Mode After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 40, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card. The other two diagrams show the separating periods NRC and NCC. MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 51 Specifications NCR cycles Host Command CMD S T Content CRC E Z Z P ****** PST Response Content CRC E Z Z Z Command response timing (data transfer mode) NRC cycles Response CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z Timing response end to next CMD start (data transfer mode) NCC cycles Host Command CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z Timing of command sequences (all modes) Figure 40. Timing Diagrams at Data Transfer Mode Figure 41 on page 53 shows basic read operation timing. In a read operation, the sequence starts with a single block read command (which specifies the start address in the argument field). The response is sent on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC , beginning from the last bit of the read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command. The data stops two clock cycles after the end bit of the stop command. MC9328MXL Advance Information, Rev. 5 52 Freescale Semiconductor Specifications NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z DAT Z****Z Z Z P ****** P S D D D D ***** NAC cycles Read Data Timing of single block read NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z DAT Z****Z ZZP ****** P S DDDD ***** P ***** P S DDDD ***** Read Data NAC cycles NAC cycles Read Data Timing of multiple block read NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T NST DAT D D D D ***** DDDDE Z Z Z ***** Timing of stop command (CMD12, data transfer mode) Response Content CRC E Z Valid Read Data Figure 41. Timing Diagrams at Data Read Figure 42 shows the basic write operation timing. As with the read operation, after the card response, the data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command. MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 53 54 NCR cycles Host Command Response ****** PST Content CRC E Z Z P ****** PP P CMD S T Content CRC E Z Z P DAT Z****Z Z ZZPPS Z ZZPPS Content Content Z****Z DAT CRC E Z Z S Status ES L*L EZ CRC E Z Z X X X X X X X X X X X X X X X X Z Busy CRC status NWR cycles Write Data Timing of the block write command CMD E Z Z P ****** Content CRC E Z Z S Status EZPPS Content CRC E Z Z S Status ES L*L DAT Z Z P P S PPP EZ DAT Z Z P P S Content Write Data CRC status CRC E Z Z X X X X X X X X Z P P S Content Write Data CRC status NWR cycles CRC E Z Z X X X X X X X X X X X X X X X X Z Busy NWR cycles Timing of the multiple block write command Specifications Figure 42. Timing Diagrams at Data Write MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor Freescale Semiconductor NCR cycles Host Command Card Response ****** PST CRC E Z Z Z Content ST CMD S T Content CRC E Z Z P Host Command Content CRC E DAT D D D D D D D D D D D D D E Z Z S L ****** Write Data Busy (Card is programming) DAT D D D D D D D Z Z S CRC E Z Z S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission during data transfer from the host. EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission during CRC status transfer from the card. DAT S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission received after last data block. Card becomes busy programming. The stop transmission command may occur when the card is in different states. Figure 43 shows the different scenarios on the bus. Figure 43. Stop Transmission During Different Scenarios MC9328MXL Advance Information, Rev. 5 DAT Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission received after last data block. Card becomes busy programming. Specifications 55 Specifications Table 20. Timing Values for Figure 39 through Figure 43 Parameter Symbol Minimum Maximum Unit Parameter MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle NCR 2 64 Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Identification response cycle NID 5 5 Identification response cycle Access time delay cycle Access time delay cycle NAC 2 TAAC + NSAC Command read cycle NRC 8 - Command read cycle Command-command cycle NCC 8 - Command-command cycle Command write cycle NWR 2 - Command write cycle Stop transmission cycle NST 2 2 Stop transmission cycle TAAC: Data read access time -1 defined in CSD register bit[119:112] NSAC: Data read access time -2 in CLK cycles (NSAC*100) defined in CSD register bit[111:104] TAAC: Data read access time -1 defined in CSD register bit[119:112] NSAC: Data read access time -2 in CLK cycles (NSAC*100) defined in CSD register bit[111:104] 3.12.2 SDIO-IRQ and ReadWait Service Handling In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data in this mode. The memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (SD_DAT[1] returns to its high level). In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt Period" during the data access, and the controller must sample SD_DAT[1] during this short period to determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes). MC9328MXL Advance Information, Rev. 5 56 Freescale Semiconductor Specifications CMD ST Content CRC E Z Z P S Response EZZZ ****** ZZZ DAT[1] For 4-bit Interrupt Period S Block Data E IRQ S Block Data E IRQ LH DAT[1] For 1-bit Interrupt Period Figure 44. SDIO IRQ Timing Diagram ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the clock running, and allows the user to submit commands as normal. After all commands are submitted, the user can switch back to the data transfer operation and all counter and status values are resumed as access continues. CMD ****** P S T CMD52 CRC E Z Z Z ****** DAT[1] For 4-bit DAT[2] For 4-bit S Block Data EZZL H S Block Data E S Block Data E Z Z L L L L L L L L L L L L L L L L L L L L L HZ S Block Data E Figure 45. SDIO ReadWait Timing Diagram 3.13 Memory Stick Host Controller The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS, MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in either four-state or two-state access mode. The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1, BS2, and BS3 states are regarded as one packet length and one communication transfer is always completed within one packet length (in four-state access mode). The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO. MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 57 Specifications 2 1 4 3 5 MS_SCLKI 6 7 8 MS_SCLKO 11 9 10 11 MS_BS 12 12 MS_SDIO(output) 14 13 MS_SDIO (input) (RED bit = 0) 15 16 MS_SDIO (input) (RED bit = 1) Figure 46. MSHC Signal Timing Diagram Table 21. MSHC Signal Timing Parameter Table Ref No. 1 2 3 4 5 6 7 8 9 10 MS_SCLKI frequency MS_SCLKI high pulse width MS_SCLKI low pulse width MS_SCLKI rise time MS_SCLKI fall time MS_SCLKO frequency1 MS_SCLKO high pulse width1 MS_SCLKO low pulse width1 MS_SCLKO rise time1 MS_SCLKO fall time1 MC9328MXL Advance Information, Rev. 5 58 Freescale Semiconductor 3.0 0.3V Parameter Minimum - 20 20 - - - 20 15 - - Maximum 25 - - 3 3 25 - - 5 5 MHz ns ns ns ns MHz ns ns ns ns Unit Specifications Table 21. MSHC Signal Timing Parameter Table (Continued) Ref No. 11 12 13 14 15 16 1. 2. MS_BS delay time1 MS_SDIO output delay time1,2 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)3 MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)4 MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4 3.0 0.3V Parameter Minimum - - 18 0 23 0 Maximum 3 3 - - - - ns ns ns ns ns ns Unit 3. 4. Loading capacitor condition is less than or equal to 30pF. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin direction changes. If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge. If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge. MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 59 Specifications 3.14 Pulse-Width Modulator The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in Figure 47 and the parameters are listed in Table 22. 2a System Clock 1 3b 2b 3a 4a PWM Output 4b Figure 47. PWM Output Timing Diagram Table 22. PWM Output Timing Parameter Table Ref No. 1 2a 2b 3a 3b 4a 4b 1. 1.8V 0.10V Parameter Minimum System CLK frequency1 Clock high time1 Clock low time1 Clock fall time1 Clock rise time1 Output delay time1 Output setup time1 CL of PWMO = 30 pF 3.0V 0.30V Unit Minimum 0 5/10 5/10 - - 5 5 Maximum 100 - - 5/10 5/10 - - MHz ns ns ns ns ns ns Maximum 87 - - 5 6.67 - - 0 3.3 7.5 - - 5.7 5.7 3.15 SDRAM Controller A write to an address within the memory region initiates the program sequence. The first command issued to the SyncFlash is Load Command Register. The value in A [7:0] determines which operation the command performs. For this write setup operation, an address of 0x40 is hardware generated. The bank and other address lines are driven with the address to be programmed. The next command is Active which registers the row address and confirms the bank address. The third command supplies the column address, re-confirms the bank address, and supplies the data to be written. SyncFlash does not support burst writes, therefore a Burst Terminate command is not required. A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register operation. The bank and other address lines are driven to the selected address. The second command is MC9328MXL Advance Information, Rev. 5 60 Freescale Semiconductor Specifications Active which sets up the status register read. The bank and row addresses are driven during this command. The third command of the triplet is Read. Bank and column addresses are driven on the address bus during this command. Data is returned from memory on the low order 8 data bits following the CAS latency. 1 SDCLK 2 3S CS 3 3S RAS 3S 3H CAS 3S 3H WE 4S ADDR 4H COL/BA 8 DQ 3H 3H ROW/BA 5 6 Data 7 3S DQM 3H Note: CKE is high during the read/write cycle. Figure 48. SDRAM/SyncFlash Read Cycle Timing Diagram Table 23. SDRAM Timing Parameter Table Ref No. 1 2 3 3S 1.8V 0.10V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM setup time 2.67 6 11.4 3.42 Maximum - - - - Minimum 4 4 10 3 Maximum - - - - ns ns ns ns 3.0V 0.30V Unit MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 61 Specifications Table 23. SDRAM Timing Parameter Table (Continued) Ref No. 3H 4S 4H 5 5 5 6 7 7 7 8 1. 1.8V 0.10V Parameter Minimum CS, RAS, CAS, WE, DQM hold time Address setup time Address hold time SDRAM access time (CL = 3) SDRAM access time (CL = 2) SDRAM access time (CL = 1) Data out hold time Data out high-impedance time (CL = 3) Data out high-impedance time (CL = 2) Data out high-impedance time (CL = 1) Active to read/write command period (RC = 1) 2.28 3.42 2.28 - - - 2.85 - - - tRCD1 Maximum - - - 6.84 6.84 22 - 6.84 6.84 22 - Minimum 2 3 2 - - - 2.5 - - - tRCD1 Maximum - - - 6 6 22 - 6 6 22 - ns ns ns ns ns ns ns ns ns ns ns 3.0V 0.30V Unit tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual. MC9328MXL Advance Information, Rev. 5 62 Freescale Semiconductor Specifications SDCLK 1 CS 3 2 RAS 6 CAS WE 4 ADDR 5 7 COL/BA 8 DQ DATA 9 / BA ROW/BA DQM Figure 49. SDRAM/SyncFlash Write Cycle Timing Diagram Table 24. SDRAM Write Timing Parameter Table Ref No. 1 2 3 4 5 6 7 1.8V 0.10V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 Active to read/write command delay 2.67 6 11.4 3.42 2.28 tRP2 tRCD2 Maximum - - - - - - - Minimum 4 4 10 3 2 tRP2 tRCD2 Maximum - - - - - - - ns ns ns ns ns ns ns 3.0V 0.30V Unit MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 63 Specifications Table 24. SDRAM Write Timing Parameter Table (Continued) Ref No. 8 9 1. 2. 1.8V 0.10V Parameter Minimum Data setup time Data hold time 4.0 2.28 Maximum - - Minimum 2 2 Maximum - - ns ns 3.0V 0.30V Unit Precharge cycle timing is included in the write timing diagram. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual. SDCLK 1 3 2 CS RAS 6 CAS 7 7 WE 4 ADDR BA 5 ROW/BA DQ DQM Figure 50. SDRAM Refresh Timing Diagram Table 25. SDRAM Refresh Timing Parameter Table Ref No. 1 2 1.8V 0.10V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width 2.67 6 Maximum - - Minimum 4 4 Maximum - - ns ns 3.0V 0.30V Unit MC9328MXL Advance Information, Rev. 5 64 Freescale Semiconductor Specifications Table 25. SDRAM Refresh Timing Parameter Table (Continued) Ref No. 3 4 5 6 7 1. 1.8V 0.10V Parameter Minimum SDRAM clock cycle time Address setup time Address hold time Precharge cycle period Auto precharge command period 11.4 3.42 2.28 tRP1 tRC1 Maximum - - - - - Minimum 10 3 2 tRP1 tRC1 Maximum - - - - - ns ns ns ns ns 3.0V 0.30V Unit tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual. SDCLK CS RAS CAS WE ADDR BA DQ DQM CKE Figure 51. SDRAM Self-Refresh Cycle Timing Diagram MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 65 Specifications 3.16 USB Device Port Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and how they work from the ground up. Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer. USBD_AFE (Output) 1 USBD_ROE (Output) tPERIOD USBD_VPO (Output) 6 3 tVPO_ROE t ROE_VPO t VMO_ROE 4 USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) USBD_VP (Input) USBD_VM (Input) tROE_VMO 2 tFEOPT 5 Figure 52. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX) Table 26. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX) 1.8V 0.10V Ref No. Parameter Minimum 1 tROE_VPO; USBD_ROE active to USBD_VPO low tROE_VMO; USBD_ROE active to USBD_VMO high tVPO_ROE; USBD_VPO high to USBD_ROE deactivated 83.14 Maximum 83.47 Minimum 83.14 Maximum 83.47 ns 3.0V 0.30V Unit 2 81.55 81.98 81.55 81.98 ns 3 83.54 83.80 83.54 83.80 ns MC9328MXL Advance Information, Rev. 5 66 Freescale Semiconductor Specifications Table 26. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX) 1.8V 0.10V Ref No. Parameter Minimum 4 tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0) tFEOPT; SE0 interval of EOP tPERIOD; Data transfer rate USBD_AFE (Output) 3.0V 0.30V Unit Minimum 248.90 Maximum 249.13 ns Maximum 249.13 248.90 5 6 160.00 11.97 175.00 12.03 160.00 11.97 175.00 12.03 ns Mb/s USBD_ROE (Output) USBD_VPO (Output) USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) 1 tFEOPR USBD_VP (Input) USBD_VM (Input) Figure 53. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX) Table 27. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX) 1.8V 0.10V Ref No. Parameter Minimum 1 tFEOPR; Receiver SE0 interval of EOP 82 Maximum - Minimum 82 Maximum - ns 3.0V 0.30V Unit MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 67 Specifications 3.17 I2C Module The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. SDA 5 SCL 1 2 3 4 6 Figure 54. Definition of Bus Timing for I2C Table 28. I2C Bus Timing Parameter Table 1.8V 0.10V Ref No. Parameter Minimum 1 2 3 4 5 6 Hold time (repeated) START condition Data hold time Data setup time HIGH period of the SCL clock LOW period of the SCL clock Setup time for STOP condition 182 0 11.4 80 480 182.4 Maximum - 171 - - - - Minimum 160 0 10 120 320 160 Maximum - 150 - - - - ns ns ns ns ns ns 3.0V 0.30V Unit 3.18 Synchronous Serial Interface The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external clock timing diagrams are shown in Figure 56 through Figure 58 on page 70. Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices. MC9328MXL Advance Information, Rev. 5 68 Freescale Semiconductor Specifications 1 STCK Output 2 STFS (bl) Output 4 6 STFS (wl) Output 8 12 10 STXD Output 11 31 SRXD Input 32 Note: SRXD input in synchronous mode only. Figure 55. SSI Transmitter Internal Clock Timing Diagram 1 SRCK Output 3 SRFS (bl) Output 5 7 SRFS (wl) Output 9 13 14 SRXD Input Figure 56. SSI Receiver Internal Clock Timing Diagram MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 69 Specifications 15 16 STCK Input 17 18 STFS (bl) Input 20 22 STFS (wl) Input 24 26 STXD Output 27 28 33 SRXD Input Note: SRXD Input in Synchronous mode only 34 Figure 57. SSI Transmitter External Clock Timing Diagram 15 16 SRCK Input 17 19 SRFS (bl) Input 21 23 SRFS (wl) Input 25 29 SRXD Input 30 Figure 58. SSI Receiver External Clock Timing Diagram Table 29. SSI (Port C Primary Function) Timing Parameter Table 1.8V 0.10V Ref No. Parameter Minimum Maximum Minimum Maximum 3.0V 0.30V Unit Internal Clock Operation1 (Port C Primary Function2) 1 2 3 STCK/SRCK clock period1 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 95 1.5 -1.2 - 4.5 -1.7 83.3 1.3 -1.1 - 3.9 -1.5 ns ns ns MC9328MXL Advance Information, Rev. 5 70 Freescale Semiconductor Specifications Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued) 1.8V 0.10V Ref No. Parameter Minimum 4 5 6 7 8 9 10 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low 2.5 0.1 1.48 -1.1 2.51 0.1 14.25 Maximum 4.3 -0.8 4.45 -1.5 4.33 -0.8 15.73 Minimum 2.2 0.1 1.3 -1.1 2.2 0.1 12.5 Maximum 3.8 -0.8 3.9 -1.5 3.8 -0.8 13.8 ns ns ns ns ns ns ns 3.0V 0.30V Unit 11a 11b 12 13 14 0.91 0.57 12.88 21.1 0 3.08 3.19 13.57 - - 0.8 0.5 11.3 18.5 0 2.7 2.8 11.9 - - ns ns ns ns ns External Clock Operation (Port C Primary Function2) 15 16 17 18 19 20 21 22 23 24 25 26 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low 92.8 27.1 61.1 - - - - - - - - 18.01 - - - 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 28.16 81.4 40.7 40.7 0 0 0 0 0 0 0 0 15.8 - - - 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 24.7 ns ns ns ns ns ns ns ns ns ns ns ns 27a 27b 8.98 9.12 18.13 18.24 7.0 8.0 15.9 16.0 ns ns MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 71 Specifications Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued) 1.8V 0.10V Ref No. Parameter Minimum 28 29 30 STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hole time after SRCK low 18.47 1.14 0 Maximum 28.5 - - Minimum 16.2 1.0 0 Maximum 25.0 - - ns ns ns 3.0V 0.30V Unit Synchronous Internal Clock Operation (Port C Primary Function2) 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 15.4 0 - - 13.5 0 - - ns ns Synchronous External Clock Operation (Port C Primary Function2) 33 34 1. SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 - - 1.0 0 - - ns ns 2. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. bl = bit length; wl = word length. Table 30. SSI (Port B Alternate Function) Timing Parameter Table Ref No. 1.8V 0.10V Parameter Minimum Maximum Minimum Maximum 3.0V 0.30V Unit Internal Clock Operation1 (Port B Alternate Function2) 1 2 3 4 5 6 7 8 STCK/SRCK clock period1 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 95 1.7 -0.1 3.08 1.25 1.71 -0.1 3.08 - 4.8 1.0 5.24 2.28 4.79 1.0 5.24 83.3 1.5 -0.1 2.7 1.1 1.5 -0.1 2.7 - 4.2 1.0 4.6 2.0 4.2 1.0 4.6 ns ns ns ns ns ns ns ns MC9328MXL Advance Information, Rev. 5 72 Freescale Semiconductor Specifications Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued) Ref No. 9 10 1.8V 0.10V Parameter Minimum SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low 1.25 14.93 Maximum 2.28 16.19 Minimum 1.1 13.1 Maximum 2.0 14.2 ns ns 3.0V 0.30V Unit 11a 11b 12 13 14 1.25 2.51 12.43 20 0 3.42 3.99 14.59 - - 1.1 2.2 10.9 17.5 0 3.0 3.5 12.8 - - ns ns ns ns ns External Clock Operation (Port B Alternate Function2) 15 16 17 18 19 20 21 22 23 24 25 26 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low 92.8 27.1 61.1 - - - - - - - - 18.9 - - - 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 29.07 81.4 40.7 40.7 0 0 0 0 0 0 0 0 16.6 - - - 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 25.5 ns ns ns ns ns ns ns ns ns ns ns ns 27a 27b 28 29 30 9.23 10.60 17.90 1.14 0 20.75 21.32 29.75 - - 8.1 9.3 15.7 1.0 0 18.2 18.7 26.1 - - ns ns ns ns ns MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 73 Specifications Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued) Ref No. 1.8V 0.10V Parameter Minimum Maximum Minimum Maximum 3.0V 0.30V Unit Synchronous Internal Clock Operation (Port B Alternate Function2) 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 18.81 0 - - 16.5 0 - - ns ns Synchronous External Clock Operation (Port B Alternate Function2) 33 34 1. SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 - - 1.0 0 - - ns ns 2. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. bl = bit length; wl = word length. MC9328MXL Advance Information, Rev. 5 74 Freescale Semiconductor Specifications 3.19 CMOS Sensor Interface The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing, a control register for statistic data generation, a status register, interface logic, a 32 x 32 image data receive FIFO, and a 16 x 32 statistic data FIFO. 3.19.1 Gated Clock Mode Figure 59 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge. Figure 60 on page 76 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in Table 31 on page 76. 1 VSYNC 7 HSYNC 5 2 6 PIXCLK DATA[7:0] Valid Data Valid Data Valid Data 3 4 Figure 59. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 75 Specifications 1 VSYNC 7 HSYNC 6 2 5 PIXCLK DATA[7:0] Valid Data Valid Data Valid Data 3 4 Figure 60. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 31. Gated Clock Mode Timing Parameters Ref No. 1 2 3 4 5 6 7 Parameter csi_vsync to csi_hsync csi_hsync to csi_pixclk csi_d setup time csi_d hold time csi_pixclk high time csi_pixclk low time csi_pixclk frequency Min 180 1 1 1 10.42 10.42 0 Max - - - - - - 48 Unit ns ns ns ns ns ns MHz The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and setup time, according to: Rising-edge latch data max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) In most of case, duty cycle is 50 / 50, therefore max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns MC9328MXL Advance Information, Rev. 5 76 Freescale Semiconductor Specifications negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time) 3.19.2 Non-Gated Clock Mode Figure 61 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge. Figure 62 on page 78 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in Table 32 on page 78. 1 VSYNC 6 4 PIXCLK 5 DATA[7:0] Valid Data Valid Data Valid Data 2 3 Figure 61. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 77 Specifications 1 VSYNC 6 5 4 PIXCLK DATA[7:0] Valid Data Valid Data Valid Data 2 3 Figure 62. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 32. Non-Gated Clock Mode Parameters Ref No. 1 2 3 4 5 6 Parameter csi_vsync to csi_pixclk csi_d setup time csi_d hold time csi_pixclk high time csi_pixclk low time csi_pixclk frequency Min 180 1 1 10.42 10.42 0 Max - - - - - 48 Unit ns ns ns ns ns MHz The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and setup time, according to: max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) In most of case, duty cycle is 50 / 50, therefore: max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time) MC9328MXL Advance Information, Rev. 5 78 Freescale Semiconductor 4 Pin-Out and Package Information Table 33 illustrates the package pin assignments for the 256-pin MAPBGA package. Table 33. MC9328MXL 256 MAPBGA Pin Assignments 1 A NVSS1 2 DAT3 3 CLK 4 NVSS4 5 USBD_ AFE USBD_ ROE USBD_ RCV 6 NVDD4 7 NVSS3 8 UART1_ RTS SSI0_ TXCLK SSI0_ RXFS 9 UART1_ RXD SPI1_ SCLK UART1_ TXD 10 NVDD3 11 N.C. 12 N.C. 13 QVDD4 14 N.C. 15 N.C. 16 N.C. Freescale Semiconductor MC9328MXL Advance Information, Rev. 5 79 B A24 DAT1 CMD SSI1_RXDAT USBD_VP SSI0_ RXCLK UART2_ RXD N.C. N.C. N.C. QVSS4 N.C. N.C. N.C. C A23 D31 DAT0 SSI1_RXCLK UART2_ CTS N.C. N.C. N.C. N.C. N.C. N.C. N.C. D A22 D30 D29 SSI1_RXFS USBD_ SUSPND DAT2 USBD_ VPO USBD_VM USBD_ VMO UART2_ RTS UART2_ TXD SSI1_ TXCLK NVSS1 NVSS1 NVSS1 NVSS1 RW SSI0_ RXDAT SSI0_ TXDAT SSI0_ TXFS UART1_ CTS QVSS1 NVDD1 NVDD1 CAS MA10 SPI1_ SPI_RDY SPI1_SS N.C. N.C. N.C. N.C. N.C. N.C. N.C. E A20 A21 D28 D26 N.C. N.C. N.C. N.C. N.C. N.C. N.C. F A18 D27 D25 A19 A16 SSI1_ TXFS SSI1_ TXDAT NVDD1 NVDD1 NVSS1 NVDD1 NVSS1 SPI1_ MISO SPI1_ MOSI QVDD1 NVSS2 NVDD2 TCK RAS N.C. N.C. REV N.C. N.C. LSCLK SPL_SPR G A15 A17 D24 D23 D21 N.C. CLS CONTRAST OE_ACD HSYNC VSYNC LD1 H J K L M A13 A12 A10 A8 A5 D22 A11 D16 A7 D12 A14 D18 A9 D13 D11 D20 D19 D17 D15 A6 NVDD1 NVDD1 NVDD1 D14 SDCLK PS NVSS2 NVDD2 TIN RESET_IN LD0 LD6 LD10 PWMO BIG_ENDI AN RESET_ OUT BOOT3 SDCKE0 CLKO LD2 LD7 LD12 CSI_MCLK CSI_D4 LD4 LD8 LD13 CSI_D0 CSI_ HSYNC CSI_ PIXCLK TRST BOOT1 TRISTATE LD5 LD11 LD14 CSI_D1 CSI_VSYNC LD9 QVDD3 TOUT2 CSI_D2 CSI_D6 LD3 QVSS3 LD15 CSI_D3 CSI_D5 Pin-Out and Package Information N A4 EB1 D10 D7 A0 D4 PA17 D1 DQM1 RESET_SF BOOT2 CSI_D7 TMS TDI P R T A3 EB2 NVSS1 D9 EB3 A2 EB0 A1 OE CS3 CS4 CS5 D6 D8 CS2 ECB D5 CS1 D2 LBA CS0 D3 BCLK1 MA11 DQM3 D0 DQM2 SDCKE1 DQM0 SDWE BOOT0 POR AVDD1 I2C_CLK TDO EXTAL16M I2C_DATA QVDD2 XTAL16M XTAL32K EXTAL32K QVSS2 1. burst clock Table 34 illustrates the package pin assignments for the 225-pin PBGA package. Table 34. MC9328MXL 225 PBGA Pin Assignments 1 A CMD 2 SSI1_ RXCLK CLK 3 SSI1_ TXCLK SSI1_ RXDAT SSI1_ RXFS DAT1 4 USBD_ ROE USBD_ AFE SSI1_ TXFS SSI1_ TXDAT D29 5 USBD_ SUSPND USBD_RCV 6 USBD_VM 7 SSI0_ RXFS SSI0_ RXDAT UART2_ RXD QVDD4 8 SSI0_ TXCLK UART1_ TXD SSI0_ TXFS UART2_ TXD UART1_ RXD SSI0_ RXCLK NVSS NVSS 9 SPI1_RDY 10 SPI1_ SCLK LSCLK 11 REV 12 PS 13 LD2 14 LD4 15 LD5 80 B C D Pin-Out and Package Information DAT3 USBD_ VMO USBD_ VPO USBD_VP SPI1_SS SPL_ SPR VSYNC LD0 LD3 LD6 LD7 D31 DAT0 DAT2 UART1_ RTS NVDD3 CONTRAST LD8 LD9 LD12 NVDD2 A23 A24 NVDD1 SPI1_ MOSI SPI1_ MISO CLS HSYNC LD1 LD11 TOUT2 LD13 MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor E A21 A22 D30 NVDD1 QVSS UART2_ RTS UART2_ CTS NVDD4 NVSS UART1_ CTS SSI0_ TXDAT NVSS NVSS OE_ ACD QVDD3 LD10 TIN CSI_D0 CSI_ MCLK CSI_D4 F A20 A19 D28 D27 NVDD1 NVDD1 LD14 LD15 CSI_D2 G H A17 A15 A18 A16 D26 D23 D25 D24 NVDD1 D22 NVSS NVSS QVSS NVDD2 PWMO CSI_D1 CSI_D3 CSI_ VSYNC TCK CSI_D7 CSI_ PIXCLK TDO CSI_HSYNC I2C_DATA CSI_D5 TMS J A14 A12 D21 D20 NVDD1 NVSS NVSS QVDD1 NVSS CSI_D6 I2C_ CLK BOOT2 BOOT1 BOOT0 K A13 A11 CS2 D19 NVDD1 NVSS QVSS NVDD1 NVSS D1 TDI BIG_ ENDIAN QVSS QVDD2 SDCKE0 SDCKE1 CAS RESET_ OUT XTAL16M RESET_IN TRISTATE CLKO SDWE XTAL32K L M N P R A10 D16 A8 D14 A6 A9 D15 A7 A5 D11 D17 D13 D12 A4 EB1 D18 D10 EB0 A3 EB2 NVDD1 EB3 D9 A2 OE NVDD1 NVDD1 D8 A1 D7 CS5 CS4 CS3 D6 A0 D2 CS1 CS0 D5 SDCLK ECB BCLK1 PA17 MA10 D4 NVSS RW D0 MA11 LBA NVSS NVSS DQM2 DQM1 D3 POR BOOT3 DQM0 RAS DQM3 EXTAL32K EXTAL16M TRST RESETSF AVDD1 1. burst clock Pin-Out and Package Information 4.1 MAPBGA 256 Package Dimensions Figure 63 illustrates the 256 MAPBGA 14 mm x 14 mm x 1.30 mm package, which has 0.8 mm spacing between the pads. The device designator for the MAPBGA package is VH. Case Outline 1367 TOP VIEW BOTTOM VIEW NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. 3. 4. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. SIDE VIEW DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 63. MC9328MXL 256 MAPBGA Mechanical Drawing MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 81 Pin-Out and Package Information 4.2 PBGA 225 Package Dimensions Figure 64 illustrates the 225 PBGA 13 mm x 13 mm x 0.8 mm package. Case Outline 1304B TOP VIEW BOTTOM VIEW NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. 3. 4. 5. DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. SIDE VIEW DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. Figure 64. MC9328MXL 225 PBGA Mechanical Drawing MC9328MXL Advance Information, Rev. 5 82 Freescale Semiconductor NOTES MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor 83 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products P.O. Box 5405 herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the Denver, Colorado 80217 suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any 1-800-521-6274 or 480-768-2130 liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters Japan: that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary Freescale Semiconductor Japan Ltd. in different applications and actual performance may vary over time. All operating parameters, Technical Information Center including "Typicals", must be validated for each customer application by customer's technical experts. 3-20-1, Minami-Azabu, Minato-ku Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Tokyo 106-8573, Japan Freescale Semiconductor products are not designed, intended, or authorized for use as components 81-3-3440-3569 in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product Asia/Pacific: could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor Hong Kong Ltd. Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall 2 Dai King Street indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and Tai Po Industrial Estate distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney Tai Po, N.T., Hong Kong fees arising out of, directly or indirectly, any claim of personal injury or death associated with such 852-26668334 unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Home Page: www.freescale.com Learn More: For more information about Freescale products, please visit www.freescale.com. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The ARM POWERED logo is the registered trademark of ARM Limited. ARM9, ARM920T, and ARM9TDMI are the trademarks of ARM Limited. (c) Freescale Semiconductor, Inc. 2004. All rights reserved. MC9328MXL/D Rev. 5 08/2004 |
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