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INTEGRATED CIRCUITS
DATA SHEET
SAA7740H Digital Audio Processing IC (DAPIC)
Product specification Supersedes data of 1996 Mar 11 File under Integrated Circuits, IC01 1997 May 30
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
FEATURES Hardware * Two digital inputs and two digital outputs in the I2S-bus format (i.e. 4 audio channels) * Independent input/output interfaces * Slave input/output interfaces * Slave processing * I2C-bus microcontroller interface * DC filtering at the inputs * One programmable 2nd-order digital filter unit * Two multiply accumulate processor units (24 x 16-bit/MAC) * DRAM interface and address computation unit for external delay lines * On-chip coefficient and external delay line address storage * Hardware controlled soft mute via the MUTE pin * Hardware controlled soft demute via the RST pin * Operating ambient temperature; -40 to +85 C. Software * 5-band parametric equalizer with selectable centre frequency, slope setting and boost/cut gain settings from -12 to +12 dB * Stereo width control from mono to stereo to spatial stereo * Stereo Hall-effects for field acoustics, such as concert halls, with 8 coefficients and 8 delayed taps per channel QUICK REFERENCE DATA SYMBOL VDD(tot) IDD(tot) fxtal Ptot Tamb PARAMETER total DC supply voltage total DC supply current input crystal frequency total power dissipation operating ambient temperature fxtal = 16.9344 MHz CONDITIONS all VDD pins fxtal = 16.9344 MHz - 12.288 - -40 MIN. 4.5 TYP. 5.0 60 16.9344 0.3 -
SAA7740H
* External delay line processing for delays up to 1 second * Reverberation with selectable reverberation time (up to 5 seconds) and energy * Three different surround sound programs to obtain a spatial effect on 4 loudspeakers * Passive DOLBY surround processing with the addition of an external dynamic noise reduction IC * Karaoke processing * Dual 16th-order correction filtering * Quad 8th-order correction filtering * Digital volume and balance control * Soft controlled soft mute/demute via the microcontroller interface * Input switching matrix * Output rear and front switching matrix. APPLICATIONS * Digital amplifiers * Audio combination sets * Car audio systems * TV audio channels.
MAX. 5.5 - 23.0 - +85 V
UNIT mA MHz W C
ORDERING INFORMATION TYPE NUMBER SAA7740H PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT319-2
1997 May 30
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
BLOCK DIAGRAM
SAA7740H
handbook, full pagewidth
VDDX 60
VSSX 61
CLKO 63
TSTCLK 45
TST1 47
TST2 48
TST3 49 9, 13, 25, 40, 46, 50, 55
CLK1/XTAL1 XTAL2
56 59 XTAL OSCILLATOR CLOCK COUNTER
VSS 7 7, 8, 26, 32, 38, 53, 54 7 VDD
SCCLK
62
DIWS DI1D DI2D DIBCK
43 41 42 44 I2 S-BUS INPUT INPUT BUFFER
DIGITAL SIGNAL PROCESSING CORE 2nd-ORDER FILTER MAC OFFSET FILTER REGISTERS
36 34 OUTPUT BUFFER I2 S-BUS OUTPUT 35 37 4 19 10 17 18 14 31 to 27/24 to 21 ADDRESS CONTROL UNIT 11, 12, 15, 16
DOWS DO1D DO2D DOBCK MUTE RAS CAS CAS2 WE OE A0 to A8 D0 to D3
RST ALL
1 64 16 PROGRAM COUNTER PROGRAMMABLE ROM 7 16 COEFFICIENT RAM
16
SAA7740H
I 2 C-BUS INTERFACE 51 AS1 52
20 33 2 3
A8B MUX SCL SDA
MLC173
AS2
Fig.1 Block diagram.
1997 May 30
3
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
PINNING SYMBOL RST SCL SDA MUTE n.c. n.c. VDD VDD VSS CAS D0 D1 VSS OE D2 D3 CAS2 WE RAS A8B A8 A7 A6 A5 VSS VDD A4 A3 A2 A1 A0 VDD MUX PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 DESCRIPTION reset input (active LOW) serial clock input (I2C-bus) serial data input/output not connected not connected supply voltage supply voltage ground supply column address strobe (DRAM) (active LOW) input/output data bus line 0 (DRAM) input/output data bus line 1 (DRAM) ground supply output buffer enable (DRAM) (active LOW) input/output data bus line 2 (DRAM) input/output data bus line 3 (DRAM) second column address strobe (active LOW) write enable (DRAM; active LOW) row address strobe (DRAM; active LOW) inverse MSB address line output (DRAM) address line output 8 (DRAM) address line output 7 (DRAM) address line output 6 (DRAM) address line output 5 (DRAM) ground supply supply voltage address line output 4 (DRAM) address line output 3 (DRAM) address line output 2 (DRAM) address line output 1 (DRAM) address line output 0 (DRAM) supply voltage address latch strobe output (SRAM) CLKO ALL 63 64 TST3 VSS AS1 AS2 VDD VDD VSS CLK1/ XTAL1 n.c. n.c. XTAL2 VDDX VSSX SCCLK 49 50 51 52 53 54 55 56 57 58 59 60 61 62 VSS TST1 TST2 46 47 48 (I2C-bus) mute input (active HIGH) SYMBOL DO1D DO2D DOWS DOBCK VDD n.c. VSS DI1D DI2D DIWS DIBCK TSTCLK PIN 34 35 36 37 38 39 40 41 42 43 44 45
SAA7740H
DESCRIPTION digital audio output 1 (I2S-bus) digital audio output 2 (I2S-bus) digital audio input word select digital audio input serial bit clock supply voltage not connected ground supply digital audio input 1 (I2S-bus) digital audio input 2 (I2S-bus) digital audio input word select digital audio input serial bit clock clock input for test mode (should be tied LOW) ground supply test pin input 1 (should be tied LOW) test pin input 2 (should be tied LOW) test pin input 3 (should be tied LOW) ground supply address select input 1 (I2C-bus) address select input 2 (I2C-bus) supply voltage supply voltage ground supply clock or crystal input not connected not connected crystal output 2 crystal supply voltage crystal ground supply scan test clock input (should be tied LOW) clock signal output mode select input (should be tied HIGH)
1997 May 30
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
56 CLK1/XTAL1
62 SCCLK
59 XTAL2
63 CLKO
60 VDDX
61 VSSX
54 VDD
53 VDD
55 VSS
64 ALL
58 n.c.
57 n.c.
handbook, full pagewidth
52 AS2 51 AS1 50 VSS 49 TST3 48 TST2 47 TST1 46 VSS 45 TSTCLK 44 DIBCK 43 DIWS 42 DI2D 41 DI1D 40 VSS 39 n.c. 38 VDD 37 DOBCK 36 DOWS 35 DO2D 34 DO1D 33 MUX VDD 32
MLC156
RST SCL SDA MUTE n.c. n.c. VDD VDD VSS
1 2 3 4 5 6 7 8 9
CAS 10 D0 11 D1 12 VSS 13 OE 14 D2 15 D3 16 CAS2 17 WE 18 RAS 19 A8B 20 A8 21 A7 22 A6 23 A5 24
SAA7740H
VSS 25
VDD 26
A4 27
A3 28
A2 29
A1 30
Fig.2 Pin configuration.
1997 May 30
5
A0 31
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
GENERAL DESCRIPTION The SAA7740H is a function-specific digital signal processor. The device is capable of performing processing for listening-environments such as equalization, hall-effects, reverberation, surround-sound and digital volume/balance control. The SAA7740H can also be reconfigured (in a dual and quad filter mode) so that it can be used as a digital filter with programmable characteristics. For reasons of silicon efficiency, the SAA7740H realises most functions directly in hardware. The flexibility exists in the possibility to download function parameters, correction coefficients and various configurations from a host microcontroller (see Fig.1). The parameters can be passed in real time and all functions can be switched on simultaneously. The communication with a host microcontroller conforms with the standard I2C-bus format. The SAA7740H accepts 2 digital stereo signals in the I2S-bus format at audio sampling frequency (fas) and provides 2 digital stereo outputs. Mode description The SAA7740H can be set in four basic modes of operation. GENERAL DAPIC MODE
SAA7740H
In the general DAPIC mode two variants are available (see Figs 3 and 4). In this mode the DAPIC accepts 2 stereo input signals. DC filtering is performed on the inputs before further processing. On one of the stereo inputs a 5-band graphic equalization can be performed. The stereo image of this signal can be controlled from mono to stereo. In the first variant (see Fig.3) a stereo hall-effect can be added to the signal by means of direct reflections. In the second variant (see Fig.4) a reverberation effect can be added to the signal by means of exponential decaying reflections. Surround-sound can then be created for the rear loudspeakers. The surround-sound module is also able to provide karaoke. The surround-sound module accepts the second stereo input, a microphone signal can be added via the 5-band equalizer. At the output, each of the 4 channels can be individually delayed via the external DRAM. The interfacing and addressing of the DRAM is performed by the DAPIC. The applications for the general mode are digital amplifiers, audio combination sets and TV audio channels.
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Product specification
SAA7740H
Fig.3 General DAPIC mode with hall-effect.
handbook, full pagewidth
1997 May 30
5 - BAND GRAPHIC EQUALIZER DELAY
(1) (1)
Philips Semiconductors
STEREO CONTROL hall effect DELAY 5 - BAND GRAPHIC EQUALIZER
(1) (1) (1)
Digital Audio Processing IC (DAPIC)
SWITCHES
DC FILTERS DELAY
(1)
VOLUME/ BALANCE
SWITCHES
7
SURROUND SOUND OR KARAOKE
MLC151
(1) External DRAM.
(1) External DRAM.
Product specification
SAA7740H
Fig.4 General DAPIC mode with reverberation.
handbook, full pagewidth
1997 May 30
(1)
Philips Semiconductors
5 - BAND GRAPHIC EQUALIZER STEREO CONTROL
(1)
reverberation generator
5 - BAND GRAPHIC EQUALIZER
(1)
Digital Audio Processing IC (DAPIC)
SWITCHES
DC FILTERS DELAY
(1)
VOLUME/ BALANCE
SWITCHES
8
SURROUND SOUND OR KARAOKE
MLC152
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
DUAL-FILTER MODE In the dual-filter mode one mono signal is accepted (see Fig.5) The input can be selected from either one of the 2 stereo inputs (from the left or right input channel). DC filtering is performed at the input before further processing. Two separate corrections, in parallel, can be performed by means of an 8-band graphic equalizer.
SAA7740H
16 poles and 16 zeros can be selected arbitrarily from the Z-domain. At the output, one of the channels can be delayed internally by the DAPIC. The two corrected outputs can be added to either one of the two stereo outputs. The application for this mode is in loudspeaker correction.
handbook, full pagewidth
16 POLE/ZERO CORRECTION FILTER
FIXED DELAY 11 SAMPLES
DC FILTERS 16 POLE/ZERO CORRECTION FILTER
SWITCHES
SWITCHES
MLC153
Fig.5 Dual filter mode.
1997 May 30
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
QUAD-FILTER MODE In the quad-filter mode two stereo signals are accepted (see Fig.6). DC filtering is performed at the inputs before further processing. A correction can be performed on the input signals using a 4-band graphic equalizer, i.e. 8 poles and 8 zeros can be placed arbitrarily in the Z-domain. At the output, different delays can be applied to the 4 channels via the external DRAM. The interfacing and addressing of the DRAM is performed by the DAPIC. The application for this mode is in 4-channel correction applications such as car and home audio systems. STEREO EXPANSION MODE
SAA7740H
In the stereo expansion mode one stereo signal is accepted (see Fig.7). DC filtering is performed at the inputs before further processing. A 4-band graphic equalization is first performed after which a complex stereo expansion is applied. A room effect can be added by the addition of early reflections. The applications for this mode are in the headphone out-of-head and incredible stereo applications.
handbook, full pagewidth
8 POLE/ZERO CORRECTION FILTER
8 POLE/ZERO CORRECTION FILTER DC FILTERS
(1)
SWITCHES
DELAY
SWITCHES
8 POLE/ZERO CORRECTION FILTER
8 POLE/ZERO CORRECTION FILTER
MLC154
(1) External DRAM.
Fig.6 Quad filter mode.
1997 May 30
10
Product specification
SAA7740H
Fig.7 Stereo expansion mode.
handbook, full pagewidth
1997 May 30
D DELAY Hall-effect DELAY
(1) (1)
Philips Semiconductors
4 - BAND EQUALIZER 8 POLE/ZERO VOLUME/ BALANCE
(1)
DC FILTERS STEREO CONTROL D
(1)
8 POLE/ZERO
4 - BAND EQUALIZER
Digital Audio Processing IC (DAPIC)
SWITCHES
SWITCHES
11
MLC155
(1) External DRAM.
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
FUNCTIONAL DESCRIPTION The SAA7740H is used as a slave device. The internal operation is automatically synchronized with the word select clock of the incoming data (I2S-bus format). Within an input frame of data, at fas, 384 clock cycles are needed to compute a stereo output sample. The external clock therefore, should be minimum 384fas. External clocks which generate more than 384 clocks cycles will cause the processor to return to a wait state. The external clock can be either a crystal connected directly to the DAPIC, or any clock generated in the system which contains DAPIC. The I2S-bus Two I2S-bus inputs and outputs are available on the DAPIC. The serial clock (DIBCK and DOBCK) and the word select (DIWS and DOWS) are applied from an external source. The two inputs and outputs are fully synchronized. However, the inputs do not have to be synchronized with the outputs. The clock and word select signals can be separated at the input and output. The input and output buses support word lengths in accordance with the I2S-bus standard. Up to 20 significant bits can be read by the DAPIC. Zeros will be added at the LSB position should less than 20 bits be applied. If more than 20 bits are applied the extra LSBs will be ignored. The stereo word rate (fas) can be either 32, 44.1 or 48 kHz. Because the DAPIC is a slave device it can only be connected to a master I2S-bus transmitter or receiver (see Chapter "Timing characteristics" and Fig.9). I2C-bus control (SCL and SDA) The I2C-bus interface is used to control the operation of the DAPIC for the audio signal processing and write the coefficients and the external delay line addresses of the different signal processing algorithms. New coefficients are updated in real time to the internal RAM. Table 1 BIT 7 0 Note I2C-bus slave address. BIT 6 0 BIT 5 1 BIT 4 1 BIT 3 0 BIT 2 AS2(1) BIT 1
SAA7740H
The transfer byte organization is as follows: START condition First byte (8 bits) Acknowledge (1-bit) Second byte (8 bits) Acknowledge (1-bit) Third to tenth byte (8 bits) Acknowledge (1-bit) STOP condition. The first byte is the address of the I2C-bus device being addressed. If the device detects its address it answers with an acknowledge by pulling down the data line (SDA) for one clock period (SCL line). The second byte contains the address of the internal RAM to which the first new coefficient should have written. The data will then be transmitted. Each new word (coefficient) is 2 bytes wide. Up to four words of data can be written within one transfer. Should the mode of the feature register be addressed then only one data word will be transferred. Because the I2C-bus (on the DAPIC) is a slave receiver bus, the clock has to be generated by the host microcontroller. The minimum time interval between two I2C-bus transfers (bus free between a STOP and START condition) should coeff + 1 be: t inv > ----------------------- ms f as Where: Number of coefficients = coeff Frequency fas should be in kHz.
BIT 0 0
AS1(1)
1. AS1 and AS2 are the hardware (pin) programmable address bits. When the device detects this address it will respond with an acknowledge pulse on the SDA line.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
Improper acknowledge generated by the DAPIC
SAA7740H
If an I2C-bus device, other than DAPIC, is addressed by the master then the DAPIC will generate a short acknowledge pulse. The DAPIC starts pulling down the SDA line at the trailing edge of the SCL clock pulse. and releases the SDA line approximately 390 ns after the leading edge of the following SCL LOW-to-HIGH transition (see Fig.8). This improper acknowledge pulse can cause the I2C-bus master to detect an incorrect acknowledgement, depending on the capturing moment of the SDA line by the I2C-bus master. Any possible non-acknowledgements of involved I2C-bus devices, including the SAA7740H, will be masked thus making the system unreliable. To avoid these problems the I2C-bus master should only capture the SDA line at such a moment that the improper acknowledge pulse will not be detected.
handbook, full pagewidth
non-DAPIC device address
data output from transmitter improper acknowledge generated by DAPIC data output from DAPIC
SCL from master S
1
2
7
8
9
START condition
390 ns (typ)
MGK425
Fig.8 Improper acknowledge generated by the DAPIC.
1997 May 30
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
DRAM interface The DRAM interface contains a nibble wide data bus, a 9-bit wide address bus and all necessary control signals to enable the different DRAM configurations. Timing of the control signals RAS, CAS, CAS2, A8B, OE and WE is related to the applied clock frequency of the DAPIC. The important timing parameters are the page mode cycle time (tcy;CAS), the access time (tacc;RAS), the refreshing rate and the maximum value for RAS to CAS delay time (tdRAS;CAS) (see Chapter "Timing characteristics" and Fig.10). A read/write operation will always be executed in the page mode (one row address and four column addresses) because every data transfer consists of 4 nibbles. The refresh time of the DRAM (trfsh) must be greater than; 2 addr t rfsh > ------------ ms 3f - as where `addr' is the number of physical address lines and fas is measured in kHz.
SAA7740H
For fast DRAMs, the maximum value for RAS to CAS delay time (tdRAS;CAS) is important. Different DRAM combinations can be connected to the DAPIC. The smallest DRAM is a 64 x 4-bit (256 kbits) RAM. For this configuration, 16K data words can be stored. When this RAM is connected to the DAPIC, the MSB address signal (A8) can be felt floating. The DAPIC can address up to 1 Mbit DRAMs. However, RAMs greater than 1 Mbit can also be connected. This, therefore, implies that the redundant address lines of the RAM must be fixed to VDD or VSS or must be joined with one of the other address pins. The choice of a 256 kbit or a 1 Mbit DRAM device must be indicated by a flag bit residing in the start address control word of the different delay lines.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VDD IIK IOK IO IDD ISS LTCH PO Ptot Tstg Tamb Ves PARAMETER DC supply voltage (each supply pin) voltage difference between VDD and VDDX DC input clamp diode current DC output clamp diode current (output type 4 mA) DC output sink or source current (output type 4 mA) DC supply current per pin DC supply current per pin latch-up protection power dissipation per output total power dissipation storage temperature operating ambient temperature electrostatic discharge note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1.5 k. 2. Machine model: C = 200 pF; L = 2.5 H; R = 0 . THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 47 CIC specification/test method VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V -0.5 < VO < VDD + 0.5 V CONDITIONS MIN. -0.5 - - - - - - 100 - - -65 -40 -3000 -300
SAA7740H
MAX. +6.5 550 10 20 20 50 50 - 100 1 +150 +85 +3000 +300 V
UNIT
mV mA mA mA mA mA mA mW W C C V V
UNIT K/W
1997 May 30
15
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
DC CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL VDDn IDD(tot) Ptot VIH PARAMETER DC supply voltage (pins 7, 8, 26, 32, 38, 53, 54 and 60) total of all DC supply current pins total power dissipation HIGH level input voltage (pins 1, 3, 4, 11, 12, 15, 16, 36, 37, 41 to 45, 47 to 49, 51, 52, 62 and 64) LOW level input voltage (pins 1, 3, 4, 11, 12, 15, 16, 36, 37, 41 to 45, 47 to 49, 51, 52, 62 and 64) Schmitt trigger positive-going threshold (pin 2) Schmitt trigger negative-going threshold (pin 2) hysteresis voltage (pin 2) HIGH level output voltage (pins 10 to 12, 14 to 24, 27 to 31, 33 to 35 and 63) LOW level output voltage (pins 3, 10 to 12, 14 to 24, 27 to 31, 33 to 35 and 63) input leakage current (pins 1, 2, 4, 36, 37, 41 to 45, 47 to 49, 51, 52 and 62) VDD = 4.5 V; IO = 4 mA fxtal = 16.9344 MHz fxtal = 16.9344 MHz CONDITIONS MIN. 4.5 - - 0.7VDD TYP. 5.0 60 300 -
SAA7740H
MAX. 5.5 - - -
UNIT V mA mW V
VIL
-
-
0.3VDD
V
Vth(pos) Vth(neg) Vhys VOH
- 0.2VDD - 4.0
- - 0.33VDD -
0.8VDD - - -
V V V V
VOL
VDD = 4.5 V; IO = 4 mA
-
-
0.5
V
ILI
VDD = 0 or 5.5 V
-
-
1
A
IZO Rpd tr(i) tf(i) tr(o)
output leakage current; 3-state VDD = 0 or 5.5 V (pins 3, 11, 12, 15 and 16) internal pull-down resistance to VSS (pin 64) input rise time input fall time output rise time for LOW-to-HIGH transition VI = VDD VDD = 5.5 V VDD = 5.5 V
- 17 - -
- - 6 6 - -
5 134 200 200 9.5 + 0.4CL 8.5 + 0.4CL
A k ns ns ns ns
VDD = 4.5 V; Tamb = 85 C; - CL = pF; pins 11, 12, 15 and 16 VDD = 4.5 V; Tamb = 85 C; CL = pF; pins 10, 14, 17 to 24, 27 to 31, 33 to 35 and 63 -
tf(o)
output fall time for HIGH-to-LOW transition
VDD = 4.5 V; Tamb = 85 C; - CL = pF; pins 11, 12, 15 and 16 VDD = 4.5 V; Tamb = 85 C; CL = pF; pins 10, 14, 17 to 24, 27 to 31, 33 to 35 and 63 -
- -
11 + 0.5CL 9.0 + 0.5CL
ns ns
1997 May 30
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
AC CHARACTERISTICS VDDX = 5 V; Tamb = +25 C; unless otherwise specified. SYMBOL fxtal f I59 g Vxtal CL
1 2Tclk
SAA7740H
PARAMETER crystal input frequency spurious frequency attenuation crystal current output (pin 59) transconductance at maximum current voltage across crystal load capacitance half clock period of external clock
CONDITIONS 384fas
MIN. 12.288 20 - -
TYP. 16.9344 - 1 - -
MAX. 23.0
UNIT MHz dB mA mS mV pF ns
slave mode only
- - - - 21
0.4 500 - -
15 -
TIMING CHARACTERISTICS SYMBOL tHC tLC tr tf th1 tsu1 th2 tsu2 tacc DRAM timing
1 2Tclk
PARAMETER pulse width HIGH, DIBCK and DOBCK pulse width LOW, DIBCK and DOBCK DIBCK and DOBCK rise time DIBCK and DOBCK fall time DIWS and DOWS hold time DIWS and DOWS set-up time DI1D and DI2D hold time DI1D and DI2D set-up time DO1D and DO2D access time 110 110 - - 10 20 10 20 -
MIN. - - 20 20 - - - -
MAX.
UNIT ns ns ns ns ns ns ns ns ns
25 + 0.5CL (CL in pF) -
1 2Tclk - 12 1 T 2 clk - 12
half clock period RAS precharge time RAS pulse width row address set-up time row address hold time RAS to CAS delay time CAS hold time RAS hold time RAS to column address column address hold time from RAS column address hold time from RAS precharge column address to RAS lead time CAS to RAS precharge time column address set-up time 17
21 4x
1 1
ns ns ns ns ns ns ns ns
2Tclk
tp;RAS tW;RAS tsu;RA th;RA tdRAS;CAS th;CAS th;RAS tRAS;CA thCA;RAS thCA;RASp tlCA;RAS tpCAS;RAS tsu;CA 1997 May 30
- - - - 2 x 12Tclk + 14 - -
1
16 x
2Tclk
-8
2Tclk - 12 1 T 2 clk 1 T 2 clk 1
2 x 12Tclk - 11 4x 2x - 5x
1 2Tclk
- 12 - 12 - 11
+8
ns ns ns ns ns ns
- - - - -
2Tclk - 12 1
3 x 12Tclk - 8 4x
1 2Tclk
- 14
2Tclk - 8
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
SYMBOL th1CA;CAS th2CA;CAS tW;CAS tp;CAS tcy;CAS tacc;CA tacc;CAS tacc;RAS thDAT;CAS trcy;def tsu;DAT th;DAT thDAT;RAS twcy;def toff
PARAMETER column address hold time to CAS column address hold time to CAS precharge CAS pulse width CAS precharge time CAS page mode cycle time access time from column address access time from CAS access time from RAS data hold time from CAS read cycle definition time data input set-up time data input hold time data input hold time from RAS write cycle definition time output data disable time 3x
1 1
MIN.
2Tclk
MAX. - - - - - 3 x 12Tclk - 20 2 x 12Tclk - 24 4x - - - - - -
1 2Tclk + 1 2Tclk
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
- 14
2Tclk - 1 1
15 - 11
2 x 12Tclk - 14 2x 4x - - - 2 4 x 12Tclk - 10
1 2Tclk - 8 3 x 12Tclk 5 x 12Tclk 2 x 12Tclk 2Tclk 2Tclk
- 22
- 16 - 15 - 12
-
8
ns
handbook, full pagewidth
VH CL VL t HC t h1 WS t LC t su1
t su2
t h2
DATA IN
t acc
DATA OUT
MLC157
Fig.9 I2S-bus timing diagram.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
handbook, full pagewidth
t p;RAS
tf t hCA;RAS
t W;RAS
tr VH VL
RAS t h;CAS t W;CAS tt t cy;CAS t p;CAS
t pCAS;RAS CAS
t dRAS;CAS
t h;RAS
t RAS;CA t su;CA t su;RA A0 to A8 t h;RA ROW ADD t h1CA;CAS tr COLUMN ADD t h2CA;CAS COLUMN ADD
t lCA;RAS t hCA;RASp COLUMN
WE t rcy;def t rcy;def READ OE t acc;RAS D0 to D3 t wcy;def t hDAT;CAS t acc;CA t acc;CAS t rcy;def t rcy;def
DATA OUT
DATA OUT
t wcy;def
WE
WRITE
OE t wcy;def t su;DAT D0 to D3 t h;DAT DATA IN t hDAT;RAS t p;RAS RAS t pCAS;RAS t p;RAS t RAS;CA t W;RAS DATA t wcy;def t off IN
REFRESH
CAS
MLC158
A0 to A8
ROW
Fig.10 Timing diagram DRAM interface.
1997 May 30
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
I2S-BUS PROTOCOL The I2S-bus digital interface is used for communication to external digital sources. It is a 3-line serial bus with one line each for data, clock and word select. Figure 11 illustrates an excerpt from the Philips I2S-bus specification interface report with respect to general timing and format of the bus. Word select (WS) at logic 0 signifies the left channel and logic 1 the right channel. The serial data is transmitted in two's complement with MSB first. One clock period after the negative edge of the WS line, the MSB of the left channel is transmitted. Data is synchronized on the negative edge of the clock and latched on the positive edge.
SAA7740H
Two data line have been implemented as input from an external processor for the four audio channels. Because of this configuration the DAPIC operates in the following manner. The I2S-bus input block reads 4 samples (left and right samples of the front and rear channel) and stores the information into the register file. The operators read from the register file, process the data and store the intermediate results back into the register file. If a delay line is required, the external RAM will need to be accessed. The output samples are read from the register file and are passed via the fade unit to the I2S-bus output block. The same operation is repeated for each incoming audio sample.
handbook, full pagewidth
T t LC SCK t sr SD WS t hr VIH VIL t HC VIH VIL
SCK
WS
SD
MSB LEFT
MSB RIGHT
MLC159
Fig.11 I2S-bus timing format.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
I2C-BUS PROTOCOL The I2C-bus is intended for 2-way, 2-line communication between different ICs or modules. The two lines are the serial data line (SDA) and the serial clock line (SCL). Both lines must be connected to the supply rail via a pull-up resistor when connected to the output stages of a microcontroller. Data transfer can only be initiated when the bus is not busy. Full details of the I2C-bus are given in the document "The I2C-bus and how to use it". This document may be ordered using the code 9398 393 40011. Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulses as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 100 kHz (see Fig.12). START and STOP condition In the START and STOP condition the data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the STOP condition (P); (see Fig.13). Data transfer
SAA7740H
A device generating a message is a `transmitter', a device receiving a message is a `receiver'. The device that controls the message is the `master' and the devices which are controlled by the device are the `slaves' (see Fig.14). Acknowledge The number of data bytes that are transferred between the START and STOP conditions, from transmitter to receiver, is unlimited. Each byte is followed by an acknowledge bit. The acknowledge bit is a HIGH level bit placed on the bus by the transmitter, whereas the master generates an extra acknowledge bit which is related to the clock pulse. A slave receiver which is addressed must generate an acknowledge bit after the reception of each byte. The master must also generate an acknowledge bit after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must also be taken into account. A master receiver must signal an end-of-data to the transmitter. This is achieved by not generating an acknowledge on the last byte that has been clocked out of the slave. In this condition the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.15).
handbook, full pagewidth
SDA
SCL data line stable data valid change of data allowed
MLC160
Fig.12 Bit transfer on the I2C bus.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
handbook, full pagewidth
SDA
SCL S START condition P STOP condition
MLC161
Fig.13 START and STOP conditions.
handbook, full pagewidth
SDA MSB acknowledgement signal from receiver byte complete interrupt within receiver clock line held LOW while interrupts are serviced 2 7 8 9 ACK 1 2 3 to 8 acknowledgement signal from receiver
SCL S
1
9 P STOP condition
MLC162
START condition
Fig.14 Data transfer on the I2C-bus.
handbook, full pagewidth
data output from transmitter not acknowledge
data output from receiver acknowledge
SCL from master S
1
2
7
8
9
MLC163
START condition
clock pulse for acknowledgement
Fig.15 Acknowledge on the I2C-bus.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
APPLICATION INFORMATION Clock circuit and oscillator The clock generation of the SAA7740H is designed to accommodate two main modes, the master and the slave. In the master mode, the DAPIC is the master in the system. The clock is generated by connecting a crystal to the oscillator pins CLK1/XTAL1 and XTAL2 (see Fig.16). In the slave mode, the DAPIC is supplied as a slave. The external clock should be connected to the oscillator at pin CLK1/XTAL1 (see Fig.17). Crystal oscillator supply The power supply for the oscillator is separate from the other supply line. This is to minimize feedback from the ground bounce of the IC to the oscillator. Pin VSSX is the ground supply and VDDX is the positive supply. Power supply connection and EMC The SAA7740H has in total 8 positive supply lines (VDD) including VDDX, and 8 ground supply lines (VSS) including VSSX. For correct current distribution all positive supply lines should be connected together on the printed circuit-board. The ground supply lines should also be connected together on the printed circuit-board. To minimize radiation the IC should be placed on a double-layer printed circuit-board with a large ground plane on one side. The ground supply lines should have a short connection to the ground plane. An LC network in the positive supply lines can be used as a high frequency filter. Test mode connections Pins SCCLK, TSTCLK, TST1, TST2 and TST3 are used to put the IC in the test mode and to test the internal connections. In the application these pins must be connected to ground.
handbook, halfpage
SAA7740H
C1 10 pF C2 10 pF
CLK1/XTAL1 R1 100 k XTAL2
56
59
MLC164
Fig.16 Master mode.
handbook, halfpage
external clock
C1 10 pF 30 pF
CLK1/XTAL1 R1 100 k XTAL2 C3
56 max 1 V (p-p)
C2
59
MLC165
10 nF
Fig.17 Slave mode.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA7740H
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
pin 1 index
wM bp
64 1 wM D HD ZD 19
20
e
bp
vMA B vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA7740H
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7740H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
NOTES
SAA7740H
1997 May 30
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/04/pp28
Date of release: 1997 May 30
Document order number:
9397 750 02262

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