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PIC16CE62X
OTP 8-Bit CMOS MCU with EEPROM Data Memory
Devices included in this data sheet:
* PIC16CE623 * PIC16CE624 * PIC16CE625
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
RA2/AN2/VREF RA3/AN3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16CE62X
High Performance RISC CPU:
* Only 35 instructions to learn * All single-cycle instructions (200 ns), except for program branches which are two-cycle * Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle Device Program Memory 512x14 1Kx14 2Kx14 RAM EEPROM Data Data Memory Memory 96x8 96x8 128x8 128x8 128x8 128x8
SSOP
RA2/AN2/VREF RA3/AN3 RA4/T0CKI MCLR VSS VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
PIC16CE62X
PIC16CE623 PIC16CE624 PIC16CE625 * * * *
Interrupt capability 16 special function hardware registers 8-level deep hardware stack Direct, Indirect and Relative addressing modes
Peripheral Features:
* 13 I/O pins with individual direction control * High current sink/source for direct LED drive * Analog comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs can be output signals * Timer0: 8-bit timer/counter with 8-bit programmable prescaler
Special Microcontroller Features (cont'd)
* 1,000,000 erase/write cycle EEPROM data memory * EEPROM data retention > 40 years * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options * Four user programmable ID locations
CMOS Technology:
* Low-power, high-speed CMOS EPROM/EEPROM technology * Fully static design * Wide operating voltage range - 3.0V to 5.5V * Commercial, industrial and extended temperature range * Low power consumption - < 2.0 mA @ 5.0V, 4.0 MHz - 15 A typical @ 3.0V, 32 kHz - < 1.0 A typical standby current @ 3.0V
Special Microcontroller Features:
* In-Circuit Serial Programming (ICSPTM) (via two pins) * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 1
PIC16CE62X
Table of Contents
1.0 General Description..................................................................................................................................................................... 3 2.0 PIC16CE62X Device Varieties .................................................................................................................................................... 5 3.0 Architectural Overview ................................................................................................................................................................ 7 4.0 Memory Organization ................................................................................................................................................................ 11 5.0 I/O Ports .................................................................................................................................................................................... 23 6.0 EEPROM Peripheral Operation................................................................................................................................................. 29 7.0 Timer0 Module .......................................................................................................................................................................... 35 8.0 Comparator Module................................................................................................................................................................... 41 9.0 Voltage Reference Module........................................................................................................................................................ 47 10.0 Special Features of the CPU..................................................................................................................................................... 49 11.0 Instruction Set Summary ........................................................................................................................................................... 65 12.0 Development Support................................................................................................................................................................ 77 13.0 Electrical Specifications............................................................................................................................................................. 81 14.0 Packaging Information............................................................................................................................................................... 93 Appendix A: Code for Accessing EEPROM Data Memory ............................................................................................................. 99 Index .................................................................................................................................................................................................. 101 PIC16CE62X Product Identification System ...................................................................................................................................... 105
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted to a new publishing software package which we believe will enhance our entire documentation process and product. As in any conversion process, information may have accidently been altered or deleted. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error from the previous version of this data sheet (PIC16CE62X Data Sheet, Literature Number DS40182A), please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS40182A-page 2
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
1.0 GENERAL DESCRIPTION
The PIC16CE62X are 18 and 20 Pin EPROM-based members of the versatile PICmicroTM family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with EEPROM data memory. All PICmicroTM microcontrollers employ an advanced RISC architecture. The PIC16CE62X have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CE62X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16CE623 and PIC16CE624 have 96 bytes of RAM. The PIC16CE625 has 128 bytes of RAM. Each microcontroller contains a 128x8 EEPROM memory array for storing non-volatile information such as calibration data or security codes. This memory has an endurance of 1,000,000 erase/write cycles and a retention of 40 plus years. Each device has 13 I/O pins and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, the PIC16CE62X adds two analog comparators with a programmable on-chip voltage reference module. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc). PIC16CE62X devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power savings. The user can wake up the chip from SLEEP through several external and internal interrupts and reset. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock- up. A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume. Table 1-1 shows the features of the PIC16CE62X mid-range microcontroller families. A simplified block diagram of the PIC16CE62X is shown in Figure 3-1. The PIC16CE62X series fit perfectly in applications ranging from multi-pocket battery chargers to low-power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high-performance, ease of use and I/O flexibility make the PIC16CE62X very versatile.
1.1
Development Support
The PIC16CE62X family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A "C" compiler and fuzzy logic support tools are also available.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 3
PIC16CE62X
TABLE 1-1: PIC16CE62X FAMILY OF DEVICES
PIC16CE623 Clock Maximum Frequency of Operation (MHz) EPROM Program Memory (x14 words) Data Memory (bytes) EEPROM Data Memory (bytes) Timer Module(s) Peripherals Comparators(s) Internal Reference Voltage Interrupt Sources I/O Pins Voltage Range (Volts) Features Brown-out Reset Packages 20 512 20 1K
PIC16CE624 20 2K
PIC16CE625
Memory
96 128 TMR0 2 Yes 4 13 3.0-5.5 Yes 18-pin DIP, SOIC; 20-pin SSOP
96 128 TMR0 2 Yes 4 13 3.0-5.5 Yes 18-pin DIP, SOIC; 20-pin SSOP
128 128 TMR0 2 Yes 4 13 3.0-5.5 Yes 18-pin DIP, SOIC; 20-pin SSOP
All PICmicroTM Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CE62X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40182A-page 4
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
2.0 PIC16CE62X DEVICE VARIETIES
2.3 Quick-Turn-Programming (QTP) Devices
A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the PIC16CE62X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. Microchip's PICSTART(R) and PRO MATE(R) programmers both support programming of the PIC16CE62X.
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who chose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.
2.4
Serialized Quick-Turn-Programming (SQTPSM) Devices
2.2
One-Time-Programmable (OTP) Devices
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 5
PIC16CE62X
NOTES:
DS40182A-page 6
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CE62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CE62X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a single-cycle (200 ns @ 20 MHz) except for program branches. The PIC16CE623 addresses 512 x 14 on-chip program memory. The PIC16CE624 addresses 1K x 14 program memory. The PIC16CE625 addresses 2K x 14 program memory. All program memory is internal. The PIC16CE62X can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16CE62X have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CE62X simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16CE62X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, bit in subtraction. See the SUBLW and SUBWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 7
PIC16CE62X
FIGURE 3-1: BLOCK DIAGRAM
Data Memory (RAM) 96 X 8 96 X 8 128 X 8 EEPROM DATA MEMORY 128 X 8 128 X 8 128 X 8
Device PIC16CE623 PIC16CE624 PIC16CE625
Program Memory 512 X 14 1K X14 2K X 14
13 Program Counter EPROM Program Memory Program Bus 8 Level Stack (13-bit)
Data Bus
8
Voltage Reference
RAM File Registers RAM Addr (1) 9 Comparator RA0/AN0 Indirect Addr
+
14 Instruction reg Direct Addr 7
Addr MUX 8
RA1/AN1 RA2/AN2/VREF RA3/AN3
FSR reg STATUS reg
+
TMR0 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset ALU MUX RA4/T0CKI
W reg
I/O Ports
PORTB
MCLR
VDD, VSS
SCL SDA VDD EEINTF EEPROM Data Memory 128x8
Note 1: Higher order bits are from the STATUS register.
DS40182A-page 8
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
TABLE 3-1:
Name
OSC1/CLKIN OSC2/CLKOUT
PIC16CE62X PINOUT DESCRIPTION
DIP/ SOIC Pin # 16 15 SSOP Pin # 18 17 I/O/P Type I O Buffer Type
Description
ST/CMOS Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. Analog comparator input Analog comparator input Analog comparator input or VREF output Analog comparator input /output Can be selected to be the clock input to the Timer0 timer/counter or a comparator output. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
MCLR/VPP
4
4
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI
17 18 1 2 3
19 20 1 2 3
I/O I/O I/O I/O I/O
ST ST ST ST ST
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VDD
6 7 8 9 10 11 12 13 5 14
7 8 9 10 11 12 13 14 5,6 15,16
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST(1)
TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) -- --
RB0/INT can also be selected as an external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = input/output P = power -- = Not used I = Input ST = Schmitt Trigger input TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Legend:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 9
PIC16CE62X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register (IR)" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC
PC PC+1 PC+2 Internal phase clock
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC2/CLKOUT (RC mode)
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTA, BIT3
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS40182A-page 10
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 4-2:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16CE624
PC<12:0>
The PIC16CE62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16CE623, 1K x 14 (0000h - 03FFh) for the PIC16CE624 and 2K x 14 (0000h - 07FFh) for the PIC16CE625 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 14 space (PIC16CE623) or 1K x 14 space (PIC16CE624) or 2K x 14 space (PIC16CE625). The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3).
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 000h
FIGURE 4-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16CE623
PC<12:0>
Interrupt Vector
0004 0005
CALL, RETURN RETFIE, RETLW
13
On-chip Program Memory 03FFh 0400h
Stack Level 1 Stack Level 2
1FFFh Stack Level 8 Reset Vector
FIGURE 4-3:
000h
PROGRAM MEMORY MAP AND STACK FOR THE PIC16CE625
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Interrupt Vector
0004 0005
Stack Level 1 Stack Level 2 Stack Level 8
On-chip Program Memory 01FFh 0200h
Reset Vector
000h
1FFFh Interrupt Vector 0004 0005
On-chip Program Memory 07FFh 0800h
1FFFh
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 11
PIC16CE62X
4.2 Data Memory Organization
4.2.1 GENERAL PURPOSE REGISTER FILE The data memory (Figure 4-4 and Figure 4-5) is partitioned into two Banks which contain the general purpose registers and the special function registers. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-7Fh (Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0) and A0-BFh (Bank1) on the PIC16CE625 are general purpose registers implemented as static RAM. Some special purpose registers are mapped in Bank 1. In all three microcontrollers, address space F0h-FFh is mapped to 70-7Fh. The register file is organized as 96 x 8 in the PIC16CE623/624 and 128 x 8 in the PIC16CE625. Each is accessed either directly or indirectly through the File Select Register FSR (Section 4.4).
DS40182A-page 12
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
FIGURE 4-4:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB
DATA MEMORY MAP FOR THE PIC16CE623/624
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register EFh F0h FFh Bank 0 Bank 1
FIGURE 4-5:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
DATA MEMORY MAP FOR THE PIC16CE625
File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
PCLATH INTCON PIR1
PCLATH INTCON PIE1 PCON EEINTF
PCLATH INTCON PIR1
PCLATH INTCON PIE1 PCON EEINTF
CMCON
VRCON
CMCON General Purpose Register
VRCON General Purpose Register
BFh C0h
Accesses 70h-7Fh 7Fh
Accesses 70h-7Fh 7Fh Bank 0 Bank 1
F0h FFh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 13
PIC16CE62X
4.2.2 SPECIAL FUNCTION REGISTERS The special function registers are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The special function registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 4-1:
Address Name Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch INDF TMR0 PCL STATUS FSR PORTA PORTB
SPECIAL REGISTERS FOR THE PIC16CE62X
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Value on all other resets(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP(2) RP1(2) RP0 TO PD Z DC C
xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
xxxx xxxx uuuu uuuu 0000 0000 000q quuu uuuu uuuu ---u 0000 uuuu uuuu -- -- -- ---0 0000 0000 000x -0-- ----- 00-- 0000
Indirect data memory address pointer -- RB7 -- RB6 -- RB5 RA4 RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0
---x 0000 xxxx xxxx -- -- --
Unimplemented Unimplemented Unimplemented PCLATH INTCON PIR1 -- GIE -- -- PEIE CMIF -- T0IE -- Write buffer for upper 5 bits of program counter INTE -- RBIE -- T0IF -- INTF -- RBIF --
---0 0000 0000 000x -0-- -----
0Dh-1Eh Unimplemented 1Fh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh-9Eh 90h 9Fh INDF OPTION PCL STATUS FSR TRISA TRISB Unimplemented Unimplemented Unimplemented PCLATH INTCON PIE1 Unimplemented PCON Unimplemented EEINTF VRCON -- VREN -- VROE -- VRR -- -- -- VR3 EESCL VR2 EESDA VR1 EEVDD VR0 -- -- -- -- -- -- POR BOR -- GIE -- -- PEIE CMIE -- T0IE -- Write buffer for upper 5 bits of program counter INTE -- RBIE -- T0IF -- INTF -- RBIF -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 CMCON C2OUT C1OUT -- -- CIS CM2 CM1 CM0
00-- 0000
xxxx xxxx 1111 1111 0000 0000
xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu ---1 1111 1111 1111 -- -- -- ---0 0000 0000 000x -0-- ----- ---- --uq -- uuuu u111 000- 0000
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx xxxx xxxx
Indirect data memory address pointer -- TRISB7 -- TRISB6 -- TRISB5 TRISA4 TRISB4 TRISA3 TRISB3 TRISA2 TRISB2 TRISA1 TRISB1 TRISA0 TRISB0
---1 1111 1111 1111 -- -- -- ---0 0000 0000 000x -0-- ----- ---- --0x -- uuuu u111 000- 0000
Legend: -- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation. Note 2: IRP & RPI bits are reserved, always maintain these bits clear.
DS40182A-page 14
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-6, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the status register as 000uu1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the "Instruction Set Summary". Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16CE62X and should be programmed as '0'. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
Note 2:
FIGURE 4-6:
STATUS REGISTER (ADDRESS 03H OR 83H)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset -x = Unknown at POR reset
Reserved Reserved
IRP RP1
bit7
bit 7:
IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear.
bit 6:5 RP1: RPO: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 15
PIC16CE62X
4.2.2.2 OPTION REGISTER The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB. Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1).
FIGURE 4-7:
R/W-1 RBPU bit7
OPTION REGISTER (ADDRESS 81H)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0 R = Readable bit W = Writable bit - n = Value at POR reset
R/W-1 INTEDG
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS40182A-page 16
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 and Section 4.2.2.5 for a description of the comparator enable and flag bits. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
FIGURE 4-8:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset -x = Unknown at POR reset
R/W-0 PEIE
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 17
PIC16CE62X
4.2.2.4 PIE1 REGISTER This register contains the individual enable bit for the comparator interrupt.
FIGURE 4-9:
U-0 -- bit7
PIE1 REGISTER (ADDRESS 8CH)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
R/W-0 CMIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as '0' CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt
bit 5-0: Unimplemented: Read as '0'
4.2.2.5
PIR1 REGISTER
This register contains the individual flag bit for the comparator interrupt. Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 4-10: PIR1 REGISTER (ADDRESS 0CH)
U-0 -- bit7 R/W-0 CMIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as '0' CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed
bit 5-0: Unimplemented: Read as '0'
DS40182A-page 18
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
4.2.2.6 PCON REGISTER The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR reset, WDT reset or a Brown-out Reset. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is cleared, indicating a brown-out has occurred. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BODEN bit in the Configuration word).
FIGURE 4-11: PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-0 BOR bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 19
PIC16CE62X
4.3 PCL and PCLATH
4.3.2 STACK The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-12 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16CE62X family has an 8 level deep x 13-bit wide hardware stack (Figure 4-2 and Figure 4-3). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1:
Instruction with PCL as Destination ALU result
FIGURE 4-12: LOADING OF PC IN DIFFERENT SITUATIONS
PCH 12 PC 5 PCLATH<4:0> 8 8 7 PCL 0
There are no STATUS bits to indicate stack overflow or stack underflow conditions. There are no instruction mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
Note 2:
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
DS40182A-page 20
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
4.4 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-13. However, IRP is not used in the PIC16CE62X.
EXAMPLE 4-1:
movlw movwf NEXT clrf incf btfss goto CONTINUE:
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
FIGURE 4-13: DIRECT/INDIRECT ADDRESSING PIC16CE62X
Direct Addressing
(1)RP1
Indirect Addressing
0 IRP
(1)
RP0
6
from opcode
7
FSR register
0
bank select
location select 00 00h 01 10 11
bank select 00h
location select
not used Data Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-4 and Figure 4-5. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 21
PIC16CE62X
NOTES:
DS40182A-page 22
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
5.0 I/O PORTS
Note: The PIC16CE62X parts have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. On reset, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption.
5.1
PORTA and TRISA Registers
TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs when using them as comparator inputs. The RA2 pin will also function as the output for the voltage reference. When in this mode, the VREF pin is a very high impedance output. The user must configure TRISA<2> bit as an input and use high impedance loads. In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function.
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as input or output. A '1' in the TRISA register puts the corresponding output driver in a hi- impedance mode. A '0' in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (comparator control register) register and the VRCON (voltage reference control register) register. When selected as a comparator input, these pins will read as '0's.
EXAMPLE 5-1:
CLRF PORTA
INITIALIZING PORTA
;Initialize PORTA by setting ;output data latches MOVLW 0X07 ;Turn comparators off and MOVWF CMCON ;enable pins for I/O ;functions BSF STATUS, RP0 ;Select Bank1 MOVLW 0x1F ;Value used to initialize ;data direction MOVWF TRISA ;Set RA<4:0> as inputs ;TRISA<7:5> are always ;read as '0'.
FIGURE 5-1:
Data bus WR PortA
BLOCK DIAGRAM OF RA1:RA0 PINS
Q VDD
FIGURE 5-2:
Data bus WR PortA D CK D WR TRISA
BLOCK DIAGRAM OF RA2 PIN
Q VDD Q Q N RA2 Pin Q VSS Analog Input Mode Schmitt Trigger Input Buffer Q EN D P
D CK D
Data Latch
Q Q
P
Data Latch I/O Pin
WR TRISA
N CK Q VSS Analog Input Mode TRIS Latch
CK
TRIS Latch
RD TRISA RD TRISA Schmitt Trigger Input Buffer Q EN RD PORTA D
RD PORTA
To Comparator VROE VREF Note: I/O pins have protection diodes to VDD and VSS.
To Comparator Note: I/O pins have protection diodes to VDD and VSS.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 23
PIC16CE62X
FIGURE 5-3:
Data bus WR PortA D
BLOCK DIAGRAM OF RA3 PIN
Comparator Mode = 110 Q Comparator Output VDD P
CK Q Data Latch D Q
WR TRISA
N CK Q VSS Analog Input Mode Schmitt Trigger Input Buffer Q EN D TRIS Latch
RA3 Pin
RD TRISA
RD PORTA
To Comparator
Note:
I/O pins have protection diodes to VDD and VSS
FIGURE 5-4:
Data bus WR PortA D CK
BLOCK DIAGRAM OF RA4 PIN
Comparator Mode = 110 Q Comparator Output Q Q N RA4 Pin
Data Latch D WR TRISA CK
Q VSS
TRIS Latch
RD TRISA Q EN RD PORTA
Schmitt Trigger Input Buffer D
TMR0 Clock Input
Note:
RA4 has protection diodes to VSS only
DS40182A-page 24
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
TABLE 5-1:
Name RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI
PORTA FUNCTIONS
Bit # bit0 bit1 bit2 bit3 bit4 Buffer Type ST ST ST ST ST Function Input/output or comparator input Input/output or comparator input Input/output or comparator input or VREF output Input/output or comparator input/output Input/output or external clock input for TMR0 or comparator output. Output is open drain type.
Legend: ST = Schmitt Trigger input
TABLE 5-2:
Address Name 05h 85h 1Fh 9Fh PORTA TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- C2OUT VREN Bit 6 -- -- C1OUT VROE Bit 5 -- -- -- VRR Bit 4 RA4 TRISA4 -- -- Bit 3 RA3 TRISA3 CIS VR3 Bit 2 RA2 TRISA2 CM2 VR2 Bit 1 RA1 TRISA1 CM1 VR1 Bit 0 RA0 TRISA0 CM0 VR0 Value on: POR / BOR ---x 0000 ---1 1111 00-- 0000 000- 0000 Value on All Other Resets ---u 0000 ---1 1111 00-- 0000 000- 0000
CMCON VRCON
Legend: -- = Unimplemented locations, read as `0' Note: Note: Shaded bits are not used by PORTA.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 25
PIC16CE62X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. Each of the PORTB pins has a weak internal pull-up (200 A typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RBIF interrupt (flag latched in INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. (See AN552 in the Microchip Embedded Control Handbook.) Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set.
The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 5-6:
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD weak P pull-up Data Latch D Q CK D Q CK I/O pin(1)
FIGURE 5-5:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2)
Data bus WR PortB
RBPU(2)
Data bus WR PortB
WR TRISB
TTL Input Buffer
WR TRISB
CK
TTL Input Buffer
RD TRISB ST Buffer RD PortB Q EN D
RD TRISB Q RD PortB Set RBIF From other RB7:RB4 pins
Latch D RB0/INT EN ST Buffer RD Port
Q EN
D
Note 1: I/O pins have diode protection to VDD and VSS. Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>).
RD Port RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. Note 2: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>).
DS40182A-page 26
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
TABLE 5-3:
Name RB0/INT
PORTB FUNCTIONS
Bit # bit0 Buffer Type
(1)
Function
Input/output or external interrupt input. Internal software programmable TTL/ST weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 Input/output pin (with interrupt on change). Internal software TTL/ST(2) programmable weak pull-up. Serial programming clock pin. RB7 bit7 Input/output pin (with interrupt on change). Internal software TTL/ST(2) programmable weak pull-up. Serial programming data pin. Legend: ST = Schmitt Trigger, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
Address Name 06h 86h 81h PORTB TRISB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 TRISB7 RBPU Bit 6 RB6 TRISB6 INTEDG Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on: POR / BOR xxxx xxxx Value on All Other Resets uuuu uuuu 1111 1111 1111 1111
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 T0CS T0SE PSA PS2 PS1 PS0 1111 1111
OPTION
Note:
Shaded bits are not used by PORTB.
u = unchanged x = unknown
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 27
PIC16CE62X
5.3
5.3.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-2:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read modify write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-2 shows the effect of two sequential read-modify-write instructions (ex., BCF, BSF, etc.) on an I/O port. A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip.
; Initial PORT settings: PORTB<7:4> Inputs ; ; PORTB<3:0> Outputs ; PORTB<7:6> have external pull-up and are not ; connected to other circuitry ; ; PORT latch PORT pins ; ---------- ---------BCF BCF BSF BCF BCF PORTB, 7 PORTB, 6 STATUS,RP0 TRISB, 7 TRISB, 6 ; 01pp ; 10pp ; ; 10pp ; 10pp pppp pppp pppp pppp 11pp pppp 11pp pppp 11pp pppp 10pp pppp
; ; Note that the user may have expected the pin ; values to be 00pp pppp. The 2nd BCF caused ; RB7 to be latched as the pin value (High).
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-7). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing this I/O port.
FIGURE 5-7:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 PC + 1 MOVF PORTB, W Read PORTB Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note: This example shows write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.
Q1 Q2 Q3 Q4 PC Instruction fetched
RB7:RB0 RB <7:0>
PC MOVWF PORTB Write to PORTB
PC + 2 NOP
PC + 3 NOP
TPD Execute MOVWF PORTB
Port pin sampled here Execute MOVF PORTB, W Execute NOP
Therefore, at higher clock frequencies, a write followed by a read may be problematic.
DS40182A-page 28
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
6.0 EEPROM PERIPHERAL OPERATION
The code for these functions is not yet determined, but will be available on our web site (www.microchip.com) when it is completed. The code will be accessed by either including the source code FLASH62X.INC or by linking FLASH62X.ASM. 6.0.1 SERIAL DATA
The PIC16CE623/624/625 each have 128 bytes of EEPROM data memory. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit1 and bit2, respectively, of the EEINTF register (SFR 90h). In addition, the power to the EEPROM can be controlled using bit0 (EEVDD) of the EEINTF register. For most applications, all that is required is calls to the following functions:
; Byte_Write: Byte write routine ; Inputs: EEPROM Address EEADDR ; EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else return 00 in W ; ; Read_Current: Read EEPROM at address currently held by EE device. ; Inputs: NONE ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W ; ; Read_Random: Read EEPROM byte at supplied address ; Inputs: EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W
SDA is a bi-directional pin used to transfer addresses and data into and data out of the memory. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 6.0.2 SERIAL CLOCK
This SCL input is used to synchronize the data transfer from and to the memory. 6.0.3 EEINTF REGISTER
The EEINTF register (SFR 90h) controls the access to the EEPROM. Figure 6.1 details the function of each bit. User code must generate the clock and data signals.
FIGURE 6-1:
U-0 bit7
EEINFT REGISTER (ADDRESS 90h)
U-0 U-0 U-0 U-0 R/W-1 EESCL R/W-1 EESDA R/W-1 EEVDD bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-3: Unimplemented: Read as '0' bit 2: EESCL: Clock line to the EEPROM 1 = Clock high 0 = Clock low EESDA: Data line to EEPROM 1 = Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor) 0 = Data line is low EEVDD: VDD control bit for EEPROM 1 = VDD is turned on EEPROM 0 = VDD is turned off EEPROM (all pins are tri-stated and the EEPROM is powered down)
bit 1:
bit 0:
Note:
EESDA, EESCL and EEVDD will read `0' if EEVDD is turned off
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 29
PIC16CE62X
6.1 BUS CHARACTERISTICS
6.1.5 ACKNOWLEDGE In this section, the term "processor" refers to the portion of the PIC16CE62X that interfaces to the EEPROM through software manipulating the EEINTF register. The following bus protocol is to be used with the EEPROM data memory. * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted by the EEPROM as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 6-2). 6.1.1 BUS NOT BUSY (A) The EEPROM will generate an acknowledge after the reception of each byte. The processor must generate an extra clock pulse which is associated with this acknowledge bit. Note: Acknowledge bits are not generated if an internal programming cycle is in progress.
Both data and clock lines remain HIGH. 6.1.2 START DATA TRANSFER (B)
When the EEPROM acknowledges, it pulls down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. The processor must signal an end of data to the EEPROM by not generating an acknowledge bit on the last byte that has been clocked out of the EEPROM. In this case, the EEPROM must leave the data line HIGH to enable the processor to generate the STOP condition (Figure 6-3).
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 6.1.3 STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 6.1.4 DATA VALID (D)
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the processor and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first-in, first-out fashion.
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
FIGURE 6-2:
SCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(C) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
FIGURE 6-3:
ACKNOWLEDGE TIMING
Acknowledge Bit
SCL SDA
1
2
3
4
5
6
7
8
9
1
2
3
Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
6.2
Device Addressing
FIGURE 6-4:
CONTROL BYTE FORMAT
Read/Write Bit
After generating a START condition, the processor transmits a control byte consisting of a EEPROM address and a Read/Write bit that indicates what type of operation is to be performed. The EEPROM address consists of a 4-bit device code (1010) followed by three don't care bits. The last bit of the control byte determines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. (Figure 6-4). The bus is monitored for its corresponding EEPROM address all the time. It generates an acknowledge bit if the EEPROM address was true and it is not in a programming mode.
Device Select Bits
Don't Care Bits 0 X X X R/W ACK
S
1
0
1
EEPROM Address Start Bit Acknowledge Bit
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 31
PIC16CE62X
6.3
6.3.1
WRITE OPERATIONS
BYTE WRITE
6.4
ACKNOWLEDGE POLLING
Following the start signal from the processor, the device code (4 bits), the don't care bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the processor. This indicates to the EEPROM that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the processor is the word address and will be written into the address pointer of the EEPROM. After receiving another acknowledge signal from the EEPROM the processor will transmit the data word to be written into the addressed memory location. The EEPROM acknowledges again and the processor generates a stop condition. This initiates the internal write cycle, and during this time the EEPROM will not generate acknowledge signals (Figure 6-6). 6.3.2 PAGE WRITE
Since the EEPROM will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the processor, the EEPROM initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the processor sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the processor can then proceed with the next read or write command. See Figure 6-5 for flow diagram.
FIGURE 6-5:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The write control byte, word address and the first data byte are transmitted to the EEPROM in the same way as in a byte write. But instead of generating a stop condition the processor transmits up to eight data bytes to the EEPROM which are temporarily stored in the onchip page buffer and will be written into the memory after the processor has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the processor should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 6-7).
Send Stop Condition to Initiate Write Cycle
Send Start
Send Control Byte with R/W = 0
Did EEPROM Acknowledge (ACK = 0)? YES Next Operation
NO
FIGURE 6-6:
BUS ACTIVITY PROCESSOR SDA LINE
BYTE WRITE
S T A R T S 1 0 1 CONTROL BYTE WORD ADDRESS DATA S T O P P A C K A C K
0
X
X
X
0 A C K
X
X
X
X
BUS ACTIVITY X = Don't Care Bit
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
FIGURE 6-7:
BUS ACTIVITY PROCESSOR
PAGE WRITE
S T A R T CONTROL BYTE WORD ADDRESS (n) S T O P
DATA n
DATAn + 1
DATAn + 7
SDA LINE
S
A C K A C K A C K A C K A C K
P
BUS ACTIVITY
6.5
READ OPERATION
6.8
Sequential Read
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the EEPROM address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.
6.6
Current Address Read
Sequential reads are initiated in the same way as a random read except that after the EEPROM transmits the first data byte, the processor issues an acknowledge as opposed to a stop condition in a random read. This directs the EEPROM to transmit the next sequentially addressed 8-bit word (Figure 6-10). To provide sequential reads the EEPROM contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.
The EEPROM contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the EEPROM address with R/W bit set to one, the EEPROM issues an acknowledge and transmits the eight bit data word. The processor will not acknowledge the transfer but does generate a stop condition and the EEPROM discontinues transmission (Figure 6-8).
6.9
Noise Protection
The EEPROM employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
6.7
Random Read
Random read operations allow the processor to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the EEPROM as part of a write operation. After the word address is sent, the processor generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the processor issues the control byte again but with the R/W bit set to a one. The EEPROM will then issue an acknowledge and transmits the eight bit data word. The processor will not acknowledge the transfer but does generate a stop condition and the EEPROM discontinues transmission (Figure 6-9).
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 33
PIC16CE62X
FIGURE 6-8: CURRENT ADDRESS READ
S T A R T CONTROL BYTE S T O P
BUS ACTIVITY PROCESSOR
DATA n
SDA LINE
S
A C K N O A C K
P
BUS ACTIVITY
FIGURE 6-9:
RANDOM READ
S T T CONTROL BYTE WORD ADDRESS (n) S T A R T CONTROL BYTE S T O P
BUS ACTIVITY A PROCESSOR R
SDA LINE
DATA n
S
A C K A C K
S
A C K N O A C K
P
BUS ACTIVITY
FIGURE 6-10: SEQUENTIAL READ
BUS ACTIVITY PROCESSOR
SDA LINE
CONTROL BYTE
A C K
A C K
A C K
S T O P
P
A C K DATA n DATA n + 1 DATA n + 2 DATA n + X N O A C K
BUS ACTIVITY
DS40182A-page 34
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
7.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The prescaler is shared between the Timer0 module and the WatchdogTimer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler.
Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the TMR0 will increment every instruction cycle (without prescaler). If Timer0 is written, the increment is inhibited for the following two cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to TMR0. Counter mode is selected by setting the T0CS bit. In this mode Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge (T0SE) control
7.1
TIMER0 Interrupt
Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. See Figure 7-4 for Timer0 interrupt timing.
FIGURE 7-1:
RA4/T0CKI pin
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler 0 PSout Sync with Internal clocks (2 cycle delay) Set Flag bit T0IF on Overflow TMR0 PSout 8
T0SE PS2:PS0 T0CS Note 1: 2: PSA
Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register. The prescaler is shared with Watchdog Timer (Figure 7-6)
FIGURE 7-2:
PC (Program Counter) Instruction Fetch
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
TMR0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 35
PIC16CE62X
FIGURE 7-3:
PC (Program Counter) Instruction Fetch TMR0 T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
T0+1
NT0
NT0+1
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 7-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) TMR0 timer T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Interrupt Latency Time
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 4TCY, where TCY = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.
DS40182A-page 36
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
7.2 Using Timer0 with External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 7.2.2 TIMER0 INCREMENT DELAY
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the TMR0 is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 7-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler output (2)
(1) (3)
External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 37
PIC16CE62X
7.3 Prescaler
The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.
FIGURE 7-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8-to-1MUX PS0 - PS2
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
DS40182A-page 38
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 7-1) must be executed when changing the prescaler assignment from Timer0 to WDT. To change prescaler from the WDT to the TMR0 module use the sequence shown in Example 7-2. This precaution must be taken even if the WDT is disabled.
EXAMPLE 7-2:
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler
CLRWDT
EXAMPLE 7-1:
1.BCF
CHANGING PRESCALER (TIMER0WDT)
BSF MOVLW
STATUS, RP0 b'xxxx0xxx'
STATUS, RP0 ;Skip if already in ; Bank 0 2.CLRWDT ;Clear WDT 3.CLRF TMR0 ;Clear TMR0 & Prescaler 4.BSF STATUS, RP0 ;Bank 1 5.MOVLW '00101111'b; ;These 3 lines (5, 6, 7) 6.MOVWF OPTION ; are required only if ; desired PS<2:0> are 7.CLRWDT ; 000 or 001 8.MOVLW '00101xxx'b ;Set Postscaler to 9.MOVWF OPTION ; desired WDT rate 10.BCF STATUS, RP0 ;Return to Bank 0
;Select TMR0, new ;prescale value and ;clock source
MOVWF BCF
OPTION_REG STATUS, RP0
TABLE 7-1:
Address 01h 0Bh/8Bh 81h 85h Name TMR0
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR / BOR Value on All Other Resets
Timer0 module register GIE RBPU -- PEIE INTEDG -- T0IE T0CS -- INTE T0SE TRISA4 RBIE PSA TRISA3 T0IF PS2 TRISA2 INTF PS1 TRISA1 RBIF PS0 TRISA0
xxxx xxxx uuuu uuuu 0000 000x 0000 000x 1111 1111 1111 1111 ---1 1111 ---1 1111
INTCON OPTION TRISA
Legend: -- = Unimplemented locations, read as `0'. Note: Shaded bits are not used by TMR0 module.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 39
PIC16CE62X
NOTES:
DS40182A-page 40
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
8.0 COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The on-chip Voltage Reference (Section 9.0) can also be an input to the comparators. The CMCON register, shown in Figure 8-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 8-2.
FIGURE 8-1:
R-0 C2OUT bit7
CMCON REGISTER (ADDRESS 1Fh)
U-0 U-0 R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit0
R-0 C1OUT
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
C2OUT: Comparator 2 output 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- C1OUT: Comparator 1 output 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- CIS: Comparator Input Switch When CM<2:0>: = 001: 1 = C1 VIN- connects to RA3 0 = C1 VIN- connects to RA0 When CM<2:0> = 010: 1 = C1 VIN- connects to RA3 C2 VIN- connects to RA2 0 = C1 VIN- connects to RA0 C2 VIN- connects to RA1
bit 6:
bit 5-4: Unimplemented: Read as '0' bit 3:
bit 2-0: CM<2:0>: Comparator mode Figure 8-2.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 41
PIC16CE62X
8.1 Comparator Configuration
There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 8-2 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 13-2. Note: Comparator interrupts should be disabled during a comparator mode change otherwise a false interrupt may occur.
FIGURE 8-2:
A A A A
COMPARATOR I/O OPERATING MODES
VINVIN+
RA0/AN0 RA3/AN3 RA1/AN1 RA2/AN2
+ + C2 C1
Off (Read as '0')
RA0/AN0 RA3/AN3 RA1/AN1 RA2/AN2
D D D D
VINVIN+
+ + C2 C1
Off (Read as '0')
VINVIN+
Off (Read as '0') CM<2:0> = 000
VINVIN+
Off (Read as '0') CM<2:0> = 111
Comparators Reset A A A A
VINVIN+
Comparators Off + + C2 C2OUT CM<2:0> = 100 C1 C1OUT RA0/AN0 A RA3/AN3 A RA1/AN1 A RA2/AN2 A CIS=0 VINCIS=1 VIN+ CIS=0 VINCIS=1 VIN+
RA0/AN0 RA3/AN3 RA1/AN1 RA2/AN2
+ + C2 C2OUT C1 C1OUT
VINVIN+
From VREF Module Four Inputs Multiplexed to Two Comparators RA0/AN0 RA3/AN3 RA1/AN1 A D A A
VINVIN+
Two Independent Comparators
CM<2:0> = 010 + C2 C2OUT C1 C1OUT
RA0/AN0 RA3/AN3 RA1/AN1 RA2/AN2
A D A A
VINVIN+
+ + C2 C2OUT CM<2:0> = 011 C1 C1OUT
VINVIN+
VINVIN+
+ RA2/AN2 RA4 Open Drain
Two Common Reference Comparators A A
CM<2:0> = 110 Two Common Rference Comparators with Outputs
RA0/AN0 RA3/AN3 RA1/AN1 RA2/AN2
D D A A
VINVIN+
+ + C2 C1
Off (Read as '0')
RA0/AN0 RA3/AN3
CIS=0 VINCIS=1 VIN+
+
C1
C1OUT
VINVIN+
C2OUT CM<2:0> = 101
RA1/AN1 RA2/AN2
A A
VINVIN+
+ C2 C2OUT CM<2:0> = 001
One Independent Comparator A = Analog Input, Port Reads Zeros Always D = Digital Input CIS = CMCON<3>, Comparator Input Switch
DS40182A-page 42
Three Inputs Multiplexed to Two Comparators
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
The code example in Example 8-1 depicts the steps required to configure the comparator module. RA3 and RA4 are configured as digital output. RA0 and RA1 are configured as the V- inputs and RA2 as the V+ input to both comparators.
8.3
Comparator Reference
EXAMPLE 8-1:
FLAG_REG CLRF CLRF MOVF ANDLW IORWF MOVLW MOVWF BSF MOVLW MOVWF
INITIALIZING COMPARATOR MODULE
An external or internal reference signal may be used depending on the comparator operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 8-3).
FIGURE 8-3:
SINGLE COMPARATOR
BCF CALL MOVF BCF BSF BSF BCF BSF BSF
0X20 ;Init flag register ;Init PORTA ;Move comparator contents to W ;Mask comparator bits ;Store bits in flag register ;Init comparator mode ;CM<2:0> = 011 ;Select Bank1 ;Initialize data direction ;Set RA<2:0> as inputs ;RA<4:3> as outputs ;TRISA<7:5> always read `0' STATUS,RP0 ;Select Bank 0 DELAY 10 ;10s delay CMCON,F ;Read CMCON to end change condition PIR1,CMIF ;Clear pending interrupts STATUS,RP0 ;Select Bank 1 PIE1,CMIE ;Enable comparator interrupts STATUS,RP0 ;Select Bank 0 INTCON,PEIE ;Enable peripheral interrupts INTCON,GIE ;Global interrupt enable
EQU FLAG_REG PORTA CMCON,W 0xC0 FLAG_REG,F 0x03 CMCON STATUS,RP0 0x07 TRISA
VIN+ VIN-
+ -
Output
VIN- VIN+
Output
8.2
Comparator Operation
8.3.1
EXTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 8-3 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 8-3 represent the uncertainty due to input offsets and response time.
When external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator(s). 8.3.2 INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 13, Instruction Sets, contains a detailed description of the Voltage Reference Module that provides this signal. The internal reference signal is used when the comparators are in mode CM<2:0>=010 (Figure 8-2). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 43
PIC16CE62X
8.4 Comparator Response Time 8.5 Comparator Outputs
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is guaranteed to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise the maximum delay of the comparators should be used (Table 13-2 ). The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110, multiplexors in the output path of the RA3 and RA4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 8-4 shows the comparator output block diagram. The TRISA bits will still function as an output enable/disable for the RA3 and RA4 pins while in this mode. Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified.
FIGURE 8-4:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX + To RA3 or RA4 Pin Bus Data RD CMCON Q D EN -
Set CMIF Bit
Q From Other Comparator
D EN CL RD CMCON NRESET
DS40182A-page 44
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
8.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit, PIR1<6>, is the comparator interrupt flag. The CMIF bit must be reset by clearing `0'. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE1<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR1<6>) interrupt flag may not get set. wake up the device from SLEEP mode when enabled. While the comparator is powered-up, higher sleep currents than shown in the power down current specification will occur. Each comparator that is operational will consume additional current as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering sleep. If the device wakes-up from sleep, the contents of the CMCON register are not affected.
8.8
Effects of a RESET
A device reset forces the CMCON register to its reset state. This forces the comparator module to be in the comparator reset mode, CM2:CM0 = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at reset time. The comparators will be powered-down during the reset interval.
8.9
The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON. This will end the mismatch condition. Clear flag bit CMIF.
Analog Input Connection Considerations
A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared.
8.7
Comparator Operation During SLEEP
When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will
A simplified circuit for an analog input is shown in Figure 8-5. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
FIGURE 8-5:
ANALOG INPUT MODEL
VDD RS AIN VT = 0.6V RIC < 10K
VA
CPIN 5 pF
VT = 0.6V
ILEAKAGE 500 nA
VSS Legend CPIN VT ILEAKAGE RIC RS VA = Input Capacitance = Threshold Voltage = Leakage Current At The Pin Due To Various Junctions = Interconnect Resistance = Source Impedance = Analog Voltage
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 45
PIC16CE62X
TABLE 8-1:
Address 1Fh 9Fh 0Bh 0Ch 8Ch 85h Name CMCON VRCON INTCON PIR1 PIE1 TRISA
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 C2OUT VREN GIE -- -- -- Bit 6 C1OUT VROE PEIE CMIF CMIE -- Bit 5 -- VRR T0IE -- -- -- Bit 4 -- -- INTE -- -- Bit 3 CIS VR3 RBIE -- -- Bit 2 CM2 VR2 T0IF -- -- Bit 1 CM1 VR1 INTF -- -- Bit 0 CM0 VR0 RBIF -- -- Value on POR / BOR Value on All Other Resets
00-- 0000 00-- 0000 000- 0000 000- 0000 0000 000x 0000 000x -0-- ---- -0-- ----0-- ---- -0-- ----
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Note:
x = Unknown - = Unimplemented, read as "0"
DS40182A-page 46
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
9.0 VOLTAGE REFERENCE MODULE
9.1 Configuring the Voltage Reference
The Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Voltage Reference are as follows: if VRR = 1: VREF = (VR<3:0>/24) x VDD if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD The setting time of the Voltage Reference must be considered when changing the VREF output (Table 13-2). Example 9-1 shows an example of how to configure the Voltage Reference for an output voltage of 1.25V with VDD = 5.0V.
The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference is not being used. The VRCON register controls the operation of the reference as shown in Figure 9-1. The block diagram is given in Figure 9-2.
FIGURE 9-1:
R/W-0 VREN bit7
VRCON REGISTER(ADDRESS 9Fh)
R/W-0 VRR U-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit0
R/W-0 VROE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
VREN: VREF Enable 1 = VREF circuit powered on 0 = VREF circuit powered down, no IDD drain VROE: VREF Output Enable 1 = VREF is output on RA2 pin 0 = VREF is disconnected from RA2 pin VRR: VREF Range selection 1 = Low Range 0 = High Range Unimplemented: Read as '0'
bit 6:
bit 5:
bit 4:
bit 3-0: VR<3:0>: VREF value selection 0 VR [3:0] 15 when VRR = 1: VREF = (VR<3:0>/ 24) * VDD when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
FIGURE 9-2:
VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
8R
R
R
R
R
8R
VRR
VR3 VREF 16-1 Analog Mux VR0 (From VRCON<3:0>)
Note:
R is defined in Table 13-3.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 47
PIC16CE62X
EXAMPLE 9-1:
MOVLW MOVWF BSF MOVLW MOVWF MOVLW MOVWF BCF CALL 0x02 CMCON STATUS,RP0 0x07 TRISA 0xA6 VRCON STATUS,RP0 DELAY10
VOLTAGE REFERENCE CONFIGURATION
; 4 Inputs Muxed ; to 2 comps. ; go to Bank 1 ; RA3-RA0 are ; outputs ; enable VREF ; low range ; set VR<3:0>=6 ; go to Bank 0 ; 10s delay
9.4
Effects of a Reset
A device reset disables the Voltage Reference by clearing bit VREN (VRCON<7>). This reset also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). The VREF value select bits, VRCON<3:0>, are also cleared.
9.5
Connection Considerations
9.2
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 9-2) keep VREF from approaching VSS or VDD. The Voltage Reference is VDD derived and therefore, the VREF output changes with fluctuations in VDD. The absolute accuracy of the Voltage Reference can be found in Table 13-3.
The Voltage Reference Module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and the VROE bit, VRCON<6>, is set. Enabling the Voltage Reference output onto the RA2 pin with an input signal present will increase current consumption. Connecting RA2 as a digital output with VREF enabled will also increase current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited drive capability, a buffer must be used in conjunction with the Voltage Reference output for external connections to VREF. Figure 9-3 shows an example buffering technique.
9.3
Operation During Sleep
When the device wakes up from sleep through an interrupt or a Watchdog Timer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the Voltage Reference should be disabled.
FIGURE 9-3:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
VREF
Module
R(1)
RA2
*
Voltage Reference Output Impedance
+ -
*
VREF Output
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 9-1:
Address 9Fh 1Fh 85h Name
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Bit 7 VREN C2OUT -- Bit 6 VROE C1OUT -- Bit 5 VRR -- -- Bit 4 -- -- TRISA4 Bit 3 VR3 CIS TRISA3 Bit 2 VR2 CM2 TRISA2 Bit 1 VR1 CM1 TRISA1 Bit 0 VR0 CM0 TRISA0 Value On POR / BOR 000- 0000 00-- 0000 ---1 1111 Value On All Other Resets 000- 0000 00-- 0000 ---1 1111
VRCON CMCON TRISA
Note:
- = Unimplemented, read as "0"
DS40182A-page 48
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
10.0 SPECIAL FEATURES OF THE CPU
The PIC16CE62X has a Watchdog Timer which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Ttimer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs which provides at least a 72 ms reset. With these three functions on-chip, most applications need no external reset circuitry. The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16CE62X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. 2. OSC selection Reset Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-Up Timer (OST) Brown-out Reset (BOR) Interrupts Watchdog Timer (WDT) SLEEP Code protection ID Locations In-circuit serial programming
3. 4. 5. 6. 7. 8.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 49
PIC16CE62X
10.1 Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h - 3FFFh), which can be accessed only during programming.
FIGURE 10-1: CONFIGURATION WORD
CP1 CP0(2) CP1 CP0(2) CP1 CP0(2) -- BODE(1) CP1 CP0(2) PWRTE(1) WDTE F0SC1 F0SC0
bit13
bit0
CONFIG Address REGISTER: 2007h
bit 13-8 5-4:
CP1:CP0 Pairs: Code protection bits(2)
Code protection for 2K program memory 11 = Program memory code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected Code protection for 1K program memory 11 = Program memory code protection off 10 =Program memory code protection on 01 = 0200h-03FFh code protected 00 = 0000h-03FFh code protected Code protection for 0.5K program memory 11 = Program memory code protection off 10 = Program memory code protection of 01 = Program memory code protection of 00 = 0000h-01FFh code protected Unimplemented: Read as '1' BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 7: bit 6:
bit 3:
bit 2:
bit 1-0:
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS40182A-page 50
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
10.2
10.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 10-1:
Ranges Tested: Mode XT
CERAMIC RESONATORS, PIC16CE62X
The PIC16CE62X can be operated in four different oscillator options. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
HS
These values are for design guidance only. See notes at bottom of page.
10.2.2
Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5%
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 10-2). The PIC16CE62X) oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (Figure 10-3).
All resonators used did not have built-in capacitors.
TABLE 10-2:
FIGURE 10-2: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)
OSC1 C1 XTAL OSC2 RS C2 see Note To internal logic
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR, PIC16CE62X
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
Osc Type LP XT
RF
SLEEP
HS
PIC16CE62X
4 MHz 8 MHz 20 MHz
See Table 10-1 and Table 10-2 for recommended values of C1 and C2. Note: A series resistor may be required for AT strip cut crystals.
These values are for design guidance only. See notes at bottom of page. Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
FIGURE 10-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
Clock from ext. system Open
OSC1 PIC16CE62X OSC2
1. 2. 3.
Recommended values of C1 and C2 are identical to the ranges tested table. Higher capacitance increases the stability of oscillator but also increases the start-up time. Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification.
4.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 51
PIC16CE62X
10.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 10.2.4 RC OSCILLATOR For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 10-6 shows how the R/C combination is connected to the PIC16CE62X. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See Section 14.0 for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). See Section 14.0 for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (Figure 3-2 for waveform).
Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 10-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180 phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This could be used for external oscillator designs.
FIGURE 10-4: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
+5V To other Devices 10k 4.7k 74AS04 74AS04 PIC16CE62X CLKIN
10k XTAL 10k 20 pF 20 pF
Figure 10-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180 phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 10-6: RC OSCILLATOR MODE
VDD PIC16CE62X Rext OSC1 Internal Clock Cext
FIGURE 10-5: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
To other Devices 74AS04 PIC16CE62X CLKIN 0.1 F
330 74AS04
330 74AS04
VDD Fosc/4 OSC2/CLKOUT
XTAL
DS40182A-page 52
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
10.3 Reset
The PIC16CE62X differentiates between various kinds of reset: a) b) c) d) e) f) Power-on reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT reset (normal operation) WDT wake-up (SLEEP) Brown-out Reset (BOR) state" on Power-on reset, on MCLR or WDT reset and on MCLR reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different reset situations as indicated in Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 10-7. The MCLR reset path has a noise filter to detect and ignore small pulses. See Table 13-6 for pulse width specification.
Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset
FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset MCLR/ VPP Pin WDT Module VDD rise detect VDD Brown-out Reset OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin On-chip(1) RC OSC R Q Chip_Reset Power-on Reset S
SLEEP WDT Time-out Reset
BODEN
PWRT 10-bit Ripple-counter
Enable PWRT Enable OST
See Table 10-3 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 53
PIC16CE62X
10.4 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR)
POWER-ON RESET (POR) disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should always be enabled when Brown-out Reset is enabled. The Power-Up Time delay will vary from chip to chip and due to VDD, temperature and process variation. See DC parameters for details. 10.4.3 OSCILLATOR START-UP TIMER (OST)
10.4.1
The on-chip POR circuit holds the chip in reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details. The POR circuit does not produce internal reset when VDD declines. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607 "Power-up Trouble Shooting". 10.4.2 POWER-UP TIMER (PWRT)
The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on power-on reset or wake-up from SLEEP. 10.4.4 BROWN-OUT RESET (BOR)
The Power-up Timer provides a fixed 72 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can
The PIC16CE62X members have on-chip Brown-out Reset circuitry. A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (refer to BVDD parameter D005) for greater than parameter (TBOR) in Table 13-6, the brown-out situation will reset the chip. A reset is not guaranteed to occur if VDD falls below 4.0V for less than parameter (TBOR). The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will now be invoked and will keep the chip in reset an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-Up Timer will execute a 72 ms reset. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 10-8 shows typical Brown-out situations.
FIGURE 10-8: BROWN-OUT SITUATIONS
VDD
BVDD
Internal Reset VDD
72 ms
BVDD
Internal Reset
<72 ms
72 ms
VDD
BVDD
Internal Reset
72 ms
DS40182A-page 54
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
10.4.5 TIME-OUT SEQUENCE 10.4.6 On power-up the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in RC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 10-9, Figure 10-10 and Figure 10-11 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 10-10). This is useful for testing purposes or to synchronize more than one PICmicro device operating in parallel. Table 10-5 shows the reset conditions for some special registers, while Table 10-6 shows the reset conditions for all the registers. POWER CONTROL (PCON)/STATUS REGISTER
The power control/status register, PCON (address 8Eh) has two bits. Bit0 is BO (Brown-out). BO is unknown on power-on-reset. It must then be set by the user and checked on subsequent resets to see if BO = 0 indicating that a brown-out has occurred. The BO status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by setting BODEN bit = 0 in the Configuration word). Bit1 is POR (Power-on-reset). It is a `0' on power-on-reset and unaffected otherwise. The user must write a `1' to this bit following a power-on-reset. On a subsequent reset if POR is `0', it will indicate that a power-on-reset must have occurred (VDD may have gone too low).
TABLE 10-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out Reset PWRTE = 0 PWRTE = 1 1024 TOSC -- 72 ms + 1024 TOSC 72 ms 72 ms + 1024 TOSC 72 ms Wake-up from SLEEP 1024 TOSC --
Oscillator Configuration XT, HS, LP RC
TABLE 10-4:
POR
STATUS/PCON BITS AND THEIR SIGNIFICANCE
TO PD
BOR
0 0 0 1 1 1 1 1
X X X 0 1 1 1 1
1 0 X X 0 0 u 1
1 X 0 X 1 0 u 0
Power-on-reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR reset during normal operation MCLR reset during SLEEP
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 55
PIC16CE62X
TABLE 10-5:
Condition Power-on Reset MCLR reset during normal operation MCLR reset during SLEEP WDT reset WDT Wake-up Brown-out Reset Interrupt Wake-up from SLEEP
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1(1) STATUS Register PCON Register
0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu
---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
TABLE 10-6:
INITIALIZATION CONDITION FOR REGISTERS
* MCLR Reset during normal operation * MCLR Reset during SLEEP * WDT Reset * Brown-out Reset (1)
Register W INDF TMR0 PCL STATUS FSR PORTA PORTB CMCON PCLATH INTCON PIR1 OPTION TRISA TRISB PIE1 PCON EEINTF VRCON
Address 00h 01h 02h 03h 04h 05h 06h 1Fh 0Ah 0Bh 0Ch 81h 85h 86h 8Ch 8Eh 90h 9Fh
Power-on Reset
* Wake up from SLEEP through interrupt * Wake up from SLEEP through WDT time-out
xxxx xxxx xxxx xxxx 0000 0000 0001 xxxx ---x xxxx 00----0 1xxx xxxx xxxx xxxx 0000 0000
uuuu uuuu uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu ---u uuuu uuuu uuuu 00-- 0000 ---0 0000 0000 000x -0-1111 ---1 1111 -0----1111 1111 1111 ----
uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu ---u uuuu uuuu uuuu uu-- uuuu ---u uuuu uuuu uuuu(2) -u-- ----(2) uuuu uuuu ---u uuuu uuuu uuuu -u-- ------- --uu uuuu u111 uuu- uuuu
0000 000x -0-1111 ---1 1111 -0----1111 1111 1111 ----
---- --0x uuuu u111 000- 0000
---- --uq(1) uuuu u111 000- 0000
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0',q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 10-5 for reset value for specific condition.
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PIC16CE62X
FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 10-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 10-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 57
PIC16CE62X
FIGURE 10-12: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD VDD
FIGURE 10-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1
VDD 33k 10k MCLR 40k PIC16CE62X VDD
D
R R1 MCLR C
PIC16CE62X
Note 1: External power-on reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
Note 1: This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit.
FIGURE 10-14: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2
VDD R1 Q1 MCLR R2 40k PIC16CE62X VDD
Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that:
R1 VDD x R1 + R2 = 0.7 V
2: Internal brown-out detection should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
10.5 Interrupts
The PIC16CE62X has 4 sources of interrupt: * * * * External interrupt RB0/INT TMR0 overflow interrupt PortB change interrupts (pins RB7:RB4) Comparator interrupt the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/INT recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 10-16). The latency is the same for one or two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on reset. The "return from interrupt" instruction, RETFIE, exits interrupt routine as well as sets the GIE bit, which re-enable RB0/INT interrupts. The INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flag is contained in the special register PIR1. The corresponding interrupt enable bit is contained in special registers PIE1. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of
2:
FIGURE 10-15: INTERRUPT LOGIC
T0IF T0IE INTF INTE RBIF RBIE CMIF CMIE Wake-up (If in SLEEP mode)
Interrupt to CPU
PEIE GIE
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Preliminary
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PIC16CE62X
10.5.1 RB0/INT INTERRUPT 10.5.3 PORTB INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. The RB0/INT interrupt can wake-up the processor from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 10.8 for details on SLEEP and Figure 10-19 for timing of wake-up from SLEEP through RB0/INT interrupt. 10.5.2 TMR0 INTERRUPT An input change on PORTB <7:4> sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<4>) bit. For operation of PORTB (Section 5.2). Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. COMPARATOR INTERRUPT
10.5.4
See Section 8.6 for complete description of comparator interrupts.
An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 7.0.
FIGURE 10-16: INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
4 1 5 Interrupt Latency 2
1
PC Inst (PC) Inst (PC-1)
PC+1 Inst (PC+1) Inst (PC)
PC+1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
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PIC16CE62X
10.6 Context Saving During Interrupts 10.7 Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt e.g. W register and STATUS register. This will have to be implemented in software. Example 10-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x70 in Bank 0 and it must also be defined at 0xF0 in Bank 1). The user register, STATUS_TEMP, must be defined in Bank 0. The Example 10-1: Stores the W register Stores the STATUS register in Bank 0 Executes the ISR code Restores the STATUS (and bank select bit register) * Restores the W register * * * * The watchdog timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the configuration bit WDTE as clear (Section 10.1). 10.7.1 WDT PERIOD
EXAMPLE 10-1: SAVING THE STATUS AND W REGISTERS IN RAM
MOVWF SWAPF BCF MOVWF : : : SWAPF STATUS_TEMP,W ;swap STATUS_TEMP register ;into W, sets bank to original ;state ;move W into STATUS register ;swap W_TEMP ;swap W_TEMP into W (ISR) W_TEMP STATUS,W STATUS,RP0 STATUS_TEMP ;copy W to temp register, ;could be in either bank ;swap status to be saved into W ;change to bank 0 regardless ;of current bank ;save status to bank 0 ;register
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. 10.7.2 WDT PROGRAMMING CONSIDERATIONS
MOVWF SWAPF SWAPF
STATUS W_TEMP,F W_TEMP,W
It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs.
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Preliminary
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PIC16CE62X
FIGURE 10-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 7-6)
0 Watchdog Timer
*
1
M U X
Postscaler 8 8 - to -1 MUX PS<2:0>
WDT Enable Bit
PSA
*
0 MUX 1
To TMR0 (Figure 7-6)
PSA
WDT Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
FIGURE 10-18: SUMMARY OF WATCHDOG TIMER REGISTERS
Address 2007h 81h Name Config. bits OPTION Bit 7 --RBPU Bit 6 BODEN INTEDG Bit 5 CP1 T0CS Bit 4 CP0 T0SE Bit 3 PWRTE PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Legend: Shaded cells are not used by the Watchdog Timer. Note:
_ = Unimplemented location, read as "0" + = Reserved for future use
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PIC16CE62X
10.8 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before SLEEP was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD, or VSS, with no external circuitry drawing current from the I/O pin and the comparators and VREF should be disabled. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). Note: It should be noted that a RESET generated by a WDT time-out does not drive MCLR pin low. WAKE-UP FROM SLEEP The first event will cause a device reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device reset. PD bit, which is set on power-up is cleared when SLEEP is invoked. TO bit is cleared if WDT Wake-up occurred. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wakeup from sleep. The sleep instruction is completely executed.
10.8.1
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin Watchdog Timer Wake-up (if WDT was enabled) Interrupt from RB0/INT pin, RB Port change, or the Peripheral Interrupt (Comparator).
The WDT is cleared when the device wakes-up from sleep, regardless of the source of wake-up.
FIGURE 10-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
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Preliminary
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PIC16CE62X
10.9 Code Protection 10.11 In-Circuit Serial Programming
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices. The PIC16CE62X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X/9XX Programming Specifications (Literature #DS30228). A typical in-circuit serial programming connection is shown in Figure 10-20.
10.10
ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Only the least significant 4 bits of the ID locations are used.
FIGURE 10-20: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC16CE62X VDD VSS MCLR/VPP RB6 RB7 VDD To Normal Connections
External Connector Signals +5V 0V VPP CLK Data I/O
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PIC16CE62X
11.0 INSTRUCTION SET SUMMARY
Each PIC16CE62X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CE62X instruction set summary in Table 11-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 11-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 11-1 lists the instructions recognized by the MPASM assembler. Figure 11-1 shows the three general formats that the instructions can have. Note: To maintain upward compatibility with future PICmicroTM products, do not use the OPTION and TRIS instructions.
TABLE 11-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1
FIGURE 11-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 8 7 k (literal) 0 0
d
label Label name TOS Top of Stack PC Program Counter
PCLATH Program Counter High Latch
0
GIE WDT TO PD dest []
Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit Destination either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
() <> italics
k = 11-bit immediate value
(c) 1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
TABLE 11-2:
Mnemonic, Operands
PIC16CE62X INSTRUCTION SET
Description Cycles MSb 14-Bit Opcode LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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11.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register.
k
Words: Cycles: Example
1 1
ADDLW 0x15 W W = = 0x10 0x25
Words: Cycles: Example
1 1
ANDLW W W 0x5F = = 0xA3 0x03
Before Instruction After Instruction
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Words: Cycles: Example
1 1
ADDWF FSR, 0 W= FSR = 0x17 0xC2 0xD9 0xC2
Words: Cycles: Example
1 1
ANDWF FSR, 1 W= FSR = 0x17 0xC2 0x17 0x02
Before Instruction
Before Instruction
After Instruction
W= FSR =
After Instruction
W= FSR =
(c) 1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
BCF FLAG_REG, 7 FLAG_REG = 0xC7
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None
01 00bb bfff ffff Bit 'b' in register 'f' is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None
01 10bb bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is skipped. If bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction.
Before Instruction After Instruction
FLAG_REG = 0x47
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE
BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None
01 01bb bfff ffff Bit 'b' in register 'f' is set.
f,b
1 1
BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
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PIC16CE62X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None
01 11bb bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction.
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set.
f
1 1
CLRF FLAG_REG FLAG_REG = = = 0x5A 0x00 1
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSS GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction After Instruction
FLAG_REG Z
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear W [ label ] CLRW None 00h (W) 1Z Z
00 0001 0xxx xxxx W register is cleared. Zero bit (Z) is set.
Status Affected: Encoding: Description:
1 1
CLRW
Words: Cycles: Example
1 2
HERE CALL THERE
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE TOS = Address HERE+1
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 69
PIC16CE62X
CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z
00 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
DECF CNT, 1 CNT Z = = = = 0x01 0 0x00 1
Words: Cycles: Example
1 1
CLRWDT
Before Instruction
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
CNT Z
After Instruction
WDT counter = WDT prescaler= TO = PD =
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (dest) Z
00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest); None
00 1011 dfff ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction.
skip if result = 0
Words: Cycles: Example
1 1
COMF REG1,0 REG1 = = = 0x13 0x13 0xEC
Words: Cycles: Example
1 1(2)
HERE DECFSZ GOTO CONTINUE * * * CNT, 1 LOOP
Before Instruction After Instruction
REG1 W
Before Instruction
PC =
address HERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
CNT if CNT PC if CNT PC = = = =
DS40182A-page 70
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction.
Words: Cycles: Example
1 2
GOTO THERE
Words: Cycles:
Address THERE
1 1(2)
INCFSZ GOTO CONTINUE * * * HERE CNT, LOOP 1
After Instruction
PC =
Example
Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1
After Instruction
CNT = if CNT= PC = if CNT PC =
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z
00 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z
11 1000 kkkk kkkk The contents of the W register is OR'ed with the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example
1 1
IORLW W 0x35 = = = 0x9A 0xBF 1
Words: Cycles: Example
1 1
INCF CNT, 1 CNT Z = = = = 0xFF 0 0x00 1
Before Instruction After Instruction
W Z
Before Instruction
After Instruction
CNT Z
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 71
PIC16CE62X
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (dest) Z
00 0100 dfff ffff Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
Words: Cycles: Example
1 1
IORWF RESULT, 0 RESULT = W = 0x13 0x91 0x13 0x93 1
Words: Cycles: Example
1 1
MOVF FSR, 0 W = value in FSR register Z =1
Before Instruction
After Instruction
RESULT = W = Z =
After Instruction
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's.
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff Move data from W register to register 'f'.
MOVLW k
MOVWF
f
0 k 255
0 f 127
1 1
MOVWF OPTION OPTION = W = 0xFF 0x4F 0x4F 0x4F
Words: Cycles: Example
1 1
MOVLW W 0x5A = 0x5A
Before Instruction
After Instruction
After Instruction
OPTION = W =
DS40182A-page 72
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
NOP
No Operation [ label ] None No operation None
00 0000 0xx0 0000
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
NOP
RETFIE
No operation.
Words: Cycles: Example
1 2
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION Syntax: Operands: Operation: Encoding: Description:
Load Option Register [ label ] None (W) OPTION
00 0000 0110 0010
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
OPTION
Status Affected: None
The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PICmicroTM products, do not use this instruction.
Words: Cycles: Example
1 2
CALL TABLE * value * TABLE * ADDWF RETLW RETLW * * * RETLW ;W contains table ;offset value ;W now has table
PC k1 k2
;W = offset ;Begin table ;
kn
; End of table
Before Instruction
W W = = 0x07 value of k8
After Instruction
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 73
PIC16CE62X
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Subroutine [ label ] None TOS PC None
00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C Register f
RETURN
Words: Cycles: Example
1 2
RETURN
After Interrupt
PC = TOS
Words: Cycles: Example
1 1
RRF REG1 C REG1,0 = = = = = 1110 0110 0 1110 0110 0111 0011 0
Before Instruction
After Instruction
REG1 W C
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C Register f
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 10.8 for more details.
RLF
f,d
SLEEP
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Words: Cycles: Example:
1 1 SLEEP
Before Instruction
After Instruction
REG1 W C
DS40182A-page 74
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk Operation: Status Affected: Encoding: Description: SUBWF Syntax: Operands: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z 00 0010 dfff ffff SUBWF f,d
The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example 1:
1 1 SUBLW 0x02
W C = = 1 ?
Subtract (2's complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Words: Cycles: Example 1:
1 1 SUBWF
REG1 W C
Before Instruction
REG1,1
= = = 3 2 ?
Before Instruction
After Instruction
W= C = tive 1 1; result is posi-
After Instruction
REG1 W C = = = 1 2 1; result is positive
Example 2:
Before Instruction
W C = = 2 ?
After Instruction
W C = = 0 1; result is zero
Example 2:
Before Instruction
REG1 W C = = = 2 2 ?
Example 3:
Before Instruction
W C = = 3 ?
After Instruction
REG1 W C = = = 0 2 1; result is zero
After Instruction
W= C = tive 0xFF 0; result is nega-
Example 3:
Before Instruction
REG1 W C = = = 1 2 ?
After Instruction
REG1 W C = = = 0xFF 2 0; result is negative
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 75
PIC16CE62X
SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None
00
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk
The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register.
1110
dfff
ffff
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: Cycles: Example:
1 1 XORLW 0xAF
W = 0xB5
Words: Cycles: Example
1 1
SWAPF REG, 0
Before Instruction After Instruction
W = = 0xA5 0x5A = 0x1A
Before Instruction
REG1 = 0xA5
After Instruction
REG1 W
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f7 (W) TRIS register f; f
XORWF Syntax: Operands: Operation:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Status Affected: None
00
0000
0110
0fff
Status Affected: Encoding: Description:
The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PICmicroTM products, do not use this instruction.
Words: Cycles: Example
1 1 XORWF
REG 1
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
REG W = = 0x1A 0xB5
DS40182A-page 76
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
12.0
12.1
DEVELOPMENT SUPPORT
Development Tools
12.3
ICEPIC: Low-Cost PICmicroTM In-Circuit Emulator
The PICmicrTM microcontrollers are supported with a full range of hardware and software development tools: * PICMASTER(R)/PICMASTER CE Real-Time In-Circuit Emulator * ICEPICTM Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C17 (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP)
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT(R) through PentiumTM based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.
12.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.
12.2
PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC14C000, PIC12CXXX, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLABTM Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x environment were chosen to best make these features available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries.
12.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.
(c) 1998 Microchip Technology Inc.
DS40182A - page 77
PIC16CE62X
12.6 PICDEM-1 Low-Cost PICmicro Demonstration Board
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
12.9
MPLABTM Integrated Development Environment Software
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file * Transfer data dynamically via DDE (soon to be replaced by OLE) * Run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
12.7
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
12.8
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include
12.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from PICMASTER, Microchip's Universal Emulator System.
DS40182A - page 78
(c) 1998 Microchip Technology Inc.
PIC16CE62X
MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.
12.14
MP-DriveWayTM - Application Code Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually configure all the peripherals in a PICmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip's MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.
12.15
SEEVAL(R) Evaluation and Programming System
12.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
12.16
KEELOQ(R) Evaluation and Programming Tools
12.12
C Compiler (MPLAB-C17)
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
The MPLAB-C Code Development System is a complete `C' compiler and integrated development environment for Microchip's PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.
12.13
Fuzzy Logic Development System (fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
(c) 1998 Microchip Technology Inc.
DS40182A - page 79
Emulator Products
Software Tools
Programmers
Demo Boards
DS40182A - page 80 (c) 1998 Microchip Technology Inc.
TABLE 12-1:
PIC16CE62X
PIC12C5XX PICMASTER(R)/ PICMASTER-CE In-Circuit Emulator ICEPICTM Low-Cost In-Circuit Emulator MPLABTM Integrated Development Environment MPLABTM C17 Compiler
PIC14000
PIC16C5X
PIC16CXXX
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
PIC17C75X
24CXX 25CXX 93CXX
HCS200 HCS300 HCS301
u u u
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u u
u u u
u u u
u u u
u u u
u u u
u
u
DEVELOPMENT TOOLS FROM MICROCHIP
u
u
u u
u u
fuzzyTECH(R)-MP Explorer/Edition Fuzzy Logic Dev. Tool
MP-DriveWayTM Applications Code Generator Total EnduranceTM Software Model PICSTART(R)Plus Low-Cost Universal Dev. Kit PRO MATE(R) II Universal Programmer KEELOQ(R) Programmer SEEVAL(R) Designers Kit PICDEM-1 PICDEM-2 PICDEM-3 KEELOQ(R) Evaluation Kit
u
u
u u
u u
u u
u u
u u
u u
u u u
u u
u u
u u
u u
u u
u u
u u
u u
u u
u u u u u u
u
u u u
u u
u
u
PIC16CE62X
13.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Ambient Temperature under bias .............................................................................................................. -40 to +125C Storage Temperature................................................................................................................................. -65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR)....................................................... -0.6V to VDD +0.6V Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V Total power Dissipation (Note 1) ...............................................................................................................................1.0W Maximum Current out of VSS pin...........................................................................................................................300 mA Maximum Current into VDD pin .............................................................................................................................250 mA Input Clamp Current, IIK (VI <0 or VI> VDD) ......................................................................................................................20 mA Output Clamp Current, IOK (VO <0 or VO>VDD) ...............................................................................................................20 mA Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA Maximum Output Current sourced by any I/O pin ...................................................................................................25 mA Maximum Current sunk by PORTA and PORTB ...................................................................................................200 mA Maximum Current sourced by PORTA and PORTB ..............................................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 81
PIC16CE62X
TABLE 13-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16CE62X-04 VDD: 3.0V to 5.5V IDD: 3.3 mA max. @5.5V IPD: 2.5 A max. @4.0V, WDT DIS Freq: 4.0 MHz max. VDD: 3.0V to 5.5V IDD: 3.3 mA max. @5.5V IPD: 2.5 A max. @4.0V, WDT DIS Freq: 4.0 MHz max. VDD: 4.5V to 5.5V IDD: 3.0 mA typ. @5.5V IPD: 1.0 A typ. @4.0V, WDT DIS Freq: 4.0 MHz max. VDD: 3.0V to 5.5V IDD: 70 A max. @32 kHz, 3.0V, WDT DIS IPD: 2.5 A max. @4.0 V, WDT DIS Freq: 200 kHz max. PIC16CE62X-20 VDD: 3.0V to 5.5V IDD: 1.8 mA typ. @5.5V IPD: 1.0 A typ. @4.0V, WDT DIS Freq: 4.0 MHz max. VDD: 3.0V to 5.5V IDD: 1.8 mA typ. @5.5V IPD: 1.0 A typ. @4.0V, WDT DIS Freq: 4.0 MHz max. VDD: 4.5V to 5.5V IDD: 7.5 mA max. @5.5V IPD: 2.5 A max. @4.0V, WDT DIS Freq: 20 MHz max. PIC16CE62X/JW VDD: 3.0V to 5.5V IDD: 3.3 mA max. @5.5V IPD: 2.5 A max. @4.0V, WDT DIS Freq: 4.0 MHz max. VDD: 3.0V to 5.5V IDD: 3.3 mA max. @5.5V IPD: 2.5 A max. @4.0V, WDT DIS Freq: 4.0 MHz max. VDD: 4.5V to 5.5V IDD: 7.5 mA max. @5.5V IPD: 2.5 A max. @4.0V, WDT DIS Freq: 20 MHz max. VDD: 3.0V to 5.5V IDD: 70 A max. @32 kHz, 3.0V, WDT DIS IPD: 2.5 A max. @4.0V, WDT DIS Freq: 200 kHz max.
OSC RC
XT
HS
LP
Do not use in LP mode
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
DS40182A-page 82
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
13.1 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended) PIC16CE62X-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Param No. D001 D001A D002 D003 D004 D005 D005A D010 Sym VDD VDR VPOR SVDD VBOR IDD Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure Power-on Reset VDD rise rate to ensure Power-on Reset Brown-out Reset Voltage Supply Current (Note 2) Min 3.0 4.5 - - 0.05* 3.7 3.7 - Typ 1.5* VSS - 4.0 4.0 1.8 Max 5.5 5.5 - - - 4.3 4.4 3.3 Units V V V V V/ms V mA Conditions XT, RC and LP osc configuration HS osc configuration Device in SLEEP mode See section on power-on reset for details See section on power-on reset for details BODEN configuration bit is cleared (Automotive) XT and RC osc configuration FOSC = 4 MHz, VDD = 5.5V, WDT disabled (Note 4) LP osc configuration, PIC16CE62X-04 only FOSC = 32 kHz, VDD = 4.0V, WDT disabled HS osc configuration FOSC = 20 MHz, VDD = 5.5V, WDT disabled VDD=4.0V, WDT disabled (125C) VDD = 4.0V (125C) BOR enabled, VDD = 5.0V VDD = 4.0V VDD = 4.0V
D010A
-
35
70
A
D013
-
3.0
7.5
mA
D021 D022 D022A D023 D023A * Note 1: 2:
IPD IWDT IBOR ICOMP IVREF
Power Down Current (Note 3) WDT Current (Note 5) Brown-out Reset Current (Note 5) Comparator Current for each Comparator (Note 5) VREF Current (Note 5)
- - - - -
1.0 6.0 75 60 90
2.5 15 20 25 150 100 200
A A A A A A A
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedence state and tied to VDD or VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in k. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 83
PIC16CE62X
13.2 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended) PIC16CE62X-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Operating voltage VDD range as described in DC spec Table 13-1 and Table 13-2
Parm Sym No.
Characteristic
Min
Typ
Max
Unit
Conditions
VIL Input Low Voltage D030 D030A D031 D032
I/O ports with TTL buffer with Schmitt Trigger input MCLR, RA4/T0CKI,OSC1 (in RC mode) OSC1 (in XT and HS) OSC1 (in LP)
VIH Input High Voltage
VSS VSS Vss Vss
-
0.8V 0.15VDD 0.2VDD 0.2VDD 0.3VDD 0.6VDD 1.0
-
V VDD = 4.5V to 5.5V otherwise(4) V For entire VDD range V Note1 V
D033
2.0V 0.25VDD + 0.8V D041 with Schmitt Trigger input 0.8VDD D042 MCLR RA4/T0CKI 0.8VDD OSC1 (XT, HS and LP) 0.7VDD D042A D043 OSC1 (in RC mode) 0.9VDD D070 IPURB PORTB weak pull-up current 50 200 Input Leakage Current IIL (Notes 2, 3) D060 I/O ports (Except PORTA) D060A PORTA D060B RA4/T0CKI OSC1, MCLR D061
D040 D040A VOL Output Low Voltage D080 D080A D083
I/O ports with TTL buffer
VDD VDD VDD VDD VDD 400
V VDD = 4.5V to 5.5V otherwise (4) For entire VDD range V V Note1 A VDD = 5.0V, VPIN = VSS A A A A VSS VPIN VDD, pin at hi-impedance Vss VPIN VDD, pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL=8.5 mA, VDD=4.5V, IOL=7.0 mA, VDD=4.5V, IOL=1.6 mA, VDD=4.5V, IOL=1.2 mA, VDD=4.5V, -40 to +85C +125C -40 to +85C +125C
1.0 0.5 1.0 5.0
I/O ports OSC2/CLKOUT (RC only)
VOH Output High Voltage (Note 3)
-
-
0.6 0.6 0.6 0.6
V V V V
D090
I/O ports (Except RA4) VDD-0.7 V IOH=-3.0 mA, VDD=4.5V, -40 to +85C These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16CE62X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: The better of the two specifications may be used. For VIL, this would be the higher voltage and for VIH, this would be the lower voltage. *
DS40182A-page 84
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
13.2 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended) PIC16CE62X-20 (Commercial, Industrial, Extended) (Cont.)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Operating voltage VDD range as described in DC spec Table 13-1 and Table 13-2
Parm Sym No. D090A D092 D150
Characteristic
Min VDD-0.7
Typ -
Max 10*
Unit
Conditions
OSC2/CLKOUT (RC only)
VOD Open-Drain High Voltage
VDD-0.7 VDD-0.7
V IOH=-2.5 mA, VDD=4.5V, +125C V IOH=-1.3 mA, VDD=4.5V, -40 to +85C V IOH=-1.0 mA, VDD=4.5V, +125C V RA4 pin
Capacitive Loading Specs on Output Pins D100 COSC OSC2 pin
2
15
D101
50 mode) * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16CE62X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: The better of the two specifications may be used. For VIL, this would be the higher voltage and for VIH, this would be the lower voltage.
Cio All I/O pins/OSC2 (in RC
pF In XT, HS and LP modes when external clock used to drive OSC1. pF
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 85
PIC16CE62X
TABLE 13-2: COMPARATOR SPECIFICATIONS
Operating Conditions: Vdd range as described in Table 12-1, -40C* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD.
TABLE 13-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions:Vdd range as described in Table 12-1, -40CD312 310
Unit Resistor Value (R) Settling Time
(1)
VRUR TSET
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
DS40182A-page 86
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
13.3 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp ck CLKOUT io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc t0
OSC1 T0CKI
P R V Z
Period Rise Valid Hi-Impedance
FIGURE 13-1: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 87
PIC16CE62X
13.4 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 13-4:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) Min DC DC DC DC 0.1 1 DC Typ -- -- -- -- -- -- - -- -- -- -- -- -- -- Fosc/4 -- -- -- -- -- -- Max 4 20 200 4 4 20 200 -- -- -- -- 10,000 1,000 -- DC -- -- -- -- -- -- Units Conditions MHz MHz kHz MHz MHz MHz kHz ns ns s ns ns ns s s ns s ns ns ns ns XT and RC osc mode, VDD=5.0V HS osc mode LP osc mode RC osc mode, VDD=5.0V XT osc mode HS osc mode LP osc mode XT and RC osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode
Sym Fos
1
Tosc
External CLKIN Period (Note 1) Oscillator Period (Note 1)
250 50 5 250 250 50 5 1.0 100* 2* 20*
2 3*
TCY TosL, TosH
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time
TCYS=FOSC/4
XT oscillator, TOSC L/H duty cycle LP oscillator, TOSC L/H duty cycle HS oscillator, TOSC L/H duty cycle XT oscillator LP oscillator HS oscillator
4*
TosR, TosF
External Clock in (OSC1) Rise or Fall Time
25* 50* 15*
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
*
DS40182A-page 88
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
FIGURE 13-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21
Note: All tests must be do with specified capacitance loads (Figure 13-1) 50 pF on I/O pins and CLKOUT
Q1
Q2
Q3
11 22 23 19 18 12 16
15 new value
TABLE 13-5:
Parameter # 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23
CLKOUT AND I/O TIMING REQUIREMENTS
Sym TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp Characteristic OSC1 to CLKOUT (1) OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time
(1) (1) (1) (1) (1)
Min -- -- -- -- -- Tosc +200 ns 0 -- 100 0 -- -- 25 TCY
Typ 75 75 35 35 -- -- -- 50 -- -- 10 10 -- --
Max 200 200 100 100 20 -- -- 150 -- -- 40 40 -- --
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CLKOUT to Port out valid Port in hold after CLKOUT
Port in valid before CLKOUT
(1)
OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time RB0/INT pin high or low time RB<7:4> change interrupt high or low time
* These parameters are characterized but not tested Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 89
PIC16CE62X
FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Timeout OSC Timeout Internal RESET Watchdog Timer RESET 34 I/O Pins 32 30
31 34
FIGURE 13-5: BROWN-OUT RESET TIMING
VDD
BVDD 35
TABLE 13-6:
Parameter No. 30 31 32 33 34 35
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ TBOR Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O hi-impedance from MCLR low Brown-out Reset Pulse Width 100* Min 2000 7* -- 28* Typ -- 18 1024 TOSC 72 -- -- Max -- 33* -- 132* 2.0 -- Units ns ms -- ms s s 3.7V VDD 4.3V Conditions -40 to +85C
VDD = 5.0V, -40 to +85C
TOSC = OSC1 period
VDD = 5.0V, -40 to +85C
*
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS40182A-page 90
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
FIGURE 13-6: TIMER0 CLOCK TIMING
RA4/T0CKI
40 42
41
TMR0
TABLE 13-7:
Parameter No. 40
TIMER0 CLOCK REQUIREMENTS
Min No Prescaler With Prescaler 0.5 TCY + 20* 10* 0.5 TCY + 20* 10* TCY + 40* N Typ -- -- -- -- -- Max -- -- -- -- -- Units Conditions ns ns ns ns ns N = prescale value (1, 2, 4, ..., 256)
Sym Characteristic Tt0H T0CKI High Pulse Width
41
Tt0L T0CKI Low Pulse Width
No Prescaler With Prescaler
42
Tt0P T0CKI Period
*
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 91
PIC16CE62X
13.5 EEPROM Timing AC CHARACTERISTICS
STANDARD MODE Min. Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max. 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc = 4.5 - 5.5V FAST MODE Min. -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max. 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns
TABLE 13-8:
Parameter
Symbol
Units
Remarks
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)
Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance Note 1: 2: 3: 4:
TOF TSP TWR
-- --
250 50
20 +0.1 CB --
250 50
ns ns
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3)
-- 10 -- 10 ms Byte or Page mode 10M -- 10M 25C, Vcc = 5.0V, Block -- -- cycles 1M 1M Mode (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 13-7: BUS TIMING DATA
TF THIGH TLOW SCL TSU:STA SDA IN THD:STA TSP TAA SDA OUT THD:STA THD:DAT TSU:DAT TSU:STO TR
TAA
TBUF
DS40182A-page 92
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
14.0 PACKAGING INFORMATION
K04-010 18-Lead Ceramic Dual In-line with Window (JW) - 300 mil Package Type:
E
W2
D
2 n W1 E1 1
A R eB
A1 L
c A2 B1 B p
Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Radius to Radius Width Overall Row Spacing Window Width Window Length * Controlling Parameter.
MIN n p B B1 R c A A1 A2 L D E E1 eB W1 W2
0.098 0.016 0.050 0.010 0.008 0.175 0.091 0.015 0.125 0.880 0.285 0.255 0.345 0.130 0.190
INCHES* NOM 0.300 18 0.100 0.019 0.055 0.013 0.010 0.183 0.111 0.023 0.138 0.900 0.298 0.270 0.385 0.140 0.200
MAX
MIN
0.102 0.021 0.060 0.015 0.012 0.190 0.131 0.030 0.150 0.920 0.310 0.285 0.425 0.150 0.210
MILLIMETERS MAX NOM 7.62 18 2.59 2.49 2.54 0.53 0.41 0.47 1.52 1.27 1.40 0.38 0.25 0.32 0.30 0.20 0.25 4.83 4.45 4.64 3.33 2.31 2.82 0.76 0.57 0.00 3.81 3.18 3.49 23.37 22.35 22.86 7.87 7.24 7.56 7.24 6.86 6.48 9.78 10.80 8.76 0.15 0.14 0.13 0.2 0.21 0.19
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 93
PIC16CE62X
Package Type: K04-007 18-Lead Plastic Dual In-line (P) - 300 mil
E
D
2 n E1 A1 A R c A2 B1 eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter.
1
L
B
p
MIN n p B B1 R c A A1 A2 L D E E1 eB
INCHES* NOM 0.300 18 0.100 0.013 0.018 0.055 0.060 0.000 0.005 0.005 0.010 0.110 0.155 0.075 0.095 0.000 0.020 0.125 0.130 0.890 0.895 0.245 0.255 0.230 0.250 0.310 0.349 5 10 5 10
MAX
MIN
0.023 0.065 0.010 0.015 0.155 0.115 0.020 0.135 0.900 0.265 0.270 0.387 15 15
MILLIMETERS NOM MAX 7.62 18 2.54 0.33 0.46 0.58 1.40 1.52 1.65 0.00 0.13 0.25 0.13 0.25 0.38 2.79 3.94 3.94 1.91 2.41 2.92 0.00 0.51 0.51 3.18 3.30 3.43 22.61 22.73 22.86 6.22 6.48 6.73 5.84 6.35 6.86 7.87 8.85 9.83 5 10 15 5 10 15
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS40182A-page 94
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) - 5.30 mm
E1 E p
D
B n
2 1 L R2
c
A A1 R1 L1 A2
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
MIN p n A A1 A2 D E E1 R1 R2 L L1 c B
INCHES NOM 0.026 20 0.073 0.068 0.036 0.026 0.005 0.002 0.283 0.278 0.208 0.205 0.306 0.301 0.005 0.005 0.005 0.005 0.020 0.015 0 4 0.005 0.000 0.007 0.005 0.012 0.010 0 5 0 5
MAX
MIN
0.078 0.046 0.008 0.289 0.212 0.311 0.010 0.010 0.025 8 0.010 0.009 0.015 10 10
MILLIMETERS* NOM MAX 0.65 20 1.86 1.99 1.73 0.91 1.17 0.66 0.13 0.21 0.05 7.20 7.33 7.07 5.29 5.38 5.20 7.65 7.78 7.90 0.25 0.13 0.13 0.25 0.13 0.13 0.38 0.64 0.51 8 0 4 0.25 0.00 0.13 0.13 0.22 0.18 0.25 0.38 0.32 0 5 10 0 5 10
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 95
PIC16CE62X
Package Type: K04-051 18-Lead Plastic Small Outline (SO) - Wide, 300 mil
E1 p E
D
2 B n X 45 1
L R2
c A R1 Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
A1
L1
A2 MILLIMETERS NOM MAX 1.27 18 2.64 2.36 2.50 1.73 1.22 1.47 0.28 0.10 0.19 11.73 11.43 11.58 7.59 7.42 7.51 10.64 10.01 10.33 0.74 0.25 0.50 0.25 0.13 0.13 0.25 0.13 0.13 0.53 0.28 0.41 4 8 0 0.51 0.25 0.38 0.30 0.23 0.27 0.48 0.36 0.42 0 12 15 0 12 15
MIN p n A A1 A2 D E E1 X R1 R2 L L1 c B
INCHES* NOM 0.050 18 0.093 0.099 0.048 0.058 0.004 0.008 0.450 0.456 0.292 0.296 0.394 0.407 0.010 0.020 0.005 0.005 0.005 0.005 0.016 0.011 0 4 0.015 0.010 0.011 0.009 0.017 0.014 0 12 0 12
MAX
MIN
0.104 0.068 0.011 0.462 0.299 0.419 0.029 0.010 0.010 0.021 8 0.020 0.012 0.019 15 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS40182A-page 96
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
14.1 Package Marking Information 18-Lead PDIP XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX AABBCDE 18-Lead SOIC (.300") XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE Example PIC16CE625 -04I/P423 9807CDK Example PIC16CE625 -04I/S0218 9807 CDK Example 16CE625 /JW 9807 CBA Example PIC16CE625 -04I/218 9807 CBP
18-Lead CERDIP Windowed XXXXXXXX XXXXXXXX AABBCDE 20-Lead SSOP XXXXXXXXXX XXXXXXXXXX AABBCDE
Legend: MM...M XX...X AA BB C
D E
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5" Line S = 6" Line H = 8" Line Mask revision number Assembly code of the plant or country of origin in which part was assembled
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 97
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NOTES:
DS40182A-page 98
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
APPENDIX A: CODE FOR ACCESSING EEPROM DATA MEMORY
To be determined. Please check our web site at www.microchip.com for code availability.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 99
PIC16CE62X
NOTES:
DS40182A-page 100
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
INDEX A
ADDLW Instruction ............................................................. 67 ADDWF Instruction ............................................................. 67 ANDLW Instruction ............................................................. 67 ANDWF Instruction ............................................................. 67 Architectural Overview .......................................................... 7 Assembler MPASM Assembler..................................................... 78 ANDLW....................................................................... 67 ANDWF ...................................................................... 67 BCF ............................................................................ 68 BSF............................................................................. 68 BTFSC........................................................................ 68 BTFSS ........................................................................ 69 CALL........................................................................... 69 CLRF .......................................................................... 69 CLRW ......................................................................... 69 CLRWDT .................................................................... 70 COMF ......................................................................... 70 DECF.......................................................................... 70 DECFSZ ..................................................................... 70 GOTO ......................................................................... 71 INCF ........................................................................... 71 INCFSZ....................................................................... 71 IORLW........................................................................ 71 IORWF........................................................................ 72 MOVF ......................................................................... 72 MOVLW ...................................................................... 72 MOVWF...................................................................... 72 NOP............................................................................ 73 OPTION...................................................................... 73 RETFIE....................................................................... 73 RETLW ....................................................................... 73 RETURN..................................................................... 74 RLF............................................................................. 74 RRF ............................................................................ 74 SLEEP ........................................................................ 74 SUBLW....................................................................... 75 SUBWF....................................................................... 75 SWAPF....................................................................... 76 TRIS ........................................................................... 76 XORLW ...................................................................... 76 XORWF ...................................................................... 76 Instruction Set Summary .................................................... 65 INT Interrupt ....................................................................... 60 INTCON Register ............................................................... 17 Interrupts ............................................................................ 59 IORLW Instruction .............................................................. 71 IORWF Instruction .............................................................. 72
B
BCF Instruction ................................................................... 68 Block Diagram TIMER0....................................................................... 35 TMR0/WDT PRESCALER .......................................... 38 Brown-Out Detect (BOD) .................................................... 54 BSF Instruction ................................................................... 68 BTFSC Instruction............................................................... 68 BTFSS Instruction............................................................... 69
C
CALL Instruction ................................................................. 69 Clocking Scheme/Instruction Cycle .................................... 10 CLRF Instruction ................................................................. 69 CLRW Instruction................................................................ 69 CLRWDT Instruction ........................................................... 70 CMCON Register ................................................................ 41 Code Protection .................................................................. 64 COMF Instruction ................................................................ 70 Comparator Configuration................................................... 42 Comparator Interrupts......................................................... 45 Comparator Module ............................................................ 41 Comparator Operation ........................................................ 43 Comparator Reference ....................................................... 43 Configuration Bits................................................................ 50 Configuring the Voltage Reference..................................... 47 Crystal Operation ................................................................ 51
D
Data Memory Organization ................................................. 12 DECF Instruction................................................................. 70 DECFSZ Instruction ............................................................ 70 Development Support ......................................................... 77 Development Tools ............................................................. 77
K
KeeLoq(R) Evaluation and Programming Tools ................... 79
E
EEPROM Peripheral Operation .......................................... 29 External Crystal Oscillator Circuit ....................................... 52
M
MOVF Instruction................................................................ 72 MOVLW Instruction ............................................................ 72 MOVWF Instruction ............................................................ 72 MP-DriveWayTM - Application Code Generator .................. 79 MPLAB C ............................................................................ 79 MPLAB Integrated Development Environment Software.... 78
F
Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) .................... 79
G
General purpose Register File ............................................ 12 GOTO Instruction................................................................ 71
N
NOP Instruction .................................................................. 73
I
I/O Ports .............................................................................. 23 I/O Programming Considerations........................................ 28 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 77 ID Locations ........................................................................ 64 INCF Instruction .................................................................. 71 INCFSZ Instruction ............................................................. 71 In-Circuit Serial Programming............................................. 64 Indirect Addressing, INDF and FSR Registers ................... 21 Instruction Flow/Pipelining .................................................. 10 Instruction Set ADDLW ....................................................................... 67 ADDWF....................................................................... 67
O
One-Time-Programmable (OTP) Devices .............................5 OPTION Instruction ............................................................ 73 OPTION Register ............................................................... 16 Oscillator Configurations .................................................... 51 Oscillator Start-up Timer (OST) .......................................... 54
P
Package Marking Information ............................................. 97 Packaging Information ........................................................ 93 PCL and PCLATH .............................................................. 20 PCON Register ................................................................... 19 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 78
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 101
PIC16CE62X
PICDEM-2 Low-Cost PIC16CXX Demo Board ................... 78 PICDEM-3 Low-Cost PIC16CXXX Demo Board................. 78 PICMASTER(R) In-Circuit Emulator...................................... 77 PICSTART(R) Plus Entry Level Development System ......... 77 PIE1 Register ...................................................................... 18 Pinout Description ................................................................. 9 PIR1 Register...................................................................... 18 Port RB Interrupt ................................................................. 60 PORTA................................................................................ 23 PORTB................................................................................ 26 Power Control/Status Register (PCON) .............................. 55 Power-Down Mode (SLEEP)............................................... 63 Power-On Reset (POR) ...................................................... 54 Power-up Timer (PWRT)..................................................... 54 Prescaler ............................................................................. 38 PRO MATE(R) II Universal Programmer............................... 77 Program Memory Organization ........................................... 11
Q
Quick-Turnaround-Production (QTP) Devices ...................... 5
R
RC Oscillator ....................................................................... 52 Reset................................................................................... 53 RETFIE Instruction.............................................................. 73 RETLW Instruction .............................................................. 73 RETURN Instruction............................................................ 74 RLF Instruction.................................................................... 74 RRF Instruction ................................................................... 74
S
SEEVAL(R) Evaluation and Programming System ............... 79 Serialized Quick-Turnaround-Production (SQTP) Devices ... 5 SLEEP Instruction ............................................................... 74 Software Simulator (MPLAB-SIM)....................................... 79 Special Features of the CPU............................................... 49 Special Function Registers ................................................. 14 Stack ................................................................................... 20 Status Register.................................................................... 15 SUBLW Instruction.............................................................. 75 SUBWF Instruction.............................................................. 75 SWAPF Instruction.............................................................. 76
T
Timer0 TIMER0....................................................................... 35 TIMER0 (TMR0) Interrupt ........................................... 35 TIMER0 (TMR0) Module ............................................. 35 TMR0 with External Clock........................................... 37 Timer1 Switching Prescaler Assignment................................. 39 Timing Diagrams and Specifications................................... 88 TMR0 Interrupt .................................................................... 60 TRIS Instruction .................................................................. 76 TRISA.................................................................................. 23 TRISB.................................................................................. 26
V
Voltage Reference Module.................................................. 47 VRCON Register................................................................. 47
W
Watchdog Timer (WDT) ...................................................... 61
X
XORLW Instruction ............................................................. 76 XORWF Instruction ............................................................. 76
DS40182A-page 102
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16CE62X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
980106
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
(c) 1998 Microchip Technology Inc.
DS40182A-page 103
PIC16CE62X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16CE62X Questions: 1. What are the best features of this document? Y N Literature Number: DS40182A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40182A-page 104
(c) 1998 Microchip Technology Inc.
PIC16CE62X
PIC16CE62X PRODUCT IDENTIFICATION SYSTEM
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.
PART NO.
-XX
X /XX XXX
Pattern: Package: 3-Digit Pattern Code for QTP (blank otherwise) P SO SS JW* I E 04 04 20 = = = = = = = = = = PDIP SOIC (Gull Wing, 300 mil body) SSOP (209 mil) Examples: Windowed CERDIP 0C to +70C -40C to +85C -40C to +125C 200kHz (LP osc) 4 MHz (XT and RC osc) 20 MHz (HS osc)
a) PIC16CE623-04/P301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. b) PIC16CE623-04I/SO = Industrial temp., SOIC package, 4MHz, industrial VDD limits.
Temperature Range: Frequency Range: Device:
PIC16CE62X :VDD range 3.0V to 5.5V PIC16CE62XT:VDD range 3.0V to 5.5V (Tape and Reel)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
(c) 1998 Microchip Technology Inc.
Preliminary
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PIC16CE62X
NOTES:
DS40182A-page 106
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(c) 1998 Microchip Technology Inc.
PIC16CE62X
NOTES:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40182A-page 107
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
ASIA/PACIFIC (CONTINUED)
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Dallas
Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 1/13/98
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338
Singapore
Microchip Technology Taiwan Singapore Branch 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 1998, Microchip Technology Incorporated, USA. 3/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40182A-page 108
(c) 1998 Microchip Technology Inc.

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