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KB3700
Keyboard Controller Datasheet
Revision 0.1 July. 2006
ENE RESERVES THE RIGHT TO AMEND THIS DOCUMENT WITHOUT NOTICE AT ANY TIME. ENE ASSUMES NO RESPONSIBILITY FOR ANY ERRORS APPEAR IN THE DOCUMENT, AND ENE DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF ENE PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, OR INFRINGEMENT OF ANY PATENTS, COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
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KB3700 Keyboard Controller Datasheet
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CONTENT
1. FEATURES ................................................................................................................... 4
1.1 FEATURE SUMMARY................................................................................................................ 4 1.2 BLOCK DIAGRAM .................................................................................................................... 7
2. PIN ASSIGNMENT AND DESCRIPTION ............................................................... 8
2.1 PIN LIST ................................................................................................................................. 8 2.2 I/O BUFFER TABLE ................................................................................................................. 9 2.3 I/O BUFFER CHARACTERISTIC TABLE ...................................................................................... 9 2.4 I/O NAMING CONVENTION ....................................................................................................... 9
3. PIN DESCRIPTIONS ................................................................................................ 10
3.1 HARDWARE TRAP.................................................................................................................. 10
4. MODULE DESCRIPTIONS ..................................................................................... 10
4.1 CHIP ARCHITECTURE .............................................................................................................11 4.1.1 Power Planes ....................................................................................................................11 4.1.2 Clock Domains..................................................................................................................11 4.1.3 Reset Domains ..................................................................................................................11 4.2 GPIO....................................................................................................................................11 4.2.1 GPIO Functional Description...........................................................................................11 4.2.2 GPIO Input / Output Control Structure............................................................................ 13 4.3 KBC .................................................................................................................................... 14 4.3.1 KBC Functional Description ........................................................................................... 14 4.3.2 KBC Registers Descriptions (Base Address = FC80h, 32 bytes)..................................... 15 4.4 PWM ................................................................................................................................... 15 4.4.1 PWM Functional Description .......................................................................................... 16 4.4.2 PWM Registers Descriptions (Base address_FE00h, 16 bytes)....................................... 16 4.5 GPT .................................................................................................................................... 17 4.5.1 GPT Functional Description............................................................................................ 17 4.5.2 GPT Register Descriptions (Base address = FE50h, 16 bytes) ....................................... 17 4.6 SPI/ISP DEVICE INTERFACE.................................................................................................. 18 4.6.1 SPI/ISP Functional Description....................................................................................... 18 4.6.2 SPI Registers Descriptions (Base address = FE70h, 16 bytes) ....................................... 18 4.6.3 ISP Registers Descriptions (8 bytes)................................................................................ 19 4.7 WDT.................................................................................................................................... 21 4.7.1 WDT Functional Description........................................................................................... 21 4.7.2 WDT Registers Descriptions (Base address = FE80h, 16 bytes) ..................................... 21
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4.8 LPC..................................................................................................................................... 22 4.8.1 LPC / FWH Functional Description ................................................................................ 22 4.8.1.1 LPC Decoding IO Ports................................................................................................ 22 4.8.1.2 LPC Decoding Memory Space...................................................................................... 22 4.8.2 LPC Registers Descriptions (Base address = FE90h, 16 bytes)...................................... 22 4.9 PS / 2 INTERFACE ................................................................................................................. 24 4.9.1 PS/2 Functional Description............................................................................................ 24 4.9.2 PS2 Registers Descriptions (Base Address = FEE0h, 32 bytes)...................................... 24 4.10 EC..................................................................................................................................... 26 4.10.1 EC Functional Description ............................................................................................ 26
4.10.1.1 Hardware EC Commands ................................................................................................................ 26 4.10.1.2 EC Status Register............................................................................................................................. 26 4.10.1.3 EC Command Register ..................................................................................................................... 26 4.10.1.4 EC Command Program Sequence ................................................................................................... 27 4.10.1.5 EC Index IO Mode ............................................................................................................................ 27 4.10.1.6 SCI Generation.................................................................................................................................. 27 4.10.1.7 SCI ID Table ...................................................................................................................................... 28
4.10.2 EC Register Descriptions (Base Address = FF00h, 32 bytes) ....................................... 28 4.11 GPWU............................................................................................................................... 32 4.11.1 GPWU Functional Description ...................................................................................... 32 4.11.2 GPWU Register Descriptions (Base Address = FF30h, 96 bytes) ................................. 32 4.12 8051 MICROPROCESSOR .................................................................................................... 32 4.12.1 Interrupt Vectors Table................................................................................................... 32 4.12.2 SFR Map ........................................................................................................................ 33 4.12.3 SFR Descriptions ........................................................................................................... 34
5. ELECTRONIC CHARACTERISTICS ................................................................... 37
5.1 ABSOLUTE MAXIMUM RATING................................................................................................ 37 5.2 RECOMMENDED OPERATING CONDITION ................................................................................ 37 5.3 OPERATING CURRENT........................................................................................................... 37
6. PACKAGING INFORMATION ............................................................................... 39
6.1 64 LQFP ............................................................................................................................. 39
7. REVISION HISTORY ............................................................................................... 40
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1. Features
1.1 Feature Summary
Low Pin Count Host Interface (LPC) SIRQ supporting IRQ1, IRQ12, SCI I/O Address Decoding: KBC IO Port 60h/64h Programmable EC IO Port 62h/66h and 68h/6Ch Programmable 4-byte Index I/O ports to access internal registers One Programmable I/O write byte-address decoding
X-Bus Interface (XBI) SPI Flash support, the operation frequency runs at least 50MHz. Addressable Memory range up to 24MB. 8051 64KB code memory can be mapped into 4 independent 16KB pages.
8051 Microprocessor Industry 8051 Instruction set complaint with 3~5 cycles per instruction. Programmable 8/16/32 MHz clock Fast instruction fetching from XBI Interface 128 bytes and 2KB tightly-coupled SRAM 24 extended interrupt sources. Two 16-bit tightly-coupled timer
8042 Keyboard Controller 8 Standard keyboard commands processed by hardware Each hardware command can be optionally processed by firmware
Embedded Controller (EC) Five EC Standard Commands can be processed by hardware ACPI Specification 2.0 compliant Support customer command by firmware Programmable EC I/O port addressing (default 62h/66h)
Analog To Digital Converter (ADC) 6 built-in ADCs with 8-bit resolution. The ADC pins can be alternatively configured as General Purpose Inputs (GPI).
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Pulse Width Modulator (PWM) 5 built-in PWMs Selectable clock sources: 1MHz/64KHz/4KHz/256Hz. Configurable cycle time (up to 1 sec) and duty cycle.
Watchdog Timer (WDT) 32.768KHz input clock with 20-bit time scale. 8-bit watchdog timer interrupt and reset setting
General Purpose Timer (GPT) Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
General Purpose Wake-Up (GPWU) All General Purpose Input pins can be configured to generate interrupts or wake-up event.
General Purpose Input/Output (GPIO) All I/O pins are bi-direction and configurable All outputs can be optionally tri-stated All inputs equipped with pull-up, high/low active, edge/level trigger selection All GPIO pins are bi-direction, input and output. Max. 43 GPIOs
Power Management Sleep State: 8051 Program Counter (PC) stopped Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
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Chip Dimension Microprocessor Built-in SRAM 8051 Clock Flash Memory Range Flash I/F Clock ADC DAC Watch Dog Timer PWM External PS/2 devices GPIOs KB matrix scan FAN Controller General Purpose Timer SM Bus
HW HW HW KBC Standard Commands IKB Standard Commands EC Standard Commands
Power Consumption
KB3700 64-pin LQFP 2 10x10 mm 8051 2048 + 128 bytes 32 ~8 MHz (adjustable) 4M bytes (SPI) 65~32 MHz (adjustable) 6 N.A. 1 5 2 Max 43 N.A. N.A. 6 N.A. N.A. 8 N.A. 5 TBD (target 12mA) TBD (target 3mA in IDLE mode) TBD(target 500 uA in STOP mode)
KB3920 144-pin LQFP 20x20 mm 8051 2048 + 128 bytes 22~8 MHz 1M bytes(ISA), 2M bytes (SPI) 65/32 MHz (2 select 1) 4 4 1 4 3 Max 89 pins 18x8 2 6 2 Interfaces 1 Internal Controller 8 10 5 15 mA(in Normal RUN) 4 mA (in IDLE mode) 10 uA( in STOP mode)
2
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1.2 Block Diagram
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2. Pin Assignment and Description
2.1 Pin List
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name GPIOE0 GPIOE1 GPIOE2 GPIOE3 SERIRQ GPIO00 LFRAME# LAD3 GPIO01 GPIO02 LAD2 LAD1 VCC LAD0 GND GPIO03 GPIOE4 GPIOE5 GPIOE6 GPIOE7 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO0A GPIO0B GPIO0C GPIO0D GPIO0E GPIO0F GPIOE8 AD3 AD4 AD5 GPIO10 AD0 AD1 AD2 AVCC AGND GPIO11 GPIO12 GPIO11 GPIO12 PSCLK1 PSDAT1 PSCLK1 PSDAT1 GPIO10 GPIO03 GPIOE4 GPIOE5 GPIOE6 GPIOE7 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO0A GPIO0B GPIO0C GPIO0D GPIO0E GPIO0F GPIOE8 E51_TXD PLLCLK32 POR SCI# PWM0/E51_TXD PWM1/E51_CLK PWM2 PWM3 PWM4 E51_TMR0 E51_TMR1 ECRST# E51_INT0 E51_INT1 ECRST# E51_RXD PCIRST# PCICLK GPIO01 GPIO02 KBRST# PLLCLK_REF2 GPIO00 GA20 GPIO GPIOE0 GPIOE1 GPIOE2 GPIOE3 Alt. Output. Alt. Input Default Reset IOCELL BQC04HU BQC04HU BQC04HU BQC04HU BCC16H BQC04HU BCC16H BCC16H BQC04HU BQC04HU BCC16H BCC16H VCC BCC16H GND BCC16H BQC04HU BQC04HU BQC04HU BQC04HU BCC16H BQC04HU BCC16H BCC16H BCC16H BCC16H BCC16H BQC04HU BQC04HU BQC04HU BQC04HU BQC04HU BQC04HU IQA IQA IQA BQC04HU IQA IQA IQA AVCC AGND BQC04HU_10K BQC04HU_10K
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45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
GPIO13 GPIO14 GPIO15 GPIO16
GPIO13 GPIO14 GPIO15 GPIO16 GPIOEC GPIOED GPIOEE GPIOEF GPIO17 GPIO18 GPIO19 GPIO1A GPIO1B
PSCLK2 PSDAT2
PSCLK2 PSDAT2 TEST_CLK TP_CLK_TEST
BQC04HU_10K BQC04HU_10K BQC04HU BQC04HU BQC04HU BQC04HU BQC04HU BQC04HU
GPIOEC GPIOED GPIOEE GPIOEF GPIO17 GPIO18 GPIO19 GPIO1A GPIO1B SPIDI SPIDO SPICLK SPICS# VCC VCC18 GND
CLK CLK32MHz(8051) CLK16MHz(peri) CLK32MHz(WDT
TP_PLL_TEST TP_ISP_MODE TP_IO_TEST
BQC04HU BQC04HU BQC04HU BQC04HU BQC04HU BCC16H BCC16H BCC16H BCC16H VCC VCC18 GND
2.2 I/O Buffer Table
IO Name BQC04HU Descriptions Schmitt trigger, 2~4mA Output / Sink Current, with , Input / Output / Pull Up Enable Pull Up Enable Applications GPIO GPIO LPC Interface ADC, GPIN
BQC04HU_10K Schmitt trigger, 2~4mA Output / Sink Current, with , Input / Output / 10K BCC16H IQA 8~16mA Output / Sink Current , 5 V Tolerance, Input / Output Enable
Mixed mode IO, ADC Enable, with GPI, 2~4mA Sink Current, Input Enable
2.3 I/O Buffer Characteristic Table
Port IO Name BQC04HU BQC04HU_10K BCC16H IQA IO V V V V I V V V O V V V V OE V V V IE V V V V V V AE 5VTor PE 40K (typ.) 10K (typ.) Output / Sink Current 2~4mA 2~4mA 8~16mA
2.4 I/O Naming Convention
I IO Buffer Input O IO Buffer Output OE IO Buffer Output Enable IE IO Buffer Input Enable PE IO Buffer Pull High Enable AE IO Buffer Analog mode Enable(AE > OE) Q Schmitt Trigger H 5V Tolerance
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3. Pin Descriptions
3.1 Hardware trap
Hardware trap pins will latch the external signal levels at the rising edge of ECRST#. Either a High or Low value will be stored internally to serve as control signals as described below. For normal application, there is no application component required for selecting the normal mode because KB3700 build-in internal pull up resistor to select the right operation mode. After KB3700 booted, the pull up resistor may be disabled by GPIO register setting.
Pin name 64 Pins HW Strap Description
TP_TEST 48 (GPIO16)
TP_TEST: Clock Test Mode (for testing and ISP Mode) Low: Clock Test Mode Enable. (all internal logic will use GPIO15 as clock source) TP_PLL: PLL Test Mode (for testing) LOW: PLL Test Mode Enable
TP_PLL 53 (GPIO17) GPIO0F is Power On Reset output. HIGH: Normal operation (MUST, Power-On Default) TP_ISP: ISP Mode (for programming external SPI flash) TP_ISP 54 (GPIO18) HIGH: Normal operation in not ISP mode (MUST, Power-On Default) TP_IO: IO Test Mode TP_IO 55 (GPIO19) HIGH: Normal operation (MUST, Power-On Default) LOW: IO Test Mode Enable (for testing) LOW: ISP Mode Enable GPIO0E is PLL 32MHz clock output.
4. Module Descriptions
The following table gives the corresponding memory map for accessing. Each module will be described detail in the individual sections.
No. Abbreviation Flash XRAM GPIO KBC PWM GPT WDT LPC XBI PS2 EC GPWU Device Full Name Program space mapped to system BIOS Embedded SRAM General Purpose IO (include ADC, DAC) Keyboard Controller Pulse Width Modulation General Purpose 16-bit timer Watchdog Timer Low Pin Count X-BUS Interface PS2 Address Range 0000h~F3FFh F400h~FBFFh FC00h~FC7Fh FC80h~FC9Fh FE00h~FE1Fh FE50h~FE6Fh FE80h~FE8Fh FE90h~FE9Fh FEA0h~FECFh FEE0h~FEFFh FF00h~FF1Fh FF20h~FE7Fh 128 32 32 32 16 16 48 32 32 96 1K Size (Byte) 61K 2K
1 2 3 4 5 6 7 8 9 10 11 12
Embedded Controller (hardware EC Space) General Purpose Wake-up (hardware EC Space)
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4.1 Chip Architecture 4.1.1 Power Planes
There are 2 power planes in this chip. One is used for all logic, the other is used for Analog parts (ADC).
4.1.2 Clock Domains
There are 4 clock domain in KB3700. Flash chip interface clock. The clock default in 16MHz, and can be to 32MHz or 64MHz. 8051 / XBI use high clock (setting in CLKCFG, FF0Dh), ranges from 22~4MHz. WDT uses 32.768KHz clock. WDT default use internal 32KHz clock. The WDTCFG bit 7 options can switch WDT clock to external 32KHz clock oscillator. Other peripherals (GPWU, PWM,.) use low clock (setting in CLKCFG, FF0Dh), ranges from 8~2MHz.
4.1.3 Reset Domains
This chip builds in power on reset. There is also a input reset signal (ECRST#) for global reset. WDT reset can reset almost all logic, except WDT and GPIO modules. The WDT reset can be set to only reset 8051 by EC register (PXCFG, FF14h). There is additional 8051 reset source from EC register (PXCFG, FF14h).
4.2 GPIO 4.2.1 GPIO Functional Description
Multi-function pin Output Function Selection (FS) bit = 0, is set for GPIO Output Function, and FS bit = 1, is set for Alternative Output. The alternative input function is enabled by Input Enable register (IE), and is not affected by FS register. Offset Register Full Name Abbreviation Bit Attr Description Register
GPIOFS00 GPIOFS08 GPIOFS10 GPIOFS18 GPIOOE00 10 ~ 15 GPIOOE08 GPIOOE10 GPIOOE18 GPIOEOE0 GPIOEOE8 20 ~ GPIOD00 GPIOD08 7~0 R/W 7~0 R/W GPIO 00~1B Output Function Selection (0: GPO, 1: Alternative Output) 00h: GPIOFS00 for GPIO00~07 01h: GPIOFS08 for GPIO08~0F 02h: GPIOFS10 for GPIO10~17 03h: GPIOFS18 for GPIO18~1B GPIO 00~1B Output Enable (0: Output Disable, 1: Output Enable) 10h: GPIOOE00 for GPIO00~07 11h: GPIOOE08 for GPIO08~0F 12h: GPIOOE10 for GPIO10~17 13h: GPIOOE18 for GPIO18~1B 14h: GPIOEOE0 for GPIOE0~7 15h: GPIOEOE8 for GPIOE8~F (GPIOE9~A is N.A.) GPIO 00~1B Data Output 7~0 R/W 20h: GPIOD00 for GPIO00~07 0 0 0 0 0 0 FC 0 FC 0 0 0 0 FC
Def Bnk
00 ~ 03
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21h: GPIOD08 for GPIO08~0F 22h: GPIOD10 for GPIO10~17 23h: GPIOD18 for GPIO18~1B 24h: GPIOED0 for GPIOE0~7 25h: GPIOED8 for GPIOE8~F (GPIOE9~A is N.A.)
0 0 0 0 0
GPIOIN00 GPIOIN08 30 ~ 36 GPIOIN10 GPIOIN18 GPIOEIN0 GPIOEIN8 GPIADIN GPIOPU00 40 ~ 45 GPIOPU08 GPIOPU10 GPIOPU18 GPIOEPU0 GPIOEPU8 50 ~ 53
GPIO 00~1B Input Status 30h: GPIOIN00 for GPIO00~07 31h: GPIOIN08 for GPIO08~0F 32h: GPIOIN10 for GPIO10~17 7~0 R/W 33h: GPIOIN18 for GPIO18~1B 34h: GPIOEIN0 for GPIOEIN0~7 35h: GPIOEIN8 for GPIOEIN8~F (GPIOEIN9~A is N.A.) 36h: GPIAD0 for GPIAD0~5 GPIO 00~1B Pull Up Enable 40h: GPIOPU00 for GPIO00~07 41h: GPIOPU08 for GPIO08~0F 7~0 R/WC 42h: GPIOPU10 for GPIO10~17 1 43h: GPIOPU18 for GPIO18~1B 44h: GPIOEPU0 for GPIOE0~7 45h: GPIOEPU8 for GPIOE8~F (GPIOE9~A is N.A.) 0 20 E0 03 0 0 0 0 0 0 0 20 E0 03 0 0 0 FC FC FC 0 FC
GPIOOD00 GPIO 00~1B Open Drain Enable 50h: GPIOOD00 for GPIO00~07 GPIOOD08 51h: GPIOOD08 for GPIO08~0F 7~0 R/W GPIOOD10 52h: GPIOOD10 for GPIO10~17 GPIOOD18 53h: GPIOOD18 for GPIO18~1F GPIO 00~1B Input Enable GPIOIE00 60h: GPIOIE00 for GPIO00~07 61h: GPIOIE08 for GPIO08~0F 62h: GPIOIE10 for GPIO10~17 7~0 R/W 63h: GPIOIE18 for GPIO18~1B 64h: GPIOEIN0 for GPIOE0~7 65h: GPIOEIN8 for GPIOE8~F (GPIOE9~A is N.A.) 66h: GPIAD0 for GPIAD0~5 GPIO MISC 7~2 RSV
60 ~ 66
GPIOIE08 GPIOIE10 GPIOIE18 GPIADIE
0 Select GPIO07 as E51_CLK. Select GPIO06 as E51_TXD. 0 0 FC
70
GPIOMISC
1 0
R/W R/W
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4.2.2 GPIO Input / Output Control Structure
GPIOFS Alt. Output Enable GPIOOD 0 GPIOOE 0 1 1
GPIOD Alt. Output
0 1
OE Output Buffer
IO PIN
GPIOFS Pull up Enable PE GPIOPIN Input Buffer IE Alt Input IE
PE
GPIOPIN
Input Buffer
INPUT PIN
Alt Input
IE
GPIOFS Alt. Output Enable GPIOOD 0 GPIOOE 0 1 1
GPIOD Alt. Output
0 1
OE OUTPUT PIN
Output Buffer
GPIOFS
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4.3 KBC 4.3.1 KBC Functional Description
a. IO 60h: KBC Data Input Register (KBDIN): When the host writes I/O ports 60h and 64h, the data is stored in KBDIN. At the same time, the input buffer full flag (IBF bit in KBSTS) is set. The input data stored in KBDIN is directly fetched by the command processing logic and IBF is also cleared automatically. b. I/O 60h: KBC Data Output Register (KBDOUT) The data responded to the host is generated by the hardware circuit. The data is pushed into KBDOUT and the output buffer full flag (OBF bit in KBSTS) is set automatically. KB3700 can be configured to generate interrupts to the host when OBF is set. OBF is automatically cleared after that the host reads KBDOUT (through I/O port 60h). c. I/O 64h: KBC Status Register (KBSTS) The host read it through I/O port 64h. The bit format of this register is as follows: Status Bit
7 6 5 4 3 2 1 0
Name
Parity Error General Timeout Aux OBF Uninhibited A2 System Flag IBF OBF
Description
PS/2 Bus parity error. PS/2 Bus timeout. KBDOUT data is from PS/2 auxiliary device. Keyboard is not inhibited. Address of the previous write cycle. POST of the system is finished. Input Buffer Full flag. Output Buffer Full flag.
d. Hardware Processed Command The following standard commands are processed by hardware directly. Value
20h
Command
Read Command Byte Read the command byte of KBC
Description
Response Command byte Read the input port of 8042 P1. Because there is no real 8042 in the chip, this command just emulates the function. Response Always return 00h Read the output port of 8042 P2. Because there is no real 8042 in the chip, this command just emulates the function. Response Bit1 is the status of GA20 Write the output port of 8042 P2. Because there is no real 8042 in the chip, this command will just emulate the function and set/clear GA20 based on data bit 1. Argument Bit1 is the status of GA20 Write data into KBDOUT as if it comes from the keyboard. Argument Keyboard data Write data into KBDOUT as if it comes from the auxiliary device. Argument Auxiliary data Read the test inputs T0 and T1 of 8042. Because there is no real 8042 in the chip, this command will just emulate the function. Response Always return 00h This command generates a 6us low pulse on KBRST#.
C0h
Read P1
D0h
Read P2
D1h
Write P2
D2h D3h
Write KB Output Buffer Write AUX Output Buffer
E0h
Read Test Input KB Reset
FEh
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4.3.2 KBC Registers Descriptions (Base Address = FC80h, 32 bytes)
Register Abbreviation Register Full Name Bit Attr Description KBC Command Byte (KBC command 20h/60h) 7 RSV 6 R/W Scan Code Conversion 5 R/W Auxiliary Device Disable 4 R/W Keyboard Device Disable 3 R/W Inhibit Override 2 R/W System Flag 1 R/W IRQ12 Enable 0 R/W IRQ1 Enable KBC Configuration 7 R/W Keyboard Lock Enable 6 R/W Fast Gate A20 Control 5~4 RSV 3 R/W Keyboard Lock 2 RSV IBF Interrupt Enable. This bit enables KBC to generate interrupt to the 8051 at the rising edge of 1 R/W IBF, when the KBC command being received will be bypassed to firmware for processing. 0 R/W OBF Interrupt Enable. This bit enables KBC to generate interrupt to the core processor at the falling edge of OBF. Def Bnk
Offset
80h
KBCCB
40
FFh
81h
KBCCFG
0
FFh
82h
KBCIF
83h
KBCHWEN
84h 85h
KBCCMD KBCDAT
86h
KBCSTS
KBC Interrupt Pending Flag 7~3 RSV KBC firmware mode in processing flag, 2 R/WC1 Exit KBC firmware mode and re-enable hardware mode by writing 1 1 R/WC1 IBF interrupt pending flag 0 R/WC1 OBF interrupt pending flag KBC Hardware Command Enable 7 R/W FEh: KB Reset command processed by hardware 6 R/W E0h: read test input command processed by hardware 5 R/W D3h: write AUX output buffer 4 R/W D2h: write KB output buffer 3 R/W D1h: write P2 command processed by hardware 2 R/W D0h: read P2 command processed by hardware 1 R/W C0h: read P0 command processed by hardware 0 R/W 20h: read command byte processed by hardware KBC Command Buffer 7~0 RO The data written to I/O port 64h will be stored in this register. KBC Data Input / Output Buffer Writing to this register will cause the output buffer full flag OBF to be set. The 7~0 R/W host can read this register through I/O port 60h. KBC Host Status Parity Error. 7 R/W When PS/2 protocol has a parity error, this bit will be set to high. This bit is also used as port indicator for PS/2 active multiplexing mode. TimeOut. 6 R/W When PS/2 protocol has a timeout error, this bit will be set to high. This bit is also used as port indicator for PS/2 active multiplexing mode. 5 R/W Auxiliary Data Flag 4 RO Uninhibited 3 RO Address (A2) 2 RO System Flag 1 R/WC1 IBF, write IBF = 1 to clear IBF 0 R/WC1 OBF, write KBCDAT will set OBF to 1. Write OBF = 1 to clear OBF
0
FFh
0
FFh
0 0
FFh FFh
0
FFh
4.4 PWM
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4.4.1 PWM Functional Description
There are 5 PWM channels with 8-bit resolution.
PWM2,3,4 are controlled by the same configuration register in PWMCFG2 with 6 bit clock prescaler. The PWM Cycle Length defines the PWM cycle time in setting clock source. The PWM High Period Length defines the PWM pulse high period length, should be less than Cycle Length . Here is the formula of PWM duty cycle. Duty Cycle = (PWM High Period Length+1)/(PWM Cycle Period Length+1) *100% Please note the following case: Condition H>C H and C=0x00 H=0x00, C=0xFF H=0xFF, C=0x00 PWM Output Always 1 (High) Always 1 (High) A short pluse Always 1 (High)
1. Where H means High Period Length (PWMHIGH) ; C means Cycle Period Length (PWMCYCL) Please refer to the following PWM register description. 2. To force PWM output Low, please force this pin to be GPIO mode and output low.
4.4.2 PWM Registers Descriptions (Base address_FE00h, 16 bytes)
Offset Register Abbreviation Register Full Name Bit Attr Description Def 0 Bnk
PWM Configuration PWM1 clock source selection 0: 1us 1: 64us 2: 256us 3: 4ms
7~6
R/W
0
5 0 PWMCFG 4
RSV R/W PWM1 Enable PWM0 clock source selection 0: 1us 1: 64us 2: 256us 3: 4ms
0 0 FE
3~2
R/W
0
1 0 1 PWMHIGH0 PWMCYCL0
RSV R/W PWM0 Enable
0 0 0 0 0 FE
PWM0 High Period Length 7~0 R/W The High Period Length of PWM should be small than Cycle Length.
2
PWM0 Cycle Length 7~0 R/W The Cycle Length of a PWM cycle, includes high and low Length.
FE
3
PWMHIGH1
PWM1 High Period Length 7~0 R/W The High Period Length of PWM should be small than Cycle Length.
0 0 0
FE
4 5 6 7
PWMCYCL1 PWMCFG2 PWMCFG3 PWMCFG4
PWM1 Cycle Length 7~0 R/W The Cycle Length of a PWM cycle, includes high and low Length.
FE FE
PWM Configuration 2, 3, 4 7 R/W PWM2, 3, 4 Enable PWM prescaler Clock Select 0: peripheral clock(by clock setting in EC CLKCFG(FF0Dh) 1: 1MHz clock(recommend set this bit to fixed clock in different clock setting)
0
6
R/W
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5~0
R/W
The 6-bit prescaler for PWM by selected clock.
8 9 A B C D
PWMHIGH2 PWMHIGH3 PWMHIGH4 PWMCYC2 PWMCYC3 PWMCYC4
PWM2, PWM3, PWM4 High Period Length 0 7~0 R/W High byte (8 bits) FE
PWM2, PWM3, PWM4 Cycle Length 0 7~0 R/W High byte (8 bits) FE
4.5 GPT 4.5.1 GPT Functional Description
There are 4 GPTs in KB3700. 2 GPTs are 16-bit, and the other 2 are 8-bit. ALL base on 30.516 us (32.768KHz) clock, and are independent on clock setting in EC register. GPT0 and GPT1 are 8-bit timer. GPT2 and GPT3 are 16-bit timer.
4.5.2 GPT Register Descriptions (Base address = FE50h, 16 bytes)
Offset Register Abbreviation Register Full Name Bit Attr Description Def Bnk
GPT Configuration 7~5 4 50 GPTCFG 3 2 1 0 RSV R/W R/W R/W R/W R/W GPT test mode, the GPT base clock will be system clock Enable GPT3 counting and GPT3 interrupt Enable GPT2 counting and GPT2 interrupt Enable GPT1 counting and GPT1 interrupt Enable GPT0 counting and GPT0 interrupt 0 0 0 FE
GPT Pending Flag 7 6 5 51 GPTPF 4 3 2 1 0 53 GPT0 WO WO WO WO GPT3 write 1 to restart GPT2 write 1 to restart GPT1 write 1 to restart GPT0 write 1 to restart
FE
R/WC1 GPT3 Interrupt Pending Flag R/WC1 GPT2 Interrupt Pending Flag R/WC1 GPT1 Interrupt Pending Flag R/WC1 GPT0 Interrupt Pending Flag 0 0 0 0 0 0 0 0 FE
GPT0 Count Value After GPT0 reach this value and interrupt will occur and GPT0 reset and counting from zero again. GPT1 Count Value 7~0 R/W After GPT1 reach this value and interrupt will occur and GPT1 reset and counting from zero again. GPT2 Count Value 7~0 R/W After GPT2 reach this value and interrupt will occur and GPT2 reset and counting from zero again. GPT3 Count Value 7~0 R/W 7~0 R/W After GPT3 reach this value and interrupt will occur and GPT3 reset and counting from zero again.
55
GPT1
FE
56 57 58 59
GPT2H GPT2L GPT3H GPT3L
FE
FE
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4.6 SPI/ISP Device Interface 4.6.1 SPI/ISP Functional Description
SPI includes several functions, as follows, 1. 2. 3. 4. 2 code segments for 8051. Performance improvement: instruction sustain fetch, and pre-fetch flash write protection ISP should be enabled by hardware trap pin during hardware reset. th st 1. The ISP packet format: If bit 7 of 1 byte is 1 means write packet, otherwise means read. 1. ISP write : [1000_XXXX] [WDATA] 2. ISP read : [ 0000_XXXX] [RDATA]
4.6.2 SPI Registers Descriptions (Base address = FE70h, 16 bytes)
Offset Register Abbreviation Register Full Name Bit 7 5~0 A1h XBISEG1 7 5~0 A4h XBIXIOEN 7~0 7 6 A5h XBICFG 4 3 2-0 7 6 5 A6h XBICS 4 3 2 1 0 RO R/W R/W R/W R/W R/W R/W RSV R/W R/W R/W Enable STOP and IDLE state let XBI state machine go to initial state. Enable EHB Fast Access A enhanced option to speed up EHB performance. Select XIO select to SELIO# (set 1) or SELIO2# (set 0). Enable Reset 8051 and XBI Segment Setting (XBISEG0~3) reset XBI registers A0~A3h(bank select) when WDT / Wakeup / EC Register reset 8051. 04h FEh Enable WR# to flash Enable extend SELMEM# and SELE51# 1 clock for RD# and WR# setup and hold time. RD# and WR# command clock count= [2:0] Enable E51CS# address 16~64K Attr R/W R/W R/W R/W R/W R/W R/W Description Enable 8051 Code Space SEG0 Remapping XBI address = XBISEG0*16k + 8051 address [13:0] Enable 8051 Code Space SEG1 Remapping XBI address = XBISEG1*16k + 8051 address [13:0] Enable related XIO channel (Only 4 channels) Enable XBI BUS IO buffer pull up Enable 8051 sustain instruction fetch 07h FEh 0 FEh 0 FEh Def Bnk
8051 Address Segment 0 (0000h-3FFFh) Mapping Configuration A0h XBISEG0 0 FEh
8051 Address Segment 1 (4000h-7FFFh) Mapping Configuration
XBI XIO Enable XBI Configuration
XBI E51CS# Configuration
A7h
XBIWE
XBI Write Enable Write 00h to reset all rest mode. 7-0 WO Write A3h to enable flash write cycles. Write C5h to SRAM test. XBI SPI Flash Address 7-0 SPIA0 = A7~0 SPIA1 = A15~8 SPIA2 = A22~16 XBI SPI Flash Output / Input Data R/W 7-0 R/W Output(write SPIDAT) / Input(read SPIDAT) data to/from SPI flash interface.
0
FEh
A8h A9h AAh
SPIA0 SPIA1 SPIA2
0
FEh
ABh ACh
SPIDAT SPICMD
0 0
FEh FEh
XBI SPI Flash Command
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7-0
R/W
The issued SPI command to SPI flash chip. The write to this register will start the SPI accessing, so that the SPIA2~0 and SPIDAT should be ready before SPICMD is written. SPICMD support command : 01h Write Status Register 02h Byte Program 03h Read 04h Write Disable 05h Read Status Register 06h Write Enable 0Bh High Speed Read 20h Sector Erase (SST) 50h Enable Write Status Register (SST) 52h Block Erase (SST) 60h Chip Erase (SST) C7h Chip Erase (PCM, NexFlash) D7h Sector Erase (PCM) D8h Block Erase (PCM, NexFlash)
SPI Flash Configuration / Status 7 6 R/W R/W Enable DPLL for ISP mode SPI Flash Offset Read Command Enable. (32h) SPI Flash Short Read Command Enable. (31h, 30h) A23~16 will not be used. A16 = 1 if 31h command. A16=0 if 30h command. The address phase will only contain A15~0, and don't care fast mode enable bit of SPICFG bit 2. SPICS# force output low. After set this bit, the protocol will control by firmware. The SPICMD will output to SPI BUS each time the write operation to SPICMD. The SPIDAT will store the read operation data from SPI BUS. SPICMD write enable. Enable SPICMD write action to start SPI flash protocol accessing. Enable SPI Flash Dummy Byte for Read Command. Enable SPI flash read by 8051 instruction by Fast Mode (High Speed Read) 0Bh command. SPI flash accessing in progress status. Use this bit to check if the SPI accessing is finished or not. Enable SPICMD follow with a SPI status check until Busy flag cleared. Output data to SPI flash interface. Reserved. SPI Offset / Short Read Command high nibble. 0 FEh 00 FEh
5
R/W
ADh
SPICFG
4
R/W
3 2 1 0 AEh SPIDATR 7-0 7-4 3-0
R/W R/W RO R/W RO RSV R/W
SPI Flash Output Data for Read Compare SPI Flash Configuration 2
AFh
SPICFG2
0
FEh
4.6.3 ISP Registers Descriptions (8 bytes)
Offset 0 1 2 Register Abbreviation ISPIA0 ISPIA1 ISPA2 Register Full Name Bit Attr Description Def
ISP SPI Flash Address SPIA0 = A7~0 7-0 R/W SPIA1 = A15~8 SPIA2 = A22~16 ISP SPI Flash Output / Input Data 7-0 R/W Output(write SPIDAT) / Input(read SPIDAT) data to/from SPI flash interface.
0
3 4
ISPDAT ISPCMD
0 0
ISP SPI Flash Command
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7-0
R/W
The issued SPI command to SPI flash chip. The write to this register will start the SPI accessing, so that the SPIA2~0 and SPIDAT should be ready before SPICMD is written. SPICMD support command : 01h Write Status Register 02h Byte Program 03h Read 04h Write Disable 05h Read Status Register 06h WriteEnable 0Bh High Speed Read 20h Sector Erase (SST) 50h Enable Write Status Register (SST) 52h Block Erase (SST) 60h Chip Erase (SST) C7h Chip Erase (PCM, NexFlash) D7h Sector Erase (PCM) D8h Block Erase (PCM, NexFlash)
ISP SPI Configuration / Status 7 ~ 5 R/W 4 5 ISPCFG R/W SPICS# force output low. After set this bit, the protocol will control by firmware. The SPICMD will output to SPI BUS each time the write operation to SPICMD. The SPIDAT will store the read operation data from SPI BUS. SPICMD write enable. Enable SPICMD write action to start SPI flash protocol accessing. SPI flash read by 8051 instruction by Fast Mode (High Speed Read) 0Bh protocol. SPI flash accessing in progress status. Use this bit to check if the SPI accessing is finished or not. Enable SPICMD follow with a SPI status check until Busy flag cleared. Output data to SPI flash interface. 0
3 2 1 0
R/W R/W RO R/W RO
0
6
ISPDATR
ISP SPI Flash Output Data for Read Compare 7-0
ISP SPI ISP RS232 Baud Rate Setting In ISP mode, 8051_SFR(SCON2) always 0 write this reg to program 8051_SFR(SCON3) Default: SCON3 = 0x89, baud-rate = 57600 (while 8051 clk = 8Mhz) set SCON3 = 0x45 for baud-rate =115200 (while 8051 clk = 8Mhz)
7-0 7 ISPSCON3 *** 7~4
WO
0
RSV Reserved 3
3~0
RO
SPI Offset / Short Read Command high nibble.
*** Please note, ISPSCON3 register gives different bitmap definition according to access. For write operation, please refer to the yellow part, and read operation please refer to the green part.
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4.7 WDT 4.7.1 WDT Functional Description
WDT timer clock uses 32.768 KHz oscillator clock and base unit is 64ms. WDT register can only be reset by power on reset and ECRST#. WDT range is between 64 ms to 16 seconds. WDT reset time is between 128ms to 32 seconds. WDT reset can reset all logic in the chip, except GPIO registers. Thus, the GPIO setting can be preserved after WDT reset occurred. The WDT reset can optionally be set only to reset 8051 logic in EC register space.
4.7.2 WDT Registers Descriptions (Base address = FE80h, 16 bytes)
Register Abbreviation Register Full Name Def Bnk Bit Attr Description
Offset
WDT Configuration WDT Extended Bits Enable 0: WDT is 20-bit timer (normal setting). 1: WDT is 24-bit timer (setting for PLLLOW in STOP mode). If EC CLKCFG.7 (PLLLOW Enable) is set, the WDT clock will become PLL output clock automatically. Set this bit to 1 before enter STOP mode to let WDT become 24-bit timer by 1~2MHz PLL output clock. Force to disable WDT by writing 1001b to this field. Write 1011b to set WDT be shorter timer. (Enable WDT shorter test mode). Write 1111b to disable WDT shorter test mode. WDT Clock Selection for testing 0: WDT clock is from WDT Clock Selection 2 (normal setting). 1: WDT clock is PLL output / 2 (i.e. 16MHz as PLL output 32MHz, maybe stopped at STOP mode. This option is only for testing). Enable WDT interrupt (WDT reset warning) Enable WDT reset, and reset WDT timer, the WDT timer and 2 pending flags will be reset and count from zero again. If the WDT and reset after a interrupt occurred, the next interrupt will occurred after 16 seconds.
7
R/W
6~3 80 WDTCFG
R/W
0
FE
2
R/W
1
R/W
0
R/W
WDT Pending Flag 7~5 81 WDTPF 1 RSV
R/WC1
WDT interrupt pending, WDT half timeout flag. If this bit is set, the following WDT timeout event will cause a WDT reset signal to system. WDT reset event pending flag (the last WDT reset was ever happened), WDT reset will assert if WDT count to WDT and WDT interrupt is pending.
0
FE
0
R/WC1
WDT 8-bit Count Value (for Watch Dog Timer reset system) 82 WDTCNT 7~0 R/W After WDT counts to this value the half of WDT/2 , the interrupt will occur. The WDT timer unit is 64ms. 0 FE
WDT Counter Value(for testing) 83 84 85 WDT19_12 WDT11_04 WDT03_00 0 RO Only for WDT testing. 0 FE
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4.8 LPC 4.8.1 LPC / FWH Functional Description
There are 5 address ranges on LPC/FWH interface will be responded by KB3700 EC. 1. Keyboard controller I/O ports: 60h, 64h 2. Embedded controller I/O ports: 2 programmable I/O ports (default 62h/66h and 68h/6Ch) 3. EC I/O Index and Data Ports: Through which the system host can access KB3925 internal registers more efficiently than through EC commands F0h/F1h. The EC I/O Index and Data Ports are two 8-bit registers with base address defined in FE92h and FE93h. Default Index Port ={002Dh, 002Eh}, Data port =002Fh. 4. LPC/FWH memory access. 5. Extended LPC write byte: can be programmed to port 80 and generate interrupt to 8051.
4.8.1.1 LPC Decoding IO Ports
The keyboard I/O ports are 60h/64h, while the EC I/O ports are programmable in LPCEBA (FE98h, FE99h). The enable/disable of I/O ports decoding on LPC bus can be configured individually via register LPCCFG (FE95h).
4.8.1.2 LPC Decoding Memory Space
Memory Setting (LPCFWH bit 7,6) 00 Memory Size 256k (default) Decoded BIOS Address 000C_0000 - 000F_FFFF FFFC_0000 - FFFF_FFFF 000C_0000 - 000F_FFFF FFF8_0000 - FFFF_FFFF 000C_0000 - 000F_FFFF FFF0_0000 - FFFF_FFFF 000C_0000 - 000F_FFFF FFE0_0000 - FFFF_FFFF
01
512k
10
1M
11
2M
4.8.2 LPC Registers Descriptions (Base address = FE90h, 16 bytes)
Offset Register Abbreviation Register Full Name Bit Attr Description Def Bnk
LPC Status (Internal Use Only) 7~2 90h LPCSTAT 1 0 91h LPCSIRQ RSV R RSV 0 FEh LPC SIRQ is current in quiet/continuous mode 1: quiet mode 0: continuous mode 0 FEh
LPC SIRQ Configuration 7 6 R/W R/W Enable don't care A22 of FWH memory cycle Enable SCI SIRQ
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5 4
R/W R/W
Enable IRQ12 SIRQ Enable IRQ1 SIRQ SCI Serial IRQ channel 0: no 1:IRQ1 2:SMI# 3:IRQ3 ... 15:IRQ15
3 - 0 R/W
92h 93h
LPCIBAH LPCIBAL
LPC Index IO Base Address 7 - 0 R/W EC index mode IO port base address. The address should be 4 bytes align.
FFh 2Ch 0
FEh
LPC FWH Configuration Memory Size (both for LPC Memory and FWH) 00: 256KB 01: 512KB 10: 1MB 11: 2MB Enable FWH memory cycle Enable FWH IDSEL check FWH ID Enable LPC memory write protection (including FWH) Enable index IO port Enable KBC IO port: 60h, 64h Enable Extended IO port (IO write only) Enable EC IO port Enable LPC memory cycle (not including FWH) Enable SIRQ fixed in continuous mode Enable LPC CLKRUN#
7 - 6 R/W 94h LPCFWH
0
FEh
5 R/W 4 R/W 3 - 0 R/W 7 6 5 95h LPCCFG 4 3 2 1 0 96h 97h 98h 99h 9Ah LPCXBAH LPCXBAL LPCEBAH LPCEBAL LPC_2EF R/W R/W R/W R/W R/W R/W R/W R/W
LPC Configuration
80h
FEh
LPC Extended IO Base Address Only LPC byte write is supported LPC EC IO Base Address LPCEBAL bit 0 and bit 1 are not ignored for decoding Address 2EF decoding and control in LPC(Internal Use Only)
00h 80h 00h 62h B0h
FEh
FEh
FEh
Address 2EF decoding and control in LPC(NOTE: Internal Use Only) 7~4 3 9Ah LPC_2EF 2 1 0 9Bh R/RW R/W R/W RSV R Decode IO(0x002F): 0:read_io_2f, 1:write_io_2f Decode IO(0x002F) r/w cycle, should cleared by FW Write 1 to clear the value. Enable interrupt of read/write_io(2f) Enable decode read_io(2e), read/write_io(2f)
7~0 LPC_2F_DATA LPC68CFG
RSV
9Ch 9Dh
LPC_2F_DATA 7~0 RO Read data for read_cycle_IO(2F) 0
LPC 68/6Ch IO Configuration 7 6~2 R/W RSV Enable LPC I/F decode IO 68h, 6Ch
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1 0
R/W R/W
IBF Interrupt Enable OBF Interrupt Enable IO68/6Ch Busy Flag. The host is accessing the 68/6Ch IO. If this bit is set, the software doesn't get the right of the 68/6Ch. This flag can be clear by write 6Ch = FFh. A2 (address bit 2) of the last write 68/6C IO.
LPC 68h IO Command Status Register 7 6 9Eh LPC68CSR 5~4 3 2 1 0 9Fh LPC68DAT R/WC1 IBF Interupt Pending Flag R/WC1 OBF Interrupt Pending Flag. R/WC1 IBF R/WC1 OBF 0 FEh RO RO
LPC 6Ch IO Data Register 7-0 R/W The data byte of current memory cycle.
4.9 PS / 2 Interface 4.9.1 PS/2 Functional Description
The PS2 Controller supports byte-level programming interface to PS2 devices, including IKB module. A PS/2 TX action will be pending if a PS/2 RX is active. After PS/2 RX is completed (received a byte), the TX will start transmitting to the specified port. PS2 Controller will maintain the PS2 channel's integrity in byte level. But the input signal should not be floating not drive low if the PS2 channel is not used (MUST set correct GPIOFS and PS2CFG Enable PS2 ports).
4.9.2 PS2 Registers Descriptions (Base Address = FEE0h, 32 bytes)
Offset Register Abbreviation Register Full Name Bit Attr Description Def Bnk 0 0 Enable PS2 port 2(TX/RX), disable will let PSCLK2 in low state Enable PS2 port 1(TX/RX), disable will let PSCLK1 in low state 0 0 0 Enable interrupt of PS2 parity error Enable interrupt of PS2 TX timeout (clock >180us or request > 100ms) Enable interrupt of PS2 transmitted byte Enable interrupt of PS2 received byte 0 0 0 0 0 0 Received Byte Port is PS2 port 2 Received Byte Port is PS2 port 1 0 0 0 0 0 0 FE FE
PS2 Configuration 7 6 5 E0 PS2CFG 4 3 2 1 0 E1 PS2PF RSV R/W R/W RSV R/W R/W R/W R/W
PS2 Pending Flag 7 6 5 4 3 2 1 RSV RO RO RSV R/WC1 Interrupt Pending Flag of PS2 parity error R/WC1 Interrupt Pending Flag of PS2 TX timeout R/WC1 Interrupt Pending Flag of PS2 transmitted byte
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0
Interrupt Pending Flag of PS2 received byte, R/WC1 Clear this bit will also clear bit 4~7 and RX timeout flag for receiving next byte from a PS/2 device. PS2 Transmitter / Receiver Control 7 6 5 RSV R/W R/W RSV WO WO RO R/W Write 1 to force reset PS2 transmitter state, for emergency usage. Write 1 to force reset PS2 receiver state, for emergency usage. Flag of PS2 RX timeout Enable PS2 transmit data port, This bit should be set for transmitting a byte (write to PS2DATA) to a device. Write to start a byte transmitting to a PS2 device, and clear previous state. Read to get the data of received byte for a PS2 device. Reserved. PS2 protocol waiting time enable 1. Wait 16 us after PS/2 bus is idle (clock-high,data-high), when PS/2 module transmits the command to divice. 2. In the protocol of PS/2 module to device, the clock is low first then the data waits 16 us to be low. PS2CLK / PS2DAT input debounce enable. (0: 1 us; 1: 2 us) Transmit Byte Port is PS2 port 2 Transmit Byte Port is PS2 port 1
0 0 0 0 0 0 0 0 0 0 0 0 FE FE
E2
PS2CTRL
4 3 2 1 0
PS2 DATA E3 PS2DATA 7~0 R/W
PS2 Configuration 2 7-2 E4 PS2CFG2 RSV
1
R/W
0
R/W
PS2 Pin Input Status 7 6 5 E5 PS2PINS 4 3 2 1 0 RSV R/W R/W RSV RSV R/W R/W RSV PS2 Port 2 Data PS2 Port 1 Data PS2 Port 2 Clock PS2 Port 1 Clock
PS2 Pin Output 7 6 5 E6 PS2PINO 4 3 2 1 0 RSV R/W R/W RSV RSV R/W R/W RSV PS2 Port 2 Data PS2 Port 1 Data PS2 Port 2 Clock PS2 Port 1 Clock
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4.10 EC
4.10.1 EC Functional Description
There are 7 parts in EC:
* * * * *
Hardware EC Commands EC Index IO mode EC Extended IO Write SCI Generation Misc functions
4.10.1.1 Hardware EC Commands
EC standard commands as described in ACPI 2.0 spec. are processed by hardware logic directly without the intervention of firmware. For EC extended commands, EC controller will forward them to 8051 and thereby processed by the firmware. The data and command/status ports are default to 62h and 66h respectively, and can be optionally mapped to other I/O address space by KBC command 61h.
4.10.1.2 EC Status Register
To read EC Status IO port register is described as follows:
Status Bit 7 6 Name Reserved Reserved Not used. Not used. This bit is set to 1 by the EC to indicate that there is/are a/more SCI event(s) in the SCI queue. The system upon detecting this bit being set should thereafter query the SCI event queue (by issuing EC command 84h) to obtain the SCI ID number. EC standard commands (80h,81h,82h,83h,84h) being received and completed by the EC will not cause the SCI bit to be set. The Burst Enable flag. 1=Enabled. 0=Disabled. Description
5
SCI
4 3 2 1 0
Burst Enable
1=Previous access port is command port (EC_CMD/EC_STS). Command or Data Flag 0=Previous access port is data port (EC_DAT). Reserved IBF OBF Not used. Input Buffer Full flag. Output Buffer Full flag.
4.10.1.3 EC Command Register
There are 7 valid EC Commands for EC command register (write IO 66h); other values are "don't care" by EC if being written.
Value 80h 81h 82h 83h 84h Others Command EC Read EC Write EC Burst Enable EC Burst Disable EC Query Firmware Command Description Read operation for an internal register in EC Space. Write operation for an internal register in EC Space. Enable EC burst operation mode. Disable EC burst operation mode. Query the SCI event queue. No responded from hardware EC. Firmware EC commands.
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4.10.1.4 EC Command Program Sequence
Command Name Programming Sequence Write EC_CMD with 80h (66h=80h) Wait SCI for IBF=0 Write address byte to EC_DAT (62h=EC address) Wait SCI for OBF=1 Read EC_DAT with data in (read data = 62h) Write EC_CMD with 81h (66h=81h) Wait SCI for IBF=0 Write address byte to EC_DAT (62h=EC address) Wait SCI for IBF=0 Write data byte to EC_DAT (62h = write data) Wait SCI for IBF=0 Write EC_CMD with 82h (66h=82h) Wait SCI for OBF=1 Read EC_DAT with 90h(Burst ACK) Write EC_CMD with 83h (66h=83h) Wait SCI for IBF=0 Write EC_CMD with 84h (66h=84h) Wait SCI for OBF=1 Read EC_DAT with SCI ID number (read data = 62h).
Command Byte
80h
Read EC
81h
Write EC
82h 83h 84h
Burst Enable Burst Disable Query EC
4.10.1.5 EC Index IO Mode
You may use EC Index IO mode to access the KB3925 register space (F400h ~FFFFh). The EC Index IO base is set in LPC register FE92h, FE93h. The base address + 1 is index high byte address. The base address + 2 is index low byte address. The base address + 3 is data port for reading from or writing to KB3925 internal register space. For example, set the base address in FE92h=00h, FE93h = 2Ch. The system IO write set 002Dh = FFh, 002Eh = 01h. The read / write to 002Fh will read / write ECFV register (FF01h).
4.10.1.6 SCI Generation
Most interrupts generated from KB3925 internal modules are connected to the 8051 core and are optionally to generate a SCI event. Each SCI has an associated SCI Enable and SCI Flag bits in EC Space 05h~0Ah. The three extended interrupt ports of 8051, each supporting 8 interrupt channels, can accommodate totally 24 interrupt channels. The pulse-width of SCI is adjustable by setting SCICFG (default is low-active with 250ns pulse-width). Setting ECCFG bit 0=1 (default=0, enabled) to disable the generation of SCI. In addition to the 24 SCI events generated by KB3925 internal hardware logic, 8051 firmware or system BIOS can also generate a SCI event by writing the desired SCI ID into SCID register (0Bh) in EC space. The SCID should be first enabled in ECCFG bit3. The SCI IDs are defined as follows.
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4.10.1.7 SCI ID Table
Name Nothing PxI N.A. N.A. N.A. N.A. N.A. N.A. N.A. WDT RSV PS2 KBC RSV LPC ECFW SCID RSV RSV RSV P0I.0 P0I.1 P0I.2 P0I.3 P0I.4 P0I.5 P0I.6 P0I.7 P1I.0 P1I.1 P1I.2 P1I.3 GPT0 GPT1 GPT2 GPT3 EXTWIO P1I.4 P1I.5 P1I.6 P1I.7 P3I.0 Not used. Indicates a General Purpose Timer 0 event. Indicates a General Purpose Timer 1 event. Indicates a General Purpose Timer 2 event. Indicates a General Purpose Timer 3 event. Indicates a Write Extended IO interrupt (Port80). Indicates a GPIO00~0F event. Indicates a GPIO10~1B event. LPC cycle interrupt EC firmware mode SCI (IBF/OBF SCI). Write SCI ID, Query value is SCID. Indicates a PS2 event. Indicates a KBC Host Interface event. Not used. Indicates a Watchdog Timer event. Description Indicates a EC Command is received from the Host. Alternatively also means nothing happens Priority Highest
SCI ID 00 01h 02h 03h 04h 05h 06h~07 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh SCID 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
GPIO00~0F P3I.1 GPIO10~1B P3I.2 RSV RSV RSV RSV ADC P3I.3 P3I.4 P3I.5 P3I.6 P3I.7
Indicates a ADC updated event.
4.10.2 EC Register Descriptions (Base Address = FF00h, 32 bytes)
Register Abbreviation ECHV Register Full Name Bit Attr Description ECHV contains the current hardware version.
Offset 00h
Def A0
Bnk FFh
EC Hardware Revision ID 7 - 0 RO EC Firmware Revision ID ECFV is written by the 8051 firmware with its current firmware version for 7 - 0 R/W system software's recognition. ADC test data input when ADC test enable. EC High Address 7~4 RSV
01h 02h
ECFV ECHA
0 F
FFh FFh
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3 - 0 R/W
High-byte address of the 64KB EC address space. Used for standard EC commands to access F000~FFFFh internal space. The default setting will let host accessing the FF00~FFFFh (EC, GPWU, SMBus) space. Enable the generation of SCI by standard EC commands (default enable) 90 FFh
SCI Configuration 7 6 03h SCICFG 5 4 R/W R/W R/W R/W Enable SCID port (Firmware generated SCI). EC SCI pulse polarity; =0, low active; (default); =1, high active.
Enable EC SCI (set 1) from SCIIFx, default is enabled. SCI pulse width = SCIPW x 64us, max length = 1 ms, as no width=0. 3 - 0 R/W IF width = 0, the pulse width will be a system clock. EC Configuration Enable EPB Fast Access 7 R/W A enhanced option to speed up EPB performance during accessing. 6 R/W Test mode. Must be programmed to 0 for normal operation. 5 4 3 04h ECCFG 2 R/W R/W R/W R/W Enable hardware EC Read/Write command Enable hardware EC Burst Enable/Disable command Enable hardware EC Query command Enable Extended IO port Interrupt to 8051 IBF Interrupt Enable, also be the Firmware Mode Enable. This bit enables KBC to generate interrupt to the 8051 at the rising edge of IBF, when the KBC command being received will be bypassed to firmware for processing. OBF Interrupt Enable. This bit enables KBC to generate interrupt to the core processor at the falling edge of OBF. 0 FFh 0 FFh
1
R/W
0 05h 06h 07h 08h 09h 0Ah 0Bh SCIE0 SCIE1 SCIE3 SCIF0 SCIF1 SCIF3 SCID
R/W
EC SCI P0, P1, P3 Interrupt Enable 7 - 0 R/W Enable extended 8051 Port 0, 1, 3 Interrupt to SCI
EC SCI P0, P1, P3 Interrupt Flag 7 - 0 R/WC1 Flags for extended 8051 Port 0, 1, 3 Interrupt to SCI. EC Query will clear the query SCI ID flag automatically, or write 1 to clear EC SCI ID Write Port for 8051 firmware to generate SCI event R/W 8051 firmware can write to this port with SCI_ID value to generate a SCI event. The host can use EC Query command to read this specified value. Enter STOP mode by writing this bit = 1, the same as 8051 PCON STOP Enter IDLE mode by writing this bit = 1, the same as 8051 PCON IDLE Enable LPC cycle wake up from STOP mode. MUST be set to '1' to enable wakeup feature. Enable SCI to be one of wake up interrupt source 8051 interrupt source will always exit Ultra Low clock to normal clock Enable Watchdog interrupt wake up from STOP mode Enable GPWU Enable Interrupt wake up from STOP mode wake up from IDLE mode Def 00h Bnk FFh 2F FFh 0 FFh
7-0
0
FFh
PMU Control / Configuration 7 6 5 0Ch PMUCFG 4 3 2 1 0 Offset 0Dh Register Abbreviation CLKCFG WO WO R/W R/W R/W R/W R/W R/W
Register Full Name Bit Attr. Description Enable PLL enter low speed state in STOP mode. Set PLL frequency control value to be PLLLOW in STOP mode. The CLKCFG bit 4 should also be enabled for this option. Flash (SPI) Interface Clock Control 1: full speed (Internal clock is 66(+-%25) MHz ) 0: half speed (default, 1/2 of supplied clock) SPI clock is 16MHz if CLKCFG set to 8 / 4 MHz. SPI clock is stopped when 8051 in IDLE if CLKCFG.0 is set. Enable PLL to generate a good 32.768MHz. (default reset PLL) This bit should be set after PCICLK is stable.
Clock Configuration 7 R/W
6
R/W
5
R/W
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4
R/W
Enable PLL enter low power state in STOP mode 8051 / Peripherals Normal Run Clock Selection. 10: 22 / 8 MHz 01: 16 / 8 MHz 00: 8 / 4 MHz (default) The SPI clock is 16MHz in this setting. Clock rate is fixed in 2/1MHz when 8051 in IDLE if CLKCFG.0 is set. The flash interface (SPI or ISA) is fixed in 32.768 MHz or higher by CLKCFG.6 setting. Enable Peripheral Auto Slow Clock Control to be 1 MHz. The Peripheral's clock will be 1 MHz when no host accessing. Enable 8051 IDLE Mode Slow Clock Control to be 2 / 1 MHz. When 8051 enters IDLE state, the clock of 8051 and peripherals will changed automatically to 2 / 1 MHz. And the flash interface clock will be stop if this bit is set. 0 FF
3-2
R/W
1
R/W
0
R/W
0Eh
EXTIO
EC Extended Write IO data 7~0 R/W Read this byte to get the host write extended IO data. PLLINIT (PLL Initial value) PLL initial value for output a default frequency. (070h)
PLL Configuration 0Fh PLLCFG 7~0 R/W 70 FF
11h
RSV Clock Configuration 2
0
FF
12h
CLKCFG2
7 - 0 R/W
1 us time unit by PLL output clock. If PLL output 32MHz(default), the setting should be 32(1Fh) or 33(20h) for 1000 ns/30.518 = 32.76 . If PLL output 25MHz, the setting should be 24(18h) for 1000 ns/40 = 25. PLLINIT High Bits (PLLINITH) High 2 bits of PLL frequency control initial value(PLLINIT). Combine with FF0Fh to be 10 bits frequency control value. PLL Reference Selection 0: select PCI clock(LPC clock) as reference clock of PLL.(default) 1: select alternative clock source from GPIO02 Alt. input. PLL Source Clock Divider 0: Disable 1: Enable (default) The PLL build-in a 1024(10-bit) divider for source clock.For PLL reference clock is high speed, as PCICLK, the divider should be enabled. For PLL reference clock is low speed, as 32KHz from GPIO02 Alt. Input, the divider should be disabled. PLL Low Speed State Setting As Enable PLL enter low speed state in STOP mode, Use this value as PLL frequency control.
1F
FF
PLL Configuration 2 7 - 6 R/W
5 13h PLLCFG2 4
R/W
11
FF
R/W
3 - 0 R/W
8051 on-chip Control 7~2 RSV Enable WDT timeout only reset 8051 1: WDT timeout event only resets 8051. 0: The WDT timeout event resets whole chip (not including GPIO module) Reset 8051 and 8051 internal peripherals(8051 serial port, timer, interrupt 0 R/W controller) . After reset, the 8051 will restart from reset vector if this bit is reset to '0'. Write '1' to reset 8051. Write '0' to restart 8051. Register Full Name 1 R/W Bit Attr Description
14h
PXCFG
0
FF
Offset 15h
Register Abbreviation ADDAEN
Def 0
Bnk FF
ADC/DAC Enable 7 6 R/W R/W Select converting ADC channel 5 (Valid in A1 Version only) Select converting ADC channel 4 (Valid in A1 Version only)
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5~0 16h PLLFRH
R/W
Enable ADC5~0 3E FF
PLL Frequency Register High byte 32MHz clock count 32.768KHz value[11:4], default count 1000( PLLFRH, PLLFRL[7:4]=3E8h) PLL Frequency Register low byte 7~0 R/W 7~4 3 17h PLLFRL 2 R/W R/W R/W 32MHz clock count 32.768KHz value[3:0] Enable show PLL lock value in CHIP ID reg Enable PLL logic from test mode clock for testing. Set PLL frequency count don't care bits 0: all comparing 1: don't care bit 1 2: don't care bit 1~0 3: don't care bit 2~0 83 FF
1~0
R/W
ADC Control Register 7~5 18h ADCTRL 4~2 1 0 19h ADCDAT RSV R/W R/W R/W Select converting ADC channel (ADC5~0) NOTE: ONLY Channel 3~0 is valid in A0 and A1 version. All these three bit need to set ZERO if channel 4 or 5 selected using ADDAEN. ADC test mode Start (write 1 action ) ADC converter and Enable ADC converted interrupt 0 FF 0 FF
ADC Data output port 7 - 0 RO After ADC converted, the value is hold here.
EC Interrupt Pending Flag 7~3 1Ah ECIF 2 1 0 1Bh ECDAT RSV R/WC1 EC firmware mode in processing flag, Exit EC firmware mode and re-enable hardware mode by writing 1 0 FF
R/WC1 IBF interrupt pending flag, as ECSTS IBF is set by host write R/WC1 OBF interrupt pending flag, as ECSTS OBF is clear by host read ECDAT 0 FF
EC Data port 7 - 0 R/W The EC Data Port serves as the window between system host and EC. Write ECDAT will set ECSTS bit 0 (OBF) at the same time. EC Command port This register stored the latest EC command from host writing EC command IO port. Normally, standard EC commands will be processed by EC hardware directly. For extended EC commands, 8051 firmware may handle the processing. The port is read-only by the EC.
1Ch
ECCMD
7 - 0 RO
0
FF
EC Status port 7 6 5 4 1Dh ECSTS 3 2 1 0 1E~1Fh PLLVAL RO RSV R/WC1 IBF, write IBF = 1 to clear IBF R/WC1 OBF, write port ECDAT will set OBF to 1. Write OBF = 1 to clear OBF Chip Part No. / PLL lock value. FF R/W R/W RO R/W Free r/w bit for host interface Free r/w bit for host interface SCI pending flag Burst Enable Status A2 (Command or Data Flag) =0, previous host write is Data =1, previous host write is Command 0 FF
15~0 RO
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4.11 GPWU 4.11.1 GPWU Functional Description
Each GPIO with GPI pin can generate events (interrupt or wakeup). The GPI input can be set as Level or Edge trigger or Change trigger. Polarity bit setting will affect Level and Edge trigger, but it poses no meaning to Change trigger.
4.11.2 GPWU Register Descriptions (Base Address = FF30h, 96 bytes)
Register Abbreviation GPWUEN00 GPWUEN08 GPWUEN10 GPWUEN18 GPWUPF00 GPWUPF08 GPWUPF10 GPWUPF18 GPWUPS00 GPWUPS08 GPWUPS10 GPWUPS18 GPWUEL00 GPWUEL08 GPWUEL10 GPWUEL18 Register Full Name Bit Attr Description
Offset 30 31 32 33 40 41 42 43 50 51 52 53 60 61 62 63
Def Bnk
GPIO Event Enable and Asynchronous Wake Up Enable 7~0 R/W Enable bit to generate event (interrupt, and wakeup) for a active input. Also Enable bit for waking up from STOP mode. 0 FF
3~0 GPIO Event Pending Flag 7~0
R/WC1 GPIO00~1B Event Pending Flag
0
FF
GPIO Polarity Selection 7~0 R/W GPIO00~1B input active polarity selection 0: Low active (falling for edge trigger) 1: High active (rising for edge trigger) GPIO00~1B input is edge or level trigger 0: Edge 1: Level 0 FF
3~0 GPIO Edge / Level Trigger Selection 7~0 3~0 R/W
0
FF
4.12 8051 Microprocessor
The embedded 8051 is compatible with industrial standard 8051(or 8031). There are 3 standard 8051 peripherals, including the Interrupt controller, the Serial port and two 16-bit timers. KB3700 extends the channels of Interrupt Controller in the original 8051 to 24 channels supporting internal peripheral devices. The Serial port use SCON2 to achieve high speed serial transmission rate up to 115200 bps. The two 16-bit timers are basically the same as that in the standard 8051's, except when SCON2 is used to generate high-speed baud rate. Under such circumstances the 2 timers will not be used for baud-rate generation but for other purposes. The 8051 uses MOVX and MOVC instructions to read or write KB3925 peripherals, i.e., EC, SMBus, GPIO, GPWU, KBC, IKB, GPT, PWM, PS2, XBI, LPC, XRAM...etc. Hereunder lists the differences between the KB3925's embedded 8051 and that of the industrial standard 8051:
4.12.1 Interrupt Vectors Table
Source IE0 Vector Addr 0003h Description 8051 external interrupt 0 SCI ID 01h Priority Highest
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000Bh 0013h 001Bh 0023h 0043h 004Bh 0053h 005Bh 0063h 006Bh 0073h 007Bh 0083h 008Bh 0093h 009Bh 00A3h 00ABh 00B3h 00BBh 00C3h 00CBh 00D3h 00DBh 00E3h 00EBh 00F3h 00FBh
8051 Timer 0 8051 external interrupt 0 8051 Timer 1 8051 Serial Port WDT N.A. PS/2 KBC Host Interface interrupt RSV LPC Interrupt EC Host Interface interrupt N.A. RSV RSV RSV N.A. GPT0 GPT1 GPT2 GPT3 EXTWIO (Write Extended IO interrupt (Port80) GPIO00~0F GPIO10~1B RSV RSV RSV RSV ADC updated
02h 03h 04h 05h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Highest Highest Highest Highest High
IE1 TF1 RI & TI P0I.0 P0I.1 P0I.2 P0I.3 P0I.4 P0I.5 P0I.6 P0I.7 P1I.0 P1I.1 P1I.2 P1I.3 P1I.4 P1I.5 P1I.6 P1I.7 P3I.0 P3I.1 P3I.2 P3I.3 P3I.4 P3I.5 P3I.6 P3I.7
Lowest
The MSB of the Interrupt Vector can be set in PCON.5 (IVHV).
4.12.2 SFR Map
Color Information
XXX XXX XXX Original Industrial standard 8051 features KB3925's embedded 8051 new features XXX Changed 8051 feature for ENE 8051
0 F8 F0 E8 E0 D8 P3IF B P1IF ACC P0IF
1
2
3
4
5
6
7 FF F7 EF E7 DF
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D7 CF C7
C8 C0 B8 B0 A8 A0 98 90 88 80 IP P3IE IE P2 SCON P1IE TCON P0IE 8 TMOD SP 9 TL0 DPL A TL1 DPH B C D TH0 TH1 PCON2 E PCON F SBUF SCON2 SCON3
BF B7 AF A7 9F 97 8F 87
This column registers are bit address-able.
P3IE, P1IE, P0IE are read/write registers used as Interrupt Enable (IE) to their corresponding interrupt inputs. These three registers are original 8051 port registers with contains 8-bits. For the embedded 8051 inside KB3925, the 3 ports are used for interrupt input (always rise pulses) extensions. Totally there are 24 interrupt events.
P3IF, P1IF, P0IF are Interrupt Flag(IF) corresponding to the 24 interrupt inputs. The Ifs are set by external interrupt event (always a rising pulse, one clock width), and are cleared by software (execute IRET instruction for active interrupt). The original alternate 8051 port 3 functions are not related with P3IE and P3IF.
4.12.3 SFR Descriptions
(Direct Addressing 80h~FFh)
Addr 80h
Register Abbr P0IE
Bit Attr Port 0 IE 7 - 0 R/W Stack Pointer 7 - 0 R/W Stack Pointer
Register Full Name Description P0 Interrupt Enable Register
Def
00h
81h
SP
07h
82h
DPL
DPTR Low Byte 7 - 0 R/W DPTR low byte
00h
83h 84h-85h 86h
DPH
DPTR High Byte 7 - 0 R/W NA DPTR high byte Reserved
00h 00h 00h
PCON2
Processor Control Register 2
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7 6 5 4
R/W R/W R/W R/W
Enable level trigger interrupt (KB910L should set to 0) TTST, Timer 0/1 test mode, let timer 12 times faster. Reserved Enable external space write. Next Interrupt Coming Flag. The same extended interrupt coming during ISR before IRET. After exit ISR with IRET instruction, the 8051 will re-enter the ISR again if the flag is 1. Write 0 to clear the flag and prevent from 8051 re-entering the interrupt again after exit ISR. Reserved
3
R/W
2~1
NA
0 R/W Enable idle loop no fetching instruction Processor Control Register 7 R/W 6 5 4 3 87h PCON 2 R/W R/W R/W R/W R/W Reserved IVHB, Interrupt vector highest bit. Let interrupt vector to be 00xxh or 80xxh, including standard and extended interrupt. Reserved GF1, general purposes flag. GF0, general purposes flag. Power Down Mode Stop all 8051 clock, including all peripherals (timer, interrupt, serial port). An external Async. wake-up event can reset the latch of 8051 gated clock. Write IDLE Mode. Set 1 to stop processor fetching instructions. But the clock will not stop. 0 WO Peripheral interrupt events will let processor exit IDLE mode. Write 1 to enter IDLE. Timer/Counter Control Register 7 6 5 88h TCON 4 3 2 1 0 R/WC R/W R/WC R/W R/WC R/W R/WC R/W TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Timer 1 overflow flag. Timer 1 run control bit. Timer 0 overflow flag. Time 0 run control bit. External Interrupt 1 edge detected flag. Interrupt 1 falling edge / low active control bit External Interrupt 0 edge detected flag. Interrupt 0 falling edge / low active control bit 00h 00h
1
WO
Processor Control Register 7 6 R/W R/W
GATE1
Gating control of TR1 and INT1. =0, be a timer 1. =1, be a counter 1. =0, Timer 1 is 13-bit timer (8048 timer). =1, Timer 1 is 16-bit timer
CT1
4~5 89h TMOD 3 2
R/W
TM1 =2, Timer 1 is 8-bit auto-reload timer 00h =3, Timer 1 is stop. Gating control of TR0 and INT0. =0, be a timer 0. =1, be a counter 0. =0, Timer 0 is 13-bit timer (8048 timer). =1, Timer 0 is 16-bit timer =2, Timer 0 is 8-bit auto-reload timer
R/W R/W
GATE0
CT0
0~1
R/W
TM0
8Ah 8Bh
TL0 TL1
Timer 0 Low Byte 7 - 0 R/W
=3, Timer 0 TL0, TH0 is two 8-bit timer. 00h 00h
Timer 0 Low Byte
Timer 1 Low Byte
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7 - 0 R/W TH0
Timer 1 Low Byte 00h
8Ch
Timer 0 High Byte 7 - 0 R/W Timer 0 High Byte
8Dh
TH1
Timer 1 Low Byte 7 - 0 R/W Port 1 IE 7 - 0 R/W NA P1 Interrupt Enable Register Reserved Timer 1 High Byte
00h
90h 91h-97h
P1IE
00h 00h
Serial Port Control Register Serial Port Mode: SM1 7~6 R/W SM0 00: 8-bit shift register mode, E51RX should be E51CLK shift clock. 01: 8-bit Serial Port(variable) 10: 9-bit Serial Port (variable) 98h SCON 5 4 3 2 1 0 99h 9Ah 9Bh SBUF SCON2 SCON3 NA R/W R/W R/W R/WC R/WC REN TB8 RB8 TI RI Reserved Enable Serial Port reception The 9th bit of transmitted in mode 2 & 3. The 9th bit of received. Transmit Interrupt flag. Receive Interrupt flag. 00h 00h
Serial Port Data Buffer 7 - 0 R/W Serial port data buffer
Serial Port Control 2 / 3 Register 7~0 R/W SCON2 is high-byte, SCON3 is low byte to be a 16-bit counter for baud rate based on 8051 clock. 00h
A0h
P2
Port 2 Latch Register 7 - 0 R/W Port 2, high address of external bank accessing.
00h
Interrupt Enable Register Disable all interrupt (include extended) if clear to 0. If set to 1, all EA 7 R/W interrupts should be enabled by individual enable bit. 6~5 R/W Reserved A8h IE 4 3 2 1 0 B0h P3IE R/W R/W R/W R/W R/W ES ET1 EX1 ET0 EX0 Enable Serial Port interrupt Enable Timer 1 Overflow interrupt Enable External Interrupt 1 Enable Timer 0 Overflow interrupt Enable External Interrupt 0 00h 00h
Port 3 Interrupt Enable 7 - 0 R/W P3 Interrupt Enable Register
Interrupt Priority Register 7~5 4 B8h IP 3 2 1 0 B0h PSW NA R/W R/W R/W R/W R/W PS PT1 PX1 PT0 PX0 Reserved Serial Port interrupt priority level Timer 1 interrupt priority level External Interrupt 1 priority level Timer 0 interrupt priority level External Interrupt 0 priority level 00h Carry flag. Auxiliary Carry flag. Flag 0, for user general purpose. Register Bank selector 1 00h
Processor Status Word 7 6 5 4 R/W R/W R/W R/W CY AC F0 RS1
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3 2 1 0
R/W R/W R/W R/W
RS0 OV F1 P
Register Bank selector 0 Overflow flag. Flag 1, for user general purpose. Parity flag.
A4h A5h A6h A7h RSV ACh ADh AEh AFh D8h P0IF Port 0 Interrupt Flag 7 - 0 R/W ACC, A 7 - 0 R/W Accumulator P0 Interrupt Flag Register 00h 00h
E0h
ACC
00h
E8h
P1IF
Port 1 Interrupt Flag 7 - 0 R/W B Register 7 - 0 R/W For MUL and DIV operations. P1 Interrupt Flag Register
00h
E0h
B
00h
F8h
P3IF
Port 3 Interrupt Flag 7 - 0 R/W P3 Interrupt Flag Register
00h
5. Electronic Characteristics
5.1 Absolute Maximum Rating
Symbol
VCC VI VO TOP
Parameter
Power source voltage Input voltage Output voltage Operating temperature
Condition
All voltages are referenced to VSS.
Ratings
-0.3 to 3.6 -0.3 to 3.6 -0.3 to 3.6 -25 to 85
Unit
V V V
5.2 Recommended Operating Condition
Symbol
VCC VSS VCCA AGND
Parameter
Power source voltage Ground voltage Analog reference voltage(A/D and D/A converter is used) Analog ground voltage
Limits Min
3 -0.3 2.5
Typ
3.3 0 3.3 0
Max
3.6 0.3 3.6
Unit
V V V V
5.3 Operating Current
Symbol Parameter Limits Min Typ Max Unit
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ICC
Typical current consumption in operating state under Windows environment: all clock domains are running, no PS2/KB/mouse actions
TBD
mA
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6. Packaging Information
6.1 64 LQFP
(10mm x 10mm x 1.4mm)
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7. Revision History
Rev. 0.1 Preliminary/Changes Initial Release Date July. 28, 2006
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