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CX2002
0.5m CMOS ASIC Production Family
Introduction
The CX2002 is a 0.5m CMOS triple-metal module array product used for high-volume cost reduction, production. CX2002 provides a migration path from the prototyping and production phase that is typically done with the 0.6m CX2001 product family. The decrease in die size from 0.6m to the 0.5m technology allows for reduced production prices. In addition, the CX2002 features 25% lower power consumption and 20% higher core utilization than the comparable CX2001 device. The no-risk migration from the CX2001 family to the CX2002 technology is achieved by using the same synthesized netlist, test vectors, and package type. Sixteen-week lead-time is available for highvolume production.
Features
0.5m CMOS TLM process 3.3V or 5V operation with mixed mode I/O 5V tolerance with reference voltage PCI compliant outputs (3.3V / 5V) Power dissipation: * 2.1W / MHz / Gate @ 5V * 0.86W / MHz / Gate @ 3.3V u 800 MHz maximum flip-flop toggle rate u u u u u u Analog PLL operating frequency up to 250 MHz u Embedded memory * Configurable as single-port RAM, dual-port RAM or ROM * Worst-case cycle performance: 200 MHz @ 5V; 150 MHz @ 3.3V * Fully static, synchronized RAM
CX2002 Product
Master Slice CX2022 CX2052 Estimated Usable Gates 10k 25k Embedded Memory Bits 2k 32k Max Memory Instantiations 1 8 APLL 3 2 Max I/O 120 208
Cell Library
u u u u u Synopsys DC and DesignWare support Low power flip-flops Built-in scan MUX in flip-flops 26 simple gates; 36 complex gates 31 flip-flops u u u u 24 latches Multiplexers, decoders Tristate / drive cells 1280 input / output buffers
CEC017 (Rev. B, 9/1/00)
1
Power Pin Assignment
All I/O cells are programmable as VDD, VSS, input, output, or bi-directional. This flexibility allows the user to properly ratio
power pins with output drive requirements or match specific pin-out when replacing existing devices.
Input & Output Bi-Directional Cells
The CX2002 library contains a large selection of input, output, and bi-directional cells that enable a wide range of designs. Input cells can be personalized with internal pull-up or pull-down resistors and with or without hysteresis. Output cells include slew rate control, current drive capability from 2mA to 12mA, as well as N channel and P channel open drains. If required, outputs can be used in parallel to enable increased drive capability. Each I/O can be programmed independently for 3.3V or 5V.
Recommended Operating Conditions
Absolute Maximum Ratings
Symbol VDD VDDIO VIN TJ TSTG TSOL Supply voltage I/O supply voltage DC input voltage Junction temperature Storage temperature Soldering lead temperature (10 seconds) Description Min 0 0 -0.3 --65 -Max 7.0 5.5 VDD+0.3 150 150 210 Unit V V V C C C
Recommended Operating Conditions
Symbol VDD Supply voltage Description Commercial (0C TJ 100C) Industrial (-40C TJ 115C) Military (-55C TJ 125C) VIH VIL TIN Input high voltage Input low voltage TTL inputs CMOS inputs TTL inputs CMOS inputs Min 4.75 4.75 4.75 2.0 0.7 VDD 0 0 -Max 5.25 5.25 5.25 VDD VDD 0.8 0.3 VDD 10 Units V V V V V V V nS
Input signal transition time
CEC017 (Rev. B, 9/1/00)
2
DC Characteristics Over Operating Conditions
Symbol VOH VOL IIN CIN Output high voltage Output low voltage Input leakage current Input capacitance QFP packages BGA packages Description TTL outputs CMOS outputs TTL outputs CMOS outputs Min 3.5 3.5 ---10 --Max --0.45 0.45 10 --Units V V V V A Note 1 Note 1
Note 1: Please refer to current packaging information on our website (www.chipexpress.com/design).
For More Info
Chip Express Corporation 2323 Owen Street Santa Clara, CA 95054 Phone: (408) 988-2445 Fax: (408) 988-2449 Toll Free: 1-800-95-CHIPX Email: moreinfo@chipx.com www.chipexpress.com
CEC017 (Rev. B, 9/1/00)
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