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PD -www..com 97031 IRF2907ZS-7PPBF Features l l l l l Advanced Process Technology Ultra Low On-Resistance 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax HEXFET(R) Power MOSFET D VDSS = 75V RDS(on) = 3.8m G S Description Specifically designed for high current, high reliability applications, this HEXFET(R) Power MOSFET utilizes the latest processing techniques and advanced packaging technology to achieve extremely low on-resistance and world -class current ratings. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Server & Telecom OR'ing, Automotive and low voltage Motor Drive Applications. S (Pin 2, 3, 5, 6, 7) G (Pin 1) ID = 160A Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS EAS EAS (tested) IAR EAR TJ TSTG Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (See Fig. 9) Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy (Thermally Limited) Single Pulse Avalanche Energy Tested Value Avalanche Current Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw 300 (1.6mm from case ) 10 lbf*in (1.1N*m) Max. 180 120 160 700 300 2.0 20 160 410 See Fig.12a,12b,15,16 -55 to + 175 Units A c W W/C V mJ A mJ C c h d g Thermal Resistance RJC RCS RJA RJA Junction-to-Case j Parameter Typ. --- 0.50 Max. 0.50 --- 62 40 Units C/W Case-to-Sink, Flat, Greased Surface Junction-to-Ambient Junction-to-Ambient (PCB Mount, steady state) j ij --- --- HEXFET(R) is a registered trademark of International Rectifier. www.irf.com 1 08/03/05 IRF2907ZS-7PPBF Static @ TJ = 25C (unless otherwise specified) Parameter V(BR)DSS VDSS/TJ RDS(on) SMD VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance www..com Min. Typ. Max. Units 75 --- --- 2.0 94 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.066 3.0 --- --- --- --- --- --- 170 55 66 21 90 92 44 4.5 7.5 7580 970 540 3750 650 1110 --- --- 3.8 4.0 --- 20 250 200 -200 260 --- --- --- --- --- --- --- --- --- --- --- --- --- --- pF Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 110A V VDS = VGS, ID = 250A S VDS = 25V, ID = 110A A VDS = 75V, VGS = 0V VDS = 75V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V nC ID = 110A VDS = 60V VGS = 10V ns VDD = 38V ID = 110A RG = 2.6 VGS = 10V D nH Between lead, e e d 6mm (0.25in.) from package G S and center of die contact VGS = 0V VDS = 25V = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 60V, = 1.0MHz VGS = 0V, VDS = 0V to 60V Diode Characteristics Parameter IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Min. Typ. Max. Units --- --- --- --- --- --- --- --- 35 40 160 A 700 1.3 53 60 V ns nC Conditions MOSFET symbol showing the integral reverse G D S p-n junction diode. TJ = 25C, IS = 110A, VGS = 0V TJ = 25C, IF = 110A, VDD = 38V di/dt = 100A/s e e Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25C, L=0.026mH, R G = 25, IAS = 110A, VGS =10V. Part not recommended for use above this value. Pulse width 1.0ms; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. 100% tested to this value in production. This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. R is measured at TJ of approximately 90C. 2 www.irf.com IRF2907ZS-7PPBF www..com 1000 TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 1000 TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V ID, Drain-to-Source Current (A) 100 BOTTOM ID, Drain-to-Source Current (A) BOTTOM 100 4.5V 10 4.5V 60s PULSE WIDTH Tj = 25C 1 0.1 1 10 100 1000 V DS, Drain-to-Source Voltage (V) 10 0.1 1 60s PULSE WIDTH Tj = 175C 10 100 1000 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 Gfs, Forward Transconductance (S) 200 T J = 25C 150 T J = 175C 100 ID, Drain-to-Source Current () 100 10 T J = 175C 1 T J = 25C 50 V DS = 10V 380s PULSE WIDTH 0 0 25 50 75 100 125 150 VDS = 25V 60s PULSE WIDTH 0.1 1 2 3 4 5 6 7 8 VGS, Gate-to-Source Voltage (V) ID,Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current www.irf.com 3 IRF2907ZS-7PPBF www..com 100000 C oss = C ds + C gd VGS, Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd 12.0 ID= 110A 10.0 8.0 6.0 4.0 2.0 0.0 VDS= 60V VDS= 38V VDS= 15V C, Capacitance(pF) 10000 Ciss Coss 1000 Crss 100 1 10 VDS, Drain-to-Source Voltage (V) 100 0 50 100 150 200 QG Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100sec 100 1msec ISD, Reverse Drain Current (A) 100 T J = 175C T J = 25C 10 ID, Drain-to-Source Current (A) 10 10msec 1 DC Tc = 25C Tj = 175C Single Pulse 0 1 10 100 1000 1 VGS = 0V 0.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VSD, Source-to-Drain Voltage (V) 0.1 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRF2907ZS-7PPBF www..com 200 Limited By Package 160 ID, Drain Current (A) RDS(on) , Drain-to-Source On Resistance (Normalized) 3.0 ID = 180A 2.5 VGS = 10V 120 2.0 80 1.5 40 1.0 0 25 50 75 100 125 150 175 T C , Case Temperature (C) 0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Normalized On-Resistance vs. Temperature 1 D = 0.50 Thermal Response ( Z thJC ) 0.1 0.20 0.10 0.05 0.01 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) J R1 R1 J 1 2 R2 R2 R3 R3 3 C 3 Ri (C/W) i (sec) 0.1072 0.000896 0.2787 0.1143 0.009380 0.121118 1 2 0.001 Ci= i/Ri Ci i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 1E-006 1E-005 0.0001 0.001 0.01 0.1 0.0001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRF2907ZS-7PPBF www..com 15V EAS , Single Pulse Avalanche Energy (mJ) VDS L DRIVER 700 600 500 400 300 200 100 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) ID 24A 34A BOTTOM 110A TOP RG VGS 20V D.U.T IAS tp + V - DD A 0.01 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp I AS Fig 12b. Unclamped Inductive Waveforms QG Fig 12c. Maximum Avalanche Energy vs. Drain Current 10 V QGS VG 4.5 QGD VGS(th) Gate threshold Voltage (V) Charge 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 ID = 250A ID = 1.0mA ID = 1.0A Fig 13a. Basic Gate Charge Waveform Current Regulator Same Type as D.U.T. 50K 12V .2F .3F D.U.T. VGS 3mA + V - DS IG ID Current Sampling Resistors T J , Temperature ( C ) Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature 6 www.irf.com IRF2907ZS-7PPBF 1000 www..com Duty Cycle = Single Pulse Avalanche Current (A) 100 0.01 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses 0.05 10 0.10 1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current vs.Pulsewidth 200 EAR , Avalanche Energy (mJ) 150 TOP Single Pulse BOTTOM 1% Duty Cycle ID = 110A 100 50 0 25 50 75 100 125 150 175 Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asT jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Starting T J , Junction Temperature (C) Fig 16. Maximum Avalanche Energy vs. Temperature www.irf.com 7 IRF2907ZS-7PPBF www..com D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt - - + RG * dv/dt controlled by RG * Driver same type as D.U.T. * I SD controlled by Duty Factor "D" * D.U.T. - Device Under Test V DD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V DS V GS RG 10V Pulse Width 1 s Duty Factor 0.1 % RD D.U.T. + -V DD Fig 18a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr t d(off) tf Fig 18b. Switching Time Waveforms 8 www.irf.com IRF2907ZS-7PPBF D2Pak - 7 Pin Package Outline Dimensions are shown in millimeters (inches) www..com D2Pak - 7 Pin Part Marking Information AIR www.irf.com 9 IRF2907ZS-7PPBF D2Pak - 7 Pin Tape and Reel www..com Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IRs Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 08/05 10 www.irf.com |
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