View MSP3460G_6810.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MICRONAS
MSP 34x0G Multistandard Sound Processor Family
Edition May 27, 2003 6251-476-1DS
MICRONAS
MSP 34x0G
Contents Page 6 7 7 8 9 10 10 10 10 11 11 11 11 13 13 13 13 13 14 14 14 15 15 15 15 15 15 15 16 16 16 16 16 17 17 17 18 18 19 19 19 19 19 19 19 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.5.5. 2.5.6. 2.5.7. 2.5.8. 2.5.8.1. 2.5.8.2. 2.5.8.3. 2.6. 2.6.1. 2.6.2. 2.7. 2.8. 2.9. 2.10. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.4.1. 3.1.4.2. 3.1.4.3. 3.1.4.4. 3.2. 3.3. Title Introduction Features of the MSP 34x0G Family MSP 34x0G Version List MSP 34x0G Versions and their Application Fields Functional Description Architecture of the MSP 34x0G Family Sound IF Processing Analog Sound IF Input Demodulator: Standards and Features Preprocessing of Demodulator Signals Automatic Sound Select Manual Mode Preprocessing for SCART and I2S Input Signals Source Selection and Output Channel Matrix Audio Baseband Processing SRS WOW BBE High Definition Sound Micronas VOICE Automatic Volume Correction (AVC) Loudspeaker and Headphone Outputs Subwoofer Output Quasi-Peak Detector Micronas BASS (MB) Dynamic Amplification Adding Harmonics Micronas BASS Parameters SCART Signal Routing SCART DSP In and SCART Out Select Stand-by Mode I2S Bus Interface ADR Bus Interface Digital Control I/O Pins and Status Change Indication Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Internal Hardware Error Handling Description of CONTROL Register Protocol Description Proposals for General MSP 34x0G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C-Controlling MSP 34x0G Programming Interface
DATA SHEET
2
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Contents, continued Page 19 23 24 24 24 26 28 29 42 43 43 43 43 43 44 44 44 46 46 51 54 57 60 62 62 64 64 65 66 67 68 68 69 70 71 72 74 75 75 76 79 Section 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.3.9. 4.6.3.10. Title User Registers Overview Description of User Registers STANDARD SELECT Register Refresh of STANDARD SELECT Register STANDARD RESULT Register Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of Minimum Initialization Codes B/G-FM (A2 or NICAM) BTSC-Stereo BTSC-SAP with SAP at Loudspeaker Channel FM-Stereo Radio Automatic Standard Detection Software Flow for Interrupt driven STATUS Check Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Analog Input and Output Recommendations Recommendations for Analog Sound IF Input Signal Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input and Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs and Outputs, AGNDC Sound IF Inputs Power Supply Rejection Analog Performance Sound Standard Dependent Characteristics
Micronas
May 27, 2003; 6251-476-1DS
3
MSP 34x0G
Contents, continued Page 83 83 84 85 85 86 86 87 87 88 89 89 89 89 91 91 92 93 95 95 97 97 97 97 98 98 98 98 99 99 99 99 99 100 100 100 100 100 100 101 101 101 101 101 Section 5. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 6. 6.1. 6.2. 6.3. 6.3.1. 6.3.1.1. 6.3.1.2. 6.3.2. 6.3.3. 6.3.4. 6.3.5. 6.3.6. 6.3.7. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.4.5. 6.4.6. 6.4.7. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.5.5. 6.5.6. 6.5.7. 6.6. 6.6.1. 6.6.2. 6.7. 6.7.1. 6.7.2. 6.8. 6.9. Title Appendix A: Overview of TV-Sound Standards NICAM 728 A2-Systems BTSC-Sound System Japanese FM Stereo System (EIA-J) FM Satellite Sound FM-Stereo Radio Appendix B: Manual/Compatibility Mode Demodulator Write and Read Registers for Manual/Compatibility Mode DSP Write and Read Registers for Manual/Compatibility Mode Manual/Compatibility Mode: Description of Demodulator Write Registers Automatic Switching between NICAM and Analog Sound Function in Automatic Sound Select Mode Function in Manual Mode A2 Threshold Carrier-Mute Threshold Register AD_CV Register MODE_REG FIR-Parameter, Registers FIR1 and FIR2 DCO-Registers Manual/Compatibility Mode: Description of Demodulator Read Registers NICAM Mode Control/Additional Data Bits Register Additional Data Bits Register CIB Bits Register NICAM Error Rate Register PLL_CAPS Readback Register AGC_GAIN Readback Register Automatic Search Function for FM-Carrier Detection in Satellite Mode Manual/Compatibility Mode: Description of DSP Write Registers Additional Channel Matrix Modes Volume Modes of SCART1/2 Outputs FM Fixed Deemphasis FM Adaptive Deemphasis NICAM Deemphasis Identification Mode for A2 Stereo Systems FM DC Notch Manual/Compatibility Mode: Description of DSP Read Registers Stereo Detection Register for A2 Stereo Systems DC Level Register Demodulator Source Channels in Manual Mode Terrestric Sound Standards SAT Sound Standards Exclusions of Audio Baseband Features Compatibility Restrictions to MSP 34x0D
DATA SHEET
4
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Contents, continued Page 103 103 104 105 106 Section 7. 7.1. 7.2. 8. 9. Title Appendix C: Application Information Phase Relationship of Analog Outputs Application Circuit Appendix D: MSP 34x0G Version History Data Sheet History
License Notice: "Dolby Pro Logic" is a trademark of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
Micronas
May 27, 2003; 6251-476-1DS
5
MSP 34x0G
Multistandard Sound Processor Family Release Note: Revision bars indicate significant changes to the previous edition. The hardware and software description in this document is valid for the MSP 34x0G version C12 and following versions.
DATA SHEET
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments. All MSP 34xxG versions are pin compatible to the MSP 34xxD. Only minor modifications are necessary to adapt a MSP 34xxD controlling software to the MSP 34xxG. The MSP 34x0G further simplifies controlling software. Standard selection requires a single I2C transmission only. The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection). The MSP 34x0G can handle very high FM deviations even in conjunction with NICAM processing. This is especially important for the introduction of NICAM in China. The ICs are produced in submicron CMOS technology. The MSP 34x0G is available in the following packages: PSDIP64-1, PSDIP52-1/-2, PMQFP80-11, and PMQFP64-2.
1. Introduction The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure 1-1 shows a simplified functional block diagram of the MSP 34x0G. These TV sound processing ICs now include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Sound IF1 ADC Sound IF2
Demodulator
Preprocessing
Loudspeaker Sound Processing
DAC
Loudspeaker Subwoofer
Source Select
I S1 I2S2 SCART1
2
Headphone Sound Processing
DAC
Headphone
Prescale
I2S DAC
SCART2 SCART3 SCART4 MONO
SCART DSP Input Select
SCART1 ADC Prescale DAC SCART Output Select SCART2
Fig. 1-1: Simplified functional block diagram of the MSP 34x0G
6
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
1.1. Features of the MSP 34x0G Family
Feature Standard Selection with single I2C transmission Automatic Standard Detection of terrestrial TV standards/Automatic Carrier Mute function Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS Two selectable sound IF (SIF) inputs Automatic Carrier Mute function Interrupt output programmable (indicating status change) Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness AVC: Automatic Volume Correction Subwoofer output with programmable low-pass and complementary high-pass filter Micronas BASS (MB) and 5-band graphic equalizer for loudspeaker channel Spatial effect for loudspeaker channel Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs Complete SCART in/out switching matrix Two I2S inputs; one I2S output All analog Mono sound carriers including AM-SECAM L Korean FM-Stereo A2 standard All analog FM-Stereo A2 and satellite standards Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) ASTRA Digital Radio (ADR) together with DRP 3510A All NICAM standards Demodulation of the BTSC multiplex signal and the SAP channel Alignment free digital DBX noise reduction for BTSC Stereo and SAP Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP BTSC stereo separation (MSP 3420/40G also EIA-J) significantly better than spec. SAP and stereo detection for BTSC system Alignment-free Japanese standard EIA-J Demodulation of the FM-Radio multiplex signal X X X X X X X X X X X X X X X 3400 X X X X X X X X X X X X X X X X X 3410 X X X X X X X X X X X X X X X X X X X X X X X X 3420 X X X X X X X X X X X X X X X X 3440 X X X X X X X X X X X X X X X X 3450 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 3460 X X
1.2. MSP 34x0G Version List
Version MSP 3400G MSP 3410G MSP 3420G MSP 3440G MSP 3450G MSP 3460G Status available available available available available available Description FM Stereo (A2) Version NICAM and FM Stereo (A2) Version NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system) NTSC Version (A2 Korea, BTSC with DBX noise reduction, Japanese EIA-J system) Global Version (all sound standards) Global Mono Version (all sound standards)
Micronas
May 27, 2003; 6251-476-1DS
7
MSP 34x0G
1.3. MSP 34x0G Versions and their Application Fields Table 1-1 provides an overview of TV sound standards that can be processed by the MSP 34x0G family. In addition, the MSP 34x0G is able to handle the FM-Radio standard. With the MSP 34x0G, a complete
DATA SHEET
multimedia receiver covering all TV sound standards together with terrestrial/cable and satellite radio sound can be built; even ASTRA Digital Radio can be processed (with a DRP 3510A coprocessor).
Table 1-1: TV Stereo Sound Standards covered by the MSP 34x0G IC Family (details see Appendix A)
MSP Version 3400 TVSystem B/G 5.5/5.85 L I 6.5/5.85 6.0/6.552 6.5/6.2578125 3400 3410 6.5/6.7421875 D/K 6.5/5.7421875 3450 6.5/5.85 6.5 7.02/7.2 7.38/7.56 etc. 4.5/4.724212 3420, 3440 M/N 4.5 4.5 FM-Radio 3460 10.7 FM-Stereo (A2, D/K3) FM-Mono/NICAM (D/K, NICAM) FM-Mono FM-Stereo ASTRA Digital Radio (ADR) with DRP 3510A FM-Stereo (A2) FM-FM (EIA-J) BTSC-Stereo + SAP FM-Stereo Radio SECAM-East PAL Poland China, Hungary FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo (A2, D/K1) FM-Stereo (A2, D/K2) PAL SECAM-L PAL SECAM-East PAL Scandinavia, Spain France UK, Hong Kong Slovak. Rep. currently no broadcast Position of Sound Carrier /MHz 5.5/5.7421875 Sound Modulation FM-Stereo (A2) Color System PAL Broadcast e.g. in: Germany
3400
Satellite
PAL
Europe Sat. ASTRA
NTSC NTSC NTSC, PAL
Korea Japan USA, Argentina USA, Europe
all Standards as above but Mono demodulation only.
33 34 39 MHz 4.5 9 MHz
SAW Filter Tuner Sound IF Mixer
Loudspeaker
1
Mono Vision Demodulator SCART1
2
Subwoofer
MSP 34x0G
2
Headphone
2 2 2
Composite Video
SCART Inputs
SCART2 SCART3 SCART4
2
SCART1 SCART2
SCART Outputs
I2S1
ADR
I2S2
Dolby Pro Logic Processor DPL 351xA
ADR Decoder DRP 3510A
Fig. 1-2: Typical MSP 34x0G application
8
May 27, 2003; 6251-476-1DS
Micronas
2. Functional Description
ANA_IN1+ AGC A D ANA_IN2+ DEMODULATOR (incl. Carrier Mute) Standard Selection Deemphasis: 50/75 s, J17 DBX/MNR Panda1 FM/AM Automatic Sound Select
FM/AM
Source Select
SCART DSP Input Select
(13hex)
SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R MONO_IN
(41hex)
(40hex)
SCART Output Select
Micronas
May 27, 2003; 6251-476-1DS
DATA SHEET
0
Prescale
(0Ehex)
Stereo or A/B
1 3
Loudspeaker Channel Matrix
(08hex)
AVC
(29hex)
Bass/ Treble or Equalize
(02hex) (03hex)
Loudness
(04hex)
Complementary Spatial Balance Highpass Effects
0.5 (2Dhex) (05hex) (01hex)
D Volume
DACM_L
DACM_R MB
(00hex)
ADR-Bus Interface
Decoded Standards: - NICAM - A2 - AM - BTSC - EIA-J - SAT - FM-Radio
NICAM Deemphasis J17 Prescale
(10hex)
Stereo or A
Lowpass Beeper
(14hex) (2Dhex)
Level Adjust
(2C hex)
A DACM_SUB
Stereo or B
4
Standard and Sound Detection
I2C Read Register
I S1 I2S_DA_IN1 I2S Interface Prescale
(16hex)
2
5
Headphone Channel Matrix
(09hex)
Volume Bass/ Treble
(31/32hex)
D A
Loudness
Balance
DACA_L
(33hex)
(30hex)
(06hex)
DACA_R
I S2 I2S_DA_IN2 I2S Interface Prescale
(12hex)
2
6
I2S Channel Matrix
(0Bhex)
I2S Interface
I2S_DA_OUT
Quasi-Peak Channel Matrix
(0Chex)
Quasi-Peak Detector
I2C Read Register
(19hex) (1Ahex)
A D
SCART 2 Prescale
(0Dhex)
SCART1 Channel Matrix
(0Ahex)
Volume
D SCART1_L/R A
(07hex)
SCART2 Channel Matrix
Volume
D SCART2_L/R A
SC1_OUT_L
SC1_OUT_R
MSP 34x0G
SC2_OUT_L
SC2_OUT_R
(13hex)
Fig. 2-1: Signal flow block diagram of the MSP 34x0G (input and output names correspond to pin names)
9
MSP 34x0G
2.1. Architecture of the MSP 34x0G Family Fig. 2-1 on page 9 shows a simplified block diagram of the IC. The block diagram contains all features of the MSP 3450G. Other members of the MSP 34x0G family do not have the complete set of features: The demodulator handles only a subset of the standards presented in the demodulator block; NICAM processing is only possible in the MSP 3410G and MSP 3450G.
DATA SHEET
BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP subcarrier. Processing of DBX noise reduction or Micronas Noise Reduction (MNR). Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L-R)-carrier. FM-Satellite Sound: Demodulation of one or two FM carriers. Processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification. FM-Stereo-Radio: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Detection and evaluation of the pilot carrier and AM demodulation of the (L-R)-carrier. The demodulator blocks of all MSP 34x0G versions have identical user interfaces. Even completely different systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Codes. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 34x0G demodulator blocks are: Standard Selection: The controlling of the demodulator is minimized: All parameters, such as tuning frequencies or filter bandwidth, are adjusted automatically by transmitting one single value to the STANDARD SELECT register. For all standards, specific MSP standard codes are defined. Automatic Standard Detection: If the TV sound standard is unknown, the MSP 34x0G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code. Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 34x0G offers a configurable carrier mute feature, which is activated automatically if the TV sound standard is selected by means of the STANDARD SELECT register. If no FM carrier is detected at one of the two MSP demodulator channels, the corresponding demodulator output is muted. This is indicated in the STATUS register.
2.2. Sound IF Processing 2.2.1. Analog Sound IF Input The input pins ANA_IN1+, ANA_IN2+, and ANA_IN- offer the possibility to connect two different sound IF (SIF) sources to the MSP 34x0G. The analog-to-digital conversion of the preselected sound IF signal is done by an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of input levels. The highpass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ see Section 7.2. "Application Circuit" on page 104 are sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, further filtering is recommended.
2.2.2. Demodulator: Standards and Features The MSP 34x0G is able to demodulate all TV-sound standards worldwide including the digital NICAM system. Depending on the MSP 34x0G version, the following demodulation modes can be performed: A2 Systems: Detection and demodulation of two separate FM carriers (FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2. NICAM Systems: Demodulation and decoding of the NICAM carrier, detection and demodulation of the analog (FM or AM) carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz. Very high deviation FM-Mono: Detection and robust demodulation of one FM carrier with a maximum deviation of 540 kHz. BTSC-Stereo: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, AM demodulation of the (L-R)-carrier and detection of the SAP subcarrier. Processing of DBX noise reduction or Micronas Noise Reduction (MNR).
10
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
- "Stereo or A" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language A (on left and right). - "Stereo or B" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language B (on left and right). Fig. 2-2 and Table 2-2 show the source channel assignment of the demodulated signals in case of Automatic Sound Select mode for all sound standards. Note: The analog primary input channel contains the signal of the mono FM/AM carrier or the L+R signal of the MPX carrier. The secondary input channel contains the signal of the 2nd FM carrier, the L-R signal of the MPX carrier, or the SAP signal.
2.2.3. Preprocessing of Demodulator Signals The NICAM signals must be processed by a deemphasis filter and adjusted in level. The analog demodulated signals must be processed by a deemphasis filter, adjusted in level, and dematrixed. The correct deemphasis filters are already selected by setting the standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/ AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically by the Automatic Sound Selection.
2.2.4. Automatic Sound Select In the Automatic Sound Select mode, the dematrix function is automatically selected based on the identification information in the STATUS register. No I2C interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). The demodulator supports the identification check by switching between mono-compatible standards (standards that have the same FM-Mono carrier) automatically and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these standards. The same action is performed for the standards: D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM. Switching is only done in the absence of any stereo or bilingual identification. If identification is found, the MSP keeps the detected standard. In case of high bit-error rates, the MSP 34x0G automatically falls back from digital NICAM sound to analog FM or AM mono. Table 2-1 summarizes all actions that take place when Automatic Sound Select is switched on.
primary channel primary channel secondary channel
FM/AM Prescale
FM/AM
0
LS Ch. Matrix Source Select
NICAM A
NICAM
Automatic Sound Select
Stereo or A/B
1
Stereo or A
3
Output-Ch. matrices must be set once to stereo.
NICAM B
Prescale
Stereo or B
4
Fig. 2-2: Source channel assignment of demodulated signals in Automatic Sound Select Mode
2.2.5. Manual Mode Fig. 2-3 shows the source channel assignment of demodulated signals in case of manual mode. If manual mode is required, more information can be found in Section 6.7. "Demodulator Source Channels in Manual Mode" on page 101.
FM/AM FM-Matrix
FM/AM 0
LS Ch. Matrix Source Select
To provide more flexibility, the Automatic Sound Select block prepares four different source channels of demodulated sound (Fig. 2-2). By choosing one of the four demodulator channels, the preferred sound mode can be selected for each of the output channels (loudspeaker, headphone, etc.). This is done by means of the Source Select registers. The following source channels of demodulated sound are defined: - "FM/AM" channel: Analog mono sound, stereo if available. In case of NICAM, analog mono only (FM or AM mono). - "Stereo or A/B" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains both languages A (left) and B (right).
secondary channel
Prescale
NICAM A
NICAM
NICAM (Stereo or A/B) 1
Output-Ch. matrices must be set according to the standard.
NICAM B
Prescale
Fig. 2-3: Source channel assignment of demodulated signals in Manual Mode
2.3. Preprocessing for SCART and I2S Input Signals The SCART and I2S inputs need only be adjusted in level by means of the SCART and I2S prescale registers.
Micronas
May 27, 2003; 6251-476-1DS
11
MSP 34x0G
Table 2-1: Performed actions of the Automatic Sound Selection
Selected TV Sound Standard B/G-FM, D/K-FM, M-Korea, and M-Japan B/G-NICAM, L-NICAM, I-NICAM, D/K-NICAM Performed Actions
DATA SHEET
Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2-2. Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2-2. In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches back to NICAM if possible. A hysteresis prevents periodical switching.
B/G-FM, B/G-NICAM or D/K1-FM, D/K2-FM, D/K3-FM, and D/K-NICAM
Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and nonaudible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-mono sound carrier. Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP keeps the corresponding standard. Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator source channels according to Table 2-2. Detection of the SAP carrier. In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP switches automatically to SAP (see Table 2-2).
BTSC-STEREO, FM Radio M-BTSC-SAP
Table 2-2: Sound modes for the demodulator source channels with Automatic Sound Select
Source Channels in Automatic Sound Select Mode Broadcasted Sound Standard M-Korea B/G-FM D/K-FM M-Japan Selected MSP Standard Code3) 02 03, 081) 04, 05, 07, 0B1) 30 Broadcasted Sound Mode MONO STEREO BILINGUAL: Languages A and B B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM
(with high deviation FM)
FM/AM
(source select: 0)
Stereo or A/B
(source select: 1)
Stereo or A
(source select: 3)
Stereo or B
(source select: 4)
Mono Stereo Left = A Right = B analog Mono analog Mono analog Mono analog Mono Mono Stereo Mono Stereo Left = Mono Right = SAP Left = Mono Right = SAP Mono Stereo
Mono Stereo Left = A Right = B analog Mono NICAM Mono NICAM Stereo Left = NICAM A Right = NICAM B Mono Stereo Mono Stereo Left = Mono Right = SAP Left = Mono Right = SAP Mono Stereo
Mono Stereo A analog Mono NICAM Mono NICAM Stereo NICAM A Mono Stereo Mono Stereo Mono Mono Mono Stereo
Mono Stereo B analog Mono NICAM Mono NICAM Stereo NICAM B Mono Stereo Mono Stereo SAP SAP Mono Stereo
08, 032) 09 0A 0B, 042), 052) 0C, 0D
NICAM not available or error rate too high MONO STEREO BILINGUAL: Languages A and B
20, 21
MONO STEREO
20 BTSC 21
MONO + SAP STEREO + SAP MONO + SAP STEREO + SAP
FM Radio
40
MONO STEREO
1) 2) 3)
The Automatic Sound Select process will automatically switch to the mono compatible analog standard. The Automatic Sound Select process will automatically switch to the mono compatible digital standard. The MSP Standard Codes are defined in (see Table 3-7 on page 23).
12
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
2.5.2. BBE High Definition Sound License Notice: BBE is a registered trademark of BBE Sound Inc., the BBE Logo is a trademark of BBE Sound Inc. A license from BBE Sound Inc. is required before a BBE-version of the MSP 34x0G can be purchased. BBE High Definition Sound or, also called, Sonic Maximizer technology improves the clarity of music when played back via loudspeakers. A more "life like" feeling is created by BBE. The BBE-approved Micronas implementation works in the digital domain and thus needs no external components and does not suffer from tolerances and aging effects. All MSP 34x0G are shipped without BBE except otherwise ordered. When a BBE-version of the MSP 34x0G is ordered, it carries a special marking on the chip for identification. The BBE Sonic Maximizer functionality must be enabled by writing a "license key" into the MSP 34x0G. For information on how to obtain this license key from Micronas, please contact your Micronas sales representative.
2.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (one of the demodulator source channels, SCART, or I2S input) to the desired output channels (loudspeaker, headphone, etc.). All input and output signals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the sound mode can be set to sound A, sound B, stereo, or mono by means of the output channel matrix. If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals.
2.5. Audio Baseband Processing 2.5.1. SRS WOW License Notice: SRS, SRS WOW, and the SRS Logo are trademarks of SRS Labs, Inc. A license from SRS Labs, Inc. is required before an SRS-version of the MSP 34x0G can be purchased. SRS Labs' WOW technology enlarges the sound image field and improves the bass performance of television speakers. Manufacturers can save costs by licensing WOW while utilizing smaller speakers and still provide a higher quality audio experience. WOW consists of three sections: - Clarity Improvement, - 3D-Audio (SRS, Sound Retrieval System), and - Bass Enhancement (TruBass).
2.5.3. Micronas VOICE Micronas VOICE was developed to add the following improvements to speech signals: - Increase speech signal over background noise to increase intelligibility in noisy environments - Move voice to the foreground, closer to the listener, while other sounds are moved to the back - Improve voices that are hard to understand, leave clear voices largely undisturbed Micronas VOICE dynamically enhances those portions of speech that are important for intelligibility while at the same time decreasing portions of the signal that disturb intelligibility. The average amplitude of the signal is not changed. According to speech theory, there are two main effects that affect the intelligibility of speech. Micronas VOICE combines both effects to achieve a maximum enhancement of intelligibility. - Forward and backward masking: For intelligibility, consonants are more important than vowels, but the amplitude of consonants is much lower than that of vowels. The consonants are masked by the vowels. Therefore, the amplitude of consonants is increased and the amplitude of vowels decreased. - Phonemes and formants: Most important for intelligibility are the second to fourth formants of speech. These formants are detected and increased, while other parts of the signal are decreased.
Key features of WOW include: - Wider and taller sound image field - Larger sweet spot - Deep, rich bass tones - Quality improvements to audio listening experience - Improved clarity of speech All MSP 34x0G are shipped without SRS except otherwise ordered. When an SRS-version of MSP 34x0G is ordered, it carries a special marking on the chip for identification. The SRS WOW functionality must be enabled by writing a "license key" into the MSP 34x0G. For information on how to obtain this license key from Micronas, please contact your Micronas sales representative.
Micronas
May 27, 2003; 6251-476-1DS
13
MSP 34x0G
All MSP 34x0G are shipped without Micronas VOICE except otherwise ordered. When a Micronas VOICE version of the MSP 34x0G is ordered, it carries a special marking on the chip for identification. The Micronas VOICE functionality must be enabled by writing a "license key" into the MSP 34x0G. For information on how to obtain this license key from Micronas, please contact your Micronas sales representative.
DATA SHEET
2.5.5. Loudspeaker and Headphone Outputs The following baseband features are implemented in the loudspeaker and headphone output channels: bass/treble, loudness, balance, and volume. A square wave beeper can be added to the loudspeaker and headphone channel. The loudspeaker channel additionally performs: equalizer (not simultaneously with bass/treble), spatial effects, and a subwoofer crossover filter.
2.5.4. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The Automatic Volume Correction (AVC) solves this problem by equalizing the volume level. To prevent clipping, the AVC's gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see page 33). For input signals ranging from -24 dBr to 0 dBr, the AVC maintains a fixed output level of -18 dBr. Fig. 2-4 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is - SCART input/output 0 dBr = 2.0 Vrms - Loudspeaker and Aux output 0 dBr = 1.4 Vrms output level [dBr]
-18
2.5.6. Subwoofer Output The subwoofer signal is created by combining the left and right channels directly behind the loudness block using the formula (L+R)/2. Due to the division by 2, the D/A converter will not be overloaded, even with full scale input signals. The subwoofer signal is filtered by a third-order low-pass with programmable corner frequency followed by a level adjustment. At the loudspeaker channels, a complementary high-pass filter can be switched on. Subwoofer and loudspeaker output use the same volume (Loudspeaker Volume Register).
dB 5 1 0 -5 -10 -15 -20 -25
Amplitude @dBD 0
3 2
-24
-30
-24
-18
-12
-6
0
input level [dBr]
200 f
2000 Hz
Fig. 2-4: Simplified AVC characteristics
Fig. 2-5: Frequency response of subwoofer filter 0: sharp edge 1: medium edge 2: soft edge 3: very soft edge
14
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
2.5.8.2. Adding Harmonics Micronas BASS exploits the psychoacoustic phenomenon of the `missing fundamental'. Adding harmonics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental. In other words: The listener has the impression that a loudspeaker system seems to reproduce frequencies although physically not possible.
Amplitude (db)
2.5.7. Quasi-Peak Detector The quasi-peak readout register can be used to read out the quasi-peak level of any input source. The feature is based on following filter time constants: attack time: 1.3 ms decay time: 37 ms
2.5.8. Micronas BASS (MB) The Micronas Bass system extends the frequency range of loudspeakers or headphones. After the adaption of MB to the loudspeakers and the cabinet, further customizing of MB allows individual fine tuning of the sound. Micronas BASS is placed in the subwoofer path. For applications without a subwoofer, the enhanced bass signal can be added back onto the Left/Right channels (see Fig. 2-1 on page 9). MB combines two effects: dynamic amplification and adding harmonics.
Frequency MB_HP
Fig. 2-7: Adding harmonics
2.5.8.1. Dynamic Amplification Low frequency signals can be boosted while the output signal amplitude is measured. If the amplitude comes close to a definable limit, the gain is reduced automatically in dynamic Volume mode. Therefore, the system adapts to the signal amplitude which is really present at the output of the MSP device. Clipping effects are avoided.
Amplitude (db)
2.5.8.3. Micronas BASS Parameters Several parameters allow tuning the characteristics of Micronas BASS according to the TV loudspeaker, the cabinet, and personal preferences (see Table 3-11). For more detailed information on how to set up MB, please refer to the corresponding application note.
2.6. SCART Signal Routing 2.6.1. SCART DSP In and SCART Out Select The SCART DSP Input Select and SCART Output Select blocks include full matrix switching facilities. To design a TV set with four pairs of SCART-inputs and two pairs of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB user register (see page 41).
Frequency MB_HP MB_LP SUBW_FREQ
Fig. 2-6: Dynamic amplification
Micronas
Signal Level
MB_LIMIT
May 27, 2003; 6251-476-1DS
15
MSP 34x0G
2.6.2. Stand-by Mode If the MSP 34x0G is switched off by first pulling STANDBYQ low and then (after >1 s delay) switching off DVSUP and AVSUP, but keeping AHVSUP (`Stand-by'-mode), the SCART switches maintain their position and function. This allows the copying from SCART-input to SCART-output in the TV set's stand-by mode. In case of power on or starting from stand-by (switching on the DVSUP and AVSUP, RESETQ going high 2 ms later), all internal registers except the ACB register (see page 41) are reset to the default configuration (see Table 3-5 on page 20). The reset position of the ACB register becomes active after the first I2C transmission into the Baseband Processing part. By transmitting the ACB register first, the reset state can be redefined. 2.7. I2S Bus Interface The MSP 34x0G has a synchronous master/slave input/output interface running on 32 kHz. The interface accepts two formats: 1. I2S_WS changes at the word boundary 2. I2S_WS changes one I2S-clock period before the word boundaries. All I2S options are set by means of the MODUS and the I2S_CONFIGURATION registers. The I2S bus interface consists of five pins: - I2S_DA_IN1, I2S_DA_IN2: I2S serial data input: 16, 18....32 bits per sample - I2S_DA_OUT: I2S serial data output: 16, 18...32 bits per sample - I2S_CL: I2S serial clock - I2S_WS: I2S word strobe signal defines the left and right sample If the MSP 34x0G serves as the master on the I2S interface, the clock and word strobe lines are driven by the IC. In this mode, only 16 or 32 bits per sample can be selected. In slave mode, these lines are input to the IC and the MSP clock is synchronized to 576 times the I2S_WS rate (32 kHz). NICAM operation is not possible in slave mode. An I2S timing diagram is shown in Fig. 4-27 on page 73. 2.9. Digital Control I/O Pins and Status Change Indication 2.8. ADR Bus Interface
DATA SHEET
For the ASTRA Digital Radio System (ADR), the MSP 3400G, MSP 3410G, and MSP 3450G performs preprocessing such as carrier selection and filtering. Via the 3-line ADR-bus, the resulting signals are transferred to the DRP 3510A coprocessor, where the source decoding is performed. To be prepared for an upgrade to ADR with an additional DRP board, the following lines of MSP 34x0G should be provided on a feature connector: - AUD_CL_OUT - I2S_DA_IN1 or I2S_DA_IN2 - I2S_DA_OUT - I2S_WS - I2S_CL - ADR_CL, ADR_WS, ADR_DA For more details, please refer to the DRP 3510A data sheet.
The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I2C-bus by means of the ACB register (see page 41). This enables the controlling of external hardware switches or other devices via I2C-bus. The digital input/output pins can be set to high impedance by means of the MODUS register (see page 26). In this mode, the pins can be used as input. The current state can be read out of the STATUS register (see page 28). Optionally, the pin D_CTR_I/O_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register STATUS. This makes polling unnecessary, I2C bus interactions are reduced to a minimum (see STATUS register on page 28 and MODUS register on page 26).
2.10. Clock PLL Oscillator and Crystal Specifications The MSP 34x0G derives all internal system clocks from the 18.432 MHz oscillator. In NICAM or in I2SSlave mode, the clock is phase-locked to the corresponding source. Therefore, it is not possible to use NICAM and I2S-Slave mode at the same time. For proper performance, the MSP clock oscillator requires a 18.432 MHz crystal. Note that for the phase-locked modes (NICAM, I2S-Slave), crystals with tighter tolerance are required.
16
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
response time is about 0.3 ms. If the MSP cannot accept another byte of data (e.g. while servicing an internal interrupt), it holds the clock line I2C_CL low to force the transmitter into a wait state. The I2C Bus Master must read back the clock line to detect when the MSP is ready to receive the next I2C transmission. The positions within a transmission where this may happen are indicated by 'Wait' in Section 3.1.3. The maximum wait period of the MSP during normal operation mode is less than 1 ms.
3. Control Interface 3.1. I2C Bus Interface The MSP 34x0G is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the MSP 34x0G device addresses. In order to allow up to three MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 34x0G responds to different device addresses. A device address pair is defined as a write address and a read address (see Table 3-1). Writing is done by sending the write device address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Refer to Section 3.1.3. for the I2C bus protocol and to Section 3.4. "Programming Tips" on page 43 for proposals of MSP 34x0G I2C telegrams. See Table 3-2 for a list of available subaddresses. Besides the possibility of hardware reset, the MSP can also be reset by means of the RESET bit in the CONTROL register by the controller via I2C bus. Due to the architecture of the MSP 34x0G, the IC cannot react immediately to an I2C request. The typical Table 3-1: I2C Bus Device Addresses
ADR_SEL Mode MSP device address Low (connected to DVSS) Write 80hex Read 81hex
3.1.1. Internal Hardware Error Handling In case of any hardware problems (e.g. interruption of the power supply of the MSP), the MSP's wait period is extended to 1.8 ms. After this time period elapses, the MSP releases data and clock lines.
Indication and solving the error status: To indicate the error status, the remaining acknowledge bits of the actual I2C-protocol will be left high. Additionally, bit[14] of CONTROL is set to one. The MSP can then be reset via the I2C bus by transmitting the RESET condition to CONTROL.
Indication of reset: Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL. A general timing diagram of the I2C bus is shown in Fig. 4-25 on page 71.
High (connected to DVSUP) Write 84hex Read 85hex Write 88hex
Left Open Read 89hex
Table 3-2: I2C Bus Subaddresses
Name CONTROL WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 Hex Value 00 10 11 12 13 Mode Read/Write Write Write Write Write Function Write: Software reset of MSP (see Table 3-3) Read: Hardware error status of MSP write address demodulator read address demodulator write address DSP read address DSP
Micronas
May 27, 2003; 6251-476-1DS
17
MSP 34x0G
3.1.2. Description of CONTROL Register
DATA SHEET
Table 3-3: CONTROL as a Write Register
Name CONTROL Subaddress 00hex Bit[15] (MSB) 1 : RESET 0 : normal Bits[14:0] 0
Table 3-4: CONTROL as a Read Register
Name CONTROL Subaddress 00hex %LW>@ 06% RESET status after last reading of CONTROL: 0 : no reset occured 1 : reset occured Bit>@ Internal hardware status: 0 : no error occured 1 : internal error occured BitV>@ not of interest
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be reset.
3.1.3. Protocol Description Write to DSP or Demodulator
S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK P high low high low
Read from DSP or Demodulator
S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK S high low read device address Wait ACK data-byte- ACK data-byte NAK P high low
Write to Control Register
S Wait write device address ACK sub-addr ACK data-byte ACK data-byte ACK P high low
Read from Control Register
S Wait write device address ACK 00hex ACK S read device address Wait ACK data-byte- ACK data-byte NAK P high low
Note: S = P= ACK = NAK =
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate `End of Read' or from MSP indicating internal error state Wait = I2C-Clock line is held low, while the MSP is processing the I2C command. This waiting time is max. 1 ms
18
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
I2C_DA S I2C_CL
1 0 P
Fig. 3-1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.4. Proposals for General MSP 34x0G I2C Telegrams 3.1.4.1. Symbols daw dar < > aa dd write device address (80hex, 84hex or 88hex) read device address (81hex, 85hex or 89hex) Start Condition Stop Condition Address Byte Data Byte
3.2. Start-Up Sequence: Power-Up and I2C-Controlling After POWER-ON or RESET (see Fig. 4-24), the IC is in an inactive state. All registers are in the Reset position (see Table 3-5 and Table 3-6), the analog outputs are muted. The controller has to initialize all registers for which a non-default setting is necessary.
3.3. MSP 34x0G Programming Interface 3.3.1. User Registers Overview
3.1.4.2. Write Telegrams

write to CONTROL register write data into demodulator write data into DSP
3.1.4.3. Read Telegrams
read data from CONTROL register read data from demodulator read data from DSP

The MSP 34x0G is controlled by means of user registers. The complete list of all user registers are given in Table 3-5 and Table 3-6. The registers are partitioned into the Demodulator section (Subaddress 10hex for writing, 11hex for reading) and the Baseband Processing sections (Subaddress 12hex for writing, 13hex for reading). Write and read registers are 16 bit wide, whereby the MSB is denoted bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All write registers, except the demodulator write registers are readable. Unused parts of the 16-bit write registers must be zero. Addresses not given in this table must not be accessed. For reasons of software compatibility to the MSP 34xxD, a Manual/Compatibility Mode is available. More read and write registers together with a detailed description can be found in "Appendix B: Manual/Compatibility Mode" on page 87.
3.1.4.4. Examples
<80 <80 <80 <80 <80 <80 00 00 10 10 11 12 80 00 00 00 02 00 00> RESET MSP statically 00> Clear RESET 30 00 01> Automatic Sound Select = ON 20 00 03> Set demodulator to stand. 03hex 00 <81 dd dd> Read STATUS 08 01 20> Set loudspeaker channel
source to Stereo or A/B and Matrix to Stereo (transparent mode)
More examples of typical application protocols are listed in Section 3.4. "Programming Tips" on page 43.
Micronas
May 27, 2003; 6251-476-1DS
19
MSP 34x0G
DATA SHEET
Table 3-5: List of MSP 34x0G Write Registers
Write Register Address (hex) Bits Description and Adjustable Range Reset See Page
I2C Subaddress = 10hex ; Registers are not readable STANDARD SELECT MODUS I2S CONFIGURATION 00 20 00 30 00 40 [15:0] [15:0] [15:0] Initial Programming of the Demodulator Demodulator, Automatic and Configuration of I2S options I2S options 00 00 00 00 00 00 24 26 27
I2C Subaddress = 12hex ; Registers are all readable by using I2C Subaddress = 13hex Volume loudspeaker channel Volume / Mode loudspeaker channel 00 00 [15:8] [7:0] [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control / Compromise/ Dynamic [0...100 / 100% and 100 / 0...100%] [-127...0 / 0 dB and 0 / -128...0 dB] [Linear / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [-100%...OFF...+100%] [SBE, SBE+PSE] [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control / Compromise/ Dynamic [+12 dB ... -114 dB, MUTE] [FM/AM, NICAM, SCART, I S1, I S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM/AM, NICAM, SCART, I2S1, I2S2]
2 2
MUTE 00hex
32
Balance loudspeaker channel [L/R] Balance mode loudspeaker Bass loudspeaker channel Treble loudspeaker channel Loudness loudspeaker channel Loudness filter characteristic Spatial effect strength loudspeaker ch. Spatial effect mode/customize Volume headphone channel Volume / Mode headphone channel
00 01
[15:8] [7:0]
100%/100% linear mode 0 dB 0 dB 0 dB NORMAL OFF SBE+PSE MUTE 00hex
33
00 02 00 03 00 04
[15:8] [15:8] [15:8] [7:0]
34 35 36
00 05
[15:8] [7:0]
37
00 06
[15:8] [7:0]
32
Volume SCART1 output channel Loudspeaker source select Loudspeaker channel matrix Headphone source select Headphone channel matrix SCART1 source select SCART1 channel matrix I2S source select I2S channel matrix Quasi-peak detector source select Quasi-peak detector matrix Prescale SCART input Prescale FM/AM FM matrix Prescale NICAM Prescale I2S2 ACB : SCART Switches a. D_CTR_I/O Beeper
00 07 00 08
[15:8] [15:8] [7:0]
MUTE FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA 00hex 00hex NO_MAT 00hex 10hex 00hex 00/00hex
40 31 31 31 31 31 31 31 31 31 31 30 29 30 30 30 41 41
00 09
[15:8] [7:0]
[SOUNDA, SOUNDB, STEREO, MONO...] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM/AM, NICAM, SCART, I S1, I S2] [SOUNDA, SOUNDB, STEREO, MONO...] [00hex ... 7Fhex] [00hex ... 7Fhex] [NO_MAT, GSTEREO, KSTEREO] [00hex ... 7Fhex] (MSP 3410G, MSP 3450G only) [00hex ... 7Fhex] Bits [15..0] [00hex ... 7Fhex]/[00hex ... 7Fhex]
2 2
00 0A
[15:8] [7:0]
00 0B
[15:8] [7:0]
00 0C
[15:8] [7:0]
00 0D 00 0E
[15:8] [15:8] [7:0]
00 10 00 12 00 13 00 14
[15:8] [15:8] [15:0] [15:0]
20
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-5: List of MSP 34x0G Write Registers, continued
Write Register Prescale I2S1 Tone control mode Equalizer loudspeaker ch. band 1 Equalizer loudspeaker ch. band 2 Equalizer loudspeaker ch. band 3 Equalizer loudspeaker ch. band 4 Equalizer loudspeaker ch. band 5 Automatic Volume Correction Address (hex) 00 16 00 20 00 21 00 22 00 23 00 24 00 25 00 29 Bits [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:12] [11:8] Subwoofer level adjust Subwoofer corner frequency Subwoofer characteristics Subwoofer complementary high-pass Balance headphone channel [L/R] Balance mode headphone Bass headphone channel Treble headphone channel Loudness headphone channel Loudness filter characteristic Volume SCART2 output channel SCART2 source select SCART2 channel matrix Micronas BASS Effect Strength Micronas BASS Amplitude Limit Micronas BASS Harmonic Content Micronas BASS Low Pass Corner Frequency Micronas BASS High Pass Corner Frequency 00 68 00 69 00 6A 00 6B 00 6C 00 40 00 41 00 31 00 32 00 33 00 30 00 2C 00 2D [15:8] [15:8] [7:4] [3:0] [15:8] [7:0] [15:8] [15:8] [15:8] [7:0] [15:8] [15:8] [7:0] [15:8] [15:8] [15:8] [15:8] [15:8] Description and Adjustable Range [00hex ... 7Fhex] [Bass/Treble, Equalizer] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [off, on] [decay time] [+12 dB ... -30 dB, mute] [50 Hz ... 400 Hz] [sharp, medium, soft, very soft] [off, on, Micronas BASS to Main] [0...100 / 100% and 100 / 0...100%] [-127...0 / 0 dB and 0 / -128...0 dB]] [Linear mode / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [+12 dB ... -114 dB, MUTE] [FM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [0 dB ... 127 dB, off] [0 dBFS... -32 dBFS] [0% ... 100%] [50 Hz ... 300 Hz] [20 Hz ... 300 Hz] Reset 10hex Bass/Treble 0 dB 0 dB 0 dB 0 dB 0 dB off 00hex 0 dB 00hex sharp off 100 %/100 % linear mode 0 dB 0 dB 0 dB NORMAL 00hex FM SOUNDA off 0 dBFS 0% 0 Hz 0 Hz 40 31 31 38 39 39 39 39 34 35 36 38 38 38 38 33 See Page 30 34 35 35 35 35 35 33
Micronas
May 27, 2003; 6251-476-1DS
21
MSP 34x0G
DATA SHEET
Table 3-6: List of MSP 34x0G Read Registers
Read Register Address (hex) Bits Description and Adjustable Range See Page
I2C Subaddress = 11hex ; Registers are not writable STANDARD RESULT STATUS 00 7E 02 00 [15:0] [15:0] Result of Automatic Standard Detection (see Table 3-8 on page 25) Monitoring of internal settings e.g. Stereo, Mono, Mute etc. . 28 28
I2C Subaddress = 13hex ; Registers are not writable Quasi peak readout left Quasi peak readout right MSP hardware version code MSP major revision code MSP product code MSP ROM version code 00 1F 00 19 00 1A 00 1E [15:0] [15:0] [15:8] [7:0] [15:8] [7:0] [00hex ... 7FFFhex]16 bit two's complement [00hex ... 7FFFhex]16 bit two's complement [00hex ... FFhex] [00hex ... FFhex] [00hex ... FFhex] [00hex ... FFhex] 42 42 42 42 42 42
22
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
3.3.2. Description of User Registers Table 3-7: Standard Codes for STANDARD SELECT register
MSP Standard Code (Data in hex) TV Sound Standard Automatic Standard Detection 00 01 Start Automatic Standard Detection and sets detected standards Standard Selection 00 02 00 03 00 04 00 05 00 06 M-Dual FM-Stereo B/G -Dual FM-Stereo1) D/K1-Dual FM-Stereo2) 4.5/4.724212 5.5/5.7421875 6.5/6.2578125 6.5/6.7421875 6.5 3400, -10, -20, -40, -50 3400, -10, -50 all Sound Carrier Frequencies in MHz MSP 34x0G Version
D/K2-Dual FM-Stereo2) D/K -FM-Mono with HDEV33), not detectable by Automatic Standard Detection, HDEV33) SAT-Mono (i.e. Eutelsat, s. Table 6-18) D/K3-Dual FM-Stereo B/G -NICAM-FM L -NICAM-AM I -NICAM-FM D/K -NICAM-FM
2) 1)
00 07 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 20 00 21 00 30 00 40 00 50 00 51 00 60
1) 2) 3) 4)
6.5/5.7421875 5.5/5.85 6.5/5.85 6.0/6.552 6.5/5.85 6.5/5.85 6.5/5.85 4.5 3420, -40, -50 3410, -50
D/K -NICAM-FM with HDEV24), not detectable by Automatic Standard Detection, for China D/K -NICAM-FM with HDEV33), not detectable by Automatic Standard Detection, for China BTSC-Stereo BTSC-Mono + SAP M-EIA-J Japan Stereo FM-Stereo Radio with 75 s Deemphasis SAT-Mono (s. Table 6-18) SAT-Stereo (s. Table 6-18) SAT ADR (Astra Digital Radio)
4.5 10.7 6.5 7.02/7.20 6.12 3400, -10, -50
In case of Automatic Sound Select, the B/G-codes 3hex and 8hex are equivalent. In case of Automatic Sound Select, the D/K-codes 4hex, 5hex, 7hex and Bhex are equivalent. HDEV3: Max. FM deviation must not exceed 540 kHz HDEV2: Max. FM deviation must not exceed 360 kHz
Micronas
May 27, 2003; 6251-476-1DS
23
MSP 34x0G
3.3.2.1. STANDARD SELECT Register The TV sound standard of the MSP 34x0G demodulator is determined by the STANDARD SELECT register. There are two ways to use the STANDARD SELECT register: - Setting up the demodulator for a TV sound standard by sending the corresponding standard code with a single I2C bus transmission. - Starting the Automatic Standard Detection for terrestrial TV standards. This is the most comfortable way to set up the demodulator. Within 0.5 s, the detection and setup of the actual TV sound standard is performed. The detected standard can be read out of the STANDARD RESULT register by the control processor. This feature is recommended for the primary setup of a TV set. Outputs should be muted during Automatic Standard Detection. The Standard Codes are listed in Table 3-7. 3.3.2.3. STANDARD RESULT Register Selecting a TV sound standard via the STANDARD SELECT register initializes the demodulator. This includes: AGC-settings and carrier mute, tuning frequencies, FIR-filter settings, demodulation mode (FM, AM, NICAM), deemphasis and identification mode. TV stereo sound standards that are unavailable for a specific MSP version are processed in analog mono sound of the standard. In that case, stereo or bilingual processing will not be possible. For a complete setup of the TV sound processing from analog IF input to the source selection, the transmissions as shown in Section 3.5. are necessary. For reasons of software compatibility to the MSP 34xxD, a Manual/Compatibility mode is available. A detailed description of this mode can be found on page 87.
DATA SHEET
3.3.2.2. Refresh of STANDARD SELECT Register A general refresh of the STANDARD SELECT register is not allowed. However, the following method enables watching the MSP 34x0G "alive" status and detection of accidental resets (only versions B6 and later): - After Power-on, bit[15] of CONTROL will be set; it must be read once to enable the reset-detection feature. - Reading of the CONTROL register and checking the reset indicator bit[15] . - If bit[15] is "0", any refresh of the STANDARD SELECT register is not allowed. - If bit[15] is "1", indicating a reset, a refresh of the STANDARD SELECT register and all other MSPG registers is required.
If Automatic Standard Detection is selected in the STANDARD SELECT register, status and result of the Automatic Standard Detection process can be read out of the STANDARD RESULT register. The possible results are based on the mentioned Standard Code and are listed in Table 3-8. In cases where no sound standard has been detected (no standard present, too much noise, strong interferers, etc.) the STANDARD RESULT register contains 00 00hex. In that case, the controller has to start further actions (for example set the standard according to a preference list or by manual input). As long as the STANDARD RESULT register contains a value greater than 07 FFhex, the Automatic Standard Detection is still active. During this period, the MODUS and STANDARD SELECT register must not be written. The STATUS register will be updated when the Automatic Standard Detection has finished. If a present sound standard is unavailable for a specific MSP-version, it detects and switches to the analog mono sound of this standard. Example: The MSPs 3420G and 3440G will detect a B/G-NICAM signal as standard 3 and will switch to the analog FMMono sound.
24
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-8: Results of the Automatic Standard Detection
Broadcasted Sound Standard Automatic Standard Detection could not find a sound standard B/G-FM B/G-NICAM I FM-Radio M-Korea M-Japan M-BTSC STANDARD RESULT Register Read 007Ehex 0000hex
0003hex 0008hex 000Ahex 0040hex 0002hex (if MODUS[14,13]=00) 0020hex (if MODUS[14,13]=01) 0030hex (if MODUS[14,13]=10)
L-AM D/K1 D/K2 D/K3 L-NICAM D/K-NICAM Automatic Standard Detection still active
0009hex (if MODUS[12]=0) 0004hex (if MODUS[12]=1) 0009hex (if MODUS[12]=0) 000Bhex (if MODUS[12]=1) >07FFhex
Micronas
May 27, 2003; 6251-476-1DS
25
MSP 34x0G
3.3.2.4. Write Registers on I2C Subaddress 10hex Table 3-9: Write registers on I2C subaddress 10hex Register Address 00 20hex Function STANDARD SELECTION Register Defines TV-Sound or FM-Radio Standard bit[15:0] 00 01hex 00 02hex ... 00 60hex start Automatic Standard Detection MSP Standard Codes (see Table 3-7) Name
DATA SHEET
STANDARD_SEL
00 30hex
MODUS Register Preference in Automatic Standard Detection: bit[15] bit[14:13] 0 1 2 3 bit[12] 0 1 0 undefined, must be 0 detected 4.5 MHz carrier is interpreted as:1) standard M (Korea) standard M (BTSC) standard M (Japan) chroma carrier (M/N standards are ignored) detected 6.5 MHz carrier is interpreted as:1) standard L (SECAM) standard D/K1, D/K2, D/K3, or D/K NICAM
MODUS
General MSP 34x0G Options bit[11:9] bit[8] bit[7] bit[6] 0 1 bit[5] bit[4] bit[3] 0 0/1 0/1 0 0/1 0/1 undefined, must be 0 ANA_IN1+/ANA_IN2+; select analog sound IF input pin active/tristate state of audio clock output pin AUD_CL_OUT I2S word strobe alignment WS changes at data word boundary WS changes one clock cycle in advance master/slave mode of I2S interface (must be set to 0 (= Master) in case of NICAM mode) active/tristate state of I2S output pins state of digital output pins D_CTR_I/O_0 and _1 active: D_CTR_I/O_0 and _1 are output pins (can be set by means of the ACB register. see also: MODUS[1]) tristate: D_CTR_I/O_0 and _1 are input pins (level can be read out of STATUS[4,3]) undefined, must be 0 disable/enable STATUS change indication by means of the digital I/O pin D_CTR_I/O_1 Necessary condition: MODUS[3] = 0 (active) off/on: Automatic Sound Select
1 bit[2] bit[1] 0 0/1
bit[0]
1)
0/1
Valid at the next start of Automatic Standard Detection.
26
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-9: Write registers on I2C subaddress 10hex, continued Register Address 00 40hex Function I2S CONFIGURATION Register bit[15:1] bit[0] 0 1 0 not used, must be set to "0" I2S_CL frequency and I2S data sample length for master mode 2 x 16 bit (1.024 MHz) 2 x 32 bit (2.048 MHz) Name I2S_CONFIG
Micronas
May 27, 2003; 6251-476-1DS
27
MSP 34x0G
3.3.2.5. Read Registers on I2C Subaddress 11hex Table 3-10: Read Registers on I2C Subaddress 11hex Register Address 00 7Ehex Function STANDARD RESULT Register Readback of the detected TV sound or FM-Radio Standard bit[15:0] 00 00hex Automatic Standard Detection could not find a sound standard MSP Standard Codes (see Table 3-8 on page 25) Name
DATA SHEET
STANDARD_RES
00 02hex ... 00 40hex >07 FFhex Automatic Standard Detection still active 02 00hex STATUS Register
STATUS
Contains all user relevant internal information about the status of the MSP bit[15:10] bit[8] 0/1 undefined "1" indicates bilingual sound mode or SAP present (internally evaluated from received analog or digital identification signals) "1" indicates independent mono sound (only for NICAM) mono/stereo indication (internally evaluated from received analog or digital identification signals) analog sound standard (FM or AM) active this pattern will not occur digital sound (NICAM) available bad reception condition of digital sound (NICAM) due to: a. high error rate b. unimplemented sound code c. data transmission only low/high level of digital I/O pin D_CTR_I/O_1 low/high level of digital I/O pin D_CTR_I/O_0 detected secondary carrier (2nd A2 or SAP sub-carrier) no secondary carrier detected detected primary carrier (Mono or MPX carrier) no primary carrier detected undefined
bit[7] bit[6]
0/1 0/1
bit[5,9]
00 01 10 11
bit[4] bit[3] bit[2] bit[1] bit[0]
0/1 0/1 0 1 0 1
If STATUS change indication is activated by means of MODUS[1]: Each change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high level. Reading the STATUS register resets D_CTR_I/O_1.
28
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
3.3.2.6. Write Registers on I2C Subaddress 12hex Table 3-11: Write Registers on I2C Subaddress 12hex Register Address Function Name
PREPROCESSING 00 0Ehex FM/AM Prescale bit[15:8] 00hex ... 7Fhex 00hex Defines the input prescale gain for the demodulated FM or AM signal off (RESET condition) PRE_FM
For all FM modes except satellite FM and AM-mode, the combinations of prescale value and FM deviation listed below lead to internal full scale with 1 kHz test signal and 50 s emphasis. FM mode bit[15:8] 7Fhex 48hex 30hex 24hex 18hex 13hex 28 kHz FM deviation 50 kHz FM deviation 75 kHz FM deviation 100 kHz FM deviation 150 kHz FM deviation 180 kHz FM deviation (limit)
FM high deviation mode (HDEV2, MSP Standard Code = Chex) bit[15:8] 30hex 14hex 150 kHz FM deviation 360 kHz FM deviation (limit)
FM very high deviation mode (HDEV3, MSP Standard Code = 6 and Dhex) bit[15:8] 20hex 1Ahex 450 kHz FM deviation 540 kHz FM deviation (limit)
Satellite FM with adaptive deemphasis bit[15:8] 10hex recommendation
AM mode (MSP Standard Code = 9) bit[15:8] 7Chex recommendation for SIF input levels from 0.1 Vpp to 0.8 Vpp (Due to the AGC being switched on, the AM-output level remains stable and independent of the actual SIF-level in the mentioned input range)
Micronas
May 27, 2003; 6251-476-1DS
29
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address
(continued)
DATA SHEET
Function FM Matrix Modes Defines the dematrix function for the demodulated FM signal bit[7:0] 00hex 01hex 02hex 03hex 04hex no matrix (used for bilingual and unmatrixed stereo sound) German stereo (Standard B/G) Korean stereo (also used for BTSC, EIA-J and FM Radio) sound A mono (left and right channel contain the mono sound of the FM/AM mono carrier) sound B mono
Name FM_MATRIX
00 0Ehex
In case of Automatic Sound Select = on, the FM Matrix Mode is set automatically. Writing to the FM/AM prescale register (00 0Ehex high part) is still allowed. In order not to disturb the automatic process, the low part of any I2C transmission to this register is ignored. Therefore, any FM-Matrix readback values may differ from data written previously. In case of Automatic Sound Select = off, the FM Matrix Mode must be set as shown in Table 6-17 of Appendix B. To enable a Forced Mono Mode set A2 THRESHOLD as described in Section 6.3.2.on page 91 00 10hex NICAM Prescale Defines the input prescale value for the digital NICAM signal bit[15:8] 00hex ... 7Fhex prescale gain examples: 00hex off 0 dB gain 20hex 9 dB gain (recommendation) 5Ahex +12 dB gain (maximum gain) 7Fhex 00 16hex 00 12hex I2S1 Prescale I2S2 Prescale Defines the input prescale value for digital I2S input signals bit[15:8] 00hex ... 7Fhex prescale gain examples: 00hex off 0 dB gain (recommendation) 10hex +18 dB gain (maximum gain) 7Fhex 00 0Dhex SCART Input Prescale Defines the input prescale value for the analog SCART input signal bit[15:8] 00hex ... 7Fhex prescale gain examples: 00hex off 0 dB gain (2 VRMS input leads to digital full scale) 19hex 7Fhex +14 dB gain (400 mVRMS input leads to digital full scale) PRE_SCART PRE_I2S1 PRE_I2S2 PRE_NICAM
30
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
SOURCE SELECT AND OUTPUT CHANNEL MATRIX 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex Source for: Loudspeaker Output Headphone Output SCART1 DA Output SCART2 DA Output I2S Output Quasi-Peak Detector bit[15:8] 00hex 01hex "FM/AM": demodulated FM or AM mono signal "Stereo or A/B": demodulator Stereo or A/B signal (in manual mode, this source is identical to the NICAM source in the MSP 3410D) "Stereo or A": demodulator Stereo Sound or Language A (only defined for Automatic Sound Select) "Stereo or B": demodulator Stereo Sound or Language B (only defined for Automatic Sound Select) SCART input I2S1 input I2S2 input SRC_MAIN SRC_AUX SRC_SCART1 SRC_SCART2 SRC_I2S SRC_QPEAK
03hex 04hex 02hex 05hex 06hex
For demodulator sources, see Table 2-2. 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex Matrix Mode for: Loudspeaker Output Headphone Output SCART1 DA Output SCART2 DA Output I2S Output Quasi-Peak Detector bit[7:0] Sound A Mono (or Left Mono) 00hex Sound B Mono (or Right Mono) 10hex Stereo (transparent mode) 20hex 30hex Mono (sum of left and right inputs divided by 2) special modes are available (see Section 6.5.1. on page 99) MAT_MAIN MAT_AUX MAT_SCART1 MAT_SCART2 MAT_I2S MAT_QPEAK
In Automatic Sound Select mode, the demodulator source channels are set according to Table 2-2. Therefore, the matrix modes of the corresponding output channels should be set to "Stereo" (transparent).
Micronas
May 27, 2003; 6251-476-1DS
31
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function
DATA SHEET
Name
LOUDSPEAKER AND HEADPHONE PROCESSING 00 00hex 00 06hex Volume Loudspeaker Volume Headphone bit[15:8] volume table with 1 dB step size +12 dB (maximum volume) 7Fhex +11 dB 7Ehex ... 74hex +1 dB 0 dB 73hex -1 dB 72hex ... -113 dB 02hex -114 dB 01hex Mute (reset condition) 00hex FFhex Fast Mute (needs about 75 ms until the signal is completely ramped down) higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table 0 must be set to 0 VOL_MAIN VOL_AUX
bit[7:5]
bit[4] bit[3:0]
clipping mode 0 reduce volume 1 reduce tone control 2 compromise 3 dynamic
With large scale input signals, positive volume settings may lead to signal clipping. The MSP 34x0G loudspeaker and headphone volume function is divided into a digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. To turn volume on again, the volume step that has been used before Fast Mute was activated must be transmitted. If the clipping mode is set to "reduce volume", the following rule is used: To prevent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB. If the clipping mode is "reduce tone control", the bass or treble value is reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume exceeds 12 dB. If the clipping mode is "compromise", the bass or treble value and volume are reduced half and half if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced half and half, where amplification together with volume exceeds 12 dB. If the clipping mode is "dynamic", volume is reduced automatically if the signal amplitudes would exceed -2 dBFS within the IC. For operation of Micronas BASS, dynamic mode must be switched on.
32
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address 00 29hex Function Automatic Volume Correction (AVC) Loudspeaker Channel bit[15:12] 00hex 08hex bit[11:8] 08hex 04hex 02hex 01hex AVC off (and reset internal variables) AVC on 8 sec decay time 4 sec decay time 2 sec decay time 20 ms decay time (should be used for approx. 100 ms after channel change) Name AVC
Note: AVC should not be used in any Dolby Prologic mode (with DPL 35xx), except in PANORAMA or 3D-PANORAMA mode, when only the loudspeaker output is active. 00 01hex 00 30hex Balance Loudspeaker Channel Balance Headphone Channel bit[15:8] Linear Mode Left muted, Right 100% 7Fhex Left 0.8%, Right 100% 7Ehex ... Left 99.2%, Right 100% 01hex Left 100%, Right 100% 00hex FFhex Left 100%, Right 99.2% ... Left 100%, Right 0.8% 82hex Left 100%, Right muted 81hex Logarithmic Mode 7Fhex Left -127 dB, Right 0 dB 7Ehex Left -126 dB, Right 0 dB ... Left -1 dB, Right 0 dB 01hex Left 0 dB, Right 0 dB 00hex Left 0 dB, Right -1 dB FFhex ... 81hex Left 0 dB, Right -127 dB Left 0 dB, Right -128 dB 80hex Balance Mode 00hex linear logarithmic 01hex BAL_MAIN BAL_AUX
bit[15:8]
bit[7:0]
Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected.
Micronas
May 27, 2003; 6251-476-1DS
33
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address 00 20hex Function Tone Control Mode Loudspeaker Channel bit[15:8] 00hex FFhex bass and treble is active equalizer is active
DATA SHEET
Name TONE_MODE
Defines whether Bass/Treble or Equalizer is activated for the loudspeaker channel. Bass and Equalizer cannot work simultaneously. If Equalizer is used, Bass, and Treble coefficients must be set to zero and vice versa. 00 02hex 00 31hex Bass Loudspeaker Channel Bass Headphone Channel bit[15:8] extended range +20 dB 7Fhex +18 dB 78hex +16 dB 70hex +14 dB 68hex normal range +12 dB 60hex +11 dB 58hex ... +1 dB 08hex 0 dB 00hex F8hex -1 dB ... -11 dB A8hex -12 dB A0hex Higher resolution is possible: an LSB step in the normal range results in a gain step of about 1/8 dB, in the extended range about 1/4 dB. With positive bass settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. BASS_MAIN BASS_AUX
34
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address 00 03hex 00 32hex Function Treble Loudspeaker Channel Treble Headphone Channel bit[15:8] 78hex 70hex ... 08hex 00hex F8hex ... A8hex A0hex +15 dB +14 dB +1 dB 0 dB -1 dB -11 dB -12 dB Name TREB_MAIN TREB_AUX
Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive treble settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. 00 21hex 00 22hex 00 23hex 00 24hex 00 25hex Equalizer Loudspeaker Channel Band 1 (below 120 Hz) Equalizer Loudspeaker Channel Band 2 (center: 500 Hz) Equalizer Loudspeaker Channel Band 3 (center: 1.5 kHz) Equalizer Loudspeaker Channel Band 4 (center: 5 kHz) Equalizer Loudspeaker Channel Band 5 (above: 10 kHz) bit[15:8] 60hex 58hex ... 08hex 00hex F8hex ... A8hex A0hex +12 dB +11 dB +1 dB 0 dB -1 dB -11 dB -12 dB EQUAL_BAND1 EQUAL_BAND2 EQUAL_BAND3 EQUAL_BAND4 EQUAL_BAND5
Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive equalizer settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain.
Micronas
May 27, 2003; 6251-476-1DS
35
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address 00 04hex 00 33hex Function Loudness Loudspeaker Channel Loudness Headphone Channel bit[15:8] Loudness Gain 44hex +17 dB +16 dB 40hex ... 04hex +1 dB +0.75 dB 03hex +0.5 dB 02hex +0.25 dB 01hex 0 dB 00hex Loudness Mode 00hex normal (constant volume at 1 kHz) 04hex Super Bass (constant volume at 2 kHz)
DATA SHEET
Name LOUD_MAIN LOUD_AUX
bit[7:0]
Higher resolution of Loudness Gain is possible: An LSB step results in a gain step of about 1/4 dB. Loudness increases the volume of low- and high-frequency signals, while keeping the amplitude of the reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz.
36
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address 00 05hex Function Spatial Effects Loudspeaker Channel bit[15:8] Effect Strength 7Fhex Enlargement 100% Enlargement 50% 3Fhex ... Enlargement 0.78% 01hex 00hex Effect off reduction 0.78% FFhex ... reduction 50% C0hex reduction 100% 80hex Spatial Effect Mode 0hex Stereo Basewidth Enlargement (SBE) and Pseudo Stereo Effect (PSE). (Mode A) 2hex Stereo Basewidth Enlargement (SBE) only. (Mode B) Spatial Effect High-Pass Gain max. high-pass gain 0hex 2/3 high-pass gain 2hex 1/3 high-pass gain 4hex 6hex min. high-pass gain automatic 8hex Name SPAT_MAIN
bit[7:4]
bit[3:0]
There are several spatial effect modes available: In mode A (low byte = 00hex), the spatial effect depends on the source mode. If the incoming signal is mono, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on. It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0hex yields a flat response for center signals (L = R), but a high-pass function for L or R only signals. A value of 6hex has a flat response for L or R only signals, but a low-pass function for center signals. By using 8hex, the frequency response is automatically adapted to the sound material by choosing an optimal high-pass gain.
Micronas
May 27, 2003; 6251-476-1DS
37
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function
DATA SHEET
Name
SUBWOOFER OUTPUT CHANNEL 00 2Chex Subwoofer Level Adjustment bit[15:8] 0Chex ... 01hex 00hex FFhex ... E3hex E2hex ... 80hex 00hex +12 dB +1 dB 0 dB (default) -1 dB -29 dB -30 dB Mute must be zero SUBW_LEVEL
bit[7:0]
If Micronas BASS is added onto the main channel, this register should be set to 00hex 00 2Dhex Subwoofer Corner Frequency bit[15:8] 5...40dec corner frequency in 10 Hz steps (range: 50...400 Hz) SUBW_FREQ
If Micronas BASS is active, SUBW_FREQ must be set to a value higher than the MB Lowpass Frequency (MB_LP). Choosing the corner frequency of the subwoofer closer to MB_LP results in a narrower MB frequency range. Recommended value: 1.5xMB_LP Subwoofer Characteristics bit[7:4] 0hex 1hex 2hex 3hex sharp edge Subwoofer characteristics (default) medium edge Subwoofer characteristics soft edge Subwoofer characteristics very soft edge Subwoofer characteristics SUBW_CHAR
An adjustable subwoofer filter characterisitic with four different filter sets can be selected. Due to the complementary filter design, the output of high- and lowpass filter add up to 0db at the crossover region for all filter sets. Subwoofer Complementary High-Pass Filter bit[3:0] 0hex 1hex 2hex loudspeaker channel unfiltered a complementary high-pass is processed in the loudspeaker output channel Micronas BASS added onto main channel SUBW_HP
MICRONAS BASS (MB) CONTROL REGISTERS 00 68hex Micronas BASS Effect Strength bit[15:8] bit[7:0] 00hex 7Fhex 00hex Micronas BASS OFF (default) maximum Micronas BASS must be zero MB_STR
The Micronas BASS effect strength can be adjusted in 1dB steps. A value of 44hex will yield a medium Micronas BASS effect.
38
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address 00 69hex Function Micronas BASS Amplitude Limit bit[15:8] 00hex FFhex ... E0hex 00hex 0 dBFS (default limitation) -1 dBFS -32 dBFS must be zero Name MB_LIM
bit[7:0]
The Micronas BASS Amplitude Limit defines the maximum allowed amplitude at the output of the MB relative to 0 dbFS. If the amplitude exceeds MB_LIM, the gain of the MB is automatically reduced. Note that the Volume Clipping Mode must be set to "dynamic" (see page 32). 00 6Ahex Micronas BASS Harmonic Content bit[15:8] 00hex 3Fhex 7Fhex 00hex no harmonics are added (default) 50% fundamentals + 50% harmonics 100% harmonics must be zero MB_HMC
bit[7:0]
MB creates harmonics of the frequencies below the MB highpass frequency (MB_HP). The variable MB_HMC describes the ratio of the harmonics towards the original signal. 00 6Bhex Micronas BASS Low Pass Corner Frequency bit[15:8] 5dec 6dec ... 30dec 00dec 50 Hz 60 Hz 300 Hz must be zero MB_LP
bit[7:0]
The MB lowpass corner frequency (range 50...300 Hz) defines the upper corner frequency of the MB bandpass filter. Recommended values are the same as for the MB highpass corner frequency (MB_HP). 00 6Chex Micronas BASS High Pass Corner Frequency bit[15:8] 3dec 4dec ... 30dec 00hex 30 Hz 40 Hz 300 Hz must be zero MB_HP
bit[7:0]
The MB highpass corner frequency defines the lower corner frequency of the MB bandpass filter. The highpass filter avoids loading the loudspeakers with low frequency components that are below the speakers' cut off frequency. Recommended values for subwoofer systems are around 5dec (=50 Hz), for regular TV sets around 10dec (=100 Hz).
Micronas
May 27, 2003; 6251-476-1DS
39
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function
DATA SHEET
Name
SCART OUTPUT CHANNEL 00 07hex 00 40hex Volume SCART1 Output Channel Volume SCART2 Output Channel bit[15:8] volume table with 1 dB step size +12 dB (maximum volume) 7Fhex +11 dB 7Ehex ... 74hex +1 dB 0 dB 73hex -1 dB 72hex ... -113 dB 02hex -114 dB 01hex Mute (reset condition) 00hex higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table 01hex this must be 01hex VOL_SCART1 VOL_SCART2
bit[7:5]
bit[4:0]
40
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
SCART SWITCHES AND DIGITAL I/O PINS 00 13hex ACB Register Defines the level of the digital output pins and the position of the SCART switches bit[15] bit[14] bit[13:5] 0/1 0/1 low/high of digital output pin D_CTR_I/O_1 (MODUS[3]=0) low/high of digital output pin D_CTR_I/O_0 (MODUS[3]=0) ACB_REG
SCART DSP Input Select xxxx00xx0 SCART1 to DSP input (RESET position) xxxx01xx0 MONO to DSP input (set Sound A Mono in the channel matrix mode for the corresponding output channels) xxxx10xx0 SCART2 to DSP input xxxx11xx0 SCART3 to DSP input xxxx00xx1 SCART4 to DSP input xxxx11xx1 mute DSP input
xx00xxx0x
bit[13:5]
SCART1 Output Select SCART3 input to SCART1 output (RESET position) xx01xxx0x SCART2 input to SCART1 output xx10xxx0x MONO input to SCART1 output xx11xxx0x SCART1 DA to SCART1 output xx00xxx1x SCART2 DA to SCART1 output xx01xxx1x SCART1 input to SCART1 output xx10xxx1x SCART4 input to SCART1 output xx11xxx1x mute SCART1 output SCART2 Output Select SCART1 DA to SCART2 output (RESET position) SCART1 input to SCART2 output MONO input to SCART2 output SCART2 DA to SCART2 output SCART2 input to SCART2 output SCART3 input to SCART2 output SCART4 input to SCART2 output mute SCART2 output
bit[13:5]
00xxxx0xx 01xxxx0xx 10xxxx0xx 00xxxx1xx 01xxxx1xx 10xxxx1xx 11xxxx1xx 11xxxx0xx
bit[4:0]
must be zero
The RESET position becomes active at the time of the first write transmission on the control bus to the audio processing part. By writing to the ACB register first, the RESET state can be redefined. BEEPER 00 14hex Beeper Volume and Frequency bit[15:8] Beeper Volume 00hex off maximum volume 7Fhex Beeper Frequency 01hex 16 Hz (lowest) 1 kHz 40hex 4 kHz FFhex BEEPER
bit[7:0]
Micronas
May 27, 2003; 6251-476-1DS
41
MSP 34x0G
3.3.2.7. Read Registers on I2C Subaddress 13hex Table 3-12: Read Registers on I2C Subaddress 13hex Register Address Function
DATA SHEET
Name
QUASI-PEAK DETECTOR READOUT 00 19hex 00 1Ahex Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right bit[15:0] 0hex... 7FFFhex QPEAK_L QPEAK_R
Values are 16 bit two's complement (only positive). A value of 4000hex corresponds to internal full scale. MSP 34x0G VERSION READOUT Registers 00 1Ehex MSP Hardware Version Code bit[15:8] 03hex MSP 34x0G - C12 MSP_HARD
A change in the hardware version code defines hardware optimizations that may have influence on the chip's behavior. The readout of this register is identical to the hardware version code in the chip's imprint. MSP Major Revision Code bit[7:0] 07hex MSP 34x1G - C12 MSP_REVISION
The major revision code of the MSP 34x0G is 7. 00 1Fhex MSP Product Code bit[15:8] 00hex 0Ahex 14hex 28hex 32hex 3Chex MSP 3400G - C12 MSP 3410G - C12 MSP 3420G - C12 MSP 3440G - C12 MSP 3450G - C12 MSP 3460G - C12 MSP_PRODUCT
By means of the MSP-Product Code, the control processor is able to decide which TV sound standards have to be considered. MSP ROM Version Code bit[7:0] 4Chex MSP 34x0G - C12 MSP_ROM
A change in the ROM version code defines internal software optimizations, that may have influence on the chip's behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new MSP 34x0G versions according to this number. To avoid compatibility problems with MSP 3410B and MSP 34x0D, an offset of 40hex is added to the ROM version code of the chip's imprint.
42
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
3.5. Examples of Minimum Initialization Codes Initialization of the MSP 34x0G according to these listings reproduces sound of the selected standard on the loudspeaker output. All numbers are hexadecimal. The examples have the following structure: 1. Perform an I2C controlled reset of the IC. 2. Write MODUS register (with Automatic Sound Select). 3. Set Source Selection for loudspeaker channel (with matrix set to STEREO). 4. Set Prescale (FM and/or NICAM and dummy FM matrix).
3.4. Programming Tips This section describes the preferred method for initializing the MSP 34x0G. The initialization is grouped into four sections: - SCART Signal Path (analog signal path) - Demodulator - SCART and I2S Inputs - Output Channels See Fig. 2-1 on page 9 for a complete signal flow.
SCART Signal Path 1. Select analog input for the SCART baseband processing (SCART DSP Input Select) by means of the ACB register. 2. Select the source for each analog SCART output (SCART Output Select) by means of the ACB register.
5. Write STANDARD SELECT register. 6. Set Volume loudspeaker channel to 0 dB.
3.5.1. B/G-FM (A2 or NICAM)
<80 00 80 00> <80 00 00 00> <80 10 00 30 20 03> // MODUS-Register: Automatic = on // Source Sel. = (St or A) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = MONO/SOUNDA // NICAM-Prescale = 5Ahex // Standard Select: A2 B/G or NICAM B/G <80 12 00 08 03 20> <80 12 00 0E 24 03> // Softreset
Demodulator For a complete setup of the TV sound processing from analog IF input to the source selection, the following steps must be performed: 1. Set MODUS register to the preferred mode and Sound IF input. 2. Choose preferred prescale (FM and NICAM) values. 3. Write STANDARD SELECT register. 4. If Automatic Sound Select is not active: Choose FM matrix repeatedly according to the sound mode indicated in the STATUS register. SCART and I2S Inputs 1. Select preferred prescale for SCART. 2. Select preferred prescale for I2S inputs (set to 0 dB after RESET).
<80 12 00 10 5A 00> <80 10 00 20 00 03> or <80 10 00 20 00 08> <80 12 00 00 73 00>
// Loudspeaker Volume 0 dB
3.5.2. BTSC-Stereo
<80 00 80 00> <80 00 00 00> <80 10 00 30 20 03> <80 12 00 08 03 20> <80 12 00 0E 24 03> <80 10 00 20 00 20> <80 12 00 00 73 00> // MODUS-Register: Automatic = on // Source Sel. = (St or A) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono // Standard Select: BTSC-STEREO // Loudspeaker Volume 0 dB // Softreset
3.5.3. BTSC-SAP with SAP at Loudspeaker Channel
<80 00 80 00> // Softreset // MODUS-Register: Automatic = on // Source Sel. = (St or B) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono // Standard Select: BTSC-SAP // Loudspeaker Volume 0 dB
Output Channels 1. Select the source channel and matrix for each output channel. 2. Set audio baseband processing. 3. Select volume for each output channel.
<80 00 00 00> <80 10 00 30 20 03> <80 12 00 08 04 20> <80 12 00 0E 24 03> <80 10 00 20 00 21> <80 12 00 00 73 00>
Micronas
May 27, 2003; 6251-476-1DS
43
MSP 34x0G
3.5.4. FM-Stereo Radio
<80 00 80 00> <80 00 00 00> <80 10 00 30 20 03> <80 12 00 08 03 20> <80 12 00 0E 24 03> <80 10 00 20 00 40> <80 12 00 00 73 00> // MODUS-Register: Automatic = on // Source Sel. = (St or A) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono // Standard Select: FM-STEREO-RADIO // Loudspeaker Volume 0 dB // Softreset
DATA SHEET
3.5.5. Automatic Standard Detection A detailed software flow diagram is shown in Fig. 3-2 on page 45.
<80 00 80 00> <80 00 00 00> <80 10 00 30 20 03> <80 12 00 08 03 20> <80 12 00 0E 24 03> <80 12 00 10 5A 00> <80 10 00 20 00 01> // MODUS-Register: Automatic = on // Source Sel. = (St or A) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono // NICAM-Prescale = 5Ahex // Standard Select: Automatic Standard Detection // Softreset
// Wait till STANDARD RESULT contains a value 07FF // IF STANDARD RESULT contains 0000 // do some error handling // ELSE <80 12 00 00 73 00> // Loudspeaker Volume 0 dB
3.5.6. Software Flow for Interrupt driven STATUS Check A detailed software flow diagram is shown in Fig. 3-2 on page 45. If the D_CTR_I/O_1 pin of the MSP 34x0G is connected to an interrupt input pin of the controller, the following interrupt handler can be applied to be automatically called with each status change of the MSP 34x0G. The interrupt handler may adjust the TV display according to the new status information.
Interrupt Handler: <80 11 02 00 <81 dd dd> // Read STATUS // adjust TV display with given status information // Return from Interrupt
44
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
@hyr for the essential bits: bdA2A AAAAAAAAAAA6hvpATqATryrpA2A
[1] = 1 Enable interrupt if STATUS changes [8] = 0 ANA_IN1+ is selected Define Preference for Automatic Standard Detection: [12] = 0 If 6.5 MHz, set SECAM-L [14:13] = 3 Ignore 4.5 MHz carrier
:ULWH 02'86 5HJLVWHU:
@hyr)
:ULWH 6285&( 6(/(&7 6HWWLQJV
set loudspeaker Source Select to "Stereo or A" set headphone Source Select to "Stereo or B" set SCART_Out Source Select to "Stereo or A/B" set Channel Matrix mode for all outputs to "Stereo"
Write FM/AM-Prescale Write NICAM-Prescale
:ULWH LQWR 67$1'$5' 6(/(&7 5HJLVWHU
(Start Automatic Standard Detection)
set previous standard or set standard manually according picture information
yes
Result = 0 ?
no expecting MSPG-interrupt
,Q FDVH RI 063* ,QWHUUXSW WR &RQWUROOHU
Read STATUS
Adjust TV-Display
If Bilingual, adjust Source Select setting if required
Fig. 3-2: Software flow diagram for a Minimum demodulator setup for a European Multistandard TV set applying the Automatic Sound Select feature
Micronas
May 27, 2003; 6251-476-1DS
45
MSP 34x0G
4. Specifications 4.1. Outline Dimensions
DATA SHEET
Fig. 4-1: PSDIP64-1: Plastic Shrink Dual In-line Package, 64 leads, 750 mil Ordering code: PP Weight approximately 8.77 g
46
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Fig. 4-2: PSDIP52-1: Plastic Shrink Dual In-line Package, 52 leads, 600 mil Ordering code: PO1) Weight approximately 5.13 g
1)
Micronas delivers two types of PSDIP52 packages (-1, -2). The packages have slightly different outline dimensions, but are considered identical. For logistics reasons, the customer cannot choose the package to be delivered.
Micronas
May 27, 2003; 6251-476-1DS
47
MSP 34x0G
DATA SHEET
Fig. 4-3: PSDIP52-2: Plastic Shrink Dual In-line Package, 52 leads, 600 mil Ordering code: PO1) Weight approximately 5.92 g
1)
Micronas delivers two types of PSDIP52 packages (-1, -2). The packages have slightly different outline dimensions, but are considered identical. For logistics reasons, the customer cannot choose the package to be delivered.
48
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Fig. 4-4: PMQFP80-11: Plastic Metric Quad Flat Package, 80 leads, 14 x 20 x 2.7 mm3, high standoff Ordering code: QA Weight approximately 1.68 g
Micronas
May 27, 2003; 6251-476-1DS
49
MSP 34x0G
DATA SHEET
Fig. 4-5: PMQFP64-2: Plastic Metric Quad Flat Package, 64 leads, 10 x 10 x 2 mm3 Ordering code: QI Weight approximately 0.5 g
50
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
4.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram DVSS: if not used, connect to DVSS AHVSS: connect to AHVSS Pin No.
PMQFP 80-11 PMQFP 64-2 PSDIP 64-1 PSDIP 52-1/-2
Pin Name
Type
Connection
(if not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
64 1 2 3 4 5 6 7 8 9 - - 10 - - 11 12 13 14 15 16 - - 17 18 19 20
8 9 10 11 12 13 14 15 16 17 - - 18 - - 19 20 21 22 23 24 - - 25 26 27 28
- 7 8 9 10 11 12 13 14 15 - - 16 - - 17 18 19 - - 20 - - 21 22 23 24
NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP DVSUP DVSS DVSS DVSS I2S_DA_IN2 NC NC NC RESETQ NC NC DACA_R DACA_L VREF2 DACM_R OUT OUT OUT IN IN IN/OUT IN/OUT IN/OUT IN/OUT OUT IN OUT OUT OUT
LV OBL OBL LV LV LV LV LV LV LV OBL OBL OBL OBL OBL OBL LV LV LV LV OBL LV LV LV LV OBL LV
Not connected I2C clock I2C data I2S clock I2S word strobe I2S data output I2S1 data input ADR data output ADR word strobe ADR clock Digital power supply 5 V Digital power supply 5 V Digital power supply 5 V Digital ground Digital ground Digital ground I2S2-data input Not connected Not connected Not connected Power-on-reset Not connected Not connected Headphone out, right Headphone out, left Reference ground 2 Loudspeaker out, right
Micronas
May 27, 2003; 6251-476-1DS
51
MSP 34x0G
DATA SHEET
Pin No.
PMQFP 80-11 PMQFP 64-2 PSDIP 64-1 PSDIP 52-1/-2
Pin Name
Type
Connection
(if not used)
Short Description
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
21 22 23 24 - 25 26 27 28 29 30 31 32 - - - 33 34 - 35 36 37 38 39 40 41 42 43 44 45 46
29 30 31 32 - 33 34 35 36 37 38 39 40 - - - 41 42 - 43 44 45 46 47 48 49 50 51 52 53 54
25 - 26 - - 27 28 29 30 31 32 33 34 - - - 35 36 - - - - 37 38 - 39 40 - 41 42 43
DACM_L NC DACM_SUB NC NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M NC NC AHVSS AHVSS AGNDC NC SC4_IN_L SC4_IN_R ASG SC3_IN_L SC3_IN_R ASG SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R VREFTOP
OUT
LV LV
Loudspeaker out, left Not connected Subwoofer output Not connected Not connected SCART output 2, right SCART output 2, left Reference ground 1 SCART output 1, right SCART output 1, left Volume capacitor AUX Analog power supply 8 V Volume capacitor MAIN Not connected Not connected Analog ground Analog ground Analog reference voltage Not connected SCART 4 input, left SCART 4 input, right Analog Shield Ground SCART 3 input, left SCART 3 input, right Analog Shield Ground SCART 2 input, left SCART 2 input, right Analog Shield Ground SCART 1 input, left SCART 1 input, right Reference voltage IF A/D converter
OUT
LV LV LV
OUT OUT
LV LV OBL
OUT OUT
LV LV OBL OBL OBL LV LV OBL OBL OBL LV or AHVSS
IN IN
LV LV AHVSS
IN IN
LV LV AHVSS
IN IN
LV LV AHVSS
IN IN
LV LV OBL
52
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Pin No.
PMQFP 80-11 PMQFP 64-2 PSDIP 64-1 PSDIP 52-1/-2
Pin Name
Type
Connection
(if not used)
Short Description
59 60 61 62 63 64 65 66 67 68
- 47 - 48 - - - 49 50 51
- 55 - 56 - - - 57 58 59
- 44 - 45 - - - 46 47 48
NC MONO_IN AVSS AVSS NC NC AVSUP AVSUP ANA_IN1+ ANA_IN- IN IN IN
LV LV OBL OBL LV LV OBL OBL LV AVSS via 56 pF / LV AVSS via 56 pF / LV OBL OBL OBL LV OUT LV LV LV IN/OUT IN/OUT IN IN LV LV OBL OBL
Not connected Mono input Analog ground Analog ground Not connected Not connected Analog power supply 5 V Analog power supply 5 V IF input 1 IF common (can be left vacant, only if IF input 1 is also not in use) IF input 2 (can be left vacant, only if IF input 1 is also not in use) Test pin Crystal oscillator Crystal oscillator Test pin Audio clock output (18.432 MHz) Not connected Not connected D_CTR_I/O_1 D_CTR_I/O_0 I2C Bus address select Stand-by (low-active)
69 70 71 72 73 74 75 76 77 78 79 80
52 53 54 55 56 57 58 59 60 61 62 63
60 61 62 63 64 1 2 3 4 5 6 7
49 50 51 52 1 2 - - 3 4 5 6
ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
IN IN IN OUT
Micronas
May 27, 2003; 6251-476-1DS
53
MSP 34x0G
4.3. Pin Descriptions Pin numbers refer to the PMQFP80-11 package. Pin 1, NC - Pin not connected. Pin 2, I2C_CL - I2C Clock Input/Output (Fig. 4-17) Via this pin, the I2C-bus clock signal has to be supplied. The signal can be pulled down by the MSP in case of wait conditions. Pin 3, I2C_DA - I2C Data Input/Output (Fig. 4-17) Via this pin, the I2C-bus data is written to or read from the MSP. Pin 4, I2S_CL - I2S Clock Input/Output (Fig. 4-18) Clock line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S clock has to be supplied. Pin 5, I2S_WS - I2S Word Strobe Input/Output (Fig. 4-18) Word strobe line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S word strobe has to be supplied. Pin 6, I2S_DA_OUT - I2S Data Output (Fig. 4-22) Output of digital serial sound data of the MSP on the I2S bus. Pin 7, I2S_DA_IN1 - I2S Data Input 1 (Fig. 4-14) First input of digital serial sound data to the MSP via the I2S bus. Pin 8, ADR_DA - ADR Bus Data Output (Fig. 4-22) Output of digital serial data to the DRP 3510A via the ADR bus. Pin 9, ADR_WS - ADR Bus Word Strobe Output (Fig. 4-22) Word strobe output for the ADR bus. Pin 10, ADR_CL - ADR Bus Clock Output (Fig. 4-22) Clock line for the ADR bus. Pins 11, 12, 13, DVSUP* - Digital Supply Voltage Power supply for the digital circuitry of the MSP. Must be connected to a +5 V or +3.3 V power supply. Pins 14, 15, 16, DVSS* - Digital Ground Ground connection for the digital circuitry of the MSP. Pin 17, I2S_DA_IN2 - I2S Data Input 2 (Fig. 4-14) Second input of digital serial sound data to the MSP via the I2S bus. Pins 18, 19, 20, NC - Pins not connected. Pin 21, RESETQ - Reset Input (Fig. 4-10) In the steady state, high level is required. A low level resets the MSP 34x0G. Pins 22, 23, NC - Pins not connected.
DATA SHEET
Pins 24, 25, DACA_R/L - Headphone Outputs (Fig. 4-20) Output of the headphone signal. A 1-nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected headphone volume. Pin 26, VREF2 - Reference Ground 2 Reference analog ground. This pin must be connected separately to ground (AHVSS). VREF2 serves as a clean ground and should be used as the reference for analog connections to the loudspeaker and headphone outputs. Pins 27, 28, DACM_R/L - Loudspeaker Outputs (Fig. 4-20) Output of the loudspeaker signal. A 1-nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected loudspeaker volume. Pin 29, NC - Pin not connected. Pin 30, DACM_SUB - Subwoofer Output (Fig. 4-20) Output of the subwoofer signal. A 1-nF capacitor to AHVSS must be connected to this pin. Due to the low frequency content of the subwoofer output, the value of the capacitor may be increased for better suppression of high-frequency noise. The DC offset on this pin depends on the selected loudspeaker volume. Pins 31, 32, NC - Pin not connected. Pins 33, 34, SC2_OUT_R/L - SCART2 Outputs (Fig. 4-21) Output of the SCART2 signal. Connections to these pins must use a 100- series resistor and are intended to be AC-coupled. Pin 35, VREF1 - Reference Ground 1 Reference analog ground. This pin must be connected separately to ground (AHVSS). VREF1 serves as a clean ground and should be used as the reference for analog connections to the SCART outputs. Pins 36, 37, SC1_OUT_R/L - SCART1 Outputs (Fig. 4-21) Output of the SCART1 signal. Connections to these pins must use a 100- series resistor and are intended to be AC-coupled.
54
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Pins 53, 54, SC2_IN_L/R - SCART2 Inputs (Fig. 4-13) The analog input signal for SCART2 is fed to this pin. Analog input connection must be AC-coupled. Pin 55, ASG - Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 56, 57, SC1_IN_L/R - SCART1 Inputs (Fig. 4-13) The analog input signal for SCART1 is fed to this pin. Analog input connection must be AC-coupled. Pin 58, VREFTOP - Reference Voltage IF A/D Converter (Fig. 4-15) Via this pin, the reference voltage for the IF A/D converter is decoupled. It must be connected to AVSS pins with a 10-F and a 100-nF capacitor in parallel. Traces must be kept short. Pin 59, NC - Pin not connected. Pin 60, MONO_IN - Mono Input (Fig. 4-13) The analog mono input signal is fed to this pin. Analog input connection must be AC-coupled. Pins 61, 62, AVSS* - Ground for Analog Power Supply Voltage Ground connection for the analog IF input circuitry of the MSP. Pins 63, 64, NC - Pins not connected. Pins 65, 66, AVSUP* - Analog Power Supply Voltage Power is supplied via this pin for the analog IF input circuitry of the MSP. This pin must be connected to the +5 V supply. Pin 67, ANA_IN1+ - IF Input 1 (Fig. 4-15) The analog sound IF signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN1+ is internally connected to one input of a symmetrical op amp, ANA_IN- to the other. Pin 68, ANA_IN- - IF Common (Fig. 4-15) This pins serves as a common reference for ANA_IN1/ 2+ inputs. Pin 69, ANA_IN2+ - IF Input 2 (Fig. 4-15) The analog sound if signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN2+ is internally connected to one input of a symmetrical op amp, ANA_IN- to the other. Pin 70, TESTEN - Test Enable Pin (Fig. 4-11) This pin enables factory test modes. For normal operation, it must be connected to ground.
Pin 38, CAPL_A - Volume Capacitor Headphone (Fig. 4-23) A 10-F capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for headphone volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1-F if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pin 39, AHVSUP* - Analog Power Supply High Voltage Power is supplied via this pin for the analog circuitry of the MSP (except IF input). This pin must be connected to the +8 V supply. Pin 40, CAPL_M - Volume Capacitor Loudspeaker (Fig. 4-23) A 10-F capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for loudspeaker volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1 F if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pins 41, 42, NC - Pins not connected. Pins 43, 44, AHVSS* - Ground for Analog Power Supply High Voltage Ground connection for the analog circuitry of the MSP (except IF input). Pin 45, AGNDC - Internal Analog Reference Voltage This pin serves as the internal ground connection for the analog circuitry (except IF input). It must be connected to the VREF pins with a 3.3-F and a 100-nF capacitor in parallel. This pins shows a DC level of typically 3.73 V (with AHVSUP = 8 V). Pin 46, NC - Pin not connected. Pins 47, 48, SC4_IN_L/R - SCART4 Inputs (Fig. 4-13) The analog input signal for SCART4 is fed to this pin. Analog input connection must be AC-coupled. Pin 49, ASG - Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 50, 51, SC3_IN_L/R - SCART3 Inputs (Fig. 4-13) The analog input signal for SCART3 is fed to this pin. Analog input connection must be AC-coupled. Pin 52, ASG - Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs.
Micronas
May 27, 2003; 6251-476-1DS
55
MSP 34x0G
Pins 71, 72, XTAL_IN, XTAL_OUT - Crystal Input and Output Pins (Fig. 4-19) These pins are connected to an 18.432 MHz crystal oscillator which is digitally tuned by integrated shunt capacitances. An external clock can be fed into XTAL_IN. The audio clock output signal AUD_CL_OUT is derived from the oscillator. External capacitors at each crystal pin to ground (AVSS) are required. It should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. Pin 73, TP - This pin enables factory test modes. For normal operation, it must be left vacant. Pin 74, AUD_CL_OUT - Audio Clock Output (Fig. 4-19) This is the 18.432 MHz main clock output. Pins 75, 76, NC - Pins not connected. Pins 77, 78, D_CTR_I/O_1/0 - Digital Control Input/ Output Pins (Fig. 4-18) General purpose input/output pins. Pin D_CTR_I/O_1 can be used as an interrupt request pin to the controller. Pin 79, ADR_SEL - I2C Bus Address Select (Fig. 4-16) By means of this pin, one of three device addresses for the MSP can be selected. The pin can be connected to ground (I2C device addresses 80/81hex), to +5 V supply (84/85hex), or left open (88/89hex). Pin 80, STANDBYQ - Stand-by In normal operation, this pin must be high. If the MSP 34x0G is switched off by first pulling STANDBYQ low and then (after >1s delay) switching off DVSUP and AVSUP, but keeping AHVSUP (`Standby'-mode), the SCART switches maintain their position and function. * Application Note: All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 F. The capacitor with the lowest value should be placed nearest to the DVSUP and DVSS pins. The ASG pins should be connected as closely as possible to the MSP ground. If they are lead with the SCART-inputs as shielding lines, they should not be connected to ground at the SCART connector.
DATA SHEET
56
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
4.4. Pin Configurations
AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L NC DACM_SUB NC
1 2 3 4 5 6 7 8 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52
TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG SC2_IN_R SC2_IN_L ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
TP AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 NC RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43
XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
MSP 34x0G
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSP 34x0G
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Fig. 4-7: PSDIP52-1/-2 package
Fig. 4-6: PSDIP64-1 package
Micronas
May 27, 2003; 6251-476-1DS
57
MSP 34x0G
DATA SHEET
SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R VREFTOP NC MONO_IN AVSS AVSS NC NC
ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC
AVSUP AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34
CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L
MSP 34x0G
33 32 31 30 29 28 27 26
25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP NC NC NC RESETQ NC
DACA_R
Fig. 4-8: PMQFP80-11 package
58
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS
ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/OUT1 D_CTR_I/OUT0 ADR_SEL STANDBYQ NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS NC I2S_DA_IN2 DVSS DVSUP ADR_CL NC NC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RESETQ 32 31 30 29 28 27 26 CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L DACA_R
MSP 34x0G
25 24 23 22 21 20 19 18 17
Fig. 4-9: PMQFP64-2 package
Micronas
May 27, 2003; 6251-476-1DS
59
MSP 34x0G
4.5. Pin Circuits DVSUP
23 k >300 k
DATA SHEET
DVSS Fig. 4-10: Input Pin: RESETQ ADR_SEL Fig. 4-16: Input Pin: ADR_SEL AVSUP
200 k 23 k
GND
Fig. 4-11: Input Pin TESTEN
N GND Fig. 4-17: Input/Output Pins: I2C_CL, I2C_DA
24 k 3.75 V
DVSUP Fig. 4-12: Input Pin: MONO_IN P N
40 k 3.75 V
GND Fig. 4-18: Input/Output Pins: I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0
Fig. 4-13: Input Pins: SC4-1_IN_L/R
P
Fig. 4-14: Input Pins: I2S_DA_IN1, I2S_DA_IN2, STANDBYQ
3-30 pF
500 k
N
2.5 V
ANA_IN1+ ANA_IN2+
A D
3-30 pF
Fig. 4-19: Input/Output Pins: XTAL_IN, XTAL_OUT, AUD_CL_OUT
ANA_IN- VREFTOP
Fig. 4-15: Input Pins: VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+
60
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
AHVSUP
0...1.2 mA
3.3 k
Fig. 4-20: Output Pins: DACA_R/L, DACM_R/L, DACM_SUB
26 pF 120 k
300 3.75 V
Fig. 4-21: Output Pins: SC_2_OUT_R/L, SC_1_OUT_R/L
DVSUP P N GND Fig. 4-22: Output Pins: I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL
0...2 V
Fig. 4-23: Capacitor Pins: CAPL_A, CAPL_M
125 k 3.75 V
Fig. 4-24: Pin: AGNDC
Micronas
May 27, 2003; 6251-476-1DS
61
MSP 34x0G
4.6. Electrical Characteristics Abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip
DATA SHEET
4.6.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolut maximum rating conditions for extended periods will affect device reliability. All voltages listed are referenced to ground (0 V, VSS ), except where noted. All grounds must be externally connected low ohmic. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolut maximum-rated voltages to this high-impedance circuit. Table 4-1: Absolute Maximum Ratings Symbol Parameter Pin Name Min. TA1) Ambient Operating Temperature PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Case Operating Temperature PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Storage Temperature Maximum Power Dissipation PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Supply Voltage 1 Supply Voltage 2 Supply Voltage 3 Input Voltage, all Digital Inputs Input Current, all Digital Pins - AHVSUP DVSUP AVSUP -0.3 -0.3 -0.3 -0.3 -20 - 0 70 70 70 65 - 0 85 90 95 100 - -40 125 1300 1200 1000 930 9.0 6.0 6.0 VSUP2+0.3 +20 C mW mW mW mW V V V V mA C Limit Values Max. C Unit
TC
TS PMAX
VSUP1 VSUP2 VSUP3 VIdig IIdig
1)
Measured on standard board according to JESD 51 Standard with maximum power consumption allowed for this package.
62
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 4-1: Absolute Maximum Ratings, continued Symbol Parameter Pin Name Min. VIana IIana IOana IOana ICana
1) 2)
Limit Values Max. VSUP1+0.3 +5
2) 2)
Unit
Input Voltage, all Analog Inputs Input Current, all Analog Inputs Output Current, all SCART Outputs Output Current, all Analog Outputs except SCART Outputs Output Current, other pins connected to capacitors
SCn_IN_s,1) MONO_IN SCn_IN_s,1) MONO_IN SCn_OUT_s1) DACp_s1) CAPL_p,1) AGNDC
-0.3 -5
2) 2)
V mA
2)
2)
"n" means "1", "2", "3", or "4", "s" means "L" or "R", "p" means "M" or "A" The analog outputs are short-circuit proof with respect to Supply Voltage 1 and ground.
Micronas
May 27, 2003; 6251-476-1DS
63
MSP 34x0G
4.6.2. Recommended Operating Conditions
DATA SHEET
Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and will result in unpredictable behaviour of the device and may result in device destruction. All voltages listed are referenced to ground (VSS = 0 V) except where noted. All grounds must be externally connected low ohmic. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power-up/-down sequences, see the instructions in Section 4.6.3.3. of this document.
4.6.2.1. General Recommended Operating Conditions Symbol Parameter Pin Name Min. TA Ambient Operating Temperature PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Case Operating Temperature PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Supply Voltage 1 (AHVSUP = 8 V) Supply Voltage 1 (AHVSUP = 5 V) VSUP2 Supply Voltage 2 (DVSUP = 5 V) Supply Voltage 2 (DVSUP = 3.3 V) VSUP3 tSTBYQ1
1)
Limit Values Typ. Max.
1)
Unit
-
C
70 70 70 65 - 85 90 95 100 AHVSUP 7.6 4.75 DVSUP 4.75 3.15 AVSUP STANDBYQ, DVSUP 4.75 1 8.0 5.0 5.0 3.3 5.0 8.7 5.25 5.25 3.45 5.25 V V V V V s C
TC
VSUP1
Supply Voltage 3 STANDBYQ Setup Time before Turn-off of Second Supply Voltage
A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the Recommended Operating Conditions must not be exceeded at worst case conditions of the application.
64
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
4.6.2.2. Analog Input and Output Recommendations Symbol Parameter Pin Name Min. CAGNDC AGNDC-Filter-Capacitor Ceramic Capacitor in Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA
1)
Limit Values Typ. 3.3 100 330 2.0 Max.
Unit
AGNDC
-20% -20%
F nF nF VRMS VRMS k 6.0 nF F +10% nF
DC-Decoupling Capacitor in front of SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main/AUX Volume Capacitor Main/AUX Filter Capacitor
SCn_IN_s1)
-20%
MONO_IN SCn_OUT_s1) 10
2.0
CAPL_p DACp_s1) -10%
10 1
"n" means "1", "2", "3", or "4", "s" means "L" or "R", "p" means "M" or "A"
Micronas
May 27, 2003; 6251-476-1DS
65
MSP 34x0G
4.6.2.3. Recommendations for Analog Sound IF Input Signal Symbol Parameter Pin Name Min. CVREFTOP VREFTOP-Filter-Capacitor Ceramic Capacitor in Parallel FIF_FMTV FIF_FMRADIO VIF_FM VIF_AM RFMNI Analog Input Frequency Range for TV Applications Analog Input Frequency for FM-Radio Applications Analog Input Range FM/NICAM Analog Input Range AM/NICAM Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) BG: I: Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) Ratio: FM-Main/FM-Sub Satellite Ratio: FM1/FM2 German FM-System Ratio: Main FM Carrier/ Color Carrier Ratio: Main FM Carrier/ Luma Components Passband Ripple Suppression of Spectrum above 9.0 MHz (not for FM Radio) Maximum FM-Deviation (approx.) normal mode HDEV2: high deviation mode HDEV3: very high deviation mode 15 15 - 15 0.1 0.1 ANA_IN1+, ANA_IN2+, ANA_IN- VREFTOP -20% -20% 0 10.7 0.8 0.45 3 0.8 Limit Values Typ. 10 100 9 Max.
DATA SHEET
Unit
F nF MHz MHz Vpp Vpp
-20 -23 -25
-7 -10 -11 7 7 - - -
0 0 0
dB dB dB dB dB
RAMNI RFM RFM1/FM2 RFC RFV PRIF SUPHF FMMAX
- - 2 -
dB dB dB dB
180 360 540
kHz kHz kHz
66
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
4.6.2.4. Crystal Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit
General Crystal Recommendations fP RR C0 CL Crystal Parallel Resonance Frequency at 12 pF Load Capacitance Crystal Series Resistance Crystal Shunt (Parallel) Capacitance External Load Capacitance1) XTAL_IN, XTAL_OUT 18.432 8 6.2 25 7.0 MHz pF pF pF
PSDIP approx. 1.5 PMQFP approx. 3.3
Crystal Recommendations for Master-Slave Applications (MSP-clock must perform synchronization to I2S clock) fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT -20 -20 19 18.431 24 18.433 +20 +20 ppm ppm fF MHz
Crystal Recommendations for FM / NICAM Applications (No MSP-clock synchronization to I2S clock possible) fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT -30 -30 15
18.4305 18.4335
+30 +30
ppm ppm fF MHz
Crystal Recommendations for all analog FM/AM Applications (No MSP-clock synchronization to I2S clock possible) fTOL DTEM fCL Accuracy of Adjustment Frequency Variation versus Temperature Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT -100 -50 18.429 +100 +50 18.435 ppm ppm MHz
Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF) VXCA
1)
External Clock Amplitude
XTAL_IN
0.7
Vpp
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor value should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are figures based on experience and should serve as "start value". To adjust the capacitor value, reset the MSP. After the reset, no I2C telegrams should be transmitted. Measure the frequency at AUD_CL_OUT-pin. Change the capacitor value until the free running frequency matches 18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency.
Note: To minimize adjustment tolerances for all MSP-generations, it is strongly recommended to use the socalled MSP-XTAL-REF ICs (available in all packages) for the capacitor adjustment.
Micronas
May 27, 2003; 6251-476-1DS
67
MSP 34x0G
4.6.3. Characteristics For Min./Max. values: at TA = 0 to 70 C, fCLOCK = 18.432 MHz VSUP1 = 7.6 to 8.7 V (4.75 to 5.25 V if VSUP1 = 5 V) VSUP2 = 4.75 to 5.25 V (3.15 to 3.45 V if VSUP2 = 3.3 V) VSUP3 = 4.75 to 5.2 V at TA = 60 C, fCLOCK = 18.432 MHz VSUP1 = 8 V (5 V if noted) VSUP2 = 5 V (3.3 V if noted) VSUP3 = 5 V
DATA SHEET
For typical values:
TJ = Junction Temperature MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel
4.6.3.1. General Characteristics
Symbol Parameter Pin Name Min. Supply ISUP1A First Supply Current (active) (AHVSUP = 8 V) First Supply Current (active) (AHVSUP = 5 V) ISUP2A Second Supply Current (active) (DVSUP = 5 V) Second Supply Current (active) (DVSUP = 3.3 V) ISUP3A ISUP1S Third Supply Current (active) First Supply Current (AHVSUP = 8 V) First Supply Current (AHVSUP = 5 V) Clock fCLOCK DCLOCK tJITTER VxtalDC tStartup VACLKAC VACLKDC routHF_ACL Clock Input Frequency Clock High to Low Ratio Clock Jitter (Verification not provided in Production Test) DC-Voltage Oscillator Oscillator Startup Time at VDD Slew-rate of 1 V/1 s Audio Clock Output AC Voltage Audio Clock Output DC Voltage HF Output Resistance XTAL_IN, XTAL_OUT AUD_CL_OUT 1.2 0.4 140 2.5 0.4 1.8 0.6 2 XTAL_IN 45 18.432 55 50 MHz % ps V ms Vpp VSUP3 load = 40 pF Imax = 0.2 mA AVSUP AHVSUP DVSUP AHVSUP 17 11 11 8 55 55 30 5.6 3.7 25 16 17 11 70 70 38 7.7 5.1 mA mA mA mA mA mA mA mA mA STANDBYQ = low Vol. Main and Aux = 0 dB Vol. Main and Aux = -30dB Vol. Main and Aux = 0 dB Vol. Main and Aux = -30 dB Limit Values Typ. Max. Unit Test Conditions
68
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
4.6.3.2. Digital Inputs, Digital Outputs
Symbol Parameter Pin Name Min. Digital Input Levels VDIGIL VDIGIH ZDIGI IDLEAK VDIGIL VDIGIH IADRSEL Digital Input Low Voltage Digital Input High Voltage Input Impedance Digital Input Leakage Current Digital Input Low Voltage Digital Input High Voltage Input Current Address Select Pin ADR_SEL 0.8 -500 -220 220 Digital Output Levels VDCTROL VDCTROH Digital Output Low Voltage Digital Output High Voltage D_CTR_I/O_0 D_CTR_I/O_1 VSUP2 -0.3 0.4 V V IDDCTR = 1 mA IDDCTR = -1 mA 500 -1 STANDBYQ D_CTR_I/O_0/1 0.5 5 1 0.2 0.2 VSUP2 VSUP2 pF A VSUP2 VSUP2 A A UADR_SEL= DVSS UADR_SEL= DVSUP 0 V < UINPUT< DVSUP D_CTR_I/O_0/1: tri-state Limit Values Typ. Max. Unit Test Conditions
Micronas
May 27, 2003; 6251-476-1DS
69
MSP 34x0G
4.6.3.3. Reset Input and Power-Up
Symbol Parameter Pin Name Min. RESETQ Input Levels VRHL VRLH ZRES IRES Reset High-Low Transition Voltage Reset Low-High Transition Voltage Input Capacitance Input High Current RESETQ 0.3 0.45 5 20 0.4 VSUP2 VSUP2 pF A Limit Values Typ. Max. Unit
DATA SHEET
Test Conditions
URESETQ = DVSUP
DVSUP AVSUP
0.9xDVSUP
t/ms
RESETQ
Low-to-High Threshold 0.45xDVSUP 0.3...0.4xDVSUP High-to-Low Threshold
Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms 0.45 x DVSUP means 2.25 Volt with DVSUP = 5.0 V t/ms
Reset Delay >2 ms
Internal Reset
High
Low
t/ms Fig. 4-25: Power-up sequence
70
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
4.6.3.4. I2C-Bus Characteristics
Symbol Parameter Pin Name Min. VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 I2C-Bus Input Low Voltage I C-Bus Input High Voltage I2C Start Condition Setup Time I2C Stop Condition Setup Time
2
Limit Values Typ. Max. 0.3 0.6 120 120 55 55
Unit
Test Conditions
I2C_CL, I2C_DA
VSUP2 VSUP2 ns ns ns ns ns ns
I2C-Data Setup Time before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2C-Clock Low Pulse Time I C-Clock High Pulse Time I C-BUS Frequency I2C-Data Output Low Voltage I2C-Data Output High Leakage Current I2C_CL, I2C_DA
2 2
I2C_CL
500 500 1.0 0.4 1.0 15 100
MHz V A ns ns fI2C = 1 MHz II2COL = 3 mA VI2COH = 5 V
I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock
1/FI2C I2C_CL TI2C4 TI2C3
TI2C1 I2C_DA as input
TI2C5
TI2C6
TI2C2
TI2COL2 I2C_DA as output
TI2COL1
Fig. 4-26: I2C bus timing diagram
Micronas
May 27, 2003; 6251-476-1DS
71
MSP 34x0G
4.6.3.5. I2S-Bus Characteristics
Symbol Parameter Pin Name Min. VI2SIL VI2SIH ZI2SI ILEAKI2S VI2SOL VI2SOH fI2SOWS fI2SOCL RI2S10/I2S20 ts_I2S th_I2S td_I2S Input Low Voltage Input High Voltage Input Impedance Input Leakage Current I2S Output Low Voltage I2S Output High Voltage I2S-Word Strobe Output Frequency I2S-Clock Output Frequency I2S-Clock Output High/Low-Ratio I2S Input Setup Time before Rising Edge of Clock I2S Input Hold Time after Rising Edge of Clock I2S Output Delay Time after Falling Edge of Clock I2S-Word Strobe Input Frequency I S-Clock Input Frequency I2S-Clock Input High/Low Ratio
2
DATA SHEET
Limit Values Typ. Max. 0.2 0.5 5 -1 1 0.4 VSUP2 - 0.3 32.0 1.024 2.048 0.9 1.0 1.1
Unit
Test Conditions
I2S_DA_IN1/2 I2S_CL I2S_WS
VSUP2 VSUP2 pF A V V kHz MHz MHz I2S_CONFIG[0] = 0 I2S_CONFIG[0] = 1 0 V < UINPUT< DVSUP II2SOL = 1 mA II2SOH = -1 mA
I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL
I2S_CL I2S_DA_IN1/2
12 40
ns ns 28 ns
for details see Fig. 4-27 "I2S bus timing diagram"
I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL 0.9 32.0 1.024
CL = 30 pF
fI2SWS fI2SCL RI2SCL
kHz 2.048 1.1 MHz
72
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
1/FI2SWS I2S_WS
MODUS[6] = 0 MODUS[6] = 1
Detail C
I2S_CL Detail A I2S_DA_IN
R LSB L MSB L LSB R MSB R LSB L LSB
16/32 bit left channel Detail B I2S_DA_OUT R LSB
L MSB L LSB R MSB
16/32 bit right channel
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Data: MSB first, I2S master
1/FI2SWS I2S_WS
MODUS[6] = 0 MODUS[6] = 1
Detail C
I2S_CL Detail A I2S_DA_IN
R LSB L MSB L LSB R MSB R LSB L LSB
16,18...32 bit left channel Detail B I2S_DA_OUT R LSB
L MSB
16, 18...32 bit right channel
16, 18...32 bit left channel
L LSB R MSB R LSB L LSB
16, 18...32 bit right channel
Data: MSB first, I2S slave
Detail C
I2S_CL
1/FI2SCL
Detail A,B
I2S_CL
Ts_I2S Ts_I2S I2S_DA_IN1/2 I2S_WS as INPUT
Th_I2S
Td_I2S
Td_I2S
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4-27: I2S bus timing diagram
Micronas
May 27, 2003; 6251-476-1DS
73
MSP 34x0G
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Symbol Parameter Pin Name Min. Analog Ground VAGNDC0 AGNDC Open Circuit Voltage (AHVSUP =8 V) AGNDC Open Circuit Voltage (AHVSUP = 5 V) RoutAGN AGNDC Output Resistance (AHVSUP = 8 V) AGNDC Output Resistance (AHVSUP = 5 V) Analog Input Resistance RinSC RinMONO SCART Input Resistance from TA = 0 to 70 C MONO Input Resistance from TA = 0 to 70 C SCn_IN_s1) MONO_IN 25 15 40 24 58 35 k k 70 47 AGNDC 3.77 2.51 125 83 180 120 V V k k Limit Values Typ. Max. Unit
DATA SHEET
Test Conditions
Rload 10 M
3 V VAGNDC 4 V
fsignal = 1 kHz, I = 0.05 mA fsignal = 1 kHz, I = 0.1 mA
Audio Analog-to-Digital-Converter VAICL Analog Input Clipping Level for Analog-to-DigitalConversion (AHVSUP = 8 V) Analog Input Clipping Level for Analog-to-DigitalConversion (AHVSUP = 5 V) SCART Outputs RoutSC SCART Output Resistance SCn_OUT_s1) 200 200 Deviation of DC-Level at SCART Output from AGNDC Voltage Gain from Analog Input to SCART Output Frequency Response from Analog Input to SCART Output Signal Level at SCART Output (AHVSUP = 8 V) Signal Level at SCART Output (AHVSUP = 5V)
1)
SCn_IN_s,1) MONO_IN
2.00
2.25
VRMS
fsignal = 1 kHz
1.13
1.51
VRMS
330
460 500 +70 +0.5 +0.5
mV dB dB VRMS VRMS
fsignal = 1 kHz, I = 0.1 mA Tj = 27 C TA = 0 to 70 C
dVOUTSC ASCtoSC frSCtoSC VoutSC
-70 SCn_IN_s,1) MONO_IN SCn_OUT_s1) SCn_OUT_s1) -1.0 -0.5 1.8 1.17 1.9 1.27
fsignal = 1 kHz with resp. to 1 kHz Bandwidth: 0 to 20000 Hz fsignal = 1 kHz Volume 0 dB Full Scale input from I2S
2.0 1.37
"n" means "1", "2", "3", or "4";
"s" means "L" or "R"
74
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
Main and AUX Outputs RoutMA Main/AUX Output Resistance DACp_s1) 2.1 2.1 VoutDCMA DC-Level at Main/AUX-Output (AHVSUP = 8 V) DC-Level at Main/AUX-Output (AHVSUP = 5 V) VoutMA Signal Level at Main/AUX-Output (AHVSUP = 8 V) Signal Level at Main/AUX-Output (AHVSUP = 5 V)
1)
3.3 2.04 61 1.36 40 1.37 0.90
4.6 5.0 2.28 1.60 1.51 1.04
k k V mV V mV VRMS VRMS
fsignal = 1 kHz, I = 0.1 mA Tj = 27 C TA = 0 to 70 C Volume 0 dB Volume -30 dB Volume 0 dB Volume -30 dB fsignal = 1 kHz Volume 0 dB Full scale input from I2S
1.80 1.12 1.23 0.76
"s" means "L" or "R";
"p" means "M" or "A"
4.6.3.7. Sound IF Inputs
Symbol Parameter Pin Name Min. RIFIN Input Impedance ANA_IN1+, ANA_IN2+, ANA_IN- VREFTOP ANA_IN1+, ANA_IN2+, ANA_IN- ANA_IN1+, ANA_IN2+, ANA_IN- 1.5 6.8 2.45 1.3 Limit Values Typ. 2 9.1 2.65 1.5 Max. 2.5 11.4 2.75 1.7 k k V V Gain AGC = 20 dB Gain AGC = 3 dB Unit Test Conditions
DCVREFTOP DCANA_IN
DC Voltage at VREFTOP DC Voltage on IF Inputs
XTALKIF BWIF AGC
Crosstalk Attenuation 3 dB Bandwidth AGC Step Width
40 10 0.85
dB MHz dB
fsignal = 1 MHz Input Level = -2 dBr
4.6.3.8. Power Supply Rejection
Symbol Parameter Pin Name Min. PSRR: Rejection of Noise on AHVSUP at 1 kHz PSRR AGNDC From Analog Input to I2S Output From Analog Input to SCART Output From I2S Input to SCART Output From I S Input to MAIN or AUX Output
1) 2
Limit Values Typ. Max.
Unit
Test Conditions
AGNDC MONO_IN, SCn_IN_s1) MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s
1)
80 70 70
dB dB dB
60 80
dB dB
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
"p" means "M" or "A"
Micronas
May 27, 2003; 6251-476-1DS
75
MSP 34x0G
4.6.3.9. Analog Performance
Symbol Parameter Pin Name Min. Specifications for AHVSUP = 8 V SNR Dynamic Range and Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 88 93 dB Limit Values Typ. Max. Unit
DATA SHEET
Test Conditions
Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, A-weighted 20 Hz...16 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...16 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...16 kHz
from Analog Input to SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1)
93
96
dB
from I2S Input to SCART Output
88
93
dB
from I2S Input to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at -30 dB THD Total Harmonic Distortion from Analog Input to I2S Output
DACp_s1) 88 81 93 86 dB dB
MONO_IN, SCn_IN_s1)
0.008
0.03
%
Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...16 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...20 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...16 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...16 kHz
from Analog Input to SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1)
0.008
0.03
%
from I2S Input to SCART Output
0.008
0.03
%
from I2S Input to Main or AUX Output
DACp_s1)
0.008
0.03
%
1)
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
"p" means "M" or "A"
76
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
Specifications for AHVSUP = 5 V SNR Dynamic Range and Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 85 90 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, A-weighted 20 Hz...16 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...16 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...16 kHz
from Analog Input to SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1)
90
93
dB
from I2S Input to SCART Output
85
90
dB
from I2S Input to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at -30 dB THD Total Harmonic Distortion from Analog Input to I2S Output
DACp_s1) 85 78 90 83 dB dB
MONO_IN, SCn_IN_s1)
0.03
0.1
%
Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...16 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...20 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...16 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...16 kHz
from Analog Input to SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1)
0.1
%
from I2S Input to SCART Output
0.1
%
from I2S Input to Main or AUX Output
DACp_s1)
0.1
%
1)
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
"p" means "M" or "A"
Micronas
May 27, 2003; 6251-476-1DS
77
MSP 34x0G
DATA SHEET
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
CROSSTALK Specifications XTALK Crosstalk Attenuation Input Level = -3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z < 1 k unweighted 20 Hz...20 kHz 80 80 80 80 dB dB dB dB unweighted 20 Hz...16 kHz 75 dB (unweighted 20 Hz...20 kHz same signal source on left and right disturbing channel, effect on each observed output channel
between left and right channel within SCART Input/Output pair (LR, RL) SCn_IN SCn_OUT1) SC1_IN or SC2_IN I2S Output SC3_IN I2S Output I2S Input SCn_OUT1) between left and right channel within Main or AUX Output pair I2S Input DACp1) between SCART Input/Output pairs D = disturbing program O = observed program D: MONO/SCn_IN SCn_OUT O: MONO/SCn_IN SCn_OUT1) D: MONO/SCn_IN SCn_OUT or unsel. O: MONO/SCn_IN I2S Output D: MONO/SCn_IN SCn_OUT O: I2S Input SCn_OUT1) D: MONO/SCn_IN unselected O: I2S Input SC1_OUT1) Crosstalk between Main and AUX Output pairs I2S Input DACp1) 90 dB 100 95 100 100 dB dB dB dB
(unweighted 20 Hz...16 kHz) same signal source on left and right disturbing channel, effect on each observed output channel (unweighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel SCART output load resistance 10 k SCART output load resistance 30 k
XTALK
Crosstalk from Main or AUX Output to SCART Output and vice versa D = disturbing program O = observed program D: MONO/SCn_IN/DSP SCn_OUT O: I2S Input DACp1) D: MONO/SCn_IN/DSP SCn_OUT O: I2S Input DACp1) D: I2S Input DACp O: MONO/SCn_IN SCn_OUT1) D: I2S Input DACM O: I2S Input SCn_OUT1) 80 85 95 95 "p" means "M" or "A" dB dB dB dB
1)
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
78
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
4.6.3.10. Sound Standard Dependent Characteristics
Symbol Parameter Pin Name Min. NICAM Characteristics (MSP Standard Code = 8) dVNICAMOUT S/NNICAM Tolerance of Output Voltage of NICAM Baseband Signal S/N of NICAM Baseband Signal DACp_s SCn_OUT_s1 -1.5 72 +1.5 dB dB 2.12 kHz, Modulator input level = 0 dBref NICAM: -6 dB, 1 kHz, RMS unweighted 0 to 15 kHz, Vol = 9 dB NIC_Presc = 7Fhex Output level 1 VRMS at DACp_s 2.12 kHz, Modulator input level = 0 dBref FM+NICAM, norm conditions Modulator input level = -12 dB dBref; RMS Limit Values Typ. Max. Unit Test Conditions
THDNICAM BERNICAM fRNICAM XTALKNICAM SEPNICAM
Total Harmonic Distortion + Noise of NICAM Baseband Signal NICAM: Bit Error Rate NICAM Frequency Response , 20...15000 Hz NICAM Crosstalk Attenuation (Dual) NICAM Channel Separation (Stereo) -1.0 80 80
0.1 1 +1.0
% 10-7 dB dB dB
FM Characteristics (MSP Standard Code = 3) dVFMOUT S/NFM THDFM Tolerance of Output Voltage of FM Demodulated Signal S/N of FM Demodulated Signal Total Harmonic Distortion + Noise of FM Demodulated Signal DACp_s, SCn_OUT_s1 -1.5 73 0.1 +1.5 dB dB % 1 FM-carrier, 50 s, 1 kHz, 40 kHz deviation; RMS 1 FM-carrier 5.5 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS, unweighted 0 to 15 kHz (for S/N); full input range, FM-Prescale = 46hex, Vol = 0 dB Output Level 1 VRMS at DACp_s 1 FM-carrier 5.5 MHz, 50 s, Modulator input level = -14.6 dBref; RMS 2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; Bandpass 1 kHz 2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS
fRFM
FM Frequency Responses, 20...15000 Hz FM Crosstalk Attenuation (Dual)
-1.0
+1.0
dB
XTALKFM
80
dB
SEPFM
FM Channel Separation (Stereo)
50
dB
AM Characteristics (MSP Standard Code = 9) S/NAM(1) S/NAM(2) THDAM fRAM
1)
S/N of AM Demodulated Signal measurement condition: RMS/Flat S/N of AM Demodulated Signal measurement condition: QP/CCIR Total Harmonic Distortion + Noise of AM Demodulated Signal AM Frequency Response 50...12000 Hz "s" means "L" or "R";
DACp_s, SCn_OUT_s1
55 45 0.6 -2.5 +1.0
dB dB % dB
SIF level: 0.1-0.8 Vpp AM-carrier 54% at 6.5 MHz Vol = 0 dB, FM/AM prescaler set for output = 0.5 VRMS at Loudspeaker out; Standard Code = 09hex no video/chroma components
"n" means "1" or "2";
"p" means "M" or "A"
Micronas
May 27, 2003; 6251-476-1DS
79
MSP 34x0G
DATA SHEET
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
BTSC Characteristics (MSP Standard Code = 20hex, 21hex) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal DACp_s, SCn_OUT_s1) 68 57 dB dB 1 kHz L or R or SAP, 100% modulation, 75 s deemphasis, RMS unweighted 0 to 15 kHz 1 kHz L or R or SAP, 100% 75 s EIM2), DBX NR or MNR, RMS unweighted 0 to 15 kHz L or R or SAP, 1%...66% EIM2), DBX NR
THDBTSC
THD+N of BTSC Stereo Signal THD+N of BTSC SAP Signal
0.1 0.5
% %
fRDBX
Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSCSAP, 50 Hz...9 kHz
-1.0 -1.0 -2.0 -2.0 76 80
1.0 1.0 2.0 2.0
dB dB dB dB dB dB
fRMNR
Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSCSAP, 50 Hz...9 kHz
L or R 5%...66% EIM2), MNR SAP, white noise, 10% Modulation, MNR 1 kHz L or R or SAP, 100% modulation, 75 s deemphasis, Bandpass 1 kHz L or R 1%...66% EIM2), DBX NR L = 300 Hz, R = 3.1 kHz 14% Modulation, MNR 4.5 MHz carrier modulated with fh = 15.734 kHz SIF level = 100 mVpp indication: STATUS Bit[6] standard BTSC stereo signal, sound carrier only
XTALKBTSC
Stereo SAP SAP Stereo
SEPDBX
Stereo Separation DBX NR 50 Hz...10 kHz 50 Hz...12 kHz Stereo Separation MNR Pilot deviation threshold Stereo off on Stereo on off ANA_IN1+, ANA_IN2+
35 30 30
dB dB dB
SEPMNR FMpil
3.2 1.2 15.563
3.5 1.5 15.843
kHz kHz kHz
fPilot
1) 2)
Pilot Frequency Range
"n" means "1" or "2"; "s" means "L" or "R"; "p" means "M" or "A" EIM refers to 75-s Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-s preemphasis network.
80
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
BTSC Characteristics (MSP Standard Code = 20hex, 21hex) with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal DACp_s, SCn_OUT_s1 64 55 dB dB 1 kHz L or R or SAP, 100% modulation, 75 s deemphasis, RMS unweighted 0 to 15 kHz 1 kHz L or R or SAP, 100% 75 s EIM2), DBX NR or MNR, RMS unweighted 0 to 15 kHz L or R or SAP, 1%...66% EIM2), DBX NR
THDBTSC
THD+N of BTSC Stereo Signal THD+N of BTSC SAP Signal
0.15 0.8
% %
fRDBX
Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSCSAP, 50 Hz...9 kHz
-1.0 -1.0 -2.0 -2.0 75 75
1.0 1.0 2.0 2.0
dB dB dB dB dB dB
fRMNR
Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSCSAP, 50 Hz...9 kHz
L or R 5%...66% EIM2), MNR SAP, white noise, 10% Modulation, MNR 1 kHz L or R or SAP, 100% modulation, 75 s deemphasis, Bandpass 1 kHz L or R 1%...66% EIM2), DBX NR L = 300 Hz, R = 3.1 kHz 14% Modulation, MNR
XTALKBTSC
Stereo SAP SAP Stereo
SEPDBX
Stereo Separation DBX NR 50 Hz...10 kHz 50 Hz...12 kHz Stereo Separation MNR
35 30 30
dB dB dB
SEPMNR
1) 2)
"n" means "1" or "2"; "s" means "L" or "R"; "p" means "M" or "A" EIM refers to 75-s Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-s preemphasis network.
Micronas
May 27, 2003; 6251-476-1DS
81
MSP 34x0G
DATA SHEET
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
EIA-J Characteristics (MSP Standard Code = 30hex) S/NEIAJ S/N of EIA-J Stereo Signal S/N of EIA-J Sub-Channel THDEIAJ THD+N of EIA-J Stereo Signal THD+N of EIA-J Sub-Channel fREIAJ Frequency Response of EIA-J Stereo, 50 Hz...12 kHz Frequency Response of EIA-J SubChannel, 50 Hz...12 kHz XTALKEIAJ Main SUB Sub MAIN -0.5 -1.0 66 80 DACp_s, SCn_OUT_s1) 60 60 0.2 0.3 1.0 1.0 dB dB % % dB dB dB dB 1 kHz L or R, 100% modulation, 75 s deemphasis, Bandpass 1 kHz EIA-J Stereo Signal, L or R 100% modulation 100% modulation, 75 s deemphasis 1 kHz L or R, 100% modulation, 75 s deemphasis, RMS unweighted 0 to 15 kHz
SEPEIAJ
Stereo Separation 50 Hz...5 kHz 50 Hz...10 kHz
35 28
dB dB
FM-Radio Characteristics (MSP Standard Code = 40hex) S/NUKW THDUKW fRUKW S/N of FM-Radio Stereo Signal THD+N of FM-Radio Stereo Signal Frequency Response of FM-Radio Stereo 50 Hz...15 kHz Stereo Separation 50 Hz...15 kHz Pilot Frequency Range "s" means "L" or "R"; ANA_IN1+ ANA_IN2+ "p" means "M" or "A" DACp_s, SCn_OUT_s1) 68 0.1 dB % 1 kHz L or R, 100% modulation, 75 s deemphasis, RMS unweighted 0 to 15 kHz L or R, 1%...100% modulation, 75 s deemphasis dB dB 19.125 kHz standard FM radio stereo signal
-1.0 45 18.844
+0.5
SEPUKW fPilot
1)
"n" means "1" or "2";
82
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
5. Appendix A: Overview of TV-Sound Standards 5.1. NICAM 728
Table 5-1: Summary of NICAM 728 sound modulation parameters
Specification Carrier frequency of digital sound Transmission rate Type of modulation Spectrum shaping Roll-off factor 1.0 Carrier frequency of analog sound component Power ratio between vision carrier and analog sound carrier Power ratio between analog and modulated digital sound carrier 6.0 MHz FM mono 10 dB 0.4 5.5 MHz FM mono 13 dB I 6.552 MHz B/G 5.85 MHz L 5.85 MHz 728 kbit/s Differentially encoded quadrature phase shift keying (DQPSK) by means of Roll-off filters 0.4 6.5 MHz AM mono terrestrial 10 dB cable 16 dB 13 dB 0.4 6.5 MHz FM mono D/K 5.85 MHz
10 dB
7 dB
17 dB
11 dB
China/ Hungary 12 dB
Poland 7 dB
Table 5-2: Summary of NICAM 728 sound coding characteristics
Characteristics Audio sampling frequency Number of channels Initial resolution Companding characteristics Coding for compressed samples Preemphasis Audio overload level Values 32 kHz 2 14 bit/sample near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks 2's complement CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz) +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
Micronas
May 27, 2003; 6251-476-1DS
83
MSP 34x0G
5.2. A2-Systems
DATA SHEET
Table 5-3: Key parameters for A2 Systems of Standards B/G, D/K, and M
Characteristics TV-Sound Standard Carrier frequency in MHz B/G 5.5 Sound Carrier FM1 D/K 6.5 M 4.5 B/G 5.7421875 Sound Carrier FM2 D/K 6.2578125 6.7421875 5.7421875 20 dB 40 Hz to 15 kHz 50 s 27/50 kHz 75 s 17/25 kHz 50 s 27/50 kHz 75 s 15/25 kHz M 4.724212
Vision/sound power difference Sound bandwidth Preemphasis Frequency deviation (nom/max) Transmission Modes Mono transmission Stereo transmission Dual sound transmission Identification of Transmission Mode Pilot carrier frequency Max. deviation portion Type of modulation / modulation depth Modulation frequency (L+R)/2
13 dB
mono (L+R)/2 R
mono (L-R)/2 language B
language A
54.6875 kHz
55.0699 kHz
2.5 kHz
AM / 50% mono: unmodulated stereo: 117.5 Hz dual: 274.1 Hz 149.9 Hz 276.0 Hz
84
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
5.3. BTSC-Sound System
Table 5-4: Key parameters for BTSC-Sound Systems
Aural Carrier (L+R) Carrier frequency (fhNTSC = 15.734 kHz) (fhPAL = 15.625 kHz) Sound bandwidth in kHz Preemphasis Max. deviation to Aural Carrier Max. Freq. Deviation of Subcarrier Modulation Type
1)
BTSC-MPX-Components Pilot fh (L-R) 2 fh SAP 5 fh Prof. Ch. 6.5 fh
4.5 MHz
Baseband
0.05 - 15 75 s 73 kHz (total) 25 kHz1) 5 kHz
0.05 - 15 DBX 50 kHz1)
0.05 - 10 DBX 15 kHz 10 kHz FM
0.05 - 3.4 150 s 3 kHz 3 kHz FM
AM
Sum does not exceed 50 kHz due to interleaving effects
5.4. Japanese FM Stereo System (EIA-J)
Table 5-5: Key parameters for Japanese FM-Stereo Sound System EIA-J
Aural Carrier FM Carrier frequency (fh = 15.734 kHz) Sound bandwidth Preemphasis Max. deviation portion to Aural Carrier Max. Freq. Deviation of Subcarrier Modulation Type Transmitter-sided delay Mono transmission Stereo transmission Bilingual transmission 20 s L+R L+R Language A 47 kHz 4.5 MHz EIA-J-MPX-Components (L+R) Baseband 0.05 - 15 kHz 75 s 25 kHz (L-R) 2 fh 0.05 - 15 kHz 75 s 20 kHz 10 kHz FM 0 s - L-R Language B Identification 3.5 fh - none 2 kHz 60% AM 0 s unmodulated 982.5 Hz 922.5 Hz
Micronas
May 27, 2003; 6251-476-1DS
85
MSP 34x0G
5.5. FM Satellite Sound
DATA SHEET
Table 5-6: Key parameters for FM Satellite Sound
Carrier Frequency 6.5 MHz 7.02/7.20 MHz 7.38/7.56 MHz 7.74/7.92 MHz Maximum FM Deviation 85 kHz 50 kHz 50 kHz 50 kHz Sound Mode Mono Mono/Stereo/Bilingual Mono/Stereo/Bilingual Mono/Stereo/Bilingual Bandwidth 15 kHz 15 kHz 15 kHz 15 kHz Deemphasis 50 s adaptive adaptive adaptive
5.6. FM-Stereo Radio
Table 5-7: Key parameters for FM-Stereo Radio Systems
Aural Carrier (L+R) Carrier frequency (fp = 19 kHz) Sound bandwidth in kHz Preemphasis: - USA - Europe Max. deviation to Aural Carrier 75 kHz (100%) 10.7 MHz Baseband 0.05 - 15 75 s 50 s 90% 10% FM-Radio-MPX-Components Pilot fp (L-R) 2 fp 0.05 - 15 75 s 50 s 90% 5% RDS/ARI 3 fp
86
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
6. Appendix B: Manual/Compatibility Mode To adapt the modes of the STANDARD SELECT register to individual requirements and for reasons of compatibility to the MSP 34x0D, the MSP 34x0G offers an Manual/Compatibility Mode, which provides sophisticated programming of the MSP 34x0G. Using the STANDARD SELECT register generally provides a more economic way to program the MSP 34x0G and will result in optimal behavior. Therefore, it is not recommend to use the Manual/Compatibility mode. In those cases, where the MSP 34x0D is to be substituted by the MSP 34x0G, the tips given in Section 6.9. on page 101 have to be obeyed by the controller software.
6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode Table 6-1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable!
Demodulator Write Registers AUTO_FM/AM Address (hex) 00 21 MSPVersion 3410, 3450 Description 1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception 2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception A2_Threshold CM_Threshold AD_CV MODE_REG 00 22 00 24 00 BB 00 83 all all all 3410, 3450 A2 Stereo Identification Threshold Carrier-Mute Threshold SIF-input selection, configuration of AGC, and Carrier-Mute Function Controlling of MSP-Demodulator and Interface options. As soon as this register is applied, the MSP 34x0G works in the MSP 34x0D compatibility mode. Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only MSP 34x0D features are available; the use of MODUS and STATUS register is not allowed. The MSP 34x0G is reset to the normal mode by first programming the MODUS register followed by transmitting a valid standard code to the STANDARD SELECTION register. FIR1 FIR2 DCO1_LO DCO1_HI DCO2_LO DCO2_HI PLL_CAPS 00 01 00 05 00 93 00 9B 00 A3 00 AB 00 1F FIR1-filter coefficients channel 1 (6 8 bit) FIR2-filter coefficients channel 2 (6 8 bit), + 3 8 bit offset (total 72 bit) Increment channel 1 Low Part Increment channel 1 High Part Increment channel 2 Low Part Increment channel 2 High Part Not of interest for the customer Switchable PLL capacitors to tune open-loop frequency 00 56 98 00 00 00 00 95 95 01 90hex 00 2Ahex 00 00 00 00 91 91 92 93 Reset Mode 00 00 Page 89
Note: All registers except AUTO_FM/AM, A2_Threshold, and CM_Threshold are initialized during STANDARD SELECTION and are automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
Micronas
May 27, 2003; 6251-476-1DS
87
MSP 34x0G
Table 6-2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!
Demodulator Read Registers C_AD_BITS ADD_BITS CIB_BITS ERROR_RATE PLL_CAPS AGC_GAIN Address (hex) 00 23 00 38 00 3E 00 57 02 1F 02 1E MSPVersion 3410, 3450 Description NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits NICAM: bit [10:3] of additional data bits NICAM: CIB1 and CIB2 control bits NICAM error rate, updated with 182 ms Not for customer use Not for customer use
DATA SHEET
Page 97 97 97 98 98 98
6.2. DSP Write and Read Registers for Manual/Compatibility Mode Table 6-3: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well
Write Register Volume SCART1 channel: Ctrl. mode FM Fixed Deemphasis FM Adaptive Deemphasis Identification Mode FM DC Notch Volume SCART2 channel: Ctrl. mode 00 15 00 17 00 40 Address (hex) 00 07 00 0F Bits [7:0] [15:8] [7:0] [7:0] [7:0] [7:0] Operational Modes and Adjustable Range [Linear mode / logarithmic mode] [50 s, 75 s, J17, OFF] [OFF, WP1] [B/G, M] [ON, OFF] [Linear mode / logarithmic mode] Reset Mode 00hex 50 s OFF B/G ON 00hex Page 99 99 99 100 100 99
Table 6-4: DSP Read Registers; Subaddress: 13hex, all registers are not writable
Additional Read Registers Stereo detection register for A2 Stereo Systems DC level readout FM1/Ch2-L DC level readout FM2/Ch1-R Address (hex) 00 18 00 1B 00 1C Bits [15:8] [15:0] [15:0] Output Range [80hex ... 7Fhex] [8000hex ... 7FFFhex] [8000hex ... 7FFFhex] 8 bit two's complement 16 bit two's complement 16 bit two's complement Page 100 100 100
88
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
6.3.1.1. Function in Automatic Sound Select Mode The Automatic Sound Select feature (MODUS[0]=1) includes the procedure mentioned above. By default, the internal ERROR_RATE threshold is set to 700dec. i.e.: - NICAM analog Sound if ERROR_RATE > 700 - analog Sound NICAM if ERROR_RATE < 700/2 The ERROR_RATE value of 700 corresponds to a BER of approximately 5.46*10-3 /s. Individual configuration of the threshold can be done using Table 6-5. However, the internal setting used by the standard selection is recommended. The optimum NICAM sound can be assigned to the MSP output channels by selecting one of the "Stereo or A/B", "Stereo or A", or "Stereo or B" source channels
6.3. Manual/Compatibility Mode: Description of Demodulator Write Registers 6.3.1. Automatic Switching between NICAM and Analog Sound In case of bad NICAM reception or loss of the NICAM-carrier, the MSP 34x0G offers an Automatic Switching (fall back) to the analog sound (FM/AMmono), without the necessity for the controller of reading and evaluating any parameters. If a proper NICAM signal returns, switching back to this source is performed automatically as well. The feature evaluates the NICAM ERROR_RATE and switches, if necessary, all output channels which are assigned to the NICAM-source, to the analog source, and vice versa. An appropriate hysteresis algorithm avoids oscillating effects (see Fig. 6-1). STATUS[9] and C_AD_BITS[11] (Address: 0023hex) provide information about the actual NICAM-FM/AM-status.
6.3.1.2. Function in Manual Mode
Selected Sound
NICAM
analog sound
ERROR_RATE threshold/2 threshold
If the manual mode (MODUS[0]=0) is required, the activation and configuration of the Automatic Switching feature has to be done as described in Table 6-6. Note that the channel matrix of the corresponding output-channels must be set according to the NICAM-mode and need not to be changed in the FM/ AM-fallback case. Example: Required threshold = 500: bits[10:1] = 00 1111 1010
Fig. 6-1: Hysteresis for Automatic Switching
Table 6-5: Coding of Automatic NICAM/Analog Sound Switching; Automatic Sound Select is on (MODUS[0] = 1)
Mode 1 Default 2 Description Automatic Switching with internal threshold Automatic Switching with external threshold (Customizing of Automatic Sound Select) Forced Analog Mono AUTO_FM [11:0] Addr. = 00 21hex bit[11:0] = 0 bit[11] =0 bit[10:1] = 25...1000 = threshold/2 bit[0] =1 bit[11] =1 bit[10:1] = ignored bit[0] =1 ERROR_RATEThreshold/dec 700 set by customer; recommended range: 50...2000 Source Select: Input at NICAM Path1) NICAM or FM/AM, depending on ERROR_RATE
3
always FM/AM
1)
The NICAM path may be assigned to "Stereo or A/B", "Stereo or A", or "Stereo or B" source channels (see Table 2-2 on page 12).
Micronas
May 27, 2003; 6251-476-1DS
89
MSP 34x0G
Table 6-6: Coding of Automatic NICAM/Analog Sound Switching; Automatic Sound Select is off (MODUS[0] = 0)
Mode 0 reset status 1 Description Forced NICAM (Automatic Switching disabled) Automatic Switching with internal threshold (Default, if Automatic Sound Select is on) Automatic Switching with external threshold (Customizing of Automatic Sound Select) Forced Analog Mono (Automatic Switching disabled) AUTO_FM [11:0] Addr. = 00 21hex bit[11] =0 bit[10:1] = 0 bit[0] =0 bit[11] =0 bit[10:1] = 0 bit[0] =1 bit[11] =0 bit[10:1] = 25...1000 = threshold/2 bit[0] =1 bit[11] =1 bit[10:1] = 0 bit[0] =1 ERROR_RATEThreshold/dec none
DATA SHEET
Source Select: Input at NICAM Path always NICAM; Mute in case of no NICAM available NICAM or FM/AM, depending on ERROR_RATE
700
2
set by customer; recommended range: 50...2000 none always FM/AM
3
90
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
6.3.2. A2 Threshold The threshold between Stereo/Bilingual and Mono Identification for the A2 Standard has been made programmable according to the user's preferences. An internal hysteresis ensures robustness and stability .
Table 6-7: Write Register on I2C Subaddress 10hex : A2 Threshold Register Address THRESHOLDS 00 22hex (write) A2 THRESHOLD Register Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual detection bit[15:0] 07F0hex ... 0190hex ... 00A0hex force Mono Identification default setting after reset minimum Threshold for stable detection A2_THRESH Function Name
recommended range : 00A0hex...03C0hex
6.3.3. Carrier-Mute Threshold The Carrier-Mute threshold has been made programmable according to the user's preferences. An internal hysteresis ensures stable behavior. Table 6-8: Write Register on I2C Subaddress 10hex : Carrier-Mute Threshold Register Address THRESHOLDS 00 24hex (write) Carrier-Mute THRESHOLD Register Defines threshold for the carrier mute feature bit[15:0] 0000hex ... 002Ahex ... 07FFhex Carrier-Mute always ON (both channels muted) default setting after reset Carrier-Mute always OFF (both channels forced on) CM_THRESH Function Name
recommended range : 0014hex...0050hex
Micronas
May 27, 2003; 6251-476-1DS
91
MSP 34x0G
6.3.4. Register AD_CV The use of this register is no longer recommended. Use it only in cases where compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x0G. Table 6-9: AD_CV Register; reset status: all bits are "0"
AD_CV (00 BBhex) Bit [0] [1:6] Function not used Reference level in case of Automatic Gain Control = on (see Table 6-10). Constant gain factor when Automatic Gain Control = off (see Table 6-11). Determination of Automatic Gain or Constant Gain Selection of Sound IF source (identical to MODUS[8]) MSP-Carrier-Mute Feature 0 = constant gain 1 = automatic gain 0 = ANA_IN1+ 1 = ANA_IN2+ 0 = off: no mute 1 = on: mute as described in section 2.2.2. must be set to 0 Settings must be set to 0
DATA SHEET
Automatic setting by STANDARD SELECT Register 2-8, 0A-60hex 0 101000 9 0 100011
[7] [8] [9]
1 X 1
1 X 0
[10:15]
not used
0
0
X : not affected while choosing the TV sound standard by means of the STANDARD SELECT Register
Note: This register is initialized during STANDARD SELECTION and is automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
Table 6-10: Reference Values for Active AGC (AD_CV[7] = 1)
Application Input Signal Contains AD_CV [6:1] Ref. Value AD_CV [6:1] in integer Range of Input Signal at pin ANA_IN1+ and ANA_IN2+
Terrestrial TV - FM Standards - NICAM/FM - NICAM/AM - NICAM only SAT ADR
1)
1 or 2 FM Carriers 1 FM and 1 NICAM Carrier 1 AM and 1 NICAM Carrier 1 NICAM Carrier only 1 or more FM Carriers FM and ADR carriers
101000 101000 100011 010100 100011
40 40 35 20 35
0.10 - 3 Vpp1) 0.10 - 3 Vpp1) 0.10 - 1.4 Vpp (recommended: 0.10 - 0.8 Vpp) 0.05 - 1.0 Vpp 0.10 - 3 Vpp1)
see DRP 3510A data sheet
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.
92
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 6-11: AD_CV parameters for Constant Input Gain (AD_CV[7]=0)
Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1)
AD_CV [6:1] Constant Gain 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100
Gain 3.00 dB 3.85 dB 4.70 dB 5.55 dB 6.40 dB 7.25 dB 8.10 dB 8.95 dB 9.80 dB 10.65 dB 11.50 dB 12.35 dB 13.20 dB 14.05 dB 14.90 dB 15.75 dB 16.60 dB 17.45 dB 18.30 dB 19.15 dB 20.00 dB
Input Level at pin ANA_IN1+ and ANA_IN2+ maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)1)
maximum input level: 0.14 Vpp
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.
6.3.5. Register MODE_REG
Note: The use of this register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x0G.
As soon as this register is applied, the MSP 34x0G works in the MSP 34x0D Manual/Compatibility Mode. In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only MSP 34x0D features are available; the use of MODUS and STATUS register is not allowed. The MSP 34x0G is reset to the normal mode by first programming the MODUS register, followed by transmitting a valid standard code to the STANDARD SELECTION register. The register `MODE_REG' contains the control bits determining the operation mode of the MSP 34x0G in the MSP 34x0D Manual/Compatibility Mode; Table 6- 12 explains all bit positions.
Micronas
May 27, 2003; 6251-476-1DS
93
MSP 34x0G
Table 6-12: Control word `MODE_REG'; reset status: all bits are "0"
MODE_REG 00 83hex Bit [0] [1] [2] Function not used DCTR_TRI I2S_TRI Digital control out 0/1 tri-state I2S outputs tri-state (I2S_CL, I2S_WS, I2S_DA_OUT) Master/Slave mode of the I2S bus WS due to the Sony or Philips-Format Switch Audio_Clock_Output to tri-state Mode of MSP-Ch1 Comment Definition 0 : must be used 0 : active 1 : tri-state 0 : active 1 : tri-state 0 : Master 1 : Slave 0 : Sony 1 : Philips 0 : on 1 : tri-state 0 : FM 1 : Nicam 0 : must be used Mode of MSP-Ch2 High Deviation Mode (channel matrix must be sound A) 0 : FM 1 : AM 0 : normal 1 : high deviation mode 0 : must be used see also Table 6-14 see also Table 6-14 Mode of MSP Ch1/ ADR-Interface Gain for AM Demodulation 0 : Gain = 6 dB 1 : Gain = 0 dB 0 : use FIR1 1 : use FIR2 0 : normal mode/tri-state 1 : ADR-mode/active 0 : 0 dB (default. of MSPB) 1 :12 dB (recommended)
DATA SHEET
Automatic setting by STANDARD SELECT Register 2-5 0 X X 8, A, B 0 X X 9 0 X X
[3] [4] [5]
I2S Mode1) I2S_WS Mode Audio_CL_OUT
X X X
X X X
X X X
[6] [7] [8] [9]
NICAM1) not used FM AM HDEV
0 0 0 0
1 0 0 0
1 0 1 0
[11:10] [12] [13] [14] [15]
1)
not used MSP-Ch1 Gain FIR1-Filter Coeff. Set ADR AM-Gain
0 0 1 0 1
0 0 0 0 1
0 0 0 0 1
NICAM and I2S-Slave mode are not allowed simultaneously
X: not affected by STANDARD SELECT register
94
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
To load the FIR-filters, the following data values are to be transferred 8 bits at a time embedded LSB-bound in a 16-bit word. The loading sequences must be obeyed. To change a coefficient set, the complete block FIR1 or FIR2 must be transmitted.
Table 6-13: Loading sequence for FIR-coefficients
FIR1 00 01hex (MSP-Ch1: NICAM/FM2) No. 1 2 3 4 5 6 Symbol Name NICAM/FM2_Coeff. (5) NICAM/FM2_Coeff. (4) NICAM/FM2_Coeff. (3) NICAM/FM2_Coeff. (2) NICAM/FM2_Coeff. (1) NICAM/FM2_Coeff. (0) Bits 8 8 8 see Table 6-14 8 8 8 Value
Note: For compatibility with MSP 3410B, IMREG1 and IMREG2 have to be transmitted. The value for IMREG1 and IMREG2 is 004. Due to the partitioning to 8-bit units, the values 04hex, 40hex, and 00hex arise.
FIR2 00 05hex (MSP-Ch2: FM1/AM) No. 1 2 3 4 5 6 7 8 9 Symbol Name IMREG1 IMREG1/ IMREG2 IMREG2 FM/AM_Coef (5) FM/AM_Coef (4) FM/AM_Coef (3) FM/AM_Coef (2) FM/AM_Coef (1) FM/AM_Coef (0) Bits 8 8 8 8 8 8 see Table 6-14 8 8 8 Value 04hex 40hex 00hex
6.3.7. DCO-Registers
Note: The use of this register is no longer recommended. It should be used only in cases where software-compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x0G.
When selecting a TV-sound standard by means of the STANDARD SELECT register, all frequency tuning is performed automatically. If manual setting of the tuning frequency is required, a set of 24-bit registers determining the mixing frequencies of the quadrature mixers can be written manually into the IC. In Table 6-15, some examples of DCO registers are listed. It is necessary to divide them up into low part and high part. The formula for the calculation of the registers for any chosen IF frequency is as follows: INCRdec = int(f/fs 224) with: int = integer function f = IF frequency in MHz fS = sampling frequency (18.432 MHz) Conversion of INCR into hex-format and separation of the 12-bit low and high parts lead to the required register values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI or LO for MSP-Ch2).
6.3.6. FIR-Parameter, Registers FIR1 and FIR2
Note: The use of this register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x0G.
Data-shaping and/or FM/AM bandwidth limitation is performed by a pair of linear phase Finite Impulse Response filters (FIR-filter). The filter coefficients are programmable and are either configured automatically by the STANDARD SELECT register or written manually by the control processor via the control bus. Two not necessarily different sets of coefficients are required: one for MSP-Ch1 (NICAM or FM2) and one for MSP-Ch2 (FM1 = FM-mono). In Table 6-14 several coefficient sets are proposed.
Micronas
May 27, 2003; 6251-476-1DS
95
MSP 34x0G
DATA SHEET
Table 6-14: 8-bit FIR-coefficients (decimal integer) for MSP 34x0D; reset status: all coefficients are "0"
Coefficients for FIR1 00 01hex and FIR2 00 05hex
Terrestrial TV Standards
FM - Satellite FIR filter corresponds to a band-pass with a bandwidth of B = 130 to 500 kHz
B fc frequency
B/G-, D/KNICAM-FM
INICAM-FM FIR1 2 4 -6 -4 40 94 0 FIR2 3 18 27 48 66 72
LNICAM-AM FIR1 -2 -8 -10 10 50 86 0 FIR2 -4 -12 -9 23 79 126
B/G-, D/K-, M-Dual FM FIR2 3 18 27 48 66 72 0
130 kHz FIR2 73 53 64 119 101 127 1
180 kHz FIR2 9 18 28 47 55 64 1
200 kHz FIR2 3 18 27 48 66 72 1
280 kHz FIR2 -8 -8 4 36 78 107 1
380 kHz FIR2 -1 -9 -16 5 65 123 1
500 kHz FIR2 -1 -1 -8 2 59 126 1
Autosearch FIR2 -1 -1 -8 2 59 126 0
Coef(i) 0 1 2 3 4 5 ModeREG[12] ModeREG[13]
FIR1 -2 -8 -10 10 50 86 0
FIR2 3 18 27 48 66 72
0
0
0
1
1
1
1
1
1
1
0
For compatibility, except for the FIR2-AM and the Autosearch-sets, the FIR-filter programming as used for the MSP 3410B is also possible. ADR coefficients are listed in the DRP data sheet.
Table 6-15: DCO registers for the MSP 34x0G; reset status: DCO_HI/LO = "0000"
DCO1_LO 00 93hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex Freq. MHz 4.5 5.04 5.5 5.58 5.7421875 6.0 6.2 6.5 6.552 7.02 7.38 DCO_HI/hex 03E8 0460 04C6 04D8 04FC 0535 0561 05A4 05B0 0618 0668 DCO_LO/hex 000 0000 038E 0000 00AA 0555 0C71 071C 0000 0000 0000 5.76 5.85 5.94 6.6 6.65 6.8 7.2 7.56 0500 0514 0528 05BA 05C5 05E7 0640 0690 0000 0000 0000 0AAA 0C71 01C7 0000 0000 Freq. MHz DCO_HI/hex DCO_LO/hex
96
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
Table 6-16: NICAM operation modes as defined by the EBU NICAM 728 specification
C4 0 0 0 0 C3 0 0 0 0 0 0 0 C2 0 0 1 1 0 0 1 C1 0 1 0 1 0 1 0 Operation Mode Stereo sound (NICAMA/B), independent mono sound (FM1) Two independent mono signals (NICAMA, FM1) Three independent mono channels (NICAMA, NICAMB, FM1) Data transmission only; no audio Stereo sound (NICAMA/B), FM1 carries same channel One mono signal (NICAMA). FM1 carries same channel as NICAMA Two independent mono channels (NICAMA, NICAMB). FM1 carries same channel as NICAMA Data transmission only; no audio Unimplemented sound coding option (not yet defined by EBU NICAM 728 specification)
6.4. Manual/Compatibility Mode: Description of Demodulator Read Registers
Note: The use of these register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the STATUS register provides a more economic way to program the MSP 34x0G and to retrieve information from the IC.
All registers except C_AD_BITs are 8 bits wide. They can be read out of the RAM of the MSP 34x0G if the MSP 34x0D Manual/Compatibility Mode is required. All transmissions take place in 16-bit words. The valid 8-bit data are the 8 LSBs of the received data word. If the Automatic Sound Select feature is not used, the NICAM or FM-identification parameters must be read and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. The FM-identification registers are described in section 6.6.1. To handle the NICAM-sound and to observe the NICAM-quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the controller. Additional data bits and CIB bits, if supplied by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS.
1 1 1
1 x
0 1
1 x
1 x
AUTO_FM: monitor bit for the AUTO_FM Status: 0: NICAM source is NICAM 1: NICAM source is FM
Note: It is no longer necessary to read out and evaluate the C_AD_BITS. All evaluation is performed in the MSP and indicated in the STATUS register.
6.4.1. NICAM Mode Control/Additional Data Bits Register NICAM operation mode control bits and A[2:0] of the additional data bits. Format:
MSB
11 Auto _FM ... ... 7 A[2]
6.4.2. Additional Data Bits Register Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system. Format:
MSB
7 A[10] 6 A[9] 5 A[8]
C_AD_BITS 00 23hex
6 A[1] 5 A[0] 4 C4 3 C3 2 C2 1 C1
LSB
0 S
ADD_BITS 00 38hex
4 A[7] 3 A[6] 2 A[5] 1 A[4]
LSB
0 A[3]
Important: "S" = Bit[0] indicates correct NICAM-synchronization (S = 1). If S = 0, the MSP 3410/3450G has not yet synchronized correctly to frame and sequence, or has lost synchronization. The remaining read registers are therefore not valid. The MSP mutes the NICAM output automatically and tries to synchronize again as long as MODE_REG[6] is set. The operation mode is coded by C4-C1 as shown in Table 6-16.
6.4.3. CIB Bits Register CIB bits 1 and 2 (see NICAM 728 specifications). Format:
MSB
7 x 6 x 5 x
CIB_BITS 00 3Ehex
4 x 3 x 2 x 1 CIB1
LSB
0 CIB2
Micronas
May 27, 2003; 6251-476-1DS
97
MSP 34x0G
6.4.4. NICAM Error Rate Register
ERROR_RATE Error free maximum error rate 00 57hex 0000hex 07FFhex
DATA SHEET
6.4.7. Automatic Search Function for FM-Carrier Detection in Satellite Mode The AM demodulation ability of the MSP 3410G and MSP 3450G offers the possibility to calculate the "field strength" of the momentarily selected FM carrier, which can be read out by the controller. In SAT receivers, this feature can be used to make automatic FM carrier search possible. For this, the MSP has to be switched to AM-mode (MODE_REG[8]), FM-Prescale must be set to 7Fhex = +127dec, and the FM DC notch (see section 6.5.7.) must be switched off. The sound-IF frequency range must now be "scanned" in the MSP-channel 2 by means of the programmable quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz). After each incrementation, a field strength value is available at the quasi-peak detector output (quasipeak detector source must be set to FM), which must be examined for relative maxima by the controller. This results in either continuing search or switching the MSP back to FM demodulation mode. During the search process, the FIR2 must be loaded with the coefficient set "AUTOSEARCH", which enables small bandwidth, resulting in appropriate field strength characteristics. The absolute field strength value (can be read out of "quasi-peak detector output FM1") also gives information on whether a main FM carrier or a subcarrier was detected; and as a practical consequence, the FM bandwidth (FIR1/2) and the deemphasis (50 s or adaptive) can be switched accordingly. Due to the fact that a constant demodulation frequency offset of a few kHz leads to a DC level in the demodulated signal, further fine tuning of the found carrier can be achieved by evaluating the "DC Level Readout FM1". Therefore, the FM DC Notch must be switched on, and the demodulator part must be switched back to FM-demodulation mode.
Average error rate of the NICAM reception in a time interval of 182 ms, which should be close to 0. The initial and maximum value of ERROR_RATE is 2047. This value is also active if the NICAM bit of MODE_REG is not set. Since the value is achieved by filtering, a certain transition time (approx. 0.5 sec) is unavoidable. Acceptable audio may have error rates up to a value of 700 int. Individual evaluation of this value by the controller and an appropriate threshold may define the fallback mode from NICAM to FM/ AM-Mono in case of poor NICAM reception. The bit error rate per second (BER) can be calculated by means of the following formula: BER = ERROR_RATE * 12.3*10-6 /s
6.4.5. PLL_CAPS Readback Register It is possible to read out the actual setting of the PLL_CAPS. In standard applications, this register is not of interest for the customer.
PLL_CAPS minimum frequency nominal frequency maximum frequency PLL_CAPS PLL open PLL closed 02 1Fhex L 1111 1111 0101 0110 RESET 0000 0000 02 1Fhex H xxxx xxx0 xxxx xxx1 FFhex 56hex 00hex
6.4.6. AGC_GAIN Readback Register It is possible to read out the actual setting of AGC_GAIN in Automatic Gain Mode. In standard applications, this register is not of interest for the customer.
AGC_GAIN max. amplification (20 dB) min. amplification (3 dB) 02 1Ehex 0001 0100 0000 0000 14hex 00hex
98
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
6.5. Manual/Compatibility Mode: Description of DSP Write Registers 6.5.1. Additional Channel Matrix Modes
Loudspeaker Matrix Headphone Matrix SCART1 Matrix SCART2 Matrix I2S Matrix Quasi-Peak Detector Matrix SUM/DIFF AB_XCHANGE PHASE_CHANGE_B PHASE_CHANGE_A A_ONLY B_ONLY 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 L L L L L L 40hex 50hex 60hex 70hex 80hex 90hex
Linear Mode Volume SCART1 Volume SCART2 OFF 0 dB gain (digital full scale (FS) to 2 VRMS output) +6 dB gain (-6 dBFS to 2 VRMS output) 00 07hex 00 40hex 0000 0000 RESET 0100 0000 H H 00hex 40hex
0111 1111
7Fhex
Note: SCART Volume linear mode will not be supported in the future (documented for compatibility reasons only).
6.5.3. FM Fixed Deemphasis
FM Deemphasis 50 s 00 0Fhex 0000 0000 RESET 0000 0001 0000 0100 0011 1111 H 00hex 01hex 04hex 3Fhex
This table shows additional modes for the channel matrix registers. The sum/difference mode can be used together with the quasi-peak detector to determine the sound material mode. If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo.
75 s J17 OFF
Note: This register is initialized during STANDARD SELECTION and is automatically updated when Auto-matic Sound Select (MODUS[0]=1) is on.
6.5.2. Volume Modes of SCART1/2 Outputs
Volume Mode SCART1 Volume Mode SCART2 linear logarithmic 00 07hex 00 40hex 0000 RESET 0001 [3:0] [3:0] 0hex 1hex WP1
6.5.4. FM Adaptive Deemphasis
FM Adaptive Deemphasis WP1 OFF 00 0Fhex 0000 0000 RESET 0011 1111 L 00hex 3Fhex
Note: This register is initialized during STANDARD SELECTION and is automatically updated when Auto-matic Sound Select (MODUS[0]=1) is on.
Micronas
May 27, 2003; 6251-476-1DS
99
MSP 34x0G
6.5.5. NICAM Deemphasis A J17 Deemphasis is always applied to the NICAM signal. It is not switchable.
DATA SHEET
6.6. Manual/Compatibility Mode: Description of DSP Read Registers All readable registers are 16-bit wide. Transmissions via I2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writable.
6.5.6. Identification Mode for A2 Stereo Systems
Identification Mode Standard B/G (German Stereo) Standard M (Korean Stereo) Reset of Ident-Filter 00 15hex 0000 0000 RESET 0000 0001 0011 1111 L 00hex 01hex 3Fhex
6.6.1. Stereo Detection Register for A2 Stereo Systems
Stereo Detection Register Stereo Mode 00 18hex H
Reading (two's complement) near zero positive value (ideal reception: 7Fhex) negative value (ideal reception: 80hex)
To shorten the response time of the identification algorithm after a program change between two FM-Stereo capable programs, the reset of the ident-filter can be applied. Sequence: 1. Program change 2. Reset ident-filter 3. Set identification mode back to standard B/G or M 4. Wait approx. 500 ms 5. Read stereo detection register
MONO STEREO BILINGUAL
Note: It is no longer necessary to read out and evaluate the A2 identification level. All evaluation is performed in the MSP and indicated in the STATUS register.
Note: This register is initialized during STANDARD SELECTION and is automatically updated when Auto-matic Sound Select (MODUS[0]=1) is on.
6.6.2. DC Level Register
DC Level Readout FM1 (MSP-Ch2) 00 1Bhex 00 1Chex H+L H+L
6.5.7. FM DC Notch The DC compensation filter (FM DC Notch) for FM input can be switched off. This is used to speed up the automatic search function (see Section 6.4.7.). In normal FM-mode, the FM DC Notch should be switched on.
FM DC Notch ON OFF 00 17hex 0000 0000 Reset 0011 1111 L 00hex 3Fhex
DC Level Readout FM2 (MSP-Ch1) DC Level
[8000hex ... 7FFFhex] values are 16 bit two's complement
The DC level register measures the DC component of the incoming FM signals (FM1 and FM2). This can be used for seek functions in satellite receivers and for IF FM frequencies fine tuning. A too low demodulation frequency (DCO) results in a positive DC-level and vice versa. For further processing, the DC content of the demodulated FM signals is suppressed. The time constant , defining the transition time of the DC Level Register, is approximately 28 ms.
100
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
6.8. Exclusions of Audio Baseband Features In general, all functions can be switched independently. Two exceptions exist: 1. NICAM cannot be processed simultaneously with the FM2 channel. 2. FM adaptive deemphasis cannot be processed simultaneously with FM-identification.
6.7. Demodulator Source Channels in Manual Mode 6.7.1. Terrestric Sound Standards Table 6-17 shows the source channel assignment of the demodulated signals in case of manual mode for all terrestric sound standards. See Table 2-2 for the assignment in the Automatic Sound Select mode. In manual mode for terrestric sound standards, only two demodulator sources are defined.
6.9. Compatibility Restrictions to MSP 34x0D 6.7.2. SAT Sound Standards Table 6-18 shows the source channel assignment of the demodulated signals for SAT sound standards. The MSP 34x0G is fully hardware compatible to the MSP 34x0D. However, to substitute a MSP 34x0D by the corresponding MSP 34x0G, the controller software has to be adapted slightly: 1. The register FM-Matrix (00 0Ehex low part) must be changed from "no matrix (00hex)" to "sound A mono (03hex)" during mono transmission of all TV-sound standards (see also Table 6-17). 2. With the MSP 34x0G, the STANDARD SELECTION initializes the FM-deemphasis, which is not the case for the MSP 34x0D. So, if STANDARD SELECTION is applied, this I2C instruction can be omitted.
Micronas
May 27, 2003; 6251-476-1DS
101
MSP 34x0G
Table 6-17: Manual Sound Select Mode for Terrestric Sound Standards
DATA SHEET
Source Channels of Sound Select Block Broadcasted Sound Standard B/G-FM D/K-FM M-Korea M-Japan Selected MSP Standard Code 03 04, 05 02 30 Broadcasted Sound Mode MONO STEREO BILINGUAL, Languages A and B B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM
(with high deviation FM)
FM Matrix
FM/AM
(use 0 for channel select)
Stereo or A/B
(use 1 for channel select)
Sound A Mono German Stereo Korean Stereo No Matrix Sound A Mono1)
Mono Stereo Left = A Right = B analog Mono
Mono Stereo Left = A Right = B no sound with AUTO_FM: analog Mono
08 09 0A 0B 0C, 0D
NICAM not available or NICAM error rate too high MONO STEREO BILINGUAL, Languages A and B MONO
Sound A Mono1) Sound A Mono1) Sound A Mono1) Sound A Mono Korean Stereo Sound A Mono Korean Stereo Sound A Mono
analog Mono analog Mono analog Mono Mono Stereo Mono Stereo Mono
NICAM Mono NICAM Stereo Left = NICAM A Right = NICAM B Mono Stereo Mono Stereo Mono
20
STEREO MONO + SAP
BTSC
STEREO + SAP MONO 21 STEREO MONO + SAP STEREO + SAP
No Matrix Sound A Mono Korean Stereo
Left = Mono Right = SAP Mono Stereo
Left = Mono Right = SAP Mono Stereo
FM-Radio
1)
40
MONO STEREO
Automatic refresh to Sound A Mono, do not write any other value to the register FM Matrix!
Table 6-18: Manual Sound Select Modes for SAT-Standards
Source Channels of Sound Select Block for SAT-Modes Broadcasted Sound Standard Selected MSP Standard Code 6, 50hex FM SAT 51hex Broadcasted Sound Mode MONO STEREO BILINGUAL FM Matrix FM/AM
(source select: 0)
Stereo or A/B
(source select: 1)
Stereo or A
(source select: 3)
Sound A Mono No Matrix No Matrix
Mono Stereo Left = A (FM1) Right = B (FM2)
Mono Stereo Left = A (FM1) Right = B (FM2)
Mono Stereo A (FM1)
102
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
7. Appendix C: Application Information 7.1. Phase Relationship of Analog Outputs The analog output signals: Loudspeaker, headphone, and SCART2 all have the same phases. The user does not need to correct output phases when using these analog outputs directly. The SCART1 output has opposite phase. Using the I2S-outputs for other DSPs or D/A converters, care must be taken to adjust for the correct phase. If the attached coprocessor is one of the MSP family, the following schematics help to determine the phase relationship.
I2S_IN1/2
I2S_OUT
Loudspeaker Headphone
SCART1-Ch. Audio Baseband Processing SCART1 SCART2 SCART3 SCART4 MONO MONO, SCART1...4 SCART Output Select SCART DSP Input Select SCART1
SCART2-Ch.
SCART2
Fig. 7-1: Phase diagram of the MSP 34x0G
Micronas
May 27, 2003; 6251-476-1DS
103
MSP 34x0G
7.2. Application Circuit
SIF 2 IN
if ANA_IN2+ not used
DATA SHEET
Tuner 2
Signal GND SIF 1 IN
10 F + 3.3 F 56 pF 56 pF 56 pF + 100 nF 100 nF 18.432 MHz
C s. section 4.6.2.
8 V(5 V)
100 pF
56 pF
Tuner 1
ANA_IN1/2+
+ 10 F + 10 F 1 k
Alternative circuit for SIF-inputs for more attenuation of video components:
XTAL_OUT
CAPL_M
ANA_IN-
ANA_IN1+
ANA_IN2+
VREFTOP
XTAL_IN
CAPL_A
AGNDC
1 F
DACM_L 330 nF MONO_IN 1 nF DACM_R 330 nF 330 nF AHVSS 330 nF 330 nF AHVSS 330 nF 330 nF AHVSS 330 nF ASG SC4_IN_L SC4_IN_R SC1_IN_L 1 nF SC1_IN_R ASG SC2_IN_L SC2_IN_R ASG SC3_IN_L SC3_IN_R DACA_R 1 nF DACA_L 1 nF 1 nF DACM_SUB
1 F 1 F
LOUD SPEAKER
1 F 1 F
HEAD PHONE
5V 5V
DVSS
330 nF
MSP 34x0G
SC1_OUT_L SC1_OUT_R
100 22 F
+
STANDBYQ ADR_SEL
100 22 F
+
DVSS I2C_DA I2C_CL ADR_WS ADR_CL ADR_DA I2S_WS I2S_CL I2S_DA_IN1 I2S_DA_IN2 I2S_DA_OUT
SC2_OUT_L
100 22 F
+
SC2_OUT_R
100 22 F
+
D_CTR_I/O_0 D_CTR_I/O_1
AUD_CL_OUT TESTEN AHVSS
RESETQ
AHVSUP
DVSUP
AHVSS
AVSUP
VREF1 AHVSS
RESETQ (from Controller, see section 4.6.3.3.)
220 pF 470 pF 1.5 nF 10 F
470 pF 1.5 nF 10 F
470 pF 1.5 nF 10 F
AHVSS
5V (3.3 V)
5V
8V (5 V)
104
AHVSS
AVSS
VREF2
DVSS
AVSS
May 27, 2003; 6251-476-1DS
Micronas
DATA SHEET
MSP 34x0G
8. Appendix D: MSP 34x0G Version History
MSP 34x0G-B8 - fine-tuning of A2-identification and carrier mute - EIA-J identification: faster transition time stereo/ bilingual to mono - J17 FM-deemphasis implemented - input specification for RESETQ and TESTEN changed - MB implemented
MSP 34x0G-B8V3 - The Automatic Sound Select (ASS) malfunction has been corrected. In the previous version, under certain circumstances and depending on the baseband features used, e.g.: Micronas BASS, Virtual Surround Sound, Equalizer... etc., the Automatic Sound Select Feature (ASS) did not work correctly. - Pseudo Stereo Effect (PSE) malfunction has been corrected
MSP 34x0G-C12 - FM-Radio available in non-BTSC versions with activation key MSP 3400G/3410G - implementation of SRS WOW - implementation of BBE - implementation of Micronas VOICE - correction of default Scart-Switch configuration during power-up
Micronas
May 27, 2003; 6251-476-1DS
105
MSP 34x0G
9. Data Sheet History 1. Preliminary data sheet: "MSP 34x0G Multistandard Sound Processor Family", March 5, 2001, 6251-476-4PD. Fourth release of the preliminary data sheet. Major changes: - specification for version B8 added (see Appendix D: Version History) - MSP 3460 added, MSP 3430 removed - description for MDB added - specification for MNR added - I2C-bus description changed - ACB register: documentation for bit allocation D_CTR_I/O changed 2. Data Sheet: "MSP 34x0G Multistandard Sound Processor Family", May 27, 2003, 6251-476-1DS. First release of the data sheet.Major changes: - specification for version C12 added - implementation of SRS WOW - implementation of BBE - implementation of Micronas VOICE - Section 4.1.: diagrams for all packages changed - PLQFP64 changed to PMQFP64-2 - Micronas Dynamic Bass (MDB) changed to Micronas BASS (MB)
DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-476-1DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
106
May 27, 2003; 6251-476-1DS
Micronas

▲Up To Search▲

Price & Availability of MSP3460G

	To Download MSP3460G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .