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K7B403625B K7B401825B
128Kx36 & 256Kx18 Synchronous SRAM
4Mb Sync. Burst SRAM Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
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* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 3.0 July 2006
K7B403625B K7B401825B
Document Title
128Kx36 & 256Kx18 Synchronous SRAM
128Kx36 & 256Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No. 0.0 0.1 History 1. Initial draft 1. Changed DC parameters Icc ; from 300mA to 250mA at -65, from 280mA to 230mA at -75, from 260mA to 210mA at -80, from 240mA to 190mA at -90, Icc ; from 140mA from 130mA from 120mA from 110mA to to to to 130mA at -65, 120mA at -75, 110mA at -80, 100mA at -90, Draft Date May. 15. 2001 June. 12. 2001 Remark Preliminary Preliminary
0.2 1.0
ISB1 ; from 100mA to 80mA 1. Add x32 org. and industrial temperature 1. Final spec release 2. Changed Pin Capacitance - Cin ; from 5pF to 4pF - Cout ; from 7pF to 6pF 1. Remove x32 organization 2. Remove -80 speed bin 1. Add lead-free package
Aug. 11. 2001 Nov. 15. 2001
Preliminary Final
2.0
Nov. 17. 2003
Final
3.0
Jul. 3, 2006
Final
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Rev. 3.0 July 2006
K7B403625B K7B401825B
128Kx36 & 256Kx18 Synchronous SRAM
4Mb SB SRAM Ordering Information
Org. 256Kx18 128Kx32 128Kx36 3.3 VDD (V) Speed (ns) 7.5 8.5 7.5 8.5 7.5 8.5 Access Time (ns) 6.5 7.5 6.5 7.5 6.5 7.5 Part Number K7B401825B-P(Q)1C(I)265 K7B401825B-Q C(I) 75
3 2
RoHS Avail.
*
K7B403225B-P(Q)1C(I)265 K7B403225B-Q C(I)75
3
*
K7B403625B-P(Q)1C(I)265 K7B403625B-Q3C(I)275
*
Note 1. P(Q) [Package type]: P-Pb Free, Q-Pb 2. C(I) [Operating Temperature]: C-Commercial, I-Industrial 3. Support only Pb package parts at this frequency. To use Pb-Free package, use faster frequency parts.
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Rev. 3.0 July 2006
K7B403625B K7B401825B
FEATURES
128Kx36 & 256Kx18 Synchronous SRAM
128Kx36 & 256Kx18-Bit Synchronous Burst SRAM
GENERAL DESCRIPTION
The K7B403625B and K7B401825B are 4,718,592 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system. And with CS1 high, ADSP is blocked to control signals. It can be organized as 128K(256K) words of 36(18) bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B403625B and K7B401825B are implemented with SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. * Synchronous Operation. * On-Chip Address Counter. * Write Self-Timed Cycle. * On-Chip Address and Control Registers. * VDD= 3.3V+0.3V/-0.165V Power Supply. * VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. * 5V Tolerant Inputs except I/O Pins. * Byte Writable Function. * Global Write Enable Controls a full bus-width write. * Power Down State via ZZ Signal. * Asynchronous Output Enable Control. * ADSP, ADSC, ADV Burst Control Pins. * LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention. * TTL-Level Three-State Output. * 100-TQFP-1420A (Lead and Lead-Free package) * Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -65 -75 Unit 7.5 6.5 3.5 8.5 7.5 3.5 ns ns ns
LOGIC BLOCK DIAGRAM
CLK LBO
CONTROL REGISTER
ADV ADSC
BURST CONTROL LOGIC
BURST ADDRESS A0~A1 COUNTER
A0~A1
128Kx36 , 256Kx18 MEMORY ARRAY
ADSP
A0~A16 or A0~A17
ADDRESS REGISTER
A2~A16 or A2~A17
CS1 CS2 CS2 GW BW WEx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd
DATA-IN REGISTER CONTROL REGISTER
or DQa0 ~ DQb7 DQPa ~ DQPb
CONTROL LOGIC
OUTPUT BUFFER
36 or 18
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Rev. 3.0 July 2006
K7B403625B K7B401825B
PIN CONFIGURATION(TOP VIEW)
128Kx36 & 256Kx18 Synchronous SRAM
ADSC
WEb
WEa
WEc
ADSP
WEd
CS2
ADV 83
CLK
CS1
CS2
VDD
GW
VSS
BW
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
LBO
VSS
VDD
A5
A4
A3
A2
A1
A0
A10
A12
A13
A14
A15
N.C.
N.C.
N.C.
N.C.
PIN NAME
SYMBOL A0 - A16 PIN NAME Address Inputs TQFP PIN NO. SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control 86 88 87 64 31 VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,41,65,91 17,40,67,90 14,16,38,39,42,43,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 83 Burst Address Advance Address Status Processor 84 Address Status Controller 85 89 Clock 98 Chip Select 97 Chip Select 92 Chip Select 93,94,95,96 Byte Write Inputs
ADV ADSP ADSC CLK CS1 CS2 CS2 WEx (x=a,b,c,d) OE GW BW ZZ LBO
A11
Output Power Supply (2.5V or 3.3V) Output Ground
A16
50
DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7B403625B(128Kx36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa
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Rev. 3.0 July 2006
K7B403625B K7B401825B
PIN CONFIGURATION(TOP VIEW)
128Kx36 & 256Kx18 Synchronous SRAM
ADSC
ADSP
WEb
WEa
A6
ADV 83
N.C.
N.C.
CLK
CS1
CS2
CS2
VDD
GW
VSS
BW
OE
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
VDD
N.C.
N.C.
VSS
A5
A4
A3
A2
A1
A0
A12
A13
A14
A15
A16
LBO
PIN NAME
SYMBOL A0 - A17 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49, 50,80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 SYMBOL VDD VSS N.C. PIN NAME Power Supply(+3.3V) Ground No Connect TQFP PIN NO. 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29, 30,38,39,42,43,51,52,53, 56,57,66,75,78,79,95,96 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV ADSP ADSC CLK CS1 CS2 CS2 WEx (x=a,b) OE GW BW ZZ LBO
Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control
A11
DQa0~a7 DQb0~b7 DQPa, Pb VDDQ VSSQ
Data Inputs/Outputs
Output Power Supply (2.5V or 3.3V) Output Ground
A17
50
N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 N.C. VDD N.C. VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7B401825B(256Kx18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS N.C. VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
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Rev. 3.0 July 2006
K7B403625B K7B401825B
FUNCTION DESCRIPTION
128Kx36 & 256Kx18 Synchronous SRAM
The K7B403625B and K7B401825B are synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the output pins. Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and individual byte write operation. All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high and BW is low. In K7B403625B, a 128Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd. CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded. ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address increases internally for the next access of the burst when ADV is sampled low. Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1
(Interleaved Burst)
Case 4 A1 1 1 0 0 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to high or low, and floating state must not be allowed.
BURST SEQUENCE TABLE
LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1 A1 1 0 0 1
(Linear Burst)
Case 4 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to high or low, and floating state must not be allowed.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
Notes 1. X means "Don't Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffersmust be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time.
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Rev. 3.0 July 2006
K7B403625B K7B401825B
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 H L L L L L L L X H X H X H X H CS2 X L X L X H H H X X X X X X X X CS2 X X H X H L L L X X X X X X X X ADSP ADSC X L L X X L H H H X H X H X H X L X X L L X L L H H H H H H H H ADV X X X X X X X X L L L L H H H H
128Kx36 & 256Kx18 Synchronous SRAM
WRITE X X X X X X L H H H L L H H L L
CLK
ADDRESS ACCESSED N/A N/A N/A N/A N/A External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address
OPERATION Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst Read Cycle Begin Burst Write Cycle Begin Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Write Cycle Continue Burst Write Cycle Suspend Burst Read Cycle Suspend Burst Read Cycle Suspend Burst Write Cycle Suspend Burst Write Cycle
Notes : 1. X means "Dont Care".
2. The rising edge of clock is symbolized by .
3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
GW H H H H H H L BW H L L L L L X WEa X H L H H L X WEb X H H L H L X WEc X H H H L L X WEd X H H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE BYTE c and d WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
WRITE TRUTH TABLE(x18)
GW H H H H H L BW H L L L L X WEa X H L H L X WEb X H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
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Rev. 3.0 July 2006
K7B403625B K7B401825B
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Voltage on I/O Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias
128Kx36 & 256Kx18 Synchronous SRAM
SYMBOL VDD VDDQ VIN VIO PD TSTG Commercial Industrial TOPR TOPR TBIAS
RATING -0.3 to 4.6 VDD -0.3 to VDD+0.3 -0.3 to VDDQ+0.3 1.4 -65 to 150 0 to 70 -40 to 85 -10 to 85
UNIT V V V V W C C C C
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0C TA70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 3.135 0 Typ. 3.3 3.3 0 MAX 3.6 3.6 0 UNIT V V V
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 2.375 0 Typ. 3.3 2.5 0 MAX 3.6 2.9 0 UNIT V V V
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25C, f=1MHz)
PARAMETER Input Capacitance Output Capacitance
*Note : Sampled not 100% tested.
SYMBOL CIN COUT
TEST CONDITION VIN=0V VOUT=0V
TYP -
MAX 4 6
UNIT pF pF
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Rev. 3.0 July 2006
K7B403625B K7B401825B
PARAMETER Input Leakage Current(except ZZ) Output Leakage Current Operating Current SYMBOL IIL IOL ICC ISB
128Kx36 & 256Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70C, VDD=3.3V+0.3V/-0.165V)
TEST CONDITIONS VDD=Max , VIN=VSS to VDD Output Disabled, VOUT=VSS to VDDQ Device Selected, IOUT=0mA, ZZVIL, All Inputs=VIL or VIH Device deselected, IOUT=0mA, ZZVIL, f=Max, All Inputs0.2V or VDD-0.2V -65 -75 -65 -75 MIN -2 -2 2.4 2.0 -0.5* 2.0 -0.3* 1.7 MAX +2 +2 250 230 130 120 80 50 0.4 0.4 0.8 VDD+03** 0.7 VDD+0.3** mA mA mA V V V V V V V V UNI A A mA
Standby Current
ISB1 ISB2
Device deselected, IOUT=0mA, ZZ0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, f=Max, All InputsVIL or VIH IOL = 8.0mA IOH = -4.0mA IOL = 1.0mA IOH = -1.0mA
Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O)
VOL VOH VOL VOH VIL VIH VIL VIH
The above parameters are also guaranteed at industrial temperature range. * VIL(Min)=-2.0(Pulse Width tCYC/2) ** VIH(Max)=4.6(Pulse Width tCYC/2) ** In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70C)
PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O) Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load
* The above parameters are also guaranteed at industrial temperature range.
VALUE 0 to 3V 0 to 2.5V 1ns 1ns 1.5V VDDQ/2 See Fig. 1
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Rev. 3.0 July 2006
K7B403625B K7B401825B
Output Load(A)
128Kx36 & 256Kx18 Synchronous SRAM
Output Load(B) (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O Dout 353 / 1538 319 / 1667
Dout Z0=50
RL=50 30pF*
VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O
5pF*
* Capacitive Load consists of all components of the test environment. Fig. 1
* Including Scope and Jig Capacitance
AC TIMING CHARACTERISTICS(TA=0 to 70C, VDD=3.3V+0.3V/-0.165V)
PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High Address Status Setup to Clock High Data Setup to Clock High Write Setup to Clock High(GW, BW, WEx) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High Address Status Hold from Clock High Data Hold from Clock High Write Hold from Clock High(GW, BW, WEx) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up Symbol tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tSS tDS tWS tADVS tCSS tAH tSH tDH tWH tADVH tCSH tPDS tPUS -65 Min 7.5 0 2.5 0 2 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 Max 6.5 3.5 3.5 3.5 Min 8.5 0 2.5 0 2 3 3 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -75 Max 7.5 3.5 3.5 3.5 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle
Notes : 1 The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. 5. At any given voltage and temperature, tHZC is less than tLZC.
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Rev. 3.0 July 2006
TIMING WAVEFORM OF READ CYCLE
tCH tCL
CLOCK
tCYC
K7B403625B K7B401825B
tSS
tSH
ADSP
tSS tSH
ADSC
BURST CONTINUED WITH NEW BASE ADDRESS
tAS A2 tWH A3
tAH
ADDRESS
A1
tWS
128Kx36 & 256Kx18 Synchronous SRAM
- 12 tADVH
(ADV INSERTS WAIT STATE)
WRITE
tCSS
tCSH
CS
tADVS
ADV
OE
tHZOE tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 tHZC Q3-4
tOE
tLZOE
Data Out
Q1-1
Rev. 3.0 July 2006
Dont Care Undefined
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF WRTE CYCLE
tCH tCL
CLOCK
tCYC
K7B403625B K7B401825B
tSS
tSH
ADSP
tSS tSH
ADSC
(ADSC EXTENDED BURST)
tAS A2 A3
tAH
ADDRESS
A1
tWS
tWH
WRITE
128Kx36 & 256Kx18 Synchronous SRAM
- 13 (ADV SUSPENDS BURST)
tCSS
tCSH
CS
tADVS tADVH
ADV
OE
tDS D1-1 D2-1 D2-2 D2-2 D2-3 D2-4 D3-1 D3-2 tDH D3-3 D3-4
Data In
tLZOE
Rev. 3.0 July 2006
Data Out
Q0-3
Q0-4
Dont Care Undefined
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
tCH tCL
CLOCK
tCYC
K7B403625B K7B401825B
tSS
tSH
ADSP tAS
tAH A2 A3 tWS tWH
ADDRESS
A1
WRITE
CS
tADVS tADVH
128Kx36 & 256Kx18 Synchronous SRAM
- 14 tDS D2-1 tHZOE Q1-1 tOE tLZOE Q3-1 Q3-2 tDH
ADV
OE
Data In
tHZC
tCD tLZC
tOH Q3-3 Q3-4
Data Out
Rev. 3.0 July 2006
Dont Care Undefined
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH)
tCH tCL
CLOCK
tCYC
K7B403625B K7B401825B
tSS
tSH
ADSC
tWS tWH A8 A9 A3 tWS tWH A4 A5 A6 A7
ADDRESS
A1
A2
WRITE
tCSS
tCSH
CS
128Kx36 & 256Kx18 Synchronous SRAM
- 15 tHZOE Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1 tDH
ADV
OE
tCD Q8-1 tOH Q9-1
tOE
tLZOE
Data Out
Q1-1
Rev. 3.0 July 2006
Data In
D7-1
Dont Care Undefined
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
tCH tCL
CLOCK
tCYC
K7B403625B K7B401825B
tSS
tSH
ADSP
tAS A3 A4 A5 A6 A7 A8 tAH A9
ADDRESS
A1
A2
WRITE
tCSS
tCSH
CS
128Kx36 & 256Kx18 Synchronous SRAM
- 16 tHZOE Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1 tDH
ADV
OE
tCD Q8-1 tOH Q9-1
tOE
tLZOE
Data Out
Q1-1
Data In
D7-1
Rev. 3.0 July 2006
Dont Care Undefined
TIMING WAVEFORM OF POWER DOWN CYCLE
tCH tCL
CLOCK
tCYC
tSS
tSH
K7B403625B K7B401825B
ADSP
ADSC
tAS A2
tAH
ADDRESS
A1
tWS
tWH
WRITE
tCSS
tCSH
128Kx36 & 256Kx18 Synchronous SRAM
- 17 tHZC tPDS
ZZ Setup Cycle Sleep State
CS
ADV
OE
tOE D2-1 tHZOE D2-2
Data In
tLZOE
Data Out
Q1-1 tPUS
ZZ Recovery Cycle Normal Operation Mode
ZZ
Rev. 3.0 July 2006
Dont Care Undefined
K7B403625B K7B401825B
APPLICATION INFORMATION
DEPTH EXPANSION
128Kx36 & 256Kx18 Synchronous SRAM
The Samsung 128Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic. Data Address A[0:17] A[17] A[0:16] I/O[0:71] A[17]
A[0:16]
Address CS2 CS2 Data
CLK
Address CS2 CS2 CLK Address CLK Cache Controller ADSC WEx OE CS1 ADV
Data
64-bits Microprocessor
128Kx36 SB SRAM (Bank 0)
CLK ADSC WEx OE CS1 ADV
128Kx36 SB SRAM (Bank 1)
ADSP
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HiGH) CLOCK
tSS tSH
ADSP
tAS tAH A2 tWS tWH A1
ADDRESS [0:n] WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
tOE
Data Out (Bank 0) Data Out (Bank 1)
tLZOE
tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 Q2-2 Q2-3 Q2-4
Dont Care Undefined
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
- 18 -
Rev. 3.0 July 2006
K7B403625B K7B401825B
APPLICATION INFORMATION
DEPTH EXPANSION
128Kx36 & 256Kx18 Synchronous SRAM
The Samsung 256Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic. Data Address I/O[0:71] A[0:18] A[18] A[0:17] Address CS2 CS2 Data A[18] A[0:17] Address CS2 CS2 256Kx18 SB SRAM (Bank 0) CLK ADSC WEx OE CS1 ADSP ADV ADSP 256Kx18 SB SRAM (Bank 1) Data
CLK
Microprocessor
Address CLK Cache Controller
CLK ADSC WEx OE CS1 ADV
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH) CLOCK
tSS tSH
ADSP
tAS tAH A2 tWS tWH A1
ADDRESS [0:n] WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
tOE
Data Out (Bank 0) Data Out (Bank 1)
tLZOE
tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 Q2-2 Q2-3 Q2-4
Dont Care Undefined
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
- 19 -
Rev. 3.0 July 2006
K7B403625B K7B401825B
PACKAGE DIMENSIONS
100-TQFP-1420A (Lead & Lead-Free)
22.00 0.30 20.00 0.20
128Kx36 & 256Kx18 Synchronous SRAM
Units:millimeters/inches
0~8
0.10 0.127 + 0.05 -
16.00 0.30 14.00 0.20 0.10 MAX
(0.83) 0.50 0.10 #1 0.65 0.30 0.10 0.10 MAX (0.58)
1.40 0.10 0.50 0.10 0.05 MIN
1.60 MAX
- 20 -
Rev. 3.0 July 2006

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