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TD7624AFN TENTATIVE
TOSHIBA BIPOLAR DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TD7624AFN
3-WIRE AND I C BUS SYSTEM, 1.3 GHz DIRECT TWO MODULUS-TYPE FREQUENCY SYNTHESIZER FOR TV AND CATV
The TD7624AFN can be combined with a micro CPU to create a highly functional frequency synthesizer. The control data conforms to 3-wire bus and standard I2C bus formats. BUS-SW can be used to easily switch for easy tuner system set-up.
2
FEATURES
= Direct two modulus-type frequency synthesizer = 3-wire bus format control = 18-bit and 19-bit automatic discrimination circuit (when 3-wire bus selected) = 4-bit bandswitch drive transistor = 5-level A / D converter (when I2C bus selected) = Frequency Step : 31.25 kHz, 50 kHz and 62.5kHz (at 4 MHz X'tal used) = Phase lock detector = Four address settings via address selector (when I2C bus selected) = Power on reset circuit = Flat, compact package : SSOP16 (0.65 mm pitch) = Power on reset operation condition Bandswitch register 1 to 4 : OFF Tuning amplifier : ON Tuning voltage output (Vt) : Low level Charge-pump output current : 60 A Phase comparator reference frequency divider ratio Note: Weight: 0.07 g (Typ.) = Standard I2C bus format control with built-in read mode
: 1 / 64
These devices are easy to be damaged by high static voltage or electric fields. In regards to this, please handle with care.
000707EBA1
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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BLOCK DIAGRAM
MAXIMUM RATINGS (Ta = 25C)
CHARACTERISTIC Supply Voltage 1 Supply Voltage 2 Power Consumption Operating Temperature Storage Temperature SYMBOL VCC1 VCC2 PD Topr Tstg RATING 6.0 12 560 -20~85 -55~150 UNIT V V mW C C
Note 1: When using the device at above Ta = 25C, decrease the power dissipation by 4.5 mW for each increase of 1C. Note 2: These devices are easy to be damaged by high static voltage or electric fields. In regards to this, please handle with care.
RECOMMENDED SUPPLY VOLTAGE
PIN No. 3 4 PIN NAME VCC1 : PLL Power Supply VCC2 : Band Switch Power Supply MIN 4.5 VCC1 TYP. 5.0 MAX 5.5 9.9 UNIT V V
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PIN INTERFACE
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ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, VCC1 = 5 V, VCC2 = 9 V, Ta = 25C)
CHARACTERISTIC Supply Voltage 1 Supply Current 1 Supply Voltage 2 SYMBOL VCC1 ICC1 VCC2 ICC2-1 Supply Current 2 ICC2-2 Bandswitch Drive Current Bandswitch Drive Maximum LOAD Bandswitch Drive Voltage Drop X'tal Operating Range X'tal Negative Resistance X'tal External Input Level Ratio Setting Range IBD IBDMAX VBD Sat OSCfin OSCR OSCin N14 N13 Vin1 Vin2 VLkL VLkH VBsL VBsH IBsL IBsH VBIL VBIH 3 3 3 1 1 TEST CIRCUIT 1 TEST CONDITION Bandswitch : OFF Vt : OFF Bandswitch : 1 Band ON IBD = 30 mA (LOAD) Bandswitch : 2 Band ON IBD = 40 mA (TOTAL LOAD) Maximum Drive Current / 1 port Maximum Total Drive Current IBD = 30 mA 3.2 MHz~4.5 MHz, Rx = 91 k 15-bit counter 14-bit counter f = 80~150 MHz f = 150~1300 MHz (lock mode, 3-wire bus mode) (unlock mode, 3-wire bus mode) Pins 13 to 15 Pins 13 to 15 Pins 13 to 15 Pins 13 to 15 MIN 4.5 13 VCC1 3.2 1.0 250 1024 1024 -25 -30 4.6 -0.3 3.0 -20 -10 0.0 4.2 TYP. 5.0 16 35 50 0.2 1.5 MAX 5.5 21 9.9 39 mA 58 30 50 0.4 4.5 1000 32767 16384 +5 +5 0.4 1.5 VCC1 +0.3 10 20 0.8 VCC1 mA mA V MHz k mVp-p Ratio UNIT V mA V
Prescaler Input Sensitivity Lock Output Low Voltage Lock Output High Voltage Logic Input Low Voltage Logic Input High Voltage Logic Input Current (low) Logic Input Current (high) BUS-SW Low Input Voltage BUS-SW High Input Voltage
2 1 1 1 1 1 1 1 1
dBmW V V V V A
V
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CHARACTERISTIC BUS-SW Low Current (low) BUS-SW Low Current (high) Charge Pump Output Current ACK Output Voltage A / D Converter Input Voltage Set-up Time Enable Hold Time Next Enable Stop Time Next Clock Stop Time Clock Width Enable Set-up Time Data Hold Time SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition Low Period of the SCL Clock High Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Rise Time of both SDA and SCL Signals Fall Time of both SDA and SCL Signals Set-up Time for STOP Condition SYMBOL IBIL IBIH Ichg VACK VADC Ts TsL TNE TNC Tc TL TH fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO (I C bus mode) Refer to data timing chart
2
TEST CIRCUIT 1 1 2 1
TEST CONDITION CP = [0] CP = [1] ISINK = 3 mA (I C-bus mode)
2
MIN. -200 50 230 0.0 2 2 6
TYP. 60 280
MAX. 200 90 420 0.4 VCC1 100 1000 300
UNIT
A
A V V
(3-wire bus mode) Refer to data timing chart
6 2 10 2 0 4.7
s
kHz
4.0 4.7 4.0 4.7 0 250 4.0
s
ns
s
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Fig.1 3-wire bus data timing chart (Falling edge timing)
Fig.2
I C bus data timing chart (Falling edge timing)
2
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OPERATION INSTRUCTIONS
TD7624AFN can be controlled with either the 3-wire bus or standard I2C bus. The 3-wire bus mode is equipped with an 18-bit / 19-bit automatic selection circuit. Frequency steps can be switched, depending on the voltage applied to the BUS-SW pin. The I2C bus conforms to the standard I2C bus format. The bus supports two-way bus communications control, consisting of WRITE mode where data are received and READ mode where data are transmitted. In READ mode, the voltage applied on the A / D converter input pin can be transmitted and output with 5-level resolution. (This function is only valid when the I2C bus is selected. When the 3-wire bus is selected, the A / D converter input pin function as the LOCK output pin.) Addresses can be set using the hardware bits. Three programmable addresses are supported. 3-wire bus and standard I2C bus are switches by the voltage applied on the BUS-SW pin. The power-on reset circuit is built in this product, and the detection voltage is designed about 1.4 V. If it raises to voltage of operation after making it stop for a while near the voltage of a power-on reset circuit of operation at the time of starting of a power supply, a power-on reset circuit may not operate normally.
FUNCTION CHART
NAME BUS-SW CL / SCL DA / SDA EN / ADR
LOCK / ADC
3-WIRE BUS MODE [OPEN] or [VCC] CLOCK INPUT DATA INPUT ENABLE INPUT
LOCK
I C BUS MODE [GND] SCL INPUT SDA IN / OUTPUT ADDRESS ADC
2
3-WIRE BUS COMMUNICATIONS CONTROL
The 3-wire bus used normal 18-bit and 19-bit data (bandswitch information and programmable counter information) and 27-bit test data (charge pump current setting, reference frequency divider ratio setting, and testing item functions) are available. The program frequency can be calculated together with normal data and test data. fosc = fr x N fosc : Program frequency fr : Phase comparator reference frequency (Step frequency) N : Counter total ratio
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(1) Normal data
Depending on the voltage (OPEN, VCC) applied on the BUS-SW pin and the transfer DATA bit length, the X'tal divider ratio setting, phase comparator reference frequency, and step frequency of the normal data are as shown in the table below. NORMAL DATA FUNCTION TABLE
BUS-SW INPUT [VCC] [VCC] [OPEN] [OPEN] TRANSFER DATA 18-bit 19-bit 18-bit 19-bit X'TAL RATIO Cannot be set 1 / 80 1 / 64 1 / 128 REFERENCE FREQUENCY 50 kHz 62.5 kHz 31.25 kHz STEP FREQUENCY 50 kHz 62.5 kHz 31.25 kHz
Note 1: The step frequency at 4 MHz X'tal used Note 2: During "OPEN", automatically set with transmitted bit length (1819 possible)
Fig.3
Normal data format (18-bit transmission)
Fig.4
Normal data format (19-bit transmission)
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l 18-bit DATA TRANSMISSION :
During a high level of the enable signal, the data is clocked into the register on the falling edge of the clock. The clock number during a high level of the enable signal must be set to 18-bit for the latch condition. (The number of clock rising edges is 18). For latch timing, the first four bits, which control the bandswitch buffers, are loaded at the fifth rising edge of the clock, and the data is updated. The programmed counter data transmits the 18-bit data, latched on the falling edge of the enable signal. During 18-bit data transmission, "N14" programmable counter data is constantly set to [0] , and the phase comparator reference frequency divider ratio is automatically set to "1 / 64". Details of the data timing, see the data timing chart (Figure 1)
l 19-bit DATA TRANSMISSION :
During a high level of the enable signal, the data is clocked into the register on the falling edge of the clock. The clock number during a high level of the enable signal must be set to 19-bit for the latch condition. (The number of clock rising edge is 19). For latch timing, the first four bits, which control the bandswitch buffers, are loaded at the fifth rising edge of the clock, and the data is updated. The programmed counter data transmits the 19-bit data, latched on the falling edge of the enable signal. During 19-bit data transmission, the phase comparator reference frequency divider ratio is automatically set to "1 / 80" or "1 / 128" in BUS-SW mode. Details of the data timing, see the data timing chart (Figure 1)
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(1) TEST MODE
In the test mode, the settings can be changed and the functions can be checked. Change from the normal mode to the test mode with a 27-bit or more of clock and data transmission during a high level of the enable signal. The data are latched at the 27th falling edge of the clock signal, validating the previous 27-bit data. The latch timing is the same as normal data. The 4-bit bandswitch data are latched at the 5th bit rising edge of the clock signal, and the data is updated. The programmable counter data are latched at the 20th bit rising edge of the clock signal, and the data is updated. The test data are latched at the 27th bit falling edge of the clock signal, and the data is updated. When the mode is changed from test to normal, RSa changes depending on the data bit length (18 or 19 bits, automatic discrimination). The data set in RSb in test mode are retained (see the table below).
REFERENCE FREQUENCY DIVIDER RATIO SETTING VIA TEST MODE 1 / 64 DATA TRANSMISSION LENGTH 18-bit 19-bit 18-bit 19-bit 18-bit 19-bit SET REFERENCE FREQUENCY DIVIDER RATIO 1 / 64 1 / 128 1 / 80 1 / 80 1 / 64 1 / 128
1 / 80
1 / 128
Fig.5
Test data format
Note:
The data timing is the same as normal data.
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TEST DATA SPECIFICATIONS
= B4~B1 : Band drive data [0] : OFF [1] : ON : Programmable divider data : Charge pump output current [0] : 60 A (Typ.) [1] : 280 A (Typ.)
= N14~N0 = CP
= T2, T1, T0 : Test mode setting bits
CHARACTERISTIC Normal operation Reference signal output 1 / 2 counter divider output Phase comparator test T2 0 1 1 0 T1 0 0 0 0 T0 1 0 1 0 NOTE Reference signal output : B4, Counter output : B2 Reference signal output : B4, 1 / 2 counter output : B2 Comparative signal input : DA Reference signal input : CL (check output : NF)
X : Don't care Note: When testing the counter divider output, programmable counter data input is necessary. : X'tal Reference frequency divider ratio select bits
DIVIDER RATIO 1 / 64 1 / 128 1 / 80 STEP FREQUENCY 62.5 k 31.25 k 50.0 k
= Rsa, Rsb
RSa 1 0 X RSb 1 1 0
Note:
X : Don't care When the mode is changed from test to normal, RSa changes depending on the data bit length (18 or 19 bits, automatic discrimination). The data set in RSb in test mode are retained. : Tuning amplifier control bit [0] : Tuning amp ON (Normal operation) [1] : Tuning amp OFF (Tr. Output is Low Level) : Don't care
= OS
=X
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I C BUS COMMUNICATIONS CONTROL
The TD7624AFN conform to standard I2C bus format. The I2C bus mode enables two-way bus communications with the WRITE mode, which receives data, and READ mode, which status data. WRITE and READ mode are set using the last bit (R / W bit) of the address byte. If the last address bit is set to [0] , WRITE mode is set ; if set to [1] READ mode is set. Address can be set using the hardware bits. Three programmable address can be programmed. With this setting, multiple frequency synthesizers can be used in the same I2C bus line. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR : Pin 15). An address is selected according to the set bits. When the correct address byte is received, during acknowledgment, serial data (SDA) line is "Low". If WRITE mode is set at this time, when the data byte is programmed, the serial data (SDA) line is "Low" during the next acknowledgment. 2
a) WRITE mode (setting command)
When WRITE mode is set, Byte 1 segment the address data ; Bytes 2 and 3 segment the frequency data ; Byte 4 segment the divider ratio setting and function setting data ; and Byte 5 segment the output port data. Data are latched and transferred at the end of Byte 3, Byte 4 and Byte 5. Byte 2 and Byte 3 are latched and transferred is done with a two byte set (Byte 2 + Byte 3). Once a correct address is received and acknowledged, the data type is determined according to [0] or [1] set in the first bit of the next byte. That is, if the first bit is [0] , the data are frequency data ; if [1] , function setting or output port data. Until the I2C bus STOP CONDITION is detected, the additional data can be input without transmitting the address again. (Ex : Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid. Byte 1 can set the hardware bit with address data. The hardware bit is set with voltage applied to the address setting pin (ADR : Pin 15). Bytes 2 and 3 are stored in the 15-bit shift register with counter data for the frequency setting, and control the 15-bit programmable counter ratio. The program frequency can be calculated in the following formula : fosc = fr x N fosc : Program frequency fr : Phase comparator reference frequency (Step frequency) N : Counter total ratio fr is calculated using the crystal oscillator frequency and the reference frequency divider ratio set in byte 4 (control byte). (fr = X'tal oscillator frequency / reference frequency divider ratio) The reference frequency divider ratio can be set to 1 / 64, 1 / 128 and 1 / 80. When using a 4 MHz crystal oscillator, fr = 62.5 kHz, 31.25 kHz and 50 kHz. The step frequency are 62.5kHz, 31.25kHz, and 50kHz. Byte 4 is a control byte used to set function. Bit 2 (CP) controls the output current of the charge-pump circuit. When bit 2 is set to [0] : the output current is set to 60 A ; when set to [1] , 280 A. Bit 3 (T2), Bit 4 (T1) and Bit 5 (T0) are used to set test mode. They are used to set the phase comparator reference signal output, and counter divider output. For details of test mode, see the test mode setting table. Bit 6 (RSa) and Bit 7 (RSb) are used to set the X'tal reference frequency divider ratio. For details of the X'tal reference frequency divider ratios, see the table for X'tal reference frequency divider ratios. Bit 8 (OS) is used to set the charge-pump drive amplifier output setting. When bit 8 is set to [0] the output is ON (Normal Use) ; when set to [1] the output is OFF (Tr. Output is Low Level). Byte 5 is used to set and control the output port (Bands 1~4). When an output port set to [0] is OFF ; when set to [1] is ON. Two output ports can be operation turned on, but be sure to keep the total output current under 50mA.
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b) READ mode (status request)
When READ mode is set, power-on reset operation status, phase comparator lock detector output status, and 5-level A / D converter pin input voltage status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply of VCC1 stops, bit 1 is set to [1] . The condition for reset to [0] , voltage supplied to VCC1 is 3 V or higher, transmission is requested in READ mode, and the status is output. (when VCC1 is turned on, bit 1 is also set to [1] .) Bit 2 (FL) indicates the phase comparator lock status. When locked, [1] is output ; when unlocked, [0] is output. Bits 6, 7 and 8 (A2, A1, A0) indicate the 5-level A / D converter status. The voltage applied to the A / D converter input pin (pin 12) is output through a 5-level resolution. For the voltage applied on the A / D converter input pin, 5-level resolution, and the output bits, see the table. (Ex : The AFT output voltage data can be given to the master device.)
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DATA FORMAT
a) WRITE MODE
BYTE 1 2 3 4 5 Address Byte Divider Byte (1) Divider Byte (2) Control Byte Band SW Byte MSB 1 0 N7 1 x 1 N14 N6 CP x 0 N13 N5 T2 x 0 N12 N4 T1 x 0 N11 N3 T0 B4 MA1 N10 N2 RSa B3 MA0 N9 N1 RSb B2 LSB R / W=0 N8 N0 OS B1 ACK ACK ACK (L) ACK (L) ACK (L)
x ACK (L)
: : :
DON'T Care Acknowledged Latch and transfer timing
b) READ MODE
BYTE 1 2 Address Byte Status Byte MSB 1 POR 1 FL 0 1 0 1 0 1 MA1 A2 MA0 A1 LSB R/W=1 A0 ACK
ACK
:
Acknowledged
DATA SPECIFICATIONS
l MA1, MA0 : Programmable hardware address bits
ADDRESS PIN APPLIED VOLTAGE 0~0.1 VCC1 0.4 VCC1~0.6 VCC1 0~VCC1 0.9 VCC1~VCC1 MA1 0 1 0 1 MA0 0 0 1 1
l CP : Charge-pump output current setting [0] : 60 A (Typ.) [1] : 280 A (Typ.)
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l T2, T1, T0 : Test mode setting
CHARACTERISTIC Normal operation Reference signal output 1 / 2 counter divider output Phase comparator test T2 0 1 1 0 T1 0 0 0 0 T0 1 0 1 0 Reference signal output NOTE : B4, Counter output : B2
Reference signal output : B4, 1 / 2 counter output : B2 Comparative signal input : SDA Reference signal input : SCL (check output : NF)
Note:
When testing the counter divider output, programmable counter data input is necessary.
l RSa, RSb : X'tal reference frequency divider ratio select bits
RSa 1 0 X RSb 1 1 0 DIVIDER RATIO 1 / 64 1 / 128 1 / 80 STEP FREQUENCY 62.5 k 31.25 k 50.0 k
X : Don't care l OS : Tuning amplifier control setting [0] : Tuning amp ON (Normal operation) [1] : Tuning amp OFF (Tr. Output is Low Level) l POR : Power-on reset flag [0] : Normal operation [1] : Reset operation l FL : Lock detect flag [0] : Unlocked [1] : Locked
l A2, A1, A0 : 5-level A / D converter status.
ADC PIN APPLIED VOLTAGE 0.60 VCC1~VCC1 0.45 VCC1~0.60 VCC1 0.30 VCC1~0.45 VCC1 0.15 VCC1~0.30 VCC1 0~0.15 VCC1 A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0
*:
Accuracy is 0.03 x VCC1
l X : DON'T Care
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I C BUS CONTROL SUMMARY
The bus control format of TD7624AFN conforms to the Philips I2C bus control format.
2
Data transmission format
(1) Start / Stop condition
(2) Bit transfer
(3) Acknowledge
(4) Slave address
A6 1 A5 1 A4 0 A3 0 A2 0 A1 * A0 *
R/W
0
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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TEST CIRCUIT 1
Evaluation circuit board
TEST CIRCUIT 2
Input sensitivity test circuit Test mode circuit
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TEST CIRCUIT 3
Bandswitch drive test circuit
SYSTEM APPLICATION DIAGRAM
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TYPICAL INPUT SENSITIVITY CURVE
FILTER COMPONENT EXPRESSION
C1 R1 C2 with Kv Icomp n N fc = [Kv * Icomp/(2)] / (n2 * N) = [2 * ] / (n * C1) = 1 / (2 * fc *R1) : = Oscillator control sensitivity (radian / Second / Volts) = Charge-pump current (A) = Natural radian frequency (radian / Second) = Total counter ratio = Dumping-factor (generally : dumping-factor is about 0.5~1.0) = filter cut-off frequency with combination resistor R1. (generally : fc is about fr (reference frequency) / 20)
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HANDLING PRECAUTIONS
1. The device should not be inserted into or removed from the test jig while the voltage is being applied: otherwise the device may be degraded or break down. Do not abruptly increase or decrease the power supply to the device either. (See Figure 1.) Overshoot or chattering of the power supply may cause the IC to be degraded. To avoid this filters should be incorporated on the power supply line.
2.
The peripheral circuits described in this datasheet are given only as system examples for evaluating the device's performance. Toshiba intend neither to recommend the configuration or related values of the peripheral circuits nor to manufacture such application systems in large quantities. Please note that high-frequency characteristics of the device may vary depending on the external components, mounting method and other factors relating to the application design. Therefore, the characteristics of application circuits must be evaluated at the responsibility of the users incorporating the device into their design. Toshiba only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customers application design. In order to better understand the quality and reliability of Toshiba semiconductor products and to incorporate them into design in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (Integrated Circuits) published by Toshiba Semiconductor Company. The handbook can also be viewed online at http://doc.semicon.toshiba.co.jp/noseek/us/sinrai/sinraifm.htm.
3.
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PACKAGE DIMENSIONS
Weight: 0.07 g (Typ.)
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