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Freescale Semiconductor, Inc.
HC05L5GRS/D REV. 2.0
Freescale Semiconductor, Inc...
General Release Specification
July 9, 1998 NON-DISCLOSURE
For More Information On This Product, Go to: www.freescale.com
AGREEMENT
68HC05L5 68HC705L5
REQUIRED
Freescale Semiconductor, Inc. General Release Specification REQUIRED
Freescale Semiconductor, Inc...
AGREEMENT
NON-DISCLOSURE
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
(c) Motorola, Inc., 1998 General Release Specification 2 For More Information On This Product, Go to: www.freescale.com MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 19
Freescale Semiconductor, Inc...
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 33 Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 51 Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 57 Section 5. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . 69 Section 6. Parallel Input/Output (I/O) . . . . . . . . . . . . . . 73 Section 7. Oscillators/Clock Distributions . . . . . . . . . . . 87 Section 8. Simple Serial Peripheral Interface (SSPI). . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Section 9. Timer System . . . . . . . . . . . . . . . . . . . . . . . . 115 Section 10. LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Section 11. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 149 Section 12. Electrical Specifications . . . . . . . . . . . . . . 167 Section 13. Mechanical Specifications . . . . . . . . . . . . 175 Section 14. Ordering Information . . . . . . . . . . . . . . . . . 177 Appendix A. MC68HC705L5 . . . . . . . . . . . . . . . . . . . . 181 AGREEMENT NON-DISCLOSURE
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA List of Sections For More Information On This Product, Go to: www.freescale.com
General Release Specification 3
REQUIRED
Freescale Semiconductor, Inc. List of Sections REQUIRED NON-DISCLOSURE
General Release Specification 4 List of Sections For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc...
AGREEMENT
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4 MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.6.2 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.6.2.1 Crystal or Ceramic Resonator . . . . . . . . . . . . . . . . . . . . .25 1.6.2.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.6.3 XOSC1 and XOSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.6.3.1 Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.6.3.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.6.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.6.5 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.6.6 Port B (PB0-PB7/KWI0-KWI7). . . . . . . . . . . . . . . . . . . . . .28 1.6.7 Port C (PC0/SDI, PC1/SDO, PC2/SCK, PC3/TCAP, PC4/EVI, PC5/EVO, PC6/IRQ2, and PC7/IRQ1) . . . . . .28 1.6.8 Port D (PD1-PD3/BP1-BP3, and PD4-PD7/FP34-FP27) . . . . . . . . . . . . . . . . . . . . . .29 1.6.9 Port E (PE0-PE7/FP38-FP35) . . . . . . . . . . . . . . . . . . . . . .29 1.6.10 VLCD1, VLCD2, and VLCD3. . . . . . . . . . . . . . . . . . . . . . . .29 1.6.11 NDLY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.7.1 Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.7.2 Single-Chip Mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.7.3 Self-Check Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Freescale Semiconductor, Inc...
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com
General Release Specification 5
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 2. Memory Map
2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.6 2.7 2.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . .35 Read/Write Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Read-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Write-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reserved Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reset Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Option Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Summary of Internal Registers and I/O Map . . . . . . . . . . . . . .37 Option Map for I/O Configurations . . . . . . . . . . . . . . . . . . . . . .43 Resistor Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . .45 Resistor Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . .46 Open-Drain Output Control Register 1 . . . . . . . . . . . . . . . .46 Open-Drain Output Control Register 2 . . . . . . . . . . . . . . . .48 Key Wakeup Input Enable Register . . . . . . . . . . . . . . . . . .48 Mask Option Status Register . . . . . . . . . . . . . . . . . . . . . . .49 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Self-Check ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Mask ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
NON-DISCLOSURE
Freescale Semiconductor, Inc...
AGREEMENT
Section 3. Central Processor Unit (CPU)
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
General Release Specification 6 Table of Contents For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Table of Contents
Section 4. Resets and Interrupts
4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.4 4.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 IRQ1 and IRQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Key Wakeup Interrupt (KWI) . . . . . . . . . . . . . . . . . . . . . . . .59 IRQ (KWI) Software Consideration . . . . . . . . . . . . . . . . . . .60 Timer 1 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 SSPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Timebase Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .64 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Freescale Semiconductor, Inc...
Section 5. Low-Power Modes
5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Section 6. Parallel Input/Output (I/O)
6.1 6.2 6.3 6.3.1 6.3.2 6.4 6.5 6.5.1 6.5.2 6.6 6.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . .77 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Port C Data Direction Register . . . . . . . . . . . . . . . . . . . . . .82 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com
General Release Specification 7
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 7. Oscillators/Clock Distributions
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.3 OSC Clock Divider and POR Counter . . . . . . . . . . . . . . . . . . .88 7.4 System Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.5 OSC and XOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.5.1 OSC on Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.5.2 XOSC on Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 7.5.2.1 XOSC with FOSCE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . .91 7.5.2.2 XOSC with FOSCE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.5.2.3 XOSC with FOSCE = 0 and STOP . . . . . . . . . . . . . . . . .92 7.5.2.4 Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . .92 7.6 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.6.1 LCDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.6.2 STUP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.6.3 TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 7.6.4 COP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.6.5 Timebase Control Register 1 . . . . . . . . . . . . . . . . . . . .97 7.6.6 Timebase Control Register 2 . . . . . . . . . . . . . . . . . . . .98 7.6.7 Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Freescale Semiconductor, Inc...
AGREEMENT
NON-DISCLOSURE
Section 8. Simple Serial Peripheral Interface (SSPI)
8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Internal Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 SPDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 SPCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 SPSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 CLKGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 SSPI Data I/O (SDI and SDO). . . . . . . . . . . . . . . . . . . . . .107 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
General Release Specification 8 Table of Contents For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Table of Contents
8.7 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 8.7.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . .110 8.7.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . .112 8.7.3 Serial Peripheral Data Register . . . . . . . . . . . . . . . . . .113 8.8 Port Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Section 9. Timer System
9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Output Compare Register . . . . . . . . . . . . . . . . . . . . . . . . .119 Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Timer During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .123 Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .123 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . .128 Timer Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . .130 Output Compare Register 2 . . . . . . . . . . . . . . . . . . . .131 Timer Counter Register 2 . . . . . . . . . . . . . . . . . . . . . .131 Time Base Control Register 1 . . . . . . . . . . . . . . . . . . .132 Timer Input 2 (EVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Event Output (EVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Freescale Semiconductor, Inc...
Section 10. LCD Driver
10.1 10.2 10.3 10.4 10.5 10.6 10.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 LCD Waveform Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Backplane Driver and Port Selection . . . . . . . . . . . . . . . . . . .144 Frontplane Driver and Port Selection . . . . . . . . . . . . . . . . . . .145 LCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 LCD Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com
General Release Specification 9
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 11. Instruction Set
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 11.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 11.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .154 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .155 11.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .156 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .158 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 11.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Freescale Semiconductor, Inc...
AGREEMENT
NON-DISCLOSURE
Section 12. Electrical Specifications
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .169 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Recommended Operating Conditions . . . . . . . . . . . . . . . . .169 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .170 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .171 2.7-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .172 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Section 13. Mechanical Specifications
13.1 13.2 13.3
General Release Specification 10 Table of Contents For More Information On This Product, Go to: www.freescale.com
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Quad Flat Pack (QFP) -- Case 841B-01 . . . . . . . . . . . . . . . .176
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Table of Contents
Section 14. Ordering Information
14.1 14.2 14.3 14.4 14.5 14.6 14.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .178 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .179 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .180 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
Freescale Semiconductor, Inc...
A.1 A.2 A.3 A.4 A.5 A.6 A.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Differences between MC68HC05L5 and MC68HC705L5 . . .182 MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . .184 Programming Voltage (VPP) . . . . . . . . . . . . . . . . . . . . . . . . . .186
A.9
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
A.10 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 A.11 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 A.11.1 Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .189 A.11.2 Program Control Register . . . . . . . . . . . . . . . . . . . . . . . . .190 A.12 COP Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 A.13 LCD 1/2 Duty and 1/2 Bias Timing Diagram . . . . . . . . . . . . .192 A.14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 A.14.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 A.14.2 Operating Temperature Range . . . . . . . . . . . . . . . . . . . . .194 A.14.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .194
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com
General Release Specification 11
NON-DISCLOSURE
A.8 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 A.8.1 Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 A.8.2 Single-Chip Mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . .187 A.8.3 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
AGREEMENT
Appendix A. MC68HC705L5
REQUIRED
Freescale Semiconductor, Inc. Table of Contents REQUIRED
A.15 Recommended Operating Conditions . . . . . . . . . . . . . . . . .194 A.15.1 EPROM Programming Voltage . . . . . . . . . . . . . . . . . . .194 A.15.2 5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . .195 A.15.3 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . .196 A.15.4 3.3-Volt and 5.0-Volt Control Timing . . . . . . . . . . . . . . . .197 A.16 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
NON-DISCLOSURE
General Release Specification 12 Table of Contents For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc...
AGREEMENT
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
List of Figures
Figure 1-1 1-2 1-3 1-4 1-5 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 Title Page
Freescale Semiconductor, Inc...
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Timer 1 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 IRQ Timing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Software Patch for IRQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 IRQ1 and IRQ2 Block Diagram . . . . . . . . . . . . . . . . . . . . . .62 Key Wakeup Interrupt (KWI) . . . . . . . . . . . . . . . . . . . . . . . .63 Interrupt Control Register (INTCR). . . . . . . . . . . . . . . . . . . .64 Interrupt Status Register (INTSR) . . . . . . . . . . . . . . . . . . . .66
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA List of Figures For More Information On This Product, Go to: www.freescale.com
General Release Specification 13
NON-DISCLOSURE
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Register Description Key . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Main I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Option Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Resistor Control Register 1 (RCR1) . . . . . . . . . . . . . . . . . . .45 Resistor Control Register 2 (RCR2) . . . . . . . . . . . . . . . . . . .46 Open-Drain Output Control Register 1 (WOM1) . . . . . . . . .46 Open-Drain Output Control Register 2 (WOM2) . . . . . . . . .48 Key Wakeup Input Enable Register (KWIEN) . . . . . . . . . . .48 Mask Option Status Register (MOSR) . . . . . . . . . . . . . . . . .49
AGREEMENT
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Pin Assignment for Single-Chip Mode . . . . . . . . . . . . . . . . .23 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Mode Entry Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
REQUIRED
Freescale Semiconductor, Inc. List of Figures REQUIRED
Figure 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 7-1 7-2 7-3 7-4 7-5 7-6 7-7 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8
General Release Specification 14 List of Figures For More Information On This Product, Go to: www.freescale.com
Title
Page
Clock State and STOP Recovery/Power-On Reset Delay Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .71 Stop/Wait Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Port I/O Circuitry for One Bit. . . . . . . . . . . . . . . . . . . . . . . . .74 Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .76 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . .77 Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .78 Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . .81 Port C Data Direction Register (DDRC) . . . . . . . . . . . . . . . .82 Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . .84 Port E Data Register (PORTE). . . . . . . . . . . . . . . . . . . . . . .85 Clock Signal Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . .88 OSC1, OSC2, XOSC1, and XOSC2 Mask Options . . . . . . .90 Unused XOSC1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Timebase Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Timebase Control Register 1 (TBCR1) . . . . . . . . . . . . . . . .97 Timebase Control Register 2 (TBCR2) . . . . . . . . . . . . . . . .98 Miscellaneous Register (MISC) . . . . . . . . . . . . . . . . . . . . .100 SSPI Master-Slave Interconnection . . . . . . . . . . . . . . . . . .105 SSPI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 SSPI Clock-Data Timing Diagram . . . . . . . . . . . . . . . . . . .108 Serial Peripheral Control Register (SPCR) . . . . . . . . . . . .110 Serial Peripheral Status Register (SPSR) . . . . . . . . . . . . .112 Serial Peripheral Data Register (SPDR) . . . . . . . . . . . . . .113 Timer System Block Diagram . . . . . . . . . . . . . . . . . . . . . . .116 Timer 1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . .121 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . .122 Timer 2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Timer 2 Timing Diagram for f(PH2) > f(TIMCLK) . . . . . . . .126 Timer 2 Timing Diagram for f(PH2) = f(TIMCLK) . . . . . . . .127 Timer Control Register 2 (TCR2) . . . . . . . . . . . . . . . . . . . .128
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
NON-DISCLOSURE
Freescale Semiconductor, Inc...
AGREEMENT
Freescale Semiconductor, Inc.
List of Figures
Figure 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 10-1 10-2 10-3 10-4 10-5 10-6 12-1 A-2 A-3 A-4 A-5
Title
Page
Freescale Semiconductor, Inc...
LCD 1/1 Duty and 1/1 Bias Timing Diagram . . . . . . . . . . .140 LCD 1/2 Duty and 1/2 Bias Timing Diagram . . . . . . . . . . .141 LCD 1/3 Duty and 1/3 Bias Timing Diagram . . . . . . . . . . .142 LCD 1/4 Duty and 1/3 Bias Timing Diagram . . . . . . . . . . .143 LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . .146 LDC Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .174 Pin Assignments for Single-Chip Mode . . . . . . . . . . . . . . .184 Mode Entry Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 Program Control Register (PCR) . . . . . . . . . . . . . . . . . . . .190
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA List of Figures For More Information On This Product, Go to: www.freescale.com
General Release Specification 15
NON-DISCLOSURE
AGREEMENT
Timer Status Register 2 (TSR2) . . . . . . . . . . . . . . . . . . . . .130 Output Compare Register 2 (OC2). . . . . . . . . . . . . . . . . . .131 Timer Counter Register 2 (TCNT2) . . . . . . . . . . . . . . . . . .131 Time Base Control Register 1 (TBCR1) . . . . . . . . . . . . . . .132 EVI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 EVI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 EVO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 EVO Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Prescaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .137
REQUIRED
Freescale Semiconductor, Inc. List of Figures REQUIRED NON-DISCLOSURE
General Release Specification 16 List of Figures For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc...
AGREEMENT
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
List of Tables
Table 1-1 1-2 4-1 7-1 7-2 7-3 7-4 7-5 7-6 9-1 9-2 9-3 9-4 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 11-6 11-7 Title Page
Freescale Semiconductor, Inc...
Interrupt Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . .58 System Bus Clock Frequency Selection. . . . . . . . . . . . . . . . .89 Recovery Time Requirements . . . . . . . . . . . . . . . . . . . . . . . .93 Timebase Interrupt Frequency . . . . . . . . . . . . . . . . . . . . . . . .95 COP Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Timebase Interrupt Frequency . . . . . . . . . . . . . . . . . . . . . . . .99 System Bus Clock Frequency Selection. . . . . . . . . . . . . . . .101 EVI Modes Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Timebase Prescale Rate Selection . . . . . . . . . . . . . . . . . . .132 EVI Modes Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Timebase Prescale Rate Selection . . . . . . . . . . . . . . . . . . .137 Backplane and Port Selection . . . . . . . . . . . . . . . . . . . . . . .144 Frontplane and Port Selection . . . . . . . . . . . . . . . . . . . . . . .145 Frontplane Data Register Bit Usage. . . . . . . . . . . . . . . . . . .148 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .154 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .155 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .157 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .158 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA List of Tables For More Information On This Product, Go to: www.freescale.com
General Release Specification 17
NON-DISCLOSURE
AGREEMENT
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Mode Select Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
REQUIRED
Freescale Semiconductor, Inc. List of Tables REQUIRED
Table 14-1 A-1 A-2 A-3 A-4 Title Page
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Differences Between MC68HC05L5 and MC68HC705L5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Mode Select Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
NON-DISCLOSURE
General Release Specification 18 List of Tables For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc...
AGREEMENT
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Section 1. General Description
1.1 Contents
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4 MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.6.2 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.6.2.1 Crystal or Ceramic Resonator . . . . . . . . . . . . . . . . . . . . .25 1.6.2.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.6.3 XOSC1 and XOSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.6.3.1 Crystal or Ceramic Resonator . . . . . . . . . . . . . . . . . . . . .27 1.6.3.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.6.4 1.6.5 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.6.6 Port B (PB0-PB7/KWI0-KWI7). . . . . . . . . . . . . . . . . . . . . .28 1.6.7 Port C (PC0/SDI, PC1/SDO, PC2/SCK, PC3/TCAP, PC4/EVI, PC5/EVO, PC6/IRQ2, and PC7/IRQ1) . . . . . .28 1.6.8 Port D (PD1-PD3/BP1-BP3, and PD4-PD7/FP34-FP27) .29 1.6.9 Port E (PE0-PE7/FP38-FP35) . . . . . . . . . . . . . . . . . . . . . .29 1.6.10 VLCD1, VLCD2, and VLCD3. . . . . . . . . . . . . . . . . . . . . . . .29 1.6.11 NDLY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.7.1 Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.7.2 Single-Chip Mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.7.3 Self-Check Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA General Description For More Information On This Product, Go to: www.freescale.com
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Freescale Semiconductor, Inc. General Description REQUIRED 1.2 Introduction
The MC68HC05L5 is an 80-pin microcontroller unit (MCU) with highly sophisticated on-chip peripheral functions. The memory map includes 8 Kbytes of user ROM and 256 bytes of static RAM. The MCU has five parallel ports: A, B, C, D, and E. The MC68HC05L5 includes a timebase circuit, 8- and 16-bit timers, a computer operating properly (COP) watchdog timer, liquid crystal display (LCD) drivers, and a simple serial peripheral interface (SSPI).
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1.3 Features
Features of the MC68HC05L5 MCU include: * * * Low-cost HC05 core 8,208 bytes of user ROM and 256 bytes of user static RAM General-purpose data pins: - 14 bidirectional pins - 10 input/ouptut-only pins - 15 output-only pins, including 8-bit key wakeup interrupts Pullup resistors options Open-drain outputs options Two interrupt request (IRQ) inputs 16-bit timer with input capture and output compare (timer 1) 8-bit event counter/modulus clock divider (timer 2) Simple serial peripheral interface (SSPI) LCD drivers -- 1-to-4 backplane drivers x 27-to-39 frontplane drivers On-chip timebase circuits with COP watchdog timer and timebase interrupts Dual oscillators and selectable system clock frequency Power-saving stop mode and wait mode 80-pin quad flat pack (QFP) package
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* * * * * * * * * * *
General Release Specification 20
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General Description MCU Structure
1.4 MCU Structure
Figure 1-1 shows the structure of the MC68HC05L5 MCU.
OSC1 OSC2 XOSC1 XOSC2
OSC DIV SEL XOSC DATA A DIR REG PORT A /2 INTERNAL PROCESSOR CLOCK TIMEBASE SYSTEM KEY WAKEUP PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 DATA B DIR REG PORT B PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
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SRAM 256 BYTES
SPI
SELF-CHECK ROM 496 BYTES COP SYSTEM USER ROM 8028 BYTES
RESET
CPU CONTROL M68HC05 CPU
ALU
TIMER2
PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6/IRQ2 PC7/IRQ1
VDD VSS
CPU REGISTERS
ACCUMULATOR INDEX REGISTER
LCD DRIVERS
FP0-PF26
NDLY(1)
PROGRAM COUNTER CONDITION CODE REG
PORT E
STACK POINTER
FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 BP3/PD3 BP2/PD2 BP1/PD1 BP0
VLCD3 VLCD2 VLCD1
Note 1. The NDLY pin should be connected to VDD.
Figure 1-1. Block Diagram
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PORT D
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DATA C DIR REG
PORT C
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NOTE:
A line over a signal name indicates an active low signal. For example, RESET is active low.
1.5 Mask Options
The three mask options on the MC68HC05L5 are: 1. RSTR: RESET pin pullup resistor 2. OSCR: OSC feedback resistor 3. XOSCR: XOSC feedback/damping resistor See 2.5.6 Mask Option Status Register.
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General Description Functional Pin Description
1.6 Functional Pin Description
The MC68HC05L5 is available in an 80-pin QFP. The pin assignment is shown in Figure 1-2.
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80 VDD FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 VLCD3 VLCD2 VLCD1 VSS NDLY(1) XOSC1 XOSC2 RESET 1
61 60 VSS FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1/PD1 BP2/PD2 BP3/PD3 VDD PC7/IRQ1 PC6/IRQ2 PC5/EVO PC4/EVI PC3/TCAP PC2/SCK
20
21
40 41
Note 1. The NDLY pin should be connected to VDD.
Figure 1-2. Pin Assignment for Single-Chip Mode
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OSC1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO
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FP27/PE7 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8
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Table 1-1. Pin Configuration
Pin Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 17 47 1 60 16 21 22 18 19 15 14 13 48 49 50 51 SCM, Self-Check PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6/IRQ2 PC7/IRQ1 NDLY(1) VDD VDD VSS VSS OSC1 OSC2 XOSC1 XOSC2 VLCD1 VLCD2 VLCD3 BP3/PD3 BP2/PD2 BP1/PD1 BP0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I/O I/O I/O I/O I/O I/O I I I I I O O I O I O I I I O O O O Pin Number 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 SCM, Self-Check FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
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Note 1.The NDLY pin should be connected to VDD.
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General Description Functional Pin Description
1.6.1 VDD and VSS Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.
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1.6.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the 2-pin on-chip oscillator. The OSC1 and OSC2 pins can accept: * * A crystal as shown in Figure 1-3 (a) An external clock signal as shown in Figure 1-3 (b)
The frequency, fOSC, of the oscillator or external clock source is divided by 64 to produce the internal operating frequency, fOP, by default. 1.6.2.1 Crystal or Ceramic Resonator The circuit in Figure 1-3 (a) shows a typical 2-pin oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup feedback resistor of ROF between OSC1 and OSC2 may be selected as a mask option for MC68HC05L5. Typical ROF resistor value is 2 M.
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MCU MASK OPTIONS ROF MCU
OSC1 OSC2 4 MHz (TYP)
OSC1
OSC2
UNCONNECTED CO1 CO2 EXTERNAL CLOCK
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(a) Crystal Connections
(b) External Clock Source Connection
Figure 1-3. Oscillator Connections 1.6.2.2 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3. This configuration is possible regardless of how the oscillator is set up.
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1.6.3 XOSC1 and XOSC2 The XOSC1 and XOSC2 pins are the connections for the 2-pin on-chip oscillator. The XOSC1 and XOSC2 pins can accept: * * A crystal as shown in Figure 1-4 (a) An external clock signal as shown in Figure 1-4 (b)
The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP, if selected by SYS1-SYS0 bits. When XOSC is not used, the XOSC1 pin must be connected to the RESET pin to assure proper initialization of the clock circuitry. XOSC2 pin should remain unconnected.
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General Description Functional Pin Description
1.6.3.1 Crystal Resonator The circuit in Figure 1-4 (a) shows a typical 2-pin oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup feedback resistor of RXOF between XOSC1 and XOSC2 and a damping resistor of RXOD in series to XOSC2 may be selected as a mask option. Typical RXOF resistor value is 5.5 M, and RXOD resistor value is 320 k.
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MCU MASK OPTIONS RXOF MCU RXOD XOSC1 XOSC2 XOSC1 XOSC2
32.768 kHz (TYP)
CXO1
CXO2 EXTERNAL CLOCK
(a) Crystal Connections
(b) External Clock Source Connection
Figure 1-4. Oscillator Connections 1.6.3.2 External Clock An external clock from another CMOS-compatible device can be connected to the XOSC1 input, with the XOSC2 input not connected, as shown in Figure 1-4 (b). This configuration is possible regardless of how the oscillator is set up.
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UNCONNECTED
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1.6.4 RESET This pin can be used as an input to reset the MCU to a known startup state by pulling it to the low state. When power is removed, the RESET pin contains a steering diode to discharge any voltage on the pin to VDD. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. An internal RESET pin pullup resistor may be selected as a mask option. A typical pullup resistor value is 33 k.
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1.6.5 Port A (PA0-PA7) Port A is an 8-bit I/O port. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. Port A outputs may be configured as open-drain outputs and connected to a pullup resistor by software option.
1.6.6 Port B (PB0-PB7/KWI0-KWI7) Port B is an 8-bit input-only port that shares its lines with the key wakeup interrupt (KWI) system. Port B has a pullup option by software option.
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1.6.7 Port C (PC0/SDI, PC1/SDO, PC2/SCK, PC3/TCAP, PC4/EVI, PC5/EVO, PC6/IRQ2, and PC7/IRQ1) Port C is a 6-bit I/O port and 2-bit input-only port. The state of the PC0-PC5 pins are software programmable and all port C lines are configured as inputs during power-on or reset. All port C lines may connect to a pullup resistor by software option. * * * Bits PC0-PC2 are shared with the SSPI subsystem and may be configured as open-drain outputs. Bit 3 is shared with the TCAP pin of timer 1 and may be configured as an open-drain output. Bit 4 is shared with the EVI bit of timer 2 and may be configured as an open-drain output.
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General Description Functional Pin Description
* * *
Bit 5 is shared with the EVO bit of timer 2 and may be configured as an open-drain output. Bit 6 is shared with the IRQ2 input. This bit is an input-only pin. Bit 7 is shared with the IRQ1 input. This bit is an input-only pin.
1.6.8 Port D (PD1-PD3/BP1-BP3 and PD4-PD7/FP34-FP27) Port D is a 7-bit output-only port that shares its bits with the LCD backplane/frontplane drivers. Port D lines are configured as LCD outputs during power-on or reset. PD1-PD3 and PD4-PD7 outputs may be configured as open-drain outputs by a software option.
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1.6.9 Port E (PE0-PE7/FP38-FP35) Port E is an 8-bit output-only port that shares its bits with LCD frontplane drivers. Port E lines are configured as LCD outputs during power-on or reset. PE0-PE3 and PE4-PE7 outputs may be configured as opendrain outputs by a software option.
1.6.10 VLCD1, VLCD2, and VLCD3 These pins provide offset to the LCD driver bias for adjusting the contrast of the LCD.
1.6.11 NDLY This pin is reserved for factory test and should be connected to VDD in single-chip mode (user mode).
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Freescale Semiconductor, Inc. General Description REQUIRED 1.7 Modes of Operation
The MC68HC05L5 has two operating modes: * * Single-chip mode (SCM) Self-check mode
Single-chip mode, also called user mode, allows maximum use of pins for on-chip peripheral functions. The self-check capability of MC68HC05L5 provides an internal check to determine if the device is functional.
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1.7.1 Mode Entry Mode entry is done at the rising edge of the RESET pin. Once the device enters one of the modes, the mode cannot be changed by software. Only an external reset can change the mode. At the rising edge of the RESET pin, the device latches the states of IRQ1 and IRQ2 and places itself in the specified mode. While the RESET pin is low, all pins are configured as single-chip mode. Table 1-2 shows the states of IRQ1 and IRQ2 for each mode entry. High voltage VTST = 2 x VDD is required to select modes other than single-chip mode. Table 1-2. Mode Select Summary
Modes Single-chip (user) mode Self-check mode RESET PC6/IRQ1 VSS or VDD VTST PC7/IRQ2 VSS or VDD VDD
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General Description Modes of Operation
SINGLE-CHIP MODE RESET VDD VSS VTST IRQ1 VDD VSS
IRQ2
VDD VSS
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Figure 1-5. Mode Entry Diagram
1.7.2 Single-Chip Mode (SCM) In this mode, all address and data bus activity occurs within the MCU. Thus, no external pins are required for these functions. The single-chip mode allows the maximum number of I/O pins for on-chip peripheral functions, for example, ports A through E, and LCD drivers.
1.7.3 Self-Check Mode In this mode, the reset vector is fetched from a 496-byte internal selfcheck ROM at $3E00-$3FEF. The self-check ROM contains a selfcheck program to test the functions of internal modules. Since this mode is not a normal user mode, all of the privileged control bits are accessible. This allows the self-check mode to be used for selftest of the device.
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VTST = 2 x VDD
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General Release Specification -- MC68HC05L5
Section 2. Memory Map
2.1 Contents
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2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.6 2.7 2.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . .35 Read/Write Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Read-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Write-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Reserved Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reset Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Option Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Summary of Internal Registers and I/O Map . . . . . . . . . . . . . .37 Option Map for I/O Configurations . . . . . . . . . . . . . . . . . . . . . .43 Resistor Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . .45 Resistor Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . .46 Open-Drain Output Control Register 1 . . . . . . . . . . . . . . . .46 Open-Drain Output Control Register 2 . . . . . . . . . . . . . . . .48 Key Wakeup Input Enable Register . . . . . . . . . . . . . . . . . .48 Mask Option Status Register. . . . . . . . . . . . . . . . . . . . . . . .49 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Self-Check ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Mask ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
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Freescale Semiconductor, Inc. Memory Map REQUIRED 2.2 Introduction
The MC68HC05L5 contains an 8,192-byte mask ROM, 480 bytes of selfcheck ROM, and 256 bytes of RAM. An additional 16 bytes of mask ROM are provided for user vectors at $3FF0-$3FFF. The MCU's memory map is shown in Figure 2-1.
$0000
$0000 I/O 64 BYTES DUAL-MAPPED I/O REGISTERS 16 BYTES $000F $0010
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$003F $0040 SRAM 256 BYTES $00C0 $00FF $013F $0140 UNUSED $0FFF $1000 MASK ROM 8 KBYTES $2FFF $3000 UNUSED $3DFF $3E00 SELF-CHECK ROM 480 BYTES $3FDF $3FE0 $3FEF $3FF0 $3FFF $003F STACK 64 BYTES
I/O 48 BYTES
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TEST VECTORS USER VECTORS
Figure 2-1. Memory Map
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Memory Map Input/Output and Control Registers
2.3 Input/Output and Control Registers
The input/output (I/O) and control registers reside in locations $0000-$003F. A summary of these registers is shown in Figure 2-3. The bit assignments for each register are shown in Figure 2-4. Reading from unimplemented bits (denoted by shading) will return unknown states (unless explicitly defined to read 0), and writing to unimplemented bits will have no effect. See also Figure 2-2.
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Register Name (Full) Read
Read: FTUP Miscellaneous Register Write: (MISC) Reset: *
Bit Name (Mnemonic) Read-Only Bit
STUP * 0 0 0 0 SYS1 1 SYS0 0 FOSCE 1 OPTM 0
$003E
Write Register Name (Mnemonic)
Reset Value
Read/Write Bit
Figure 2-2. Register Description Key
2.3.1 Read/Write Bits Read/write bits are typically control bits. They are, in general, not modified by a module. Reset indicates the initial value of the latch.
2.3.2 Read-Only Bits Read-only bits are status flag bits. They are indicators of module status. Reset indicates the value that will be read immediately after system reset or before the module is enabled.
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Register Address (Main map unless otherwise specified)
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2.3.3 Write-Only Bits Write-only bits are control bits. They typically return a state of 0 to prevent an inadvertent write to this bit by a READ-MODIFY-WRITE instruction. Reset indicates the value that will be read immediately after system reset, which is the forced read value (typically 0).
2.3.4 Reserved Bits Reserved bits are read-only bits that typically read 0. Writes to these bits are ignored, and the user should not write 1 for future compatibility. Reset indicates the value that will be read immediately after system reset which is the forced read value (typically 0).
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2.3.5 Reset Value Values specified on the row marked Reset: are initial values of register bits after system reset. Those bits unaffected by reset are marked with the letter U. Those bits that are unaffected by reset but initialized by power-on reset are marked with an asterisk (*).
NON-DISCLOSURE
2.3.6 Option Map Address locations $0000-$000F are dual mapped. When the OPTM bit in the MISC register is cleared, the main address map is accessed. When the OPTM bit in the MISC register is set, the option address map is accessed.
NOTE:
Although not necessary for this device, for future compatibility the OPTM bit should be cleared when accessing memory locations $0010 and above.
General Release Specification 36 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Summary of Internal Registers and I/O Map
2.4 Summary of Internal Registers and I/O Map
Figure 2-3 contains a detailed memory map of the I/O registers.
Addr. $0000 Register Name Read: Port A Data Register Write: (PORTA) Reset: Read: Port B Data Register Write: (PORTB) Reset: Read: Port C Data Register Write: (PORTC) Reset: Read: Port D Data Register Write: (PORTD) Reset: Read: Port E Data Register Write: (PORTE) Reset: Reserved Reserved Reserved Bit 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0
Unaffected by reset PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
$0001
Freescale Semiconductor, Inc...
$0002
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Unaffected by reset PD7 1 PE7 1 R R R PD6 1 PE6 1 R R R IRQ2E 0 IRQ2F 0 PD5 1 PE5 1 R R R 0 0 0 0 PD4 1 PE4 1 R R R KWIE 0 KWIF 0 R PD3 1 PE3 1 R R R IRQ1S 0 0 RIRQ1 0 = Reserved PD2 1 PE2 1 R R R IRQ2S 0 0 RIRQ2 0 PD1 1 PE1 1 R R R 0 0 0 0 1 1 PE0 1 R R R 0 0 0 RKWIF 0
$0003
$0004
$0006 $0007
$0008
Read: IRQ1E Interrupt Control Register Write: (INTCR) Reset: 0 Read: Interrupt Status Register Write: (INTSR) Reset: IRQ1F 0
$0009
= Unimplemented
Figure 2-3. Main I/O Map (Sheet 1 of 6)
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
General Release Specification 37
NON-DISCLOSURE
$0005
AGREEMENT
Unaffected by reset
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED
Addr. $000A
Register Name Read: Serial Peripheral Control Write: Register (SPCR) Reset:
Bit 7 SPIE 0 SPIF 0 MSB
6 SPE 0 DCOL 0 BIT 6
5 DORD 0 0 0 BIT 5
4 MSTR 0 0 0 BIT 4
3 0 0 0 0 BIT 3
2 0 0 0 0 BIT 2
1 0 0 0 0 BIT 2
Bit 0 SPR 0 0 0 LSB
Read: Serial Peripheral Status Register $000B Write: (SPSR) Reset: Read: Serial Peripheral Data Register Write: (SPDR) Reset: Reserved Reserved Reserved
Freescale Semiconductor, Inc...
AGREEMENT
$000C
Unaffected by reset R R R R R R 0 0 TBIE 0 OC1IE 0 OC1F U BIT 14 R R R LCLK 0 TBR1 1 TOIE 0 TOF U BIT 13 R R R 0 0 TBR0 1 0 0 0 0 BIT 12 R R R 0 0 0 RTBIF 0 0 0 0 0 BIT 11 R R R 0 0 0 0 0 0 0 0 BIT 10 R R R T2R1 0 0 COPE 0 IEDG U 0 0 BIT 9 R R R T2R0 0 0 COPC 0 OLVL 0 0 0 BIT 8
$000D $000E $000F
$0010
Read: TBCLK Timer Base Control Register 1 Write: (TBCR1) Reset: 0 Read: Timer Base Control Register 2 Write: (TBCR2) Reset: Read: Timer Control Register Write: (TCR) Reset: Read: Timer Status Register Write: (TSR) Reset: Read: Input Capture Register High Write: (ICH) Reset: TBIF 0 ICIE 0 ICF U BIT 15
NON-DISCLOSURE
$0011
$0012
$0013
$0014
Unaffected by reset = Unimplemented R = Reserved U = Unaffected
Figure 2-3. Main I/O Map (Sheet 2 of 6)
General Release Specification 38 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Summary of Internal Registers and I/O Map
Addr. $0015
Register Name Read: Input Capture Register Low Write: (ICL) Reset:
Bit 7 BIT 7
6 BIT 6
5 BIT 5
4 BIT 4
3 BIT 3
2 BIT 2
1 BIT 1
Bit 0 BIT 0
Unaffected by reset BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
Read: Output Compare Register 1 High $0016 Write: (OC1H) Reset: Read: Output Compare Register 1 Low $0017 Write: (OC1L) Reset: Read: Timer Counter Register High Write: (TCNTH) Reset: Read: Timer Counter Register Low Write: (TCNTL) Reset: Read: Alternate Timer Counter Write: Register High (ACNTH) Reset: Read: Alternate Timer Counter Write: Register Low (ACMTL) Reset: Read: Timer Control Register 2 Write: (TCR2) Reset: Read: Timer Status Register 2 Write: (TSR2) Reset: Read: Output Compare Register 2 Write: (OC2) Reset:
Unaffected by reset BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Freescale Semiconductor, Inc...
Unaffected by reset BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
$0018
Unaffected by reset BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$0019
Unaffected by reset BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
$001A
Unaffected by reset BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$001B
Unaffected by reset TI2IE 0 TI2F 0 BIT 7 0 OC2IE 0 OC2F 0 BIT 6 0 0 0 0 0 BIT 5 0 T2CLK 0 0 0 BIT 4 0 IM2 0 0 RTI2F 0 BIT 3 0 IL2 0 0 ROC2F 0 BIT 2 0 OE2 0 0 0 BIT 1 0 OL2 0 0 0 BIT 0 0
$001C
$001D
$001E
= Unimplemented
Figure 2-3. Main I/O Map (Sheet 3 of 6)
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com General Release Specification 39
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED
Addr. $001F
Register Name Read: Timer Counter Register 2 Write: (TCNT2) Reset: Read: LCD Control Register Write: (LCDCR) Reset: Read: LCD Data Register 1 Write: (LCDR1) Reset: Read: LCD Data Register 2 Write: (LCDR2) Reset: Read: LCD Data Register 3 Write: (LCDR3) Reset: Read: LCD Data Register 4 Write: (LCDR4) Reset: Read: LCD Data Register 5 Write: (LCDR5) Reset: Read: LCD Data Register 6 Write: (LCDR6) Reset: Read: LCD Data Register 7 Write: (LCDR7) Reset:
Bit 7 BIT 7 0 LCDE 0 F1B3
6 BIT 6 0 DUTY1 0 F1B2
5 BIT 5 0 DUTY0 0 F1B1
4 BIT 4 0 0 0 F1B0
3 BIT 3 0 PEH 0 F0B3
2 BIT 2 0 PEL 0 F0B2
1 BIT 1 0 PDH 0 F0B1
Bit 0 BIT 0 1 0 0 F0B0
$0020
Freescale Semiconductor, Inc...
AGREEMENT
$0021
Unaffected by reset F3B3 F3B2 F3B1 F3B0 F2B3 F2B2 F2B1 F2B0
$0022
Unaffected by reset F5B3 F5B2 F5B1 F5B0 F4B3 F4B2 F4B1 F4B0
$0023
Unaffected by reset F7B3 F7B2 F7B1 F7B0 F6B3 F6B2 F6B1 F6B0
$0024
NON-DISCLOSURE
Unaffected by reset F9B3 F9B2 F9B1 F9B0 F8B3 F8B2 F8B1 F8B0
$0025
Unaffected by reset F11B3 F11B2 F11B1 F11B0 F10B3 F10B2 F10B1 F10B0
$0026
Unaffected by reset F13B3 F13B2 F13B1 F13B0 F12B3 F12B2 F12B1 F12B0
$0027
Unaffected by reset
Figure 2-3. Main I/O Map (Sheet 4 of 6)
General Release Specification 40 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Summary of Internal Registers and I/O Map
Addr. $0028
Register Name Read: LCD Data Register 8 Write: (LCDR8) Reset: Read: LCD Data Register 9 Write: (LCDR9) Reset: Read: LCD Data Register 10 Write: (LCDR10) Reset: Read: LCD Data Register 11 Write: (LCDR11) Reset: Read: LCD Data Register 12 Write: (LCDR12) Reset: Read: LCD Data Register 13 Write: (LCDR13) Reset: Read: LCD Data Register 14 Write: (LCDR14) Reset: Read: LCD Data Register 15 Write: (LCDR15) Reset: Read: LCD Data Register 16 Write: (LCDR16) Reset:
Bit 7 F15B3
6 F15B2
5 F15B1
4 F15B0
3 F14B3
2 F14B2
1 F14B1
Bit 0 F14B0
Unaffected by reset F17B3 F17B2 F17B1 F17B0 F16B3 F16B2 F16B1 F16B0
$0029
Unaffected by reset F19B3 F19B2 F19B1 F19B0 F18B3 F18B2 F18B1 F18B0
Freescale Semiconductor, Inc...
$002A
Unaffected by reset F21B3 F21B2 F21B1 F21B0 F20B3 F20B2 F20B1 F20B0
$002B
Unaffected by reset F23B3 F23B2 F23B1 F23B0 F22B3 F22B2 F22B1 F22B0
$002C
Unaffected by reset F25B3 F25B2 F25B1 F25B0 F24B3 F24B2 F24B1 F24B0
$002D
$002E
F27B3
F27B2
F27B1
F27B0
F26B3
F26B2
F26B1
F26B0
Unaffected by reset F29B3 F29B2 F29B1 F29B0 F28B3 F28B2 F28B1 F28B0
$002F
Unaffected by reset F31B3 F31B2 F31B1 F31B0 F30B3 F30B2 F30B1 F30B0
$0030
Unaffected by reset
Figure 2-3. Main I/O Map (Sheet 5 of 6)
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
General Release Specification 41
NON-DISCLOSURE
Unaffected by reset
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED
Addr. $0031
Register Name Read: LCD Data Register 17 Write: (LCDR17) Reset: Read: LCD Data Register 18 Write: (LCDR18) Reset: Read: LCD Data Register 19 Write: (LCDR19) Reset: Read: LCD Data Register 20 Write: (LCDR20) Reset: Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read: Miscellaneous Register Write: (MISC) Reset: Reserved
Bit 7 F33B3
6 F33B2
5 F33B1
4 F33B0
3 F32B3
2 F32B2
1 F32B1
Bit 0 F32B0
Unaffected by reset F35B3 F35B2 F35B1 F35B0 F34B3 F34B2 F34B1 F34B0
$0032
Unaffected by reset F37B3 F37B2 F37B1 F37B0 F36B3 F36B2 F36B1 F36B0
Freescale Semiconductor, Inc...
AGREEMENT
$0033
Unaffected by reset 0 0 0 0 F38B3 F38B2 F38B1 F38B0
$0034
Unaffected by reset R R R R R R R R R FTUP * R R R R R R R R R R STUP * R R R R R R R R R R 0 0 R R R R R R R R R R 0 0 R R R R R R R R R R R SYS1 1 R = Reserved R R R R R R R R R SYS0 0 R R R R R R R R R R FOSCE 1 R R R R R R R R R R OPTM 0 R
$0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D
NON-DISCLOSURE
$003E
$003F
* Unaffected by reset but initialized by power-on reset
= Unimplemented
Figure 2-3. Main I/O Map (Sheet 6 of 6)
General Release Specification 42 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Option Map for I/O Configurations
2.5 Option Map for I/O Configurations
Most of the I/O configurations are done in the option map (Figure 2-4). Some options still remain as mask options for the MC68HC05L5 such as a pullup resistor for the RESET pin and resistors for the OSC1/OSC2 and XOSC1/XOSC2 pins. These mask options may be read by the MOSR ($000F) in the option map. The option map is located at $0000-$000F of the main memory map and it is available when the OPTM bit in the MISC register ($003E) is set. Main registers at $0000-$000F are not available when OPTM = 1. I/O port data direction registers are contained in the option map in Figure 2-4.
Addr. $0000 Bit 7 Read: DDRA7 Port A Data Direction Register Write: (DDRA) Reset: 0 Reserved Read: Port C Data Direction Register Write: (DDRC) Reset: Reserved Reserved Reserved Reserved Reserved Read: Resistor Control Register 1 Write: (RCR1) Reset: R 0 0 R R R R R 0 0 R Register Name 6 DDRA6 0 R 0 0 R R R R R 0 0 = Reserved 5 DDRA5 0 R DDRC5 0 R R R R R 0 0 4 DDRA4 0 R DDRC4 0 R R R R R 0 0 3 DDRA3 0 R DDRC3 0 R R R R R RBH 0 2 DDRA2 0 R DDRC2 0 R R R R R RBL 0 1 DDRA1 0 R DDRC1 0 R R R R R RAH 0 Bit 0 DDRA0 0 R DDRC0 0 R R R R R RAL 0
Freescale Semiconductor, Inc...
$0001
$0002
$0003 $0004 $0005 $0006 $0007
$0008
Figure 2-4. Option Map (Sheet 1 of 2)
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com General Release Specification 43
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED
Addr. $0009
Register Name Read: Resistor Control Register 2 Write: (RCR2) Reset:
Bit 7 RC7 0
6 RC6 0
5 RC5 0
4 RC4 0
3 RC3 0 0 0
2 RC2 0 0 0
1 RC1 0
Bit 0 RC0 0
$000A
Read: DWOMH DWOML EWOMH EWOML Open-Drain Output Control Write: Register 1 (WOM1) Reset: 0 0 0 0 Read: Open-Drain Output Control Write: Register 2 (WOM2) Reset: Reserved Reserved 0 0 R R 0 0 R R KWIE6 0 OSCR U
AWOMH AWOML 0 0
Freescale Semiconductor, Inc...
AGREEMENT
$000B
CWOM5 CWOM4 CWOM3 CWOM2 CWOM1 CWOM0 0 R R KWIE5 0 XOSCR U 0 R R KWIE4 0 0 0 R 0 R R KWIE3 0 0 0 = Reserved 0 R R KWIE2 0 0 0 0 R R KWIE1 0 0 0 U = Unaffected 0 R R KWIE0 0 0 0
$000C $000D
$000E
Read: KWIE7 Key Wakeup Input Enable Write: Register (KWIEN) Reset: 0 Read: Mask Option Status Register Write: Reset: RSTR U
$000F
NON-DISCLOSURE
= Unimplemented
Figure 2-4. Option Map (Sheet 2 of 2)
General Release Specification 44 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Option Map for I/O Configurations
2.5.1 Resistor Control Register 1
Address: Option Map -- $0008 Bit 7 Read: 0 Write: Reset: 0 0 0 0 0 0 0 0 0 0 0 RBH RBL RAH RAL 6 5 4 3 2 1 Bit 0
Figure 2-5. Resistor Control Register 1 (RCR1)
Freescale Semiconductor, Inc...
Bits 7-4 -- Reserved These bits are not used and always read as logic 0. RBH -- Port B Pullup Resistor (H) When this bit is set, pullup resistors are connected to the upper four bits of port B. This bit is cleared on reset. RBL -- Port B Pullup Resistor (L) When this bit is set, pullup resistors are connected to the lower four bits of port B. This bit is cleared on reset. RAH -- Port A Pullup Resistor (H) When this bit is set, pullup resistors are connected to the upper four bits of port A. This bit is cleared on reset. RAL -- Port A Pullup Resistor (L) When this bit is set, pullup resistors are connected to the lower four bits of port A. This bit is cleared on reset.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
General Release Specification 45
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED
2.5.2 Resistor Control Register 2
Address: Option Map -- $0009 Bit 7 Read: RC7 Write: Reset: 0 0 0 0 0 0 0 0 RC6 RC5 RC4 RC3 RC1 RC1 RC0 6 5 4 3 2 1 Bit 0
Figure 2-6. Resistor Control Register 2 (RCR2)
Freescale Semiconductor, Inc...
AGREEMENT
RCx -- Port C Pullup Resistor (Bitx) When RCx bit is set, the pullup resistor is connected to the corresponding bit of port C. This bit is cleared on reset.
2.5.3 Open-Drain Output Control Register 1
Address: Option Map -- $000A Bit 7 Read: DWOMH Write: Reset: 0 0 0 0 0 0 0 0 DWOML EWOMH EWOML 0 0 AWOMH AWOML 6 5 4 3 2 1 Bit 0
NON-DISCLOSURE
Figure 2-7. Open-Drain Output Control Register 1 (WOM1) DWOMH -- Port D Open-Drain Mode (H) When this bit is set, the upper four bits of port D are configured as open-drain outputs if these bits are selected as port D output by the PDH bit in the LCDCR. This bit is cleared on reset. DWOML -- Port D Open-Drain Mode (L) When this bit is set, the lower three bits of port D are configured as open-drain outputs if the corresponding BPx pin is not used by the LCD driver. This bit is cleared on reset.
General Release Specification 46 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Option Map for I/O Configurations
EWOMH -- Port E Open-Drain Mode (H) When this bit is set, the upper four bits of port E (that are configured as I/O output by the PEH bit in the LCDCR) are configured as opendrain outputs. This bit is cleared on reset. EWOML -- Port E Open-Drain Mode (L) When this bit is set, the lower four bits of port E (that are configured as I/O output by the PEL bit in the LCDCR) are configured as opendrain outputs. This bit is cleared on reset.
Freescale Semiconductor, Inc...
Bits 3 and 2 -- Reserved These bits are not used and always return to logic 0. AWOMH -- Port A Open-Drain Mode (H) When this bit is set, the upper four bits of port A that are configured as output (corresponding to the DDRA bit set) become open-drain outputs. This bit is cleared on reset. AWOML -- Port E Open-Drain Mode (L) When this bit is set, the lower four bits of port A that are configured as output (corresponding DDRA bit set) become open-drain outputs. This bit is cleared on reset.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
General Release Specification 47
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED
2.5.4 Open-Drain Output Control Register 2
Address: Option Map -- $000B Bit 7 Read: 0 Write: Reset: 0 0 0 0 0 0 0 0 0 CWOM5 CWOM4 CWOM3 CWOM2 CWOM1 CWOM0 6 5 4 3 2 1 Bit 0
Figure 2-8. Open-Drain Output Control Register 2 (WOM2)
Freescale Semiconductor, Inc...
AGREEMENT
Bits 7 and 6 -- Reserved These bits are not used and always read as logic 0. CWOMx -- Port C Open-Drain Mode (Bitx) When CWOMx bit is set, port C bits x are configured as open-drain outputs if DDRCx is set. This bit is cleared on reset.
2.5.5 Key Wakeup Input Enable Register
Address: Option Map -- $000E Bit 7 Read: KWIE7 Write: Reset: 0 0 0 0 0 0 0 0 KWIE6 KWIE5 KWIE4 KWIE3 KWIE2 KWIE1 KWIE0 6 5 4 3 2 1 Bit 0
NON-DISCLOSURE
Figure 2-9. Key Wakeup Input Enable Register (KWIEN) KWIEx -- Key Wakeup Input Enable (Bitx) When KWIEx bit is set, the KWIx (PBx) input is enabled for key wakeup interrupt. This bit is cleared on reset.
General Release Specification 48 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Memory Map Option Map for I/O Configurations
2.5.6 Mask Option Status Register The mask option status register (MOSR) indicates the state of mask options specified prior to production of the MC68HC05L5.
Address: Option Map -- $000F Bit 7 Read: Write: RSTR 6 OSCR 5 XOSCR 4 0 3 0 2 0 1 0 Bit 0 0
Freescale Semiconductor, Inc...
Reset:
U
U
U
0 U = Unaffected
0
0
0
0
= Unimplemented
Figure 2-10. Mask Option Status Register (MOSR) RSTR -- RESET Pin Pullup Resistor When this bit is set, it indicates an internal pullup resistor is attached to the RESET pin by mask option. OSCR -- OSC Feedback Resistor When this bit is set, it indicates that an internal feedback resistor is attached between OSC1 and OSC2 by mask option. XOSCR -- OSC Feedback Resistor When this bit is set, it indicates that an internal feedback resistor is attached between XOSC1 and XOSC2. The damping resistor at the XOSC2 pin is attached by mask option. Bits 4-0 -- Reserved These bits are not used and always read as logic 0.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Memory Map For More Information On This Product, Go to: www.freescale.com
General Release Specification 49
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED 2.6 RAM
The 256-byte internal RAM is positioned at $0040-$013F in the memory map. The lower 192 bytes are positioned in the page zero which are accessible by the direct addressing mode. The upper 64 bytes of this area (page zero) are used for the CPU stack area. Care should be taken if the stack area is used for data storage. The remaining 64 byte of RAM at $0100-$013F are accessed by extended addressing mode. The RAM is implemented with static cells and retains its contents during the stop and wait modes.
Freescale Semiconductor, Inc...
AGREEMENT
2.7 Self-Check ROM
Self-check ROM is 480 bytes of mask ROM positioned at $3E00-$3FDF. This ROM contains self-check programs and reset/interrupt vectors in the self-check mode.
2.8 Mask ROM
The 8,192-byte user ROM is positioned at $1000-$2FFF, and an additional 16 bytes of ROM are located at $3FF0-$3FFF for user vectors.
NON-DISCLOSURE
General Release Specification 50 Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Section 3. Central Processor Unit (CPU)
3.1 Contents
Freescale Semiconductor, Inc...
3.2 Introduction
This section describes the central processor unit (CPU).
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
General Release Specification 51
NON-DISCLOSURE
AGREEMENT
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
REQUIRED
Freescale Semiconductor, Inc. Central Processor Unit (CPU) REQUIRED 3.3 CPU Registers
The MCU contains five registers as shown in Figure 3-1. The interrupt stacking order is shown in Figure 3-2.
7 A 7 X
0 ACCUMULATOR 0 INDEX REGISTER 0
AGREEMENT
Freescale Semiconductor, Inc...
13 PC 13 0 0 0 0 0 0 7 1
PROGRAM COUNTER 0 1 SP CCR H I N Z C CONDITION CODE REGISTER STACK POINTER
Figure 3-1. Programming Model
7 1 1 1 CONDITION CODE REGISTER 0 STACK I N T E R R U P T
NON-DISCLOSURE
INCREASING MEMORY ADDRESSES
R E T U R N
ACCUMULATOR INDEX REGISTER PCH PCL
DECREASING MEMORY ADDRESSES
UNSTACK NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order.
Figure 3-2. Stacking Order
General Release Specification 52 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Central Processor Unit (CPU) Accumulator
3.4 Accumulator
The accumulator (A) is a general-purpose, 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.
7 A 0
3.5 Index Register
Freescale Semiconductor, Inc...
The index register (X) is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area.
7 X 0
3.6 Condition Code Register
The condition code register (CCR) is a 5-bit register in which the H, N, Z, and C bits are used to indicate the results of the instruction just executed, and the I bit is used to enable or disable interrupts. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs.
CCR H I N Z C
Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the I bit is cleared.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com General Release Specification 53
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Central Processor Unit (CPU) REQUIRED
Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was 0. Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. This bit is affected also during bit test and branch instructions and during shifts and rotates.
Freescale Semiconductor, Inc...
AGREEMENT
3.7 Stack Pointer
The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the eight most significant bits are permanently set to 00000011. These eight 0 bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
13 0 0 0 0 0 0 7 1 1 SP 0
NON-DISCLOSURE
General Release Specification 54 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Central Processor Unit (CPU) Program Counter
3.8 Program Counter
The program counter (PC) is a 14-bit register that contains the address of the next byte to be fetched.
13 PC 0
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3.9 Arithmetic Logic Unit
The arithmetic logic unit (ALU) performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal processor cycles to complete this chain of operations.
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General Release Specification 55
NON-DISCLOSURE
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REQUIRED
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General Release Specification 56 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
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AGREEMENT
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
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General Release Specification -- MC68HC05L5
Section 4. Resets and Interrupts
4.1 Contents
Freescale Semiconductor, Inc...
In user operating modes, the reset/interrupt vectors are located at the top of the address space ($3FF0-$3FFF). In self-check mode, the reset/interrupt vectors are located at $3FE0-$3FEF in the internal selfcheck ROM. Descriptions in this section assume a user operating mode is in use. Table 4-1 shows the address assignments for the vectors.
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General Release Specification 57
NON-DISCLOSURE
4.2 Introduction
AGREEMENT
4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.4 4.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 IRQ1 and IRQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Key Wakeup Interrupt (KWI) . . . . . . . . . . . . . . . . . . . . . . . .59 IRQ (KWI) Software Consideration . . . . . . . . . . . . . . . . . . .60 Timer 1 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 SSPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Timebase Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
REQUIRED
Freescale Semiconductor, Inc. Resets and Interrupts REQUIRED
Table 4-1. Interrupt Vector Assignments
Vector Address 3FF0-3FF1 3FF2-3FF3 3FF4-3FF5 Interrupt Source Timebase SSPI Timer 2 TI2I OC2I ICI OC1I TOI Masked by I bit I bit I bit I bit I bit I bit I bit I bit IRQ1 IRQ2 I bit I bit None COP RESET pin Power-on None None None Local Mask TBIE SPIE TI2IE OC2IE ICIE OC1IE TOIE KWIE IRQ1E IRQ2E None COPE None None Priority (1 = Highest) 7 6 5 5 4 4 4 3 2 2 Same level as an instruction 1 1 1
3FF6-3FF7
Timer 1 KWI IRQ SWI
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AGREEMENT
3FF8-3FF9 3FFA-3FFB 3FFC-3FFD
3FFE-3FFF
Reset
NON-DISCLOSURE
Upon reset, the I bit in the condition code register is set and interrupts are disabled (masked). When an interrupt occurs, the I bit is set automatically by hardware after stacking the condition code register (CCR). All interrupts in the MC68HC05L5 follow a fixed hardware priority circuit to resolve simultaneous requests. Each interrupt has a software programmable interrupt mask bit which may be used to selectively inhibit automatic hardware response. In addition, the I bit in the CCR acts as a class inhibit mask to inhibit all sources in the I-bit class. RESET and software interrupt (SWI) are not masked by the I bit in the CCR. SWI is an instruction rather than a prioritized asynchronous interrupt source. In a sense, it is lower in priority than any source because once any interrupt sequence has begun, SWI cannot override it. In another sense, it is higher in priority than any hardware sources, except reset, because once the SWI opcode is fetched, no other sources can be honored until after the first instruction in the SWI service routine has been executed. SWI causes the I mask bit in the CCR to be set.
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Resets and Interrupts Interrupts
4.3 Interrupts
There are six hardware interrupt sources in the MC68HC05L5: * IRQ1 and IRQ2 * Key wakeup interrupt (KWI) * Timer 1 (TOI, ICI, and OC1I) * Timer 2 (TI2I and OC2I) * Serial transfer complete interrupt (SSPI) * Timebase interrupt (TBI)
Freescale Semiconductor, Inc...
4.3.1 IRQ1 and IRQ2 Two external interrupt request inputs, IRQ1 and IRQ2, share the same vector address at $3FFA and $3FFB. Bits IRQ1S and IRQ2S in interrupt control register (INTCR) control whether IRQ1 and IRQ2, respectively, respond only to the falling edge or falling edge and low level to trigger an interrupt. The IRQ1 and IRQ2 are enabled by IRQ1E and IRQ2E bits and IRQ1F and IRQ2F bits are provided as an indicator in the interrupt status register (INTSR). Since the IRQ1(2)F can be set by either the pins or the data latches of PC7(6), be sure to clear the flags by software before setting the IRQ1(2)E bit. The IRQ1 and the IRQ2 pins are shared with port C bit 7 and bit 6, respectively, and IRQx pin states can be determined by reading port C pins. The BIL and BIH instructions apply only to the IRQ1 input. 4.3.2 Key Wakeup Interrupt (KWI) Eight key wakeup inputs (KWI0-KWI7) share pins with port B. Each key wakeup input is enabled by the corresponding bit in the KWIEN register which resides in the option map, and KWI is enabled by the KWIE bit in the INTCR. When a falling edge is detected at one of the enabled key wakeup inputs, the KWIF bit in the INTSR is set and KWI is generated if KWIE = 1. Each input has a latch which responds only to the falling edge at the pin, and all input latches are cleared at the same time by clearing the KWIF bit. See Figure 4-6.
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General Release Specification 59
NON-DISCLOSURE
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REQUIRED
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4.3.3 IRQ (KWI) Software Consideration IRQ and KWI interrupts have a timing delay in a case described in Figure 4-2. This section shows programming for proper interrupts with IRQ or KWI. Figure 4-1 shows an example of timer 1 interrupt. In this case, the interrupt by TOF occurs as soon as the TOIE (timer 1 overflow interrupt enable) bit is set.
. . CLI BSET TOIE, TCR LDA #$55 . . . TOF INTERRUPT PENDING INTERRUPT OCCURS BEFORE THIS INSTRUCTION
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Figure 4-1. Timer 1 Interrupt Figure 4-2 shows an example of IRQ1 interrupt. In this case, the interrupt occurs after execution the instruction following the instruction which sets IRQ1E bit. The similar action occurs against IRQ2 and KWI interrupts.
. . CLI BSET IRQ1E, INTCR LDA #$55 . . . IRQ1 INTERRUPT PENDING INTERRUPT OCCURS AFTER THIS INSTRUCTION
NON-DISCLOSURE
Figure 4-2. IRQ Timing Delay This problem can be solved by using a software patch like Figure 4-3. A similar procedure could be used for IRQ2 or KWI.
. . CLI BSET IRQ1E, INTCR NOP LDA #$55 . . IRQ1 INTERRUPT PENDING INTERRUPT OCCURS AFTER THIS INSTRUCTION
Figure 4-3. Software Patch for IRQ1
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Freescale Semiconductor, Inc.
Resets and Interrupts Interrupts
FROM RESET
Y
I BIT IN CCR SET ? N IRQ EXTERNAL INTERRUPT N INTERNAL INTERRUPT(1) N Y Y CLEAR IRQ REQUEST LATCH
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STACK PC, X, A, CCR
FETCH NEXT INSTRUCTION
SET I BIT IN CC REGISTER
N RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR, A, X, PC EXECUTE INSTRUCTION
Y
Note 1. KWI, timer 1, timer 2, SSPI, and TBI
Figure 4-4. Interrupt Flowchart
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General Release Specification 61
NON-DISCLOSURE
SWI INSTRUCTION ?
Y
LOAD PC FROM SWI: $3FFC-$3FFD IRQx: $3FFA-$3FFB KWI: $3FF8-$3FF9 TIMER 1: $3FF6-$3FF7 TIMER 2: $3FF4-$3FF5 SSPI: $3FF2-$3FF3 TBI: $3FF0-$3FF1
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REQUIRED
Freescale Semiconductor, Inc. Resets and Interrupts REQUIRED
FOR BIH/BIL 0 SEL H IRQ1 (PC7) D C R IRQ1S Q 1 S Q IRQ1F R DATA BUS READ INSTRUCTION
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AGREEMENT
RESET/POR WRITE 1 TO RIRQ1 IRQ1E INT IRQ2E WRITE 1 TO RIRQ2 RESET/POR
NON-DISCLOSURE
IRQ2S R IRQ2 (PC6) H C D Q SEL
R IRQ2F Q S DATA BUS
1 READ INSTRUCTION
0
Figure 4-5. IRQ1 and IRQ2 Block Diagram
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Resets and Interrupts Interrupts
KWIE0
H KWI0 (PB0)
D C R
Q
KWIE1
H KWI1 (PB1)
D C
Q
Freescale Semiconductor, Inc...
READ KWIF KWI2 TO KWI6
S KWIE7 Q KWIF R H KWI7 (PB7) D C R Q DATA BUS
RESET/POR WRITE 1 TO RKWIF KWI KWIE
Figure 4-6. Key Wakeup Interrupt (KWI)
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General Release Specification 63
NON-DISCLOSURE
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R
REQUIRED
Freescale Semiconductor, Inc. Resets and Interrupts REQUIRED
4.3.4 Timer 1 Interrupt Three timer 1 interrupts (TOI, ICI, and OC1I) share the same interrupt vector at $3FF6 and $3FF7. See 9.3 Timer 1.
4.3.5 Timer 2 Interrupt Two timer 2 interrupts (TI2I and OC2I) share the same interrupt vector at $3FF4 and $3FF5. See 9.4.1 Timer Control Register 2.
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4.3.6 SSPI Interrupt The SSPI transfer complete interrupt uses the vector at $3FF2 and $3FF3. See Section 8. Simple Serial Peripheral Interface (SSPI).
4.3.7 Timebase Interrupt The timebase interrupt uses the vector at $3FF0 and $3FF1. See 7.6 Timebase.
NON-DISCLOSURE
4.4 Interrupt Control Register
Address: $0008 Bit 7 Read: IRQ1E Write: Reset: 0 0 0 0 0 0 0 0 IRQ2E 0 KWIE IRQ1S IRQ2S 0 0 6 5 4 3 2 1 Bit 0
Figure 4-7. Interrupt Control Register (INTCR)
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Resets and Interrupts Interrupt Control Register
IRQ1E -- IRQ1 Interrupt Enable The IRQ1E bit enables IRQ1 interrupt when IRQ1F is set. This bit is cleared on reset. 0 = IRQ1 interrupt disabled 1 = IRQ1 interrupt enabled IRQ2E -- IRQ2 Interrupt Enable The IRQ2E bit enables IRQ2 interrupt when IRQ2F is set. This bit is cleared on reset. 0 = IRQ2 interrupt disabled 1 = IRQ2 interrupt enabled Bit 5 -- Reserved This bit is not used and is always read as logic 0. KWIE -- Key Wakeup Interrupt (KWI) Enable The KWIE bit enables key wakeup interrupt when KWIF is set. This bit is cleared on reset. 0 = KWI disabled 1 = KWI enabled IRQ1S -- IRQ1 Select Edge Sensitive Only 0 = IRQ1 configured for low level and negative edge sensitive 1 = IRQ1 configured to respond only to negative edges IRQ2S -- IRQ2 Select Edge Sensitive Only 0 = IRQ2 configured for low level and negative edge sensitive 1 = IRQ2 configured to respond only to negative edges Bits 1 and 0 -- Reserved These bits are not used and always read as logic 0.
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General Release Specification 65
NON-DISCLOSURE
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REQUIRED
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Address: $0009 Bit 7 Read: Write: Reset: 0 0 0 0 IRQ1F 6 IRQ2F 5 0 4 KWIF 3 0 RIRQ1 0 2 0 0 RIRQ2 0 0 RKWIF 0 1 Bit 0 0
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AGREEMENT
= Unimplemented
Figure 4-8. Interrupt Status Register (INTSR) IRQ1F -- IRQ1 Interrupt Flag When IRQ1S = 0, the falling edge or low level at the IRQ1 pin sets IRQ1F. When IRQ1S = 1, only the falling edge sets the IRQ1F bit. If the IRQ1E bit and this bit are set, an interrupt is generated. This readonly bit is cleared by writing a logic 1 to the RIRQ1 bit. Reset clears this bit. IRQ2F -- IRQ2 Interrupt Flag When IRQ2S = 0, the falling edge or low level at the IRQ2 pin sets IRQ2F. When IRQ2S = 1, only the falling edge sets the IRQ2F bit. If the IRQ2E bit and this bit are set, an interrupt is generated. This readonly bit is cleared by writing a logic 1 to the RIRQ2 bit. Reset clears this bit. Bit 5 -- Reserved This bit is not used and is always read as logic 0. KWIF -- Key Wakeup Interrupt Flag When the KWIEx bit in the KWIEN register is set, the falling edge at the KWIx pin sets the KWIF bit. If the KWIE bit and this bit are set, an interrupt is generated. This read-only bit is cleared by writing a logic 1 to the RKWIF bit. Reset clears this bit.
NON-DISCLOSURE
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Resets and Interrupts Interrupt Status Register
RIRQ1 -- Reset IRQ1 Flag The RIRQ1 bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the IRQ1F bit and writing logic 0 to this bit has no effect. RIRQ2 -- Reset IRQ2 Flag The RIRQ2 bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the IRQ2F bit and writing a logic 0 to this bit has no effect.
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Bit 1 -- Reserved This bit is not used and is always read as logic 0. RKWIF -- Reset KWI Flag The RKWIF bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the KWIF bit and writing a logic 0 to this bit has no effect.
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General Release Specification 67
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Resets and Interrupts REQUIRED NON-DISCLOSURE
General Release Specification 68 Resets and Interrupts For More Information On This Product, Go to: www.freescale.com
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AGREEMENT
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General Release Specification -- MC68HC05L5
Section 5. Low-Power Modes
5.1 Contents
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5.2 Introduction
The MCU has two power-saving modes, stop and wait. Flowcharts of these modes are shown in Figure 5-2.
5.3 Stop Mode
The STOP instruction places the MCU in its lowest-power mode. In stop mode, the internal main oscillator OSC is turned off, halting all internal processing, including timer operations (timer 1, timer 2, and computer operating properly (COP) watchdog timer. Suboscillator XOSC does not stop oscillating. Therefore, if XOSC is used as the clock source for the COP watchdog timer, COP is still functional in stop mode. See Section 7. Oscillators/Clock Distributions. During stop mode, the timer prescaler is cleared. The I bit in the condition code register (CCR) is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of stop mode only by RESET or an interrupt from IRQ1, IRQ2, KWI, SSPI (slave mode only), or TBI. See Section 7. Oscillators/Clock Distributions.
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General Release Specification 69
NON-DISCLOSURE
AGREEMENT
5.2 5.3 5.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
REQUIRED
Freescale Semiconductor, Inc. Low-Power Modes REQUIRED 5.4 Wait Mode
The WAIT instruction places the MCU in a low-power mode, but wait mode consumes more power than stop mode. All CPU action is suspended, but on-chip peripherals and oscillators remain active. Any interrupt or reset (including a COP reset) will cause the MCU to exit wait mode. During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The timers may be enabled to allow a periodic exit from wait mode. Wait mode must be exited and the COP must be reset to prevent a COP timeout. The reduction of power in wait mode depends on how many of the onchip peripheral's clocks can be shut down. Therefore, the amount of power that will be consumed is dependent on the application, and it would be prohibitive to test all parts for all variations. For these reasons, the values given in Section 12. Electrical Specifications reflect typical application conditions after initial characterization of silicon.
NON-DISCLOSURE
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AGREEMENT
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Low-Power Modes Wait Mode
STATE A CPU: RUN PH2: X1/2 X1: ON X2: ON
RESET INT
Freescale Semiconductor, Inc...
STOP STATE D CPU: RUN PH2: X2/2 X1: ON X2: ON
RESET DELAY INT STOP
X1EN = 0
X1EN = 1 RESET INT STOP
INT
Notes: PH2 is at same frequency as internal processor clock E. X1 = OSC X2 = XOSC Low Power High Speed X1EN = FOSCE STOP E D C B A
Figure 5-1. Clock State and STOP Recovery/Power-On Reset Delay Diagrams
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General Release Specification 71
NON-DISCLOSURE
STATE E CPU: RUN PH2: X2/2 X1: OFF X2: ON
POWER-ON STATE D STATE E
AGREEMENT
STATE B CPU: RUN PH2: X1/4 X1: ON X2: ON
STATE C CPU: RUN PH2: X1/64 X1: ON X2: ON
STATE A STATE B STATE C
REQUIRED
Freescale Semiconductor, Inc. Low-Power Modes REQUIRED
STOP
WAIT
STOP OSCILLATOR OSC AND ALL CLOCKS EXCEPT XOSC CLEAR I BIT
OSCILLATOR ACTIVE TIMER CLOCK ACTIVE PROCESSOR CLOCKS STOPPED CLEAR I BIT
N RESET? RESET?
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AGREEMENT
N Y Y Y EXTERNAL INTERRUPT IRQ? N KWI INTERRUPT? N TIMER 1 INTERRUPT? N TIMER 2 INTERRUPT? N SSPI INTERRUPT? N RESTART PROCESSOR CLOCK Y TIMEBASE INTERRUPT? N 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE
EXTERNAL INTERRUPT IRQ? N KWI INTERRUPT ? N
Y
Y
Y
Y SSPI INTERRUPT ? N Y TIMEBASE INTERRUPT ? Y Y
NON-DISCLOSURE
N
Y IF FOSC = 1 TURN ON OSCILLATOR OSC WAIT FOR TIME
Notes: Slave Mode Only When TBCLK = 0
Figure 5-2. Stop/Wait Flowcharts
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General Release Specification -- MC68HC05L5
Section 6. Parallel Input/Output (I/O)
6.1 Contents
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General Release Specification 73
NON-DISCLOSURE
AGREEMENT
6.2 6.3 6.3.1 6.3.2 6.4 6.5 6.5.1 6.5.2 6.6 6.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . .77 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Port C Data Direction Register . . . . . . . . . . . . . . . . . . . . . .82 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
REQUIRED
Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED 6.2 Introduction
The MCU has five parallel ports: * * * * * Port A has eight input/output (I/O) pins. Port B has eight input-only pins. Port C has six I/O pins and tow input-only pins. Port D has seven output-only pins. Port E has eight output-only pins.
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AGREEMENT
Most of these 39 I/O pins serve multiple purposes, depending on the configuration of the MCU system. The configuration is in turn controlled by hardware mode selection as well as internal control registers.
DATA DIRECTION REGISTER BIT INTERNAL HC05 CONNECTIONS
LATCHED OUTPUT DATA BIT
OUTPUT
I/O PIN
NON-DISCLOSURE
INPUT REG BIT INPUT I/O
Figure 6-1. Port I/O Circuitry for One Bit
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Parallel Input/Output (I/O) Port A
6.3 Port A
Port A is an 8-bit, bidirectional, general-purpose port. The data direction of a port A pin is determined by its corresponding DDRA bit. When a port A pin is programmed as an output by the corresponding DDRA bit, data in the PORTA data register becomes output data to the pin. This data is returned when the PORTA register is read. Open drain or CMOS outputs are selected by AWOMH and AWOML bits in the WOM1 register. If the AWOMH bit is set, the P-channel drivers of bits 7-4 output buffers are disabled (open drain). If the AWOML bit is set, the P-channel drivers of bits 3-0 output buffers are disabled (open drain). When a bit is programmed as input by the corresponding DDRA bit, the pin level is read by the CPU. Port A has optional pullup resistors. When the RAH bit or RAL bit in the RCR1 is set, pullup resistors are attached to the upper four bits or lower four bits of port A pins, respectively. When a pin outputs a low level, the pullup resistor is disconnected regardless of the RAH or RAL bit state.
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General Release Specification 75
NON-DISCLOSURE
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REQUIRED
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6.3.1 Port A Data Register
Address:
$0000 Bit 7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0
Read: PA7 Write: Reset: Unaffected by reset
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AGREEMENT
Figure 6-2. Port A Data Register (PORTA) Read Anytime; returns pin level if DDR set to input; returns output data latch if DDR set to output Write Anytime; data stored in an internal latch; drives pin only if DDR set for output Reset Becomes high-impedance inputs
NON-DISCLOSURE
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Parallel Input/Output (I/O) Port A
6.3.2 Port A Data Direction Register
Address: Option Map -- $0000 Bit 7 Read: DDRA7 Write: Reset: 0 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 6 5 4 3 2 1 Bit 0
Freescale Semiconductor, Inc...
Read Anytime when OPTM = 1 Write Anytime when OPTM = 1 Reset Cleared to $00; all general-purpose I/O configured for input DDRAx -- Port A Data Direction Register Bit x 0 = Configure I/O pin PAx to input 1 = Configure I/O pin PAx to output
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
General Release Specification 77
NON-DISCLOSURE
AGREEMENT
Figure 6-3. Port A Data Direction Register (DDRA)
REQUIRED
Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED 6.4 Port B
Port B pins serve two basic functions: KWI input pins and generalpurpose input pins. Each KWI input is enabled or disabled by the corresponding KWIEx bit in the KWIEN register, and the usage of the KWI input does not affect the general-purpose input function. Port B pin states may be read any time regardless of the configurations. Since there is no output drive logic associated with port B, there is no DDRB register and the write to the PORTB register has no meaning. Port B has optional pullup resistors. When the RBH or RBL bit in the RCR1 is set, pullup resistors are attached to the upper four bits or lower four bits of port A pins, respectively.
Address: $0001 Bit 7 Read: PB7 Write: Reset: Unaffected by reset PB6 PB5 PB4 PB3 PB2 PB1 PB0 6 5 4 3 2 1 Bit 0
NON-DISCLOSURE
Freescale Semiconductor, Inc...
AGREEMENT
Figure 6-4. Port B Data Register (PORTB) Read Anytime; returns pin level Write Has no meaning or effect Reset Unaffected; always an input port
General Release Specification 78 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Port C
6.5 Port C
Port C pins share functions with several on-chip peripherals. A pin function is controlled by the enable bit of each associated peripheral. Bit 7 and bit 6 of port C are input-only pins and IRQ input pins. Since IRQ1F or IRQ2F can be set by either the pins or the data latches, when using IRQs, be sure to clear the flags by software before enabling the IRQ1E or IRQ2E bits.
Freescale Semiconductor, Inc...
NOTE:
Since the TCAP pin is shared with the PC3 I/O pin, changing the state of the PC3 DDR or data register can cause an unwanted TCAP interrupt. This can be handled by clearing the ICIE bit before changing the configuration of PC3 and clearing any pending interrupts before enabling ICIE. Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should always be cleared whenever EVI is used. EVI should not be used when DDRC4 is high.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
General Release Specification 79
NON-DISCLOSURE
The PC4 and PC3 pins share functions with the timer input pins (EVI and TCAP). These bits are not affected by the usage of timer input functions and the directions of pins are always controlled by the DDRC4 and DDRC3 bits. Also, the DDRC4 and DDRC3 bits determine whether the pin states or data latch states should be read by the CPU.
AGREEMENT
The PC5 pin is a general-purpose I/O pin and the direction of the pin is determined by the DDRC5 bit in the data direction register C (DDRC). When the event output (EVO) is enabled, the PC5 is configured as an event output pin and the DDRC5 bit has meaning only for the read of PC5 bit in the PORTC register; if the DDRC5 is set, the PC5 data latch is read by the CPU. Otherwise, PC5 pin level (EVO state) is read. When EVO is disabled, the DDRC5 bit decides the idling state of EVO (if DDRC5 = 1).
REQUIRED
Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED
The PC2-PC0 pins are shared with the simple serial peripheral interface (SSPI). When the SSPI is not used (SPE = 0), DDRC2-DDRC0 bits control the direction of the pins, and when the SSPI is enabled, the pins are configured as serial clock output or input (SCK), serial data output (SDO), and serial data input (SDI). The direction of the SCK depends on the MSTR bit in the SPCR. When PORTC is read, the value read will be determined by the data direction register. When the port is configured for input (DDRC2, DDRC1, or DDRC0 equal to logic 0), the pin state is read. When the port is configured for output (DDRC2, DDRC1, or DDRC0 equal to logic 0), the output data latch is read. Port C has optional pullup resistors. When the RCx bit in the RCR2 is set, pullup resistors are attached to the PCx pin. When a pin outputs a low level, the pullup resistor is disconnected regardless of an RCR2 register bit being set Bits 5-0 have open drain or CMOS output options, which are controlled by the corresponding WOM2 register bits. These open drain or CMOS output options may be selected for either the general-purpose output ports or the peripheral outputs (EVO, SCK, and SDO).
NON-DISCLOSURE
General Release Specification 80 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc...
AGREEMENT
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Port C
6.5.1 Port C Data Register
Address:
$0002 Bit 7 6 PC6 5 PC5 4 PC4 3 PC3 2 PC2 1 PC1 Bit 0 PC0
Read: PC7 Write: Reset: Unaffected by Reset
Freescale Semiconductor, Inc...
Read Anytime; returns pin level if DDR set to input; returns output data latch if DDR set to output, PC7 and PC6 are input-only pins Write Anytime; data stored in an internal latch; drives pin only if DDR set for output; writes do not change pin state; when pin configured for SDO, SCK, and EVO peripheral output, bits 7 and 6 are read-only bits and write has no effect Reset Becomes high-impedance input
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
General Release Specification 81
NON-DISCLOSURE
AGREEMENT
Figure 6-5. Port C Data Register (PORTC)
REQUIRED
Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED
6.5.2 Port C Data Direction Register
Address: Option Map -- $0002 Bit 7 Read: 0 Write: Reset: 0 0 0 0 0 0 0 0 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 6 5 4 3 2 1 Bit 0
Freescale Semiconductor, Inc...
AGREEMENT
Figure 6-6. Port C Data Direction Register (DDRC) Read Anytime when OPTM = 1 Write Anytime when OPTM = 1; bits7 and 6 are read-only and write has no effect Reset Cleared to $00; all general-purpose I/O configured for input Bits 7 and 6 -- Not used Always read logic 0 DDRC5-DDRC0 -- Port C Data Direction Register Bit x The timer and SSPI force the I/O state to be an output for each port C line associated with an enabled output function such as SDO and EVO. For these cases, the data direction bits will not change. 0 = Configure I/O pin PCx to input 1 = Configure I/O pin PCx to output
NON-DISCLOSURE
General Release Specification 82 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Port D
6.6 Port D
Port D pins serve one of two basic functions, depending on the MCU mode selected: * * LCD frontplane and backplane driver outputs General-purpose output pins
Since port D is an output-only port, there is no DDRD register.
Freescale Semiconductor, Inc...
By writing a 1 the PDH bit in the LCD control register (LCDCR), LCD frontplanes drivers (FP35-FP38) are disabled and the upper four bits of port D output are connected to the pins. The pin connections of the lower three bits of port D depend on the LCD duty selection by the DUTY1 and DUTY0 bits in the LCDCR. When the LCD duty is not 1/4, the unused backplane driver(s) is (are) replaced by the port D output pin(s) automatically. If DWOMH bit or DWOML bit in the WOM1 register is set, the P-channel drivers of output buffers at the upper four bits or lower three bits, respectively, are disabled (open-drain mode). These open-drain controls do not apply to the pins which are configured as frontplane or backplane driver outputs.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
General Release Specification 83
NON-DISCLOSURE
AGREEMENT
On reset, all port D outputs are disconnected from the pins and the port D data latches are set to a logic 1.
REQUIRED
Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED
Address:
$0003 Bit 7 6 PD6 1 5 PD5 1 4 PD4 1 3 PD3 1 2 PD2 1 1 PD1 1 Bit 0 1 1
Read: PD7 Write: Reset: 1
Figure 6-7. Port D Data Register (PORTD) Read Anytime; returns output data latch; bit 0 is always read logic 1 Write Anytime; writes do not change pin state when configured for LCD driver output Reset All bits set to logic 1 and output ports disconnected from the pins; LCD is enabled on reset
NON-DISCLOSURE
General Release Specification 84 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc...
AGREEMENT
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Port E
6.7 Port E
Port E pins serve one of two basic functions, depending on the MCU mode selected: * * LCD frontplane driver outputs General-purpose output pins
Since port E is an output-only port, there is no DDRE register.
Freescale Semiconductor, Inc...
The upper or lower four bits of port E output are connected to the pins instead of the LCD frontplane drivers by writing 1 to the PEH or PEL bit, respectively, in the LCD control register(LCDCR). If EWOMH bit or EWOML bit in the WOM1 register is set, the P-channel driver of output buffers at the upper or lower four bits, respectively, are disabled (open-drain mode). These open-drain controls do not apply to the pins which are configured as frontplane driver outputs.
Address: $0004 Bit 7 Read: PE7 Write: Reset: 1 1 1 1 1 1 1 1 PE6 PE5 PE4 PE3 PE2 PE1 PE0 6 5 4 3 2 1 Bit 0
Figure 6-8. Port E Data Register (PORTE) Read Anytime; returns output data latch Write Anytime; writes do not change pin state when configured for LCD driver output Reset All bits set to logic 1 and output ports disconnected from the pins; LCD is enabled on reset
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com General Release Specification 85
NON-DISCLOSURE
AGREEMENT
On reset, all port E outputs are disconnected from the pins and the port E data latches are set to a logic 1.
REQUIRED
Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED NON-DISCLOSURE
General Release Specification 86 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc...
AGREEMENT
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Section 7. Oscillators/Clock Distributions
7.1 Contents
Freescale Semiconductor, Inc...
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Oscillators/Clock Distributions For More Information On This Product, Go to: www.freescale.com
General Release Specification 87
NON-DISCLOSURE
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.3 OSC Clock Divider and POR Counter . . . . . . . . . . . . . . . . . . .88 7.4 System Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.5 OSC and XOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.5.1 OSC on Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.5.2 XOSC on Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 7.5.2.1 XOSC with FOSCE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . .91 7.5.2.2 XOSC with FOSCE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.5.2.3 XOSC with FOSCE = 0 and STOP . . . . . . . . . . . . . . . . .92 7.5.2.4 Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . .92 7.6 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.6.1 LCDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.6.2 STUP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.6.3 TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 7.6.4 COP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.6.5 Timebase Control Register 1. . . . . . . . . . . . . . . . . . . . . . . .97 7.6.6 Timebase Control Register 2. . . . . . . . . . . . . . . . . . . . . . . .98 7.6.7 Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . .100
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Oscillators/Clock Distributions REQUIRED 7.2 Introduction
The two oscillator blocks are OSC and XOSC. Several combinations of the clock distributions are allowed for the modules in the MC68HC05L5. Refer to Figure 7-1.
FOSCE/ PWRON OSC1 OSC OSC2 1/20 1/21 1/25
WAIT
Freescale Semiconductor, Inc...
AGREEMENT
OSC DIVIDER 7-BIT
SEL
1/2
CPU
SYSTEM CLOCK SYS1 SYS0
SSPI
TIMER1 CLK CTRL STOP 1/27 XOSC1 XOSC XOSC2 XCLK TIMEBASE POR 6-BIT FTUP TIMER2 EXCLK
1/27
NON-DISCLOSURE
Figure 7-1. Clock Signal Distribution
7.3 OSC Clock Divider and POR Counter
The OSC clock is divided by a 7-bit counter which is used for the system clock, timebase, and power-on reset (POR) counter. Clocks divided by 2, 4, and 64 are available for the system clock selections and a clock divided by 128 is provided for the timebase and POR counter. The POR counter is a 6-bit clock counter that is driven by the OSC divided by 128. The overflow of this counter is used for setting FTUP bit, releasing the POR, and resuming operation from stop mode.
General Release Specification 88 Oscillators/Clock Distributions For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
LCD DRIVER AND PORTS
Freescale Semiconductor, Inc.
Oscillators/Clock Distributions System Clock Control
The 7-bit divider and POR counter are initialized to $0078 by two conditions: * * Power-on detection When FOSCE bit is cleared
7.4 System Clock Control
The system clock is provided for all internal modules except timebase. Both OSC and XOSC are available as the system clock source. The divide ratio is selected by the SYS1 and SYS0 bits in the MISC register. (See Table 7-1.) By default, OSC divided by 64 is selected on reset.
Freescale Semiconductor, Inc...
NOTE:
Do not switch the system clock to XOSC (SYS1 and SYS0 = 11) when XOSC clock is not available. The XOSC clock is available when STUP flag is set. Do not switch the system clock to OSC (SYS1 and SYS0 = 00, 01, or 10) when OSC clock is not available. The OSC clock is available when FTUP flag is set.
Table 7-1. System Bus Clock Frequency Selection
CPU Bus Frequency (Hz) SYS1 SYS0 Divide Ratio OSC = 4.0 M 0 0 1 1 0 1 0 1 OSC / 2 OSC / 4 OSC / 64 XOSC / 2 2.0 M 1.0 M 62.5 k -- OSC = 4.1943 M 2.0972 M 1.0486 M 65.536 k -- XOSC = 32.768 k -- -- -- 16.384 k
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Oscillators/Clock Distributions For More Information On This Product, Go to: www.freescale.com
General Release Specification 89
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Oscillators/Clock Distributions REQUIRED 7.5 OSC and XOSC
The secondary oscillator (XOSC) runs continuously after power up. The main oscillator (OSC) can be stopped to conserve power via the STOP instruction or the FOSCE bit in the MISC register. The effects of restarting the OSC will vary depending on the current state of the MCU, including SYS0, SYS1, and FOSCE.
7.5.1 OSC on Line
Freescale Semiconductor, Inc...
AGREEMENT
If the system clock is OSC, FOSCE should remain logic 1. Executing the STOP instruction in this condition will halt OSC, put the MCU into a lowpower mode and clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ or reset re-starts the oscillator. When the POR counter overflows, internal reset is released and execution can begin. The stabilization time will vary between 8064 and 8192 counts.
NOTE:
Exiting STOP with external reset will always return the MCU to the state as defined by the default register definitions, for example, SYS0:SYS1 = 1:0, FOSCE = 1.
NON-DISCLOSURE
OSC OSC1 Rf OSC2 XOSC1
XOSC XOSC2 Rf Rd ON CHIP OFF CHIP
MASK OPTION
MASK OPTION
Figure 7-2. OSC1, OSC2, XOSC1, and XOSC2 Mask Options
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Freescale Semiconductor, Inc.
Oscillators/Clock Distributions OSC and XOSC
7.5.2 XOSC on Line If XOSC is the system clock (SYS:SYS1 = 1:1), OSC can be stopped either by the STOP instruction or by clearing the FOSCE bit. The suboscillator (XOSC) never stops except during power down. This clock also may be used as the clock source of the system clock and timebase. STUP bit indicates that the XOSC clock is available. OSC and XOSC pins have options for feedback and damping resistor implementations. These options are set through mask option and may be read through the MOSR register.
Freescale Semiconductor, Inc...
NOTE:
When XOSC is not used, the XOSC1 input pin should be connected to the RESET pin.
RESET LOGIC RESET ON CHIP OFF CHIP XOSC1
XOSC XOSC2
NO CONNECT FROM EXTERNAL RESET CIRCUIT
Figure 7-3. Unused XOSC1 Pin 7.5.2.1 XOSC with FOSCE = 1 If the system clock is XOSC and FOSCE = 1, executing the STOP instruction will halt OSC, put the MCU into a low-power mode and clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ re-starts the oscillator; however, execution begins immediately using XOSC. When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the system clock. The stabilization time will vary between 8064 and 8192 counts.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Oscillators/Clock Distributions For More Information On This Product, Go to: www.freescale.com
General Release Specification 91
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Oscillators/Clock Distributions REQUIRED
7.5.2.2 XOSC with FOSCE = 0 If XOSC is the system clock, clearing FOSCE will stop OSC and preset the 7-bit divider and 6-bit POR counter to $0078. Execution will continue with XOSC and when FOSCE is set again, OSC will re-start. When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the system clock. The stabilization time will be 8072 counts. 7.5.2.3 XOSC with FOSCE = 0 and STOP If XOSC is the system clock and FOSCE is cleared, further power reduction can be achieved by executing the STOP instruction. In this case, OSC is stopped, the 7-bit divider and 6-bit POR counter are preset to $0078 (since FOSCE = 0) and execution is halted. Exiting STOP with external IRQ does not re-start the OSC; however, execution begins immediately using XOSC. OSC may be re-started by setting FOSCE. When the POR counter overflows, FTUP will be set, signaling that OSC is stable and can be used as the system clock. The stabilization time will be 8072 counts. 7.5.2.4 Stop Mode and Wait Mode During stop mode, the main oscillator (OSC) is shut down and the clock path from the second oscillator (XOSC) is disconnected. All modules except timebase are halted. Entering stop mode clears the FTUP flag in the MISC register and initializes the POR counter. Stop mode is exited by RESET, IRQ1, IRQ2, KWI, SSPI (slave mode), or timebase interrupt. If OSC is selected as the system clock source during stop mode, CPU resumes after the overflow of the POR counter and this overflow also sets the FTUP status flag. If XOSC is selected as the system clock source during stop mode, no stop recovery time is required for exiting stop mode because XOSC never stops. Re-start of the main oscillator depends on the FOSCE bit. During wait mode, only the CPU clocks are halted and the peripheral modules are not affected. Wait mode is exited by RESET and any interrupts.
General Release Specification 92 Oscillators/Clock Distributions For More Information On This Product, Go to: www.freescale.com MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
NON-DISCLOSURE
Freescale Semiconductor, Inc...
AGREEMENT
Freescale Semiconductor, Inc.
Oscillators/Clock Distributions Timebase
Table 7-2. Recovery Time Requirements
Before Reset or Interrupt CPU Clock Source -- OSC (OSC on) OSC (OSC off) Stop -- Out Out In In(1) Out Out In In FOSCE -- 1 0(2) 1 0(1) 1 0 1 0 Power-On Reset Wait -- -- -- -- -- -- -- -- External Reset -- No wait Wait Wait Wait No wait Wait Wait Wait Exit Stop Mode by Interrupt -- -- -- Wait Wait -- -- No wait No wait
Freescale Semiconductor, Inc...
XOSC (OSC off)
Notes:
1. This case never occurs. 2. This case has no meaning for the applications.
7.6 Timebase
Timebase is a 14-bit up-counter which is clocked by XOSC input or OSC input divided by 128. TBCLK bit in the TBCR1 register selects the clock source. This 14-bit divider is initialized to $0078 only upon power-on reset (POR). After counting 8072 clocks, the STUP bit in the MISC register is set. The divided clocks from the timebase are used for LCDCLK, STUP, TBI, and COP. (See Figure 7-4).
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General Release Specification 93
NON-DISCLOSURE
AGREEMENT
XOSC (OSC on)
REQUIRED
Freescale Semiconductor, Inc. Oscillators/Clock Distributions REQUIRED
TBCLK
LCLK
1 OSC/27 XCLK 0 SEL 7-BIT DIVIDER
1/26 1/27
0 SEL 1 1/20 1/25 1/26 1/27 TBR1 TBIE LCD CLOCK
7-BIT DIVIDER
SEL
TBIF
TBI
Freescale Semiconductor, Inc...
AGREEMENT
TBR0 COP RESET
COP CLEAR
DIVIDE BY 4
COP ENABLE
Figure 7-4. Timebase Clock Divider
7.6.1 LCDCLK The clocks divided by 64 and 128 are used as LCD clocks at the LCD driver module, and clocks are selected by the LCLK bit in the TBCR1.
NON-DISCLOSURE
7.6.2 STUP Timebase divider is initialized to $0078 by the power-on detection and when the count reaches 8072, the STUP flag in the MISC register is set. Once the STUP flag is set, it is never cleared until power down.
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Oscillators/Clock Distributions Timebase
7.6.3 TBI Timebase interrupts may be generated every 0.5, 0.25, 0.125, or 0.0039 seconds with a 32.768-kHz crystal at XOSC pins. The timebase interrupt flag (TBIF) is set every period and interrupt is requested if the enable bit (TBIE) is set. The clock divided by 128, 4096, 8192, or 16,384 is used to set TBIF, and this clock is selected by the TBR1 and TBR0 bits in the TBCR2 register. (See Table 7-3.)
Freescale Semiconductor, Inc...
Table 7-3. Timebase Interrupt Frequency
TBCR2 Divide Ratio TBR1 TBR0 0 0 1 1 0 1 0 1 TBCLK / 128 TBCLK / 4096 TBCLK / 8192 TBCLK / 16,384 OSC = 4.0 M OSC = 4.1943 M XOSC = 32.768 k 244 7.63 3.81 1.91 256 8.00 4.00 2.00 256 8.00 4.00 2.00 Frequency (Hz)
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Oscillators/Clock Distributions For More Information On This Product, Go to: www.freescale.com
General Release Specification 95
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Oscillators/Clock Distributions REQUIRED
7.6.4 COP The computer operating properly (COP) watchdog timer is controlled by the COPE and COPC bits in the TBCR2 register. The COP uses the same clock as TBI that is selected by the TBR1 and TBR0 bits. The TBI is divided by four and overflow of this divider generates COP timeout reset if the COP enable (COPE) bit is set. The COP timeout reset has the same vector address as POR and external RESET. To prevent the COP timeout, the COP divider is cleared by writing a logic 1 to the COP clear (COPC) bit. When the timebase divider is driven by the OSC clock, clock for the divider is suspended during stop mode or when FOSCE is a logic 0. This may cause COP period stretching or no COP timeout reset when processing errors occur. To avoid these problems, it is recommended that the XOSC clock be used for the COP functions. When the timebase (COP) divider is driven by the XOSC clock, the divider does not stop counting and the COPC bit must be triggered to prevent the COP timeout. Table 7-4. COP Timeout Period
TBCR2 OSC = 4.0 MHz TBR1 0 0 1 1 TBR0 Min 0 1 0 1 12.3 393 786 1573 Max 16.4 524 1048 2097 Min 11.7 375 750 1500 Max 15.6 500 1000 2000 Min 11.7 375 750 1500 Max 15.6 500 1000 2000 COP Period (ms) OSC = 4.1943 MHz XOSC = 32.768 kHz
NON-DISCLOSURE
Freescale Semiconductor, Inc...
AGREEMENT
General Release Specification 96 Oscillators/Clock Distributions For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Oscillators/Clock Distributions Timebase
7.6.5 Timebase Control Register 1
Address: $0010 Bit 7 Read: TBCLK Write: Reset: 0 0 0 0 0 0 0 0 0 LCLK 0 0 0 T2R1 T2R0 6 5 4 3 2 1 Bit 0
Figure 7-5. Timebase Control Register 1 (TBCR1)
Freescale Semiconductor, Inc...
Read Anytime Write Anytime; only one write is allowed on bit 7 after reset TBCLK -- Timebase Clock The TBCLK bit selects the timebase clock source. This bit is cleared on reset. After reset, a write to this bit is allowed only once. 0 = XOSC clock selected 1 = OSC clock divided by 128 selected Bit 6 -- Reserved This bit is not used and always reads as logic 0. LCLK -- LCD Clock The LCLK bit selects the clock for the LCD driver. This bit is cleared on reset. 0 = Divide by 64 selected 1 = Divide by 128 selected Bits 4-2 -- Reserved These bits are not used and always read as logic 0. T2R1 and T2R0 -- Timer 2 Prescale Rate Select Bits T2R1 and T2R0 select timer 2 clock rate. See 9.4 Timer 2 for more detail.
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7.6.6 Timebase Control Register 2
Address: $0011 Bit 7 Read: Write: Reset: 0 0 1 1 TBIF TBIE TBR1 TBR0 RTBIF 0 0 6 5 4 3 0 0 COPE 0 COPC 0 2 1 0 Bit 0 0
= Unimplemented
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AGREEMENT
Figure 7-6. Timebase Control Register 2 (TBCR2) Read Anytime; bits 3 and 0 are write-only bits and always read as logic 0 Write Anytime; bit 7 is a read-only bit and write has no effect; bit 1 is 1-time write bit TBIF -- Timebase Interrupt Flag The TBIF bit is set every timeout interval of the timebase counter. This read-only bit is cleared by writing a logic 1 to the RTBIF bit. Reset clears the TBIF bit. The timebase interrupt period between reset and the first TBIF depends on the time elapsed during reset, since the timebase divider is not initialized on reset. TBIE -- Timebase Interrupt Enable The TBIE bit enables the timebase interrupt capability. If TBIF = 1 and TBIE = 1, the timebase interrupt is generated. 0 = Timebase interrupt disabled 1 = Timebase interrupt requested when TBIF = 1 TBR1 and TBR0 -- Timebase Interrupt Rate Select The TBR1 and TBR0 bits select one of four rates for the timebase interrupt period (see Table 7-3). The TBI rate is also related to the COP timeout reset period. These bits are set to logic 1 on reset.
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Oscillators/Clock Distributions Timebase
Table 7-5. Timebase Interrupt Frequency
TBCR2 Divide Ratio TBR1 TBR0 0 0 1 1 0 1 0 1 TBCLK / 128 TBCLK / 4096 TBCLK / 8192 TBCLK / 16,384 OSC = 4.0 M OSC = 4.1943 M XOSC = 32.768 k 244 7.63 3.81 1.91 256 8.00 4.00 2.00 256 8.00 4.00 2.00 Frequency (Hz)
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RTBIF -- Reset Timebase Interrupt Flag The RTBIF bit is a write-only bit and is always read as logic 0. Writing logic 1 to this bit clears the TBIF bit and writing logic 0 to this bit has no effect. Bit 2 -- Reserved This bit is not used and is always read as logic 0. COPE -- COP Enable When the COPE bit is logic 1, the COP reset function is enabled. This bit is cleared on reset (including COP timeout reset) and write to this bit is allowed only once after reset. COPC -- COP Clear Writing logic 1 to the COPC bit clears the 2-bit divider to prevent COP timeout. (The COP timeout period depends on the TBI rate.) This bit is write-only and returns to logic 0 when read.
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Address:
$003E Bit 7 6 STUP 5 0 4 0 SYS1 SYS0 0 FOSCE 1 OPTM 0 3 2 1 Bit 0
Read: Write: Reset:
FTUP
*
*
0
0
1
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= Unimplemented
* Unaffected by reset but initialized by power-on reset
Figure 7-7. Miscellaneous Register (MISC) FTUP -- OSC Time Up Flag Power-on detection and clearing the FOSCE bit clears this read-only bit. This bit is set by the overflow of the POR counter. Reset does not affect this bit. 0 = During POR or OSC shut down 1 = OSC clock available for the system clock STUP -- XOSC Time Up Flag Power-on detection clears this read-only bit. This bit is set after the timebase has counted 8072 clocks. Reset does not affect this bit. 0 = XOSC not stabilized or no signal on XOSC1 and XOSC2 pins 1 = XOSC clock available for the system clock Bits 5 and 4 -- Reserved These bits are not used and always read as logic 0. SYS1 and SYS0 -- System Clock Select These two bits select the system clock source. On reset, the SYS1 and SYS0 bits are initialized to 1 and 0, respectively.
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Oscillators/Clock Distributions Timebase
NOTE:
Do not switch the system clock to XOSC (SYS1 and SYS0 = 11) when the XOSC clock is not available. The XOSC clock is available when the STUP flag is set. Do not switch the system clock to OSC (SYS1 and SYS 0 = 00, 01, or 10) when the OSC clock is not available. The OSC clock is available when the FTUP flag is set.
Table 7-6. System Bus Clock Frequency Selection
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CPU Bus Frequency (Hz) OSC = 4.0 M 0 0 1 1 0 1 0 1 OSC / 2 OSC / 4 OSC / 64 XOSC / 2 2.0 M 1.0 M 62.5 k -- OSC = 4.1943 M XOSC = 32.768 k 2.0972 M 1.0486 M 65.536 k -- -- -- -- 16.384 k
FOSCE -- Fast (Main) Oscillator Enable The FOSCE bit controls the main oscillator activity. This bit should not be cleared by the CPU when the main oscillator is selected as the system clock source. When this bit is cleared: 1. OSC is shut down. 2. 7-bit dividers at the OSC input and POR counter are initialized to $0078. 3. FTUP flag is cleared. When this bit is set: 1. Main oscillator starts again. 2. FTUP flag is set by the POR counter overflow (8072 clocks). OPTM -- Option Map Select The OPTM bit selects one of two register maps at $0000-$000F. This bit is cleared on reset. 0 = Main register map selected 1 = Option map selected
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General Release Specification -- MC68HC05L5
Section 8. Simple Serial Peripheral Interface (SSPI)
8.1 Contents
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8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 8.7 8.7.1 8.7.2 8.7.3 8.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Internal Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 SPDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 SPCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 SPSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 CLKGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 SSPI Data I/O (SDI and SDO). . . . . . . . . . . . . . . . . . . . . .107 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Serial Peripheral Control Register. . . . . . . . . . . . . . . . . . .110 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . .112 Serial Peripheral Data Register. . . . . . . . . . . . . . . . . . . . .113 Port Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
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Freescale Semiconductor, Inc. Simple Serial Peripheral Interface (SSPI) REQUIRED 8.2 Introduction
The simple serial peripheral interface (SSPI) of the MC68HC05L5 is a master/slave synchronous serial communication module. SSPI uses a 3-wire protocol: data input, data output, and serial clock. In this format, the clock is not being included in the data stream and must be provided as a separate signal. When the SSPI is enabled (SPE = 1), bits 0-2 of port C become SDI (serial data in), SDO (serial data out), and SCK (serial clock) pins. The corresponding DDRC bit does not change the direction of the pin. The MSTR bit decides the SSPI operation mode. The SCK pin is configured as output in master mode and configured as input in slave mode. The DORD bit in the serial peripheral control register (SPCR) selects the data transmission order. When DORD is set, the least significant bit (LSB) of serial data is shifted out/in first. When the DORD is clear, serial data is shifted from/to the most significant bit (MSB). Master serial clock speed is selected by the SPR bit in the SPCR. An interrupt may be generated by the completion of a transfer.
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Features of the SSPI are: * * * * * * * Full-duplex, 3-wire synchronous transfers Master or slave operation Programmable data transmission order, LSB or MSB first 1.05-MHz (maximum) transmission bit frequency at 2.1-MHz CPU bus frequency at 5 Vdc Two programmable transmission bit rates End-of-transmission interrupt flag Wakeup from stop mode (slave mode only)
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Simple Serial Peripheral Interface (SSPI) Functional Descriptions
8.4 Functional Descriptions
In master mode, the clock start logic is triggered by the CPU (detection of a CPU write to the 8-bit shift register (SPDR)). The SCK is based on the internal processor clock. This clock is also used in the 3-bit counter and 8-bit shift register. See Figure 8-2. When data is written to the 8-bit shift register of the master device, it is then shifted out to the SDO pin for application to the slave device. At the same time, data applied from the slave device via the SDI pin is shifted into the 8-bit shift register. After 8-bit data is shifted in/out, SCK stops and SPIF is set. If SPIE is enabled, an interrupt request is generated. The slave device in stop mode wakes up by this interrupt. Further transfers (writes to SPDR) are inhibited while SPIF is a logic 1. The master-slave basic interconnection is illustrated in Figure 8-1.
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MASTER DEVICE
SDO SPDR HFF SDI
SLAVE DEVICE
SPDR HFF
SCK
SCK
CLOCK GENERATOR SDI SDO
CLOCK GENERATOR
Figure 8-1. SSPI Master-Slave Interconnection
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Freescale Semiconductor, Inc. Simple Serial Peripheral Interface (SSPI) REQUIRED 8.5 Internal Block Descriptions
The following paragraphs describe the main blocks in the SSPI module. (See Figure 8-2).
HC05 INTERNAL BUS INTERRUPT CONTROLS AND ADDRESS BUS CONTROL LOGIC DATA BUS
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0 0 0 0 00 SPSR S P I F D C O L S T A R T S P E
00 0 SPCR MS SP TR R SPDR HFF SDO
DORD
SDI
CLOCK GENERATOR
SCK
Figure 8-2. SSPI Block Diagram
NON-DISCLOSURE
8.5.1 Control This block is an interface to the HC05 internal bus and generates a start signal when a write to the SPDR is detected in master mode. It also generates an interrupt request to the CPU.
8.5.2 SPDR This serial peripheral data register (SPDR) is an 8-bit shift register. The DORD bit in the SPCR determines the bus connection between the internal data bus and SPDR. This register can be read and written by the CPU.
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Simple Serial Peripheral Interface (SSPI) Signal Descriptions
8.5.3 SPCR Bits in the serial peripheral control register (SPCR) control SSPI functions.
8.5.4 SPSR The serial peripheral status register (SPSR) mainly sets flags such as SPIF and DCOL.
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8.5.5 CLKGEN In master mode, this block generates SCK when the CPU writes to the data register (SPDR) and the clock rate is selected by the SPR bit in the control register. In slave mode, the external clock from the SCK pin is used instead of the master mode clock, and SPR has no affect. This clock generator includes a 3-bit clock counter. Overflow of this counter sets SPIF.
8.6 Signal Descriptions
Three basic signals -- SDI, SDO, and SCK -- are described in the following subsections. The relationship among SCK, SDI, and SDO is shown in Figure 8-3.
8.6.1 SSPI Data I/O (SDI and SDO) The two serial data lines -- SDI for input and SDO for output -- are connected to PC0 and PC1, respectively, when SSPI is enabled (SPE = 1). At the falling edge of SCK, a serial data bit is transmitted out of the SDO pin. At the rising edge of SCK, a serial data bit on the SDI pin is sampled internally.
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SCK
SDO DORD = 0
MSB
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
SDI DORD = 0
MSB
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
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SDO DORD = 1
LSB
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
MSB
SDI DORD = 1
LSB
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
MSB
DATA SAMPLE
Figure 8-3. SSPI Clock-Data Timing Diagram When data is transmitted to other devices via the SDO line, the receiving data is shifted into the shift register through the SDI pin. This implies fullduplex transmission with both data-out and data-in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full status bits. A single status bit, SPIF, is used to signify the completion of data transfer.
NON-DISCLOSURE
8.6.2 Serial Clock (SCK) SCK is used for synchronization of both input and output data streams through its SDI and SDO pins. The master and slave devices are capable of exchanging a data byte during a sequence of eight clock pulses. Since the SCK is generated by
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Simple Serial Peripheral Interface (SSPI) Registers
the master, slave data transfer is accomplished by synchronization to SCK. The master generates the SCK through a circuit driven by the internal processor clock and uses the SCK to latch incoming slave device data on the SDI pin and shift out data to the slave via the SDO pin. The SPR bit in the SPCR of the master selects the transmission clock rate. The slave device receives the SCK from the master device, and uses the SCK to latch incoming master device data on the SDI pin and shifts out data to the master via the SDO pin. The SPR bit in the SPCR of the slave has no meaning.
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NOTE:
PC2/SCK should be at VDD level before SSPI is enabled. This can be done with an internal or external pullup resistor or by setting DDRC2 = 1 and PC2 = 1 prior to enabling the SSPI. Otherwise, the circuit will not initialize correctly.
8.7 Registers
Three registers are in the SSPI provide control, status, and data storage functions. They are: * * * Serial peripheral control register, SPCR location $000A Serial peripheral status register, SPSR location $000B Serial peripheral data register, SPDR location $000C
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8.7.1 Serial Peripheral Control Register
Address: $000A Bit 7 Read: SPIE Write: Reset: 0 0 0 0 0 0 0 0 SPE DORD MSTR 0 0 0 SPR 6 5 4 3 2 1 Bit 0
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Figure 8-4. Serial Peripheral Control Register (SPCR) SPIE -- SSPI Interrupt Enable If the serial peripheral interrupt enable (SPIE) bit is set, an interrupt is generated when SPIF in the SPSR is set and I bit (interrupt mask bit) in the condition code register (CCR) is clear. During stop mode, an SSPI request is accepted only in slave mode. Interrupt in master mode will be pending until stop mode is exited. STOP instruction does not change SPIF and SPIE. 0 = Disable SSPI interrupt 1 = Enable SSPI interrupt SPE -- SSPI Enable When the SSPI enable (SPE) bit is set, the SSPI system is enabled and connected to the port C pins. Clearing the SPE bit initializes all control logic in the SSPI modules and disconnects the SSPI from port C pins. This bit is cleared on reset. 0 = Disable SSPI 1 = Enable SSPI
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Simple Serial Peripheral Interface (SSPI) Registers
DORD -- Data Transmission ORDer When this bit is set, the data in the 8-bit shift register (SPDR) is shifted in/out from the LSB. When this bit is cleared, the data in the SPDR is shifted in/out from the MSB. This bit is cleared on reset. 0 = MSB first 1 = LSB first MSTR -- MaSTeR Mode Select
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In master mode (MSTR = 1), the SCK pin is configured as an output and the serial clock is generated by the internal clock generator when the CPU writes to the SPDR. In slave mode (MSTR = 0), the SCK pin is configured as an input and the serial clock is applied externally. This bit is cleared on reset. 0 = Slave mode 1 = Master mode Bits 3-1 -- Reserved These bits are not used and are fixed to 0. SPR -- SSPI Clock Rate Select This serial peripheral clock rate bit selects one of two bit rates of SCK. This bit is cleared on reset. 0 = Internal processor clock divided by 2 1 = Internal processor clock divided by 16
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The MSTR bit determines whether the device is in master mode or slave mode.
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Freescale Semiconductor, Inc. Simple Serial Peripheral Interface (SSPI) REQUIRED
8.7.2 Serial Peripheral Status Register
Address: $000B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 SPIF 6 DCOL 5 0 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
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Figure 8-5. Serial Peripheral Status Register (SPSR) SPIF -- Serial Transfer Complete Flag The serial peripheral data transfer complete flag bit notifies the user that a data transfer between the MC68HC05L5 and an external device has been completed. With the completion of the data transfer, the rising edge of the eighth pulse sets SPIF, and if SPIE is set, SSPI is generated. However, during STOP, the interrupt request is serviced only in slave mode. STOP execution never affects the SPIF flag or SPIE. When SPIF is set, the ninth clock from the clock generator or from the SCK pin is inhibited. Clearing the SPIF bit is done by a software sequence of accessing the SPSR while the SPIF bit is set followed by accessing SPDR (8-bit shift register). This also clears the DCOL bit. While SPIF is set, all writes to the SPDR are inhibited until SPSR is read by the CPU. The SPIF bit is a read-only bit and is cleared on reset. 0 = Data transfer not complete 1 = Data transfer complete DCOL -- Data COLlision The data collision bit notifies the user that an attempt was made to write or read the serial peripheral data register while a data transfer was taking place with an external device. The transfer continues uninterrupted; therefore, a write will be unsuccessful, and a data read will be incorrect.
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Simple Serial Peripheral Interface (SSPI) Registers
A data collision only sets the DCOL bit and does not generate an SSPI interrupt. The DCOL bit indicates only the occurrence of data collision. Clearing the DCOL bit is done by a software sequence of accessing the SPSR while SPIF is set followed by accessing the SPDR. Both the SPIF and DCOL bits will be cleared by this sequence. The DCOL bit is cleared on reset. 0 = No data collision 1 = Data collision occurred
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Bits 5-0 -- Reserved These bits are not used and are fixed to 0.
8.7.3 Serial Peripheral Data Register
Address: $000C Bit 7 Read: MSB Write: Reset: Unaffected by Reset BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 2 LSB 6 5 4 3 2 1 Bit 0
Figure 8-6. Serial Peripheral Data Register (SPDR) Read A read during transmission causes DCOL to be set. Write A write during transmission causes DCOL to be set. The SPDR is used to transmit and receive data on the serial bus. In master mode, a write to this register initiates transmission/reception of a data byte. The SPIF status bit is set at the completion of data byte transmission. A write to the SPDR is inhibited while this register is shifting (a write
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attempt sets DCOL) or when the SPIF bit is set without reading SPSR. Data collision never affects the receiving and transmitting data in SPDR. A write or read of the SPDR after accessing the SPSR with SPIF set will clear the SPIF and DCOL bits. The ability to access the SPDR is inhibited when a transmission is taking place. It is important to read the discussion defining the DCOL and SPIF bits to understand the limits on using the SPDR. When SSPI is not used (SPE = 0), the SPDR can be used as a generalpurpose data storage register.
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8.8 Port Function
The SSPI shares I/O pins with PC0-PC2. When SPE is set, PC0 becomes SDI input, PC1 becomes SDO output and PC2 becomes SCK. The direction of SCK depends on the MSTR bit. Setting DDRC bits 0-2 does not change the data direction of the pin to output, but instead changes the source of data when PC0-PC2 is read. If DDRCx = 1, port C bit x data latch is read and if DDRCx = 0, PORTCx pin level is read by the CPU. When SPE is clear, SSPI is disconnected from the I/O pins and PC0-PC2 are used as general-purpose I/O pins. See 6.5 Port C.
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General Release Specification -- MC68HC05L5
Section 9. Timer System
9.1 Contents
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General Release Specification 115
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9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Output Compare Register . . . . . . . . . . . . . . . . . . . . . . . . .119 Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Timer During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .123 Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .123 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .128 Timer Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . .130 Output Compare Register 2 . . . . . . . . . . . . . . . . . . . . . . .131 Timer Counter Register 2 . . . . . . . . . . . . . . . . . . . . . . . . .131 Timebase Control Register 1. . . . . . . . . . . . . . . . . . . . . . .132 Timer Input 2 (EVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Event Output (EVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
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Freescale Semiconductor, Inc. Timer System REQUIRED 9.2 Introduction
The MC68HC05L5 has two timer modules: timer 1 with a 16-bit counter and timer 2 with an 8-bit counter. Timer 1 has one input pin (TCAP) and no output pin. Timer 2 has one input pin (EVI) and one output pin (EVO). Figure 9-1 illustrates the timer system of the MC68HC05L5.
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AGREEMENT
CAP
OVF1 TIMER1 16-BIT COUNTER
TCAP
INPUT CONTROL 1 CLK1
CMP1
IEDG
T2CLK
EXCLK
EVI
INPUT CONTROL 2
CLK2
SEL
TIMER2 8-BIT COUNTER
CMP2
OUTPUT CONTROL
EVO
IM2
IL2 O L 2 O E 2
NON-DISCLOSURE
PH2
PRESCALER
TIMER REGISTERS
Figure 9-1. Timer System Block Diagram
General Release Specification 116 Timer System For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Timer 1
9.3 Timer 1
Timer 1 consists of a 16-bit software-programmable counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output compare interrupt. Pulse widths can vary from several microseconds to many seconds. See Figure 9-2.
INTERNAL BUS
Freescale Semiconductor, Inc...
HIGH BYTE
LOW BYTE
INTERNAL PROCESSOR CLOCK
8-BIT BUFFER HIGH LOW BYTE BYTE
/4 $16 $17 OUTPUT COMPARE REGISTER HIGH BYTE 16-BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER LOW BYTE $18 $19
INPUT CAPTURE REGISTER
$14 $15
$1A $1B
OUTPUT COMPARE CIRCUIT
OVERFLOW DETECT CIRCUIT
EDGE DETECT CIRCUIT
TIMER STATUS REGULAR
ICF
OCF
TOF
$13
OUTPUT LEVEL REGULAR
DQ CLK C
ICIE
OCIE
TOIE
IEDG
TIMER RESET OLVL CONTROL REGULAR $12 (TCMP) OUTPUT EDGE INPUT LEVEL (TCAP) (NOT CONNECTED TO A PIN)
INTERRUPT CIRCUIT
Figure 9-2. Timer 1 Block Diagram
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com
General Release Specification 117
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. These registers contain the high byte and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is accessed also.
NOTE:
Freescale Semiconductor, Inc...
AGREEMENT
The I bit in the condition code register (CCR) should be set while manipulating both the high byte and low byte register of a specific timer function to ensure that an interrupt does not occur.
9.3.1 Counter The key element in the programmable timer is a 16-bit, free-running counter or counter register preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations: $18-$19 (counter register) or $1A-$1B (counter alternate register). A read from only the least significant byte (LSB) of the freerunning counter ($19, $1B) receives the count value at the time of the read. If a read of the free-running counter or counter alternate register first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be read to complete the sequence. The counter alternate register differs from the counter register in one respect: A read of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF.
General Release Specification 118 Timer System For More Information On This Product, Go to: www.freescale.com MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
NON-DISCLOSURE
Freescale Semiconductor, Inc.
Timer System Timer 1
The free-running counter is configured to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator startup delay. Because the free-running counter is 16 bits preceded by a fixed dividedby-4 prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt also can be enabled when counter roll over occurs by setting its interrupt enable bit (TOIE).
Freescale Semiconductor, Inc...
The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. The output compare register contents are compared with the contents of the free-running counter continually, and if a match is found, the corresponding output compare flag (OCF) bit is set. The output compare register values should be changed after each successful comparison to establish a new elapsed timeout. An interrupt also can accompany a successful output compare, provided the corresponding interrupt enable bit (OCIE) is set. After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) also is written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com
General Release Specification 119
NON-DISCLOSURE
AGREEMENT
9.3.2 Output Compare Register
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
9.3.3 Input Capture Register Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the timer used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the freerunning counter transfer since they occur on opposite edges of the internal bus clock.
NON-DISCLOSURE
Freescale Semiconductor, Inc...
AGREEMENT
NOTE:
Since the TCAP pin is shared with the PC3 I/O pin, changing the state of the PC3 DDR or data register can cause an unwanted TCAP interrupt. This can be handled by clearing the ICIE bit before changing the configuration of PC3 and clearing any pending interrupts before enabling ICIE.
General Release Specification 120 Timer System For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Timer 1
9.3.4 Timer Control Register The TCR is a read/write register containing five control bits. Three bits enable interrupts associated with the timer status register flags ICF, OCF, and TOF.
Address: $0012 Bit 7 Read: Write: ICIE 0 U = Unaffected 6 OC1IE 0 5 TOIE 0 4 0 0 3 0 0 2 0 0 1 IEDG U Bit 0 OLVL 0
Freescale Semiconductor, Inc...
Reset:
Figure 9-3. Timer Control Register (TCR) ICIE -- Input Capture Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled OC1IE -- Output Compare 1 Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled TOIE -- Timer Overflow Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled IEDG -- Input Edge The value of the input edge determines which level transition on the TCAP pin will trigger free-running counter transfer to the input capture register. Reset does not affect the IEDG bit. 0 = Negative edge 1 = Positive edge Bits 2-4 -- Not Used Always read logic 0 OLVL -- Not Used Always read logic 0
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com General Release Specification 121
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
9.3.5 Timer Status Register The TSR is a read-only register containing three status flag bits.
Address: $0013 Bit 7 Read: Write: ICF 6 OC1F 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0
Freescale Semiconductor, Inc...
AGREEMENT
Reset:
U
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 9-4. Timer Status Register (TSR) ICF -- Input Capture Flag 0 = Flag cleared when TSR and input capture low register ($15) are accessed 1 = Flag set when selected polarity edge is sensed by input capture edge detector OC1F -- Output Compare 1 Flag 0 = Flag cleared when TSR and output compare low register ($17) are accessed 1 = Flag set when output compare register contents match the freerunning counter contents TOF -- Timer Overflow Flag 0 = Flag cleared when TSR and counter low register ($19) are accessed 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs Bits 0-4 -- Not Used Always read logic 0 Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit.
NON-DISCLOSURE
General Release Specification 122 Timer System For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Timer 1
A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set. 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag.
Freescale Semiconductor, Inc...
9.3.6 Timer During Wait Mode The CPU clock halts during wait mode, but timer 1 remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode.
9.3.7 Timer During Stop Mode In stop mode, timer 1 stops counting and holds the last count value if STOP is exited by an interrupt. If RESET is used, the counter is forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake up the MCU. When the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during stop mode. If RESET is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com
General Release Specification 123
NON-DISCLOSURE
AGREEMENT
The counter alternate register at address $1A and $1B contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register.
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED 9.4 Timer 2
Timer 2 is an 8-bit event counter which has one compare register, one event input pin (EVI), and one event output pin (EVO). The event counter is clocked by the external clock (EXCLK) or prescaled system clock (CLK2), selected by the T2CLK bit in the TCR2 register. The EXCLK may be EVI direct or EVI gated by CLK2, which is selected by the IM2 bit at the EVI block (see 9.4.6 Timer Input 2 (EVI)). Timer 2 may be used as a modulus clock divider with EVO pin, freerunning counter (when compare register is $00), or periodic interrupt timer. The timer counter 2 (TCNT2) is an 8-bit up counter with preset input. The counter is preset to $01 by a CMP2 signal from the comparator or by a CPU write to it that is done while the system clock (PH2) is low.
Freescale Semiconductor, Inc...
AGREEMENT
COUNTER WRITE
CLK2
0
$01 S E L COUNTER 2
$01
NON-DISCLOSURE
EXCLK
1
T2CLK COMPARATOR 2 BUFFER 2 TRANSFER TRANSFER CMP2
REGISTER (OC2)
Figure 9-5. Timer 2 Block Diagram
General Release Specification 124 Timer System For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Timer 2
The CLK2 from the prescaler or the EXTCLK from the EVI block is selected as timer clock by the T2CLK bit in the TCR2 register. The CLK2 and the EXCLK are synchronized to the falling edge of system clock in the prescaler and the EVI blocks. The minimum pulse width of CLK2 is the same as the system clock, and the minimum pulse width of EXCLK (event mode) is one PH2 cycle. When the EXCLK (event mode) is selected, 50% duty is not guaranteed. The counter is incremented by the falling edge of the timer clock and the period between two falling edges is defined as one timer cycle in the following description. The compare register (OC2) is provided for comparison with the timer counter 2 (TCNT2). The OC2 data is transferred to the buffer register when the counter is preset by a CPU write or by a compare output (CMP2). This buffer register is compared with the timer counter 2 (TCNT2). The comparison between the counter and the OC2 buffer register is done when the system clock is high in each bus cycle. If the counter matches with the OC2 buffer register, the comparator latches this result during the current timer cycle. When the next timer cycle begins, the comparator outputs CMP2 signal (if the compare match is detected during previous timer cycle). This CMP2 is used in the counter preset data transfer to the buffer register, setting OC2F in the TSR2 and the EVO block. The counter preset overrides the counter increment. The OC2F bit may generate interrupt requests if the OC2IE bit in the TCR2 is set.
Freescale Semiconductor, Inc...
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com
General Release Specification 125
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
OC2 = 2, 3, 4 . . . FF, 0
COUNT UP COMPARE PH2 COUNT UP COUNT UP
TIMCLK PRESET COUNTER2 N 01
Freescale Semiconductor, Inc...
AGREEMENT
OC2 (BUFFER)
N
CMP2
EVO
OC2 = 1
COUNT UP COMPARE PH2 COUNT UP COUNT UP
NON-DISCLOSURE
TIMCLK PRESET COUNTER2 01 PRESET 01 PRESET
OC2 (BUFFER)
01
CMP2
EVO
Figure 9-6. Timer 2 Timing Diagram for f(PH2) > f(TIMCLK)
General Release Specification 126 Timer System For More Information On This Product, Go to: www.freescale.com MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Timer 2
OC2 = 2, 3, 4 . . . FF, 0
1 2 PH2 1 2 1 2 1 2
TIMCLK
3
COUNTER2 N-1 N 01 02
Freescale Semiconductor, Inc...
OC2 (BUFFER)
N
CMP2
EVO Legend: 1. COUNT UP 2. COMPARE 3. PRESET that overrides COUNT UP
OC2 = 1
1 2 PH2
1 2
1 2
1 2
TIMCLK 3 COUNTER2 01 3 01 3 01 3 01
OC2 (BUFFER)
01
CMP2
EVO Legend: 1. COUNT UP 2. COMPARE 3. PRESET that overrides COUNT UP
Figure 9-7. Timer 2 Timing Diagram for f(PH2) = f(TIMCLK)
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com General Release Specification 127
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
9.4.1 Timer Control Register 2
Address: $001C BIt 7 Read: TI2IE Write: Reset: 0 0 0 0 0 0 0 0 OC2IE 0 T2CLK IM2 IL2 OE2 OL2 6 5 4 3 2 1 Bit 0
Freescale Semiconductor, Inc...
AGREEMENT
Figure 9-8. Timer Control Register 2 (TCR2) TI2IE -- Timer Input 2 Interrupt Enable The TI2IE bit enables timer input 2 (EVI) interrupt when TI2F is set. This bit is cleared on reset. 0 = Timer input 2 interrupt disabled 1 = Timer input 2 interrupt enabled OC2IE -- Compare 2 Interrupt Enable The OC2IE bit enables compare 2 (CMP2) interrupt when compare match is detected (OC2F is set). This bit is cleared on reset. 0 = Timer input 2 interrupt disabled 1 = Timer input 2 interrupt enabled Bit 5 -- Reserved This bit is not used and is always read as logic 0. T2CLK -- Timer 2 Clock Select The T2CLK bit selects the clock source for the timer counter 2. This bit is cleared on reset. 0 = CLK2 from prescaler selected 1 = EXCLK from EVI input block selected IM2 -- Timer Input 2 Mode Select The IM2 bit selects whether EVI input is gated or not gated by CLK2. This bit is cleared on reset. 0 = EVI not gated by CLK2 (event mode) 1 = EVI gated by CLK2 (gate mode)
NON-DISCLOSURE
General Release Specification 128 Timer System For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Timer 2
IL2 -- Timer Input 2 Active Edge (Level) Select The IL2 bit selects the active edge of EVI to increment the counter for event mode (IM2 = 0) or gate enable level of EVI for gate mode (IM2 = 1). This bit is cleared on reset. 0 = Falling edge selected (event mode) Low level enables counting (gate mode) 1 = Rising edge selected (event mode) High level enables counting (gate mode)
Freescale Semiconductor, Inc...
IM2 0 0 1 1
IL2 0 1 0 1
Action on Clock Falling edge of EVI increments counter Rising edge of EVI increments counter Low level on EVI enables counting High level on EVI enables counting
OE2 -- Timer Output 2 (EVO) Output Enable The OE2 bit enables EVO output on the PC5 pin. When this bit is changed, control of the pin is delayed (synchronized) until the next active edge of EVO is selected by the OL2 bit. This bit is cleared on reset. 0 = EVO output disabled 1 = EVO output enabled OL2 -- Timer Output 2 Edge Select for Synchronization The OL2 bit selects which edge of EVO clock should be synchronized by the OE2 bit control. The OL2 bit also decides the initial value of the CMP2 divider, when counter 2 is written to by the CPU. This bit is cleared on reset. 0 = The falling edge of EVO switches EVO output and PC5 if the OE2 bit has been changed. 1 = The rising edge of EVO switches EVO output and PC5 if the OE2 bit has been changed.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com
General Release Specification 129
NON-DISCLOSURE
AGREEMENT
Table 9-1. EVI Modes Selection
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
9.4.2 Timer Status Register 2
Address: Read: Write: Reset: 0 0 $001D BIt 7 TI2F 6 OC2F 5 0 0 4 0 0 3 0 RTI2F 0 2 0 ROC2F 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 9-9. Timer Status Register 2 (TSR2)
AGREEMENT
Freescale Semiconductor, Inc...
TI2F -- Timer Input 2 (EVI) Interrupt Flag In event mode, the event edge sets TI2F. In gated time accumulation mode, the trailing edge of the gate signal at the EVI input pin sets TI2F. When the TI2IE bit and this bit are set, an interrupt is generated. This bit is a read-only bit and writes have no effect. The TI2F is cleared by writing a logic 1 to the RTI2F bit and on reset. OC2F -- Compare 2 Interrupt Flag The OC2F bit is set when compare match is detected between counter 2 and OC2 register. When OC2IE bit and this bit are set, an interrupt is generated. This bit is a read-only bit and writes have no effect. The OC2F is cleared by writing a logic 1 to ROC2F bit and on reset. Bits 5 and 4 -- Reserved These bits are not used and always read as logic 0. RTI2F -- Reset Timer Input 2 Flag The RTI2F bit is a write-only bit and always reads as logic 0. Writing logic 1 to this bit clears the TI2F bit and writing a logic 0 to this bit has no effect. ROC2F -- Reset Output Compare 2 Flag The ROC2F bit is a write-only bit and always reads as logic 0. Writing logic 1 to this bit clears the OC2F bit and writing a logic 0 to this bit has no effect. Bits 1 and 0 -- Reserved These bits are not used and always read as logic 0.
General Release Specification 130 Timer System For More Information On This Product, Go to: www.freescale.com MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
NON-DISCLOSURE
Freescale Semiconductor, Inc.
Timer System Timer 2
9.4.3 Output Compare Register 2
Address: $001E BIt 7 Read: BIT 7 Write: Reset: 0 0 0 0 0 0 0 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 6 5 4 3 2 1 Bit 0
Figure 9-10. Output Compare Register 2 (OC2)
Freescale Semiconductor, Inc...
The OC2 register data is transferred to the buffer register when the CPU writes to TCNT2, when the CMP2 presets the TCNT2, or when system resets. When the OC2 buffer register matches the TCNT2 register, the OC2F bit in the TSR2 register is set and TCNT2 is preset to $01.
9.4.4 Timer Counter Register 2
Address: $001F
Read: BIT 7 Write: Reset: 0 0 0 0 0 0 0 1 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Figure 9-11. Timer Counter Register 2 (TCNT2) TCNT2 is incremented by the falling edge of the timer clock, which is synchronized and has the same timing as the falling edge of PH2. The TCNT2 register is compared with the OC2 buffer register and initialized to $01 if it matches. It is also initialized to $01 on reset and any CPU write to this register. The CPU read of this counter should be done while PH2 is high. Data may be latched by the local or main data bus while PH2 is low.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com
General Release Specification 131
NON-DISCLOSURE
BIt 7
6
5
4
3
2
1
Bit 0
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
9.4.5 Timebase Control Register 1
Address: $0010 BIt 7 Read: TBCLK Write: Reset: 0 0 0 0 0 0 0 0 0 LCLK 0 0 0 T2R1 T2R0 6 5 4 3 2 1 Bit 0
Freescale Semiconductor, Inc...
AGREEMENT
Figure 9-12. Timebase Control Register 1 (TBCR1) T2R1/T2R0 -- Prescale Rate Select Bits for Timer 2 The T2R1 and T2R0 bits select prescale rate of CLK2 for timer 2 and timer input 2. These bits are cleared on reset. Table 9-2. Time Base Prescale Rate Selection
T2R1 0 0 1 1 T2R0 0 1 0 1 System Clock Divided by 1 4 32 256
NON-DISCLOSURE
9.4.6 Timer Input 2 (EVI) The event input (EVI) is used as an external clock input for timer 2.
TO TI2F
PC4 EVI
SYNC
ACTIVE EDGE/LEVEL SELECTOR
GATE/EVENT MODE CONTROL
EXCLK
PC4
PH2
IL2
IM2
CLK2
Figure 9-13. EVI Block Diagram
General Release Specification 132 Timer System For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Timer 2
Since the external clock may be asynchronous to the internal clock, this input has a synchronizer which samples external clock by the internal system clock. (The input transition synchronizes to the falling edge of PH2. Therefore, to be measured, the minimum pulse width for EVI must be larger than one system clock.) The IM2 and IL2 bits in the TCR2 determine how this synchronized external clock is used. The IM2 bit decides between event mode and gate mode, and the IL2 bit decides which level or edge is activated.
Freescale Semiconductor, Inc...
Table 9-3. EVI Modes Selection
IM2 0 0 1 1 IL2 0 1 0 1 Action on Clock Falling edge of EVI increments counter Rising edge of EVI increments counter Low level on EVI enables counting High level on EVI enables counting
In gate mode (IM2 = 1), the EVI input is gated by CLK2 from the prescaler and gate output drives the timer 2 counter. The IL2 bit decides active level of the external input. When the transition from active level to inactive level is detected, the TI2F bit is set. Changing the IM2 bit may cause an illegal count up of TCNT2, thus presetting TCNT2 after initializing IM2 is required.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com
General Release Specification 133
NON-DISCLOSURE
NOTE:
Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should always be cleared whenever EVI is used. EVI should not be used when DDRC4 is high.
AGREEMENT
In event mode (IM2 = 0), the external clock drives the timer 2 counter directly and the active edge at the EVI pin is selected by the IL2 bit. When an active edge is detected, the TI2F bit in the TCR2 is set.
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
IM2 = 0 Event Mode
EVI
PH2
EXCLK IL2 = 0 COUNTER X X+1 X+2
Freescale Semiconductor, Inc...
AGREEMENT
EXCLK IL2 = 1 COUNTER X X+1 X+2
IM2 = 1 Gate Mode
EVI SYNCHRONIZED CLK2
NON-DISCLOSURE
EXCLK IL2 = 0 COUNTER
EXCLK IL2 = 1 COUNTER
Figure 9-14. EVI Timing Diagram
General Release Specification 134 Timer System For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Timer 2
9.4.7 Event Output (EVO) The EVO pin is the clock output pin of timer 2. The compare output from the timer 2 (CMP2) is divided in this block for 50% duty output signal. This 1/2 divider is initialized to the level of the OL2 bit when the timer counter 2 is written to by the CPU (initialized). When the OE2 bit in the timer control register 2 (TCR2) is set, the EVO output is activated, and, when OE2 is cleared, EVO is deactivated. These controls must be done synchronously to the EVO output signal to avoid an incomplete pulse on the pin. The OL2 bit in the TCR2 decides which edge of EVO should be synchronized. When the DDRC5 bit is set or the synchronized output enable is high (clock on), the output buffer at the EVO/PC5 pin is enabled. If the DDRC5 bit is set to 1, the pin state during the idling condition (clock off) depends on the PC5 output data latch. If the DDRC5 bit is cleared, the pin becomes high impedance during clock off.
Freescale Semiconductor, Inc...
DDRC5 OE2 D Q
C
CMP2
1/2
1 SEL 0 PC5 EVO
CNTR2 WRITE
PC5 (OUT)
PC5 (IN)
Figure 9-15. EVO Block Diagram
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Timer System For More Information On This Product, Go to: www.freescale.com
General Release Specification 135
NON-DISCLOSURE
OL2
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Timer System REQUIRED
OL2 = 0
CNTR2 WRITE
CMP2
OE2
CMP2/2
AGREEMENT
Freescale Semiconductor, Inc...
EVO PC5 = 0/EVO
OL2 = 1
CMP2
OE2
NON-DISCLOSURE
CMP2/2 EVO PC5 = 1/EVO
Figure 9-16. EVO Timing Diagram
General Release Specification 136 Timer System For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Timer System Prescaler
9.5 Prescaler
The 8-bit prescaler in the timer system divides system clock (PH2) and provides divided clock to each timer and event input. CLK1 for timer 1 is a fixed frequency clock (PH2/PH4). CLK2 for timer 2 is selected by T2R1 and T2R0 bits in the TBCR1, and this clock is also used as the event input for gate mode. The CLK2 transitions must be synchronous to the falling edge of PH2.
Freescale Semiconductor, Inc...
Table 9-4. Timebase Prescale Rate Selection
T2R1 0 0 1 1 T2R0 0 1 0 1 System Clock Divided by 1 4 32 256
RST PH2 8-BIT DIVIDER
SEL 1 1 1 4 1 32 1 256 T2R1 T2R0
CLK2 FOR TIMER 2
Figure 9-17. Prescaler Block Diagram
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General Release Specification 137
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1 4
CLK1 FOR TIMER 1
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Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Section 10. LCD Driver
10.1 Contents
Freescale Semiconductor, Inc...
10.2 Introduction
The LCD driver may be configured with four backplanes (BP) and 39 frontplanes (FP) maximum. The VDD voltage is the highest level of the output waveform and the lower three levels are applied from VLCD1, VLCD2, and VLCD3 inputs. On reset, LCD enable bit (LCDE) in the LCD control register (LCDCR) is cleared (LCD drivers at a disabled state) and all BP pins and FP pins output VDD levels. The LCD clock is generated by the timebase module, and the LCLK bit in the TBCR1 selects the clock frequency.
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10.2 10.3 10.4 10.5 10.6 10.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 LCD Waveform Examples . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Backplane Driver and Port Selection . . . . . . . . . . . . . . . . . . .144 Frontplane Driver and Port Selection . . . . . . . . . . . . . . . . . . .145 LCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 LCD Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
REQUIRED
Freescale Semiconductor, Inc. LCD Driver REQUIRED 10.3 LCD Waveform Examples
Figure 10-1, Figure 10-2, Figure 10-3, and Figure 10-4 illustrate the LCD timing examples.
DUTY = 1/1 (STATIC) BIAS = 1/1 (VLCD1 = VDD, VLCD2 = VLCD3 = VDD-VLCD) 1 FRAME BP0 VDD, VLCD1 VLCD2, 3
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AGREEMENT
FPx (XXX1)
VDD, VLCD1 VLCD2, 3
FPy (XXX1)
VDD, VLCD1 VLCD2, 3
+VLCD BP0-FPx (0FF) 0 -VLCD
+VLCD BP0-FPy (ON) 0 -VLCD
NON-DISCLOSURE
Figure 10-1. LCD 1/1 Duty and 1/1 Bias Timing Diagram
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LCD Driver LCD Waveform Examples
DUTY = 1/2 BIAS = 1/2 (VLCD1 = VLCD2 = VDD-VLCD/2, VLCD3 = VDD-VLCD) 1 FRAME
VDD BP0 VLCD1, 2 VLCD3 VDD BP1 VLCD1, 2 VLCD3
Freescale Semiconductor, Inc...
FPX (XX01)
VDD VLCD1, 2 VLCD3
FPY (XX00)
VDD VLCD1, 2 VLCD3
VLCD VLCD/2 BP0-FPX (ON) 0
-VLCD
VLCD VLCD/2 BP1-FPX (OFF) 0 -VLCD/2 -VLCD
VLCD VLCD/2 BP0-FPY (0FF) 0 -VLCD/2 -VLCD
Figure 10-2. LCD 1/2 Duty and 1/2 Bias Timing Diagram
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-VLCD/2
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REQUIRED
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DUTY = 1/3 BIAS = 1/3 (VLCD1 = VDD-VLCD/3, VLCD2 = VDD-2VLCD/3, VLCD3 = VDD-VLCD) 1 FRAME VDD VLCD1 BP0 VLCD2 VLCD3
VDD
AGREEMENT
BP1
VLCD1 VLCD2 VLCD3
Freescale Semiconductor, Inc...
VDD BP2 VLCD1 VLCD2 VLCD3
VDD FPx (X010) VLCD1 VLCD2 VLCD3
NON-DISCLOSURE
+VLCD +2VLCD/3 BP0-FPx (OFF) +VLCD/3 0 -VLCD/3 -2VLCD/3 -VLCD
+VLCD +2VLCD/3 +VLCD/3 BP1-FPx (ON) 0 -VLCD/3 -2VLCD/3 -VLCD
Figure 10-3. LCD 1/3 Duty and 1/3 Bias Timing Diagram
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
LCD Driver LCD Waveform Examples
DUTY = 1/4 BIAS = 1/3 (VLCD1 = VDD-VLCD/3, VLCD2 = VDD-2VLCD/3, VLCD3 = VDD-VLCD) 1 FRAME VDD VLCD1 BP0 VLCD2 VLCD3
VDD BP1 VLCD1 VLCD2 VLCD3
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VDD BP2 VLCD1 VLCD2 VLCD3
VDD BP3 VLCD1 VLCD2 VLCD3
VDD FPX (1001) VLCD1 VLCD2 VLCD3 +VLCD +2VLCD/3 +VLCD/3 BP0-FPX (ON) 0 -VLCD/3 -2VLCD/3 -VLCD +VLCD +2VLCD/3 +VLCD/3 BP1-FPX (OFF) 0 -VLCD/3 -2VLCD/3 -VLCD
Figure 10-4. LCD 1/4 Duty and 1/3 Bias Timing Diagram
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NON-DISCLOSURE
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REQUIRED
Freescale Semiconductor, Inc. LCD Driver REQUIRED 10.4 Backplane Driver and Port Selection
The number of backplane (port D) pins depends on the LCD duty. It is automatically selected by DUTY1 and DUTY0 bits in the LCD control register (LCDCR). On reset, these bits are cleared and 1/4 duty is selected. (See Table 10-1.) Table 10-1. Backplane and Port Selection
LCD Control Pin Selection BP3/PD3 PD3 PD3 PD3 BP3 BP2/PD2 PD2 PD2 BP2 BP2 BP1/PD1 PD1 BP1 BP1 BP1 BP0 BP0 BP0 BP0 BP0 Duty DUTY1 1/1 1/2 1/3 1/4 0 1 1 0 DUTY0 1 0 1 0
NON-DISCLOSURE
General Release Specification 144 LCD Driver For More Information On This Product, Go to: www.freescale.com
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LCD Driver Frontplane Driver and Port Selection
10.5 Frontplane Driver and Port Selection
The number of frontplane (FP) pins depends on the number of port D and port E bits. If port bits are selected as a parallel output port, the number of the FP pins is decreased to 27 as a minimum. The selections between frontplane and port (nibble wide) are done by the PEH, PEL, and PDH bits in the LCDCR (see Table 10-2). On reset, port D and port E bits are disconnected and FP27-FP38 pins output VDD levels. Table 10-2. Frontplane and Port Selection
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FP / Port Control PEH PEL PDH 0 1 0 1 0 1 FP27:FP30 PE7:PE4 FP27:FP30/ PE7:PE4
Port Selection FP31:FP34/ PE3:PE0 FP35:FP38/ PD7:PD4 FP35:FP38 PD7:PD4 FP31:FP34 PE3:PE0
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REQUIRED
Freescale Semiconductor, Inc. LCD Driver REQUIRED 10.6 LCD Control Register
Address: $0020 Bit 7 Read: LCDE Write: Reset: 0 0 0 0 0 0 0 0 DUTY1 DUTY0 0 PEH PEL PDH 0 6 5 4 3 2 1 Bit 0
Figure 10-5. LCD Control Register (LCDCR)
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LCDE -- LCD Output Enable The LCDE bit enables all BP and FP outputs. (This bit does not affect PEH, PEL, or PDH bits.) This bit is cleared on reset. 0 = All dedicated FP pins output highest (VDD) level; BP and FP pins are shared with an output port data. 1 = All BP and FP pins output LCD waveforms. DUTY1 and DUTY0 -- LCD Duty Select The DUTY1 and DUTY0 bits select the duty of the LCD driver. The number of BP pins is related to this duty selection. The unused BP pin is used as a port D pin. Default duty is 1/4 duty. These bits are cleared on reset. See Table 10-1. Bit 4 -- Reserved This bit is not used and always reads as logic 0. PEH -- Select Port E (H) The PEH bit enables the upper four bits of port E instead of LCD drivers. This bit is cleared on reset. See 10.5 Frontplane Driver and Port Selection. 0 = FP27-FP30 selected 1 = PE7-PE4 selected
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
LCD Driver LCD Control Register
PEL -- Select Port E (L) The PEL bit enables the lower four bits of port E instead of LCD drivers. This bit is cleared on reset. See 10.5 Frontplane Driver and Port Selection. 0 = FP31-FP34 selected 1 = PE3-PE0 selected PDH -- Select Port D (H) The PDH bit enables the upper four bits of port D instead of LCD drivers. This bit is cleared on reset. See 10.5 Frontplane Driver and Port Selection. 0 = FP35-FP38 selected 1 = PD7-PD4 selected Bit 0 -- Reserved This bit is not used and is always read as logic 0.
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Freescale Semiconductor, Inc. LCD Driver REQUIRED 10.7 LCD Data Register
Address: $0021-$0034 FP (2x-1) Bit 7 Read: BP3 Write: Reset: Unaffected by Reset BP2 BP1 BP0 BP3 BP2 BP1 BP0 6 5 4 3 2 FP (2x-2) 1 Bit 0
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Figure 10-6. LDC Data Registers LCDRx -- LCD Data Registers Data in the LCDRx (LCDR1-LCDR20) controls the waveform of the two frontplane drivers. Bits 0-3 and bits 4-7 of this register decide the waveforms at the BP0-BP3 timings. If the LCD duty is not 1/4, the register bit for the unused backplane has no meaning. The upper four bits of LCDR20 are not implemented and unknown data may be read. (See Table 10-3.) 0 = Output deselect waveform at the corresponding backplane timing 1 = Output select waveform at the corresponding backplane timing Table 10-3. Frontplane Data Register Bit Usage
Frontplane Data Register Bit Usage Duty Bit 7 1/1 1/2 1/3 1/4 -- -- -- BP3 Bit 6 -- -- BP2 BP2 Bit 5 -- BP1 BP1 BP1 Bit 4 BP0 BP0 BP0 BP0 Bit 3 -- -- -- BP3 Bit 2 -- -- BP2 BP2 Bit 1 -- BP1 BP1 BP1 Bit 0 BP0 BP0 BP0 BP0
NON-DISCLOSURE
General Release Specification 148
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Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Section 11. Instruction Set
11.1 Contents
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General Release Specification 149
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11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 11.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 11.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .154 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .155 11.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .156 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .158 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 11.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
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REQUIRED
Freescale Semiconductor, Inc. Instruction Set REQUIRED 11.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.
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11.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative
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General Release Specification 150
MC68HC(7)05L5 -- Rev. 2.0 Instruction Set For More Information On This Product, Go to: www.freescale.com MOTOROLA
Freescale Semiconductor, Inc.
Instruction Set Addressing Modes
11.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
11.3.2 Immediate
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Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
11.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
11.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
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11.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.
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11.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
NON-DISCLOSURE
11.3.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.
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Instruction Set Instruction Types
11.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction.
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11.4 Instruction Types
The MCU instructions fall into the following five categories: * * * * * Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions
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When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
REQUIRED
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11.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1. Register/Memory Instructions
Instruction Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
AGREEMENT
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Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator
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Freescale Semiconductor, Inc.
Instruction Set Instruction Types
11.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 11-2. Read-Modify-Write Instructions
Instruction Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2)
Freescale Semiconductor, Inc...
Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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11.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register.
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Instruction Set Instruction Types
Table 11-3. Jump and Branch Instructions
Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL
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Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine
BRCLR BRN BRSET BSR JMP JSR
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BRA
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11.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 11-4. Bit Manipulation Instructions
Instruction Mnemonic BCLR BRCLR BRSET BSET
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Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
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Instruction Set Instruction Types
11.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 11-5. Control Instructions
Instruction Clear Carry Bit Clear Interrupt Mask Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA
WAIT
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No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts
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Freescale Semiconductor, Inc. Instruction Set REQUIRED 11.5 Instruction Set Summary
Table 11-6. Instruction Set Summary
Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Operation
Description
H I NZC
Add with Carry
A (A) + (M) + (C)
--
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AGREEMENT
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
A9 ii 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 A4 ii 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
----
--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----
NON-DISCLOSURE
ff
dd
Arithmetic Shift Right
b7 b0
C
----
ff
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
rr dd dd dd dd dd dd dd dd rr rr rr rr
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL
BCS rel BEQ rel BHCC rel BHCS rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1
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Cycles
Effect on CCR
Operand
Address Mode
Opcode
Freescale Semiconductor, Inc.
Instruction Set Instruction Set Summary
Table 11-6. Instruction Set Summary (Continued)
Source Form
BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low
Operation
Description
H I NZC
PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 ---------- ---------- ----------
REL REL REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL
22 24 2F 2E
rr rr rr rr
3 3 3 3
Freescale Semiconductor, Inc...
Bit Test Accumulator with Memory Byte
(A) (M)
----
--
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1
----------
25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E
rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd
3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1 ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if Bit n Clear
PC (PC) + 2 + rel ? Mn = 0
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
----------
REL
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSET n opr
Set Bit n
Mn 1
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Instruction Set For More Information On This Product, Go to: www.freescale.com
General Release Specification 161
NON-DISCLOSURE
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
AGREEMENT
A5 ii 2 B5 dd 3 C5 hh ll 4 D5 ee ff 5 E5 ff 4 F5 3
Cycles
Effect on CCR
REQUIRED
Operand
Address Mode
Opcode
Freescale Semiconductor, Inc. Instruction Set REQUIRED
Table 11-6. Instruction Set Summary (Continued)
Source Form Operation Description
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0 M $00 A $00 X $00 M $00 M $00
H I NZC
Branch to Subroutine ----------
BSR rel
REL
AD
rr
6
CLC CLI
Clear Carry Bit Clear Interrupt Mask
-------- 0 -- 0 ------
INH INH DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX
98 9A 3F 4F 5F 6F 7F dd
2 2 5 3 3 6 5
Freescale Semiconductor, Inc...
AGREEMENT
CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X
Clear Byte
---- 0 1 --
ff
Compare Accumulator with Memory Byte
(A) - (M)
----
A1 ii 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M)
----
1
ff
NON-DISCLOSURE
Compare Index Register with Memory Byte
(X) - (M)
----
A3 ii 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
----
--
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
----
--
A8 ii 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
----
--
ff
General Release Specification 162 Instruction Set For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Cycles
Effect on CCR
Operand
Address Mode
Opcode
Freescale Semiconductor, Inc.
Instruction Set Instruction Set Summary
Table 11-6. Instruction Set Summary (Continued)
Source Form
JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X
Operation
Description
H I NZC
Unconditional Jump
PC Jump Address
----------
DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX
BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 A6 ii 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2
Freescale Semiconductor, Inc...
Jump to Subroutine
Load Accumulator with Memory Byte
A (M)
----
--
Load Index Register with Memory Byte
X (M)
----
--
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff
dd
Logical Shift Right
0 b7 b0
C
---- 0
ff
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
Negate Byte (Two's Complement)
----
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
----
--
AA ii 2 BA dd 3 CA hh ll 4 DA ee ff 5 EA ff 4 FA 3
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Instruction Set For More Information On This Product, Go to: www.freescale.com
General Release Specification 163
NON-DISCLOSURE
AGREEMENT
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address
----------
Cycles
Effect on CCR
REQUIRED
Operand
Address Mode
Opcode
Freescale Semiconductor, Inc. Instruction Set REQUIRED
Table 11-6. Instruction Set Summary (Continued)
Source Form
ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
H I NZC
Rotate Byte Left through Carry Bit
C b7 b0
----
DIR INH INH IX1 IX DIR INH INH IX1 IX INH
39 49 59 69 79 36 46 56 66 76 9C
dd
ff
5 3 3 6 5 5 3 3 6 5 2
dd
Freescale Semiconductor, Inc...
AGREEMENT
Rotate Byte Right through Carry Bit
b7 b0
C
----
ff
Reset Stack Pointer
SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL)
----------
RTI
Return from Interrupt

INH
80
9
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Return from Subroutine
----------
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
81
6
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
NON-DISCLOSURE
A2 ii 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B 2 2
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
Store Accumulator in Memory
M (A)
----
--
B7 dd 4 C7 hh ll 5 D7 ee ff 6 E7 ff 5 F7 4 8E 2
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
----
--
BF dd 4 CF hh ll 5 DF ee ff 6 EF ff 5 FF 4 A0 ii 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3
Subtract Memory Byte from Accumulator
A (A) - (M)
----
General Release Specification 164 Instruction Set For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Cycles
Effect on CCR
Operand
Address Mode
Opcode
Freescale Semiconductor, Inc.
Instruction Set Opcode Map
Table 11-6. Instruction Set Summary (Continued)
Source Form Operation Description Cycles
10 2 dd 4 3 3 5 4 2 2
Effect on CCR H I NZC
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ----------
INH
83
Freescale Semiconductor, Inc...
TAX TST opr TSTA TSTX TST opr,X TST ,X TXA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
Transfer Accumulator to Index Register
INH DIR INH INH IX1 IX INH INH
97 3D 4D 5D 6D 7D 9F 8F
Test Memory Byte for Negative or Zero
(M) - $00
----
--
ff
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
A (X)
---------- -- 0 ------
11.6 Opcode Map
See Table 11-7.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Instruction Set For More Information On This Product, Go to: www.freescale.com
General Release Specification 165
NON-DISCLOSURE
opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
AGREEMENT
REQUIRED
Operand
Address Mode
Opcode
N O N - D I S C LFreescale Semiconductor, IN T OSURE A G R E E M E nc... R E Q U I R E D
Instruction Set
166
Table 11-7. Opcode Map
Branch REL DIR 3 4 5 6 7 8 9 A B C D E F
3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA 2 IX 3 EOR IX 3 ADC 1 1 1 1 1 IX 3 ORA IX 3 ADD IX 2 JMP 2 IX 5 JSR IX 3 LDX IX 4 STX 2 MSB LSB IX
Bit Manipulation DIR DIR IX IMM DIR IX1 IX 2
Read-Modify-Write INH INH IX1
Control INH INH
Register/Memory EXT IX2
MSB LSB 2 2 2 10 SWI INH 2 2 2 2 1 1
0
1
MSB LSB
0
0 1 2 3 4 5 6 7 8 9 A B C D E F
General Release Specification
9 RTI INH 6 RTS INH 2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2 6 BSR REL 2 2 LDX 2 IMM 2 2 STOP INH 2 2 WAIT TXA INH 1 INH 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3 5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2 4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1
1
2
3
4
5
6
7
8
9
A
Freescale Semiconductor, Inc.
Instruction Set For More Information On This Product, Go to: www.freescale.com
0
LSB of Opcode in Hexadecimal REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
B
C
D
E
F
5 5 3 5 3 3 6 5 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BCLR0 BRN 3 DIR 2 DIR 2 REL 1 5 5 3 11 BRSET1 BSET1 BHI MUL 3 DIR 2 DIR 2 REL 1 INH 5 5 3 5 3 3 6 5 BRCLR1 BCLR1 BLS COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BCLR5 BMI 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BSET6 BMC INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BSET7 BIL 3 DIR 2 DIR 2 REL 1 5 5 3 5 3 3 6 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1
MSB of Opcode in Hexadecimal
MC68HC(7)05L5 -- Rev. 2.0
MOTOROLA
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
0
5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Section 12. Electrical Specifications
12.1 Contents
Freescale Semiconductor, Inc...
12.2 Introduction
This section contains parametric and timing information.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Electrical Specifications For More Information On This Product, Go to: www.freescale.com
General Release Specification 167
NON-DISCLOSURE
AGREEMENT
12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .169 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Recommended Operating Conditions . . . . . . . . . . . . . . . . .169 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .170 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .171 2.7-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .172 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
REQUIRED
Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 12.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. Keep VIn and VOut within the range VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating Symbol VDD VLCD1 VLCD2 VLCD3 VIn VIn VOut I TJ Tstg Value -0.3 to +7.0 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD + 0.3 VSS -0.3 to 2 x VDD + 0.3 VSS -0.3 to VDD + 0.3 12.5 +150 -55 to +150 Unit
Freescale Semiconductor, Inc...
AGREEMENT
Supply voltage
V
Input voltage Self-check mode (IRQ1 pin only) Output voltage Current drain per pin excluding VDD and VSS Operating junction temperature Storage temperature range
V V V mA C C
NON-DISCLOSURE
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 12.7 5.0-Volt DC Electrical Characteristics and 12.8 3.3-Volt DC Electrical Characteristics for guaranteed operating conditions.
General Release Specification 168 Electrical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Electrical Specifications Operating Temperature Range
12.4 Operating Temperature Range
Characteristic Operating temperature range MC68HC05L5 (standard) MC68HC05L5C (extended) Symbol TA Value TL to TH 0 to +70 -40 to +85 Unit C
12.5 Thermal Characteristics
Freescale Semiconductor, Inc...
Characteristic Thermal resistance 80-pin plastic quad flat pack
Symbol JA
Value 120
Unit C/W
12.6 Recommended Operating Conditions
Rating(1) (fOP = 2.1 MHz) (fOP = 1.0 MHz) Supply voltage Symbol VDD VDD VLCD1 VLCD2 VLCD3 Fast clock oscillation frequency External capacitance (fOSC = 3.52 MHz) Slow clock oscillation frequency External capacitance (fXOSC = 32.768 kHz) fOSC C1 C2 fXOSC CX1 CX2 -- -- -- -- -- -- Min 4.5 2.2 Typ 5.0 -- Max 5.5 5.5 Unit V V V V V MHz pF MHz pF
VDD - 1/3 VLCD VDD - 2/3 VLCD VDD - 3/3 VLCD 3.52 33 33 32.768 18 22 4.2 -- -- -- -- --
1. +2.2 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Electrical Specifications For More Information On This Product, Go to: www.freescale.com
General Release Specification 169
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 12.7 5.0-Volt DC Electrical Characteristics
Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 5.0 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Output low voltage (VDD = 5.0 V) (ILoad = 0.8 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fop = 2.1 MHz) Wait (fop = 2.1 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 5.0 V, TA = +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 5.0 V) PA0-PA7 PB0-PB7 PC0-PC7 LCD pin output impedance FP0-FP26 BP0-BP3 Symbol VOL VOH VOH Min -- VDD -0.1 VDD -0.8 Typ -- -- -- Max 0.1 -- -- Unit V
V
Freescale Semiconductor, Inc...
AGREEMENT
VOL
--
--
0.4
V
VIH VIL
0.8 x VDD VSS
-- --
VDD 0.2 x VDD
V V
IDD
-- -- -- --
6.0 3.0 3.0 17.0 --
12.0 6.0 10.0 -- 1.0
mA mA A A A A A A k k
NON-DISCLOSURE
Iin
--
Iin
40 40 150 -- --
150 150 500 10 5
340 340 1000 20 18
Zo, FP Zo, BP
1. +4.5 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 4.2 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current is measured with output transistor turned off and VIn = 0 V.
General Release Specification 170 Electrical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Electrical Specifications 3.3-Volt DC Electrical Characteristics
12.8 3.3-Volt DC Electrical Characteristics
Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 3.5 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Symbol VOL VOH VOH Min -- VDD -0.1 VDD -0.8 Typ -- -- -- Max 0.1 -- -- Unit V
V
Freescale Semiconductor, Inc...
Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET,OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fop = 1.0 MHz) Wait (fop = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 3.0 V, TA= +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 3.3 V) PA0-PA7 PB0-PB7 PC0-PC7 LCD pin output impedance FP0-FP26 BP0-BP3
VIH VIL
0.8 x VDD VSS
-- --
VDD 02 x VDD
V V
IDD
-- -- -- --
1.8 0.8 2.0 8.0 --
8.0 5.0 10.0 -- 1.0
mA mA A A A A A A k k
IIn
--
IIn
20 20 60 -- --
80 80 300 10 5
230 230 760 20 18
Zo, FP Zo, BP
1. +3.0 VDD < +4.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current is measured with output transistor turned off and VIn = 0 V.
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General Release Specification 171
NON-DISCLOSURE
AGREEMENT
Output low voltage (VDD = 3.5 V) (ILoad = 0.8 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7
VOL
--
--
0.4
V
REQUIRED
Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 12.9 2.7-Volt DC Electrical Characteristics
Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 2.2 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Output low voltage (VDD = 2.2 V) (ILoad = 0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fop = 1.0 MHz) Wait (fop = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 2.2 V, TA= +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 2.7 V) PA0-PA7 PB0-PB7 PC0-PC7 LCD pin output impedance FP0-FP26 BP0-BP3 Symbol VOL VOH VOH Min -- VDD -0.1 VDD -0.6 Typ -- -- -- Max 0.1 -- -- Unit V
V
Freescale Semiconductor, Inc...
AGREEMENT
VOL
--
--
0.3
V
VIH VIL
0.8 x VDD VSS
-- --
VDD 0.2 x VDD
V V
-- -- IDD -- -- IIn --
0.7 0.4 1.5 5.0 --
8.0 5.0 10.0 -- 1.0
mA mA A A A A A A k k
NON-DISCLOSURE
IIn
5 5 30 -- --
40 40 150 10 5
110 110 420 20 18
Zo, FP Zo, BP
1. +2.2 VDD < +3.0 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current is measured with output transistor turned off and VIn = 0 V.
General Release Specification 172 Electrical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Electrical Specifications Control Timing
12.10 Control Timing
Characteristic(1) Frequency of oscillation (OSC) Crystal External clock Internal operating frequency(2), crystal or external clock (fOSC/2) VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V Symbol fosc Min -- dc -- -- 480 1.0 1.5 4.0 284 284 note 3 110 Max 4.2 4.2 2.1 1.0 -- -- -- -- -- -- -- -- Unit MHz
fop
MHz
Freescale Semiconductor, Inc...
RESET pulse width when bus clock active Timer Resolution Input capture (TCAP) pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period(3) OSC1 pulse width (external clock input)
tRL tRESL tTH, tTL tILIH tILIL tOH, tOL
tcyc tcyc ns ns tcyc ns
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Electrical Specifications For More Information On This Product, Go to: www.freescale.com
General Release Specification 173
NON-DISCLOSURE
1. +2.2 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. 2. The system clock divider configuration (SYS1-SYS0 bits) should be selected such that the internal operating frequency (fOP) does not exceed value specified in fOP for a given fOSC. 3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc.
AGREEMENT
Cycle time (fast OSC selected) VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V
tcyc
ns s
REQUIRED
Freescale Semiconductor, Inc. Electrical Specifications REQUIRED
OSC11 tRL RESET
tILIH IRQ2 tILCH IRQ3 8092 tcyc
Freescale Semiconductor, Inc...
AGREEMENT
INTERNAL CLOCK
INTERNAL ADDRESS BUS Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option 4. RESET vector address shown for timing example
FFFE
FFFE
FFFE
FFFE
FFFF4
RESET OR INTERRUPT VECTOR FETCH
NON-DISCLOSURE
Figure 12-1. Stop Recovery Timing Diagram
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Section 13. Mechanical Specifications
13.1 Contents
Freescale Semiconductor, Inc...
13.2 Introduction
This section describes the dimensions of the quad flat pack (QFP).
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Mechanical Specifications For More Information On This Product, Go to: www.freescale.com
General Release Specification 175
NON-DISCLOSURE
AGREEMENT
13.2 13.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Quad Flat Pack (QFP) -- Case 841B-01 . . . . . . . . . . . . . . . .176
REQUIRED
Freescale Semiconductor, Inc. Mechanical Specifications REQUIRED 13.3 Quad Flat Pack (QFP) -- Case 841B-01
L
60 61 41 40 S S
D
D
B B
S
S
-A-
-BB
AGREEMENT
Freescale Semiconductor, Inc...
L
0.20 (0.008) M C A-B 0.05 (0.002) A-B
V
0.20 (0.008)
M
H A-B
P
-A,B,DDETAIL A
DETAIL A
80 1 20
21
F
-DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B 0.20 (0.008)
M S
D
S
S H A-B
J
S
N
D
S
E C -CSEATING PLANE
M DETAIL C
DATUM PLANE
D 0.20 (0.008)
M
C A-B
S
D
S
NON-DISCLOSURE
SECTION B-B
-HH M G
0.01 (0.004)
U
T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A , B AND D TO BE DETERMINED AT DATUM PLANE H . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC 0.25 0.13 0.23 0.65 0.95 12.35 BSC 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 0 16.95 17.45 0.35 0.45 1.6 REF
INCHES MIN MAX 0.547 0.555 0.547 0.555 0.084 0.096 0.009 0.015 0.079 0.094 0.009 0.013 0.026 BSC 0.010 0.005 0.009 0.026 0.037 0.486 BSC 5 10 0.005 0.007 0.013 BSC 0 7 0.005 0.012 0.667 0.687 0.005 0 0.667 0.687 0.014 0.018 0.06 REF
General Release Specification 176 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Section 14. Ordering Information
14.1 Contents
Freescale Semiconductor, Inc...
14.2 Introduction
This section contains instructions for ordering custom-masked ROM MCUs.
14.3 MCU Ordering Forms
To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Motorola representative. Submit the following items when ordering MCUs: * * * A current MCU ordering form that is completely filled out (Contact your Motorola sales office for assistance.) A copy of the customer specification if the customer specification deviates from the Motorola specification for the MCU Customer's application program on one of the media listed in 14.4 Application Program Media
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General Release Specification 177
NON-DISCLOSURE
AGREEMENT
14.2 14.3 14.4 14.5 14.6 14.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .178 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .179 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .180 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
REQUIRED
Freescale Semiconductor, Inc. Ordering Information REQUIRED
The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, type bbs in lowercase letters. Then press the return key to start the BBS software.
14.4 Application Program Media
Please deliver the application program to Motorola in one of the following media: * * * Macintosh(R)1 3 1/2-inch diskette (double-sided 800 K or double-sided high-density 1.4 M) MS-DOS(R)2 or PC-DOSTM3 3 1/2-inch diskette (double-sided 720 K or double-sided high-density 1.44 M) MS-DOS(R) or PC-DOSTM 5 1/4-inch diskette (double-sided double-density 360 K or double-sided high-density 1.2 M)
Freescale Semiconductor, Inc...
AGREEMENT
Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with the following information: * * * * * * * Customer name Customer part number Project or product name File name of object code Date Name of operating system that formatted diskette Formatted capacity of diskette
NON-DISCLOSURE
On diskettes, the application program must be in Motorola's S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers.
1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation.
General Release Specification 178 Ordering Information For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
Ordering Information ROM Program Verification
NOTE:
Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern re-submission if non-user areas contain any non-zero code.
If the memory map has two user ROM areas with the same addresses, then write the two areas in separate files on the diskette. Label the diskette with both filenames.
Freescale Semiconductor, Inc...
In addition to the object code, a file containing the source code can be included. Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the filename of the source code.
14.5 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer's application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Motorola inputs the customer's application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain non-user ROM code, such as self-check code. Motorola sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Motorola will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask.
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA Ordering Information For More Information On This Product, Go to: www.freescale.com General Release Specification 179
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Ordering Information REQUIRED 14.6 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer's application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Motorola then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer's user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Motorola Quality Assurance.
Freescale Semiconductor, Inc...
AGREEMENT
14.7 MC Order Numbers
Table 14-1 shows the MC order numbers for the available package types. Table 14-1. MC Order Numbers
Package Type Operating Temperature Range 0 C to +70 C -40 C to +85 C MC Order Number MC68HC05L5FU MC68HC05L5CFU
NON-DISCLOSURE
80-pin plastic quad flat pack (QFP)
General Release Specification 180 Ordering Information For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
General Release Specification -- MC68HC05L5
Appendix A. MC68HC705L5
A.1 Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Differences between MC68HC05L5 and MC68HC705L5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 A.4 MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 A.5 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 A.6 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . .184 A.7 Programming Voltage (VPP) . . . . . . . . . . . . . . . . . . . . . . . . .186 A.8 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 A.8.1 Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 A.8.2 Single-Chip Mode (SCM) . . . . . . . . . . . . . . . . . . . . . . . . .187 A.8.3 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 A.9 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 A.10 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 A.11 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 A.11.1 Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .189 A.11.2 Program Control Register . . . . . . . . . . . . . . . . . . . . . . . . .190 A.12 COP Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 A.13 LCD 1/2 Duty and 1/2 Bias Timing Diagram . . . . . . . . . . . . .192 A.14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 A.14.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 A.14.2 Operating Temperature Range . . . . . . . . . . . . . . . . . . . . .194 A.14.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .194 A.15 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . .194 A.15.1 EPROM Programming Voltage . . . . . . . . . . . . . . . . . . . . .194 A.15.2 5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . .195 A.15.3 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . .196 A.15.4 3.3-Volt and 5.0-Volt Control Timing . . . . . . . . . . . . . . . . .197 A.16 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA MC68HC705L5 For More Information On This Product, Go to: www.freescale.com General Release Specification 181
Freescale Semiconductor, Inc...
NON-DISCLOSURE
AGREEMENT
A.2 A.3
REQUIRED
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED A.2 Introduction
The MC68HC705L5 is similar to the MC68HC05L5 with the exception of the EPROM feature. The program ROM on the MC68HC05L5 has been replaced by 8-K electrically programmable read-only memory to allow modification of the program code for emulation. All information pertaining to the MC68HC05L5 in this document applies to the EPROM part with the additions and exceptions explained in this appendix. The additional features available on the MC68HC705L5 are:
Freescale Semiconductor, Inc...
AGREEMENT
* * *
8,192 bytes of EPROM On-chip bootstrap firmware for programming use Self-check mode replaced by bootstrap capability
A.3 Differences between MC68HC05L5 and MC68HC705L5
Table A-1. Differences Between MC68HC05L5 and MC68HC705L5
Item
ROM memory type Internal test mode LCD 1/2 duty 1/2 bias waveform COP watch dog timer EPROM programming Mask option OSC, XOSC, and RESET pin resistor option
MC68HC05L5
Mask ROM Self-check mode See Figure 10-2 Software selectable Not applicable Customer specified Available by mask option
MC68HC705L5
EPROM Bootstrap mode See Figure A-6 No COP function Through VPP pin and PCR No mask option Not available
NON-DISCLOSURE
A.4 MCU Structure
Figure A-1 shows the structure of the MC68HC705L5 MCU.
General Release Specification 182 MC68HC705L5 For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
MC68HC705L5
OSC1 OSC2 XOSC1 XOSC2
OSC SEL XOSC INTERNAL PROCESSOR CLOCK TIME BASE SYSTEM PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 DATA B DIR REG KEY WAKEUP PORT B /2 DATA A DIR REG DIV PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
SRAM 256 BYTES
Freescale Semiconductor, Inc...
BOOTSTRAP ROM DATA C DIR REG SPI 496 BYTES PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6/IRQ2 PC7/IRQ1
8,192 BYTES
RESET
CPU CONTROL M68HC05 CPU
ALU
VDD VSS
CPU REGISTERS
ACCUMULATOR INDEX REGISTER
TIMER2
EPROM
LCD DRIVERS
FP0-PF26
VPP(1)
PROGRAM COUNTER CONDITION CODE REG
PORT E
STACK POINTER
FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 BP3/PD3 BP2/PD2 BP1/PD1 BP0
VLCD3 VLCD2 VLCD1
Note 1. The VPP pin should be connected to VDD in single-chip mode.
Figure A-1. Block Diagram
NOTE:
A line over a signal name indicates an active low signal. For example, RESET is active low.
General Release Specification MC68HC705L5 For More Information On This Product, Go to: www.freescale.com 183
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
NON-DISCLOSURE
PORT D
AGREEMENT
PORT C
REQUIRED
PORT A
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED A.5 Mask Options
There are no mask options available for the MC68HC705L5. For this reason, the MOR register at address $000F of option map shown in Section 2. Memory Map has no meaning.
A.6 Functional Pin Description
The MC68HC705L5 is available in the 80-pin quad flat pack (QFP). The pin assignment is shown in Figure A-2.
FP27/PE7 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 80 VDD FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 VLCD3 VLCD2 VLCD1 VSS VPP(1) XOSC1 XOSC2 RESET 1 61 60 VSS FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1/PD1 BP2/PD2 BP3/PD3 VDD PC7/IRQ1 PC6/IRQ2 PC5/EVO PC4/EVI PC3/TCAP PC2/SCK 20 21 40 41
NON-DISCLOSURE
Freescale Semiconductor, Inc...
AGREEMENT
Note 1. The VPP pin should be connect to VDD in single-chip mode.
Figure A-2. Pin Assignments for Single-Chip Mode
General Release Specification 184 MC68HC705L5 For More Information On This Product, Go to: www.freescale.com MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
OSC1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO
Freescale Semiconductor, Inc.
MC68HC705L5
Table A-2. Pin Configuration
Pin Number 23 24 25 26 27 28 29 30 SCM, Bootstrap PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6/IRQ2 PC7/IRQ1 VPP(1) VDD VDD VSS VSS OSC1 OSC2 XOSC1 XOSC2 VLCD1 VLCD2 VLCD3 BP3/PD3 BP2/PD2 BP1/PD1 BP0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I/O I/O I/O I/O I/O I/O I I I I I O O I O I O I I I O O O O Pin Number 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 SCM, Bootstrap FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
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31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 17 47 1 60 16 21 22 18 19 15 14 13 48 49 50 51
Note 1. The VPP pin should be connected to VDD in single-chip mode.
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REQUIRED
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED A.7 Programming Voltage (VPP)
In single-chip (user) mode, the VPP pin should be tied to VDD level.
A.8 Modes of Operation
The MC68HC705L5 has two operating modes: single-chip mode (SCM) and bootstrap mode. Single-chip mode, also called user mode, allows maximum use of pins for on-chip peripheral functions. The bootstrap mode is provided for EPROM programming, dumping EPROM contents, and loading programs into the internal RAM and executing them. This is a very versatile mode because there are essentially no limitations on the special-purpose program that is bootloaded into the internal RAM.
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A.8.1 Mode Entry
Mode entry is done at the rising edge of the RESET pin. Once the device enters one of the modes, the mode cannot be changed by software. Only an external reset can change the mode. At the rising edge of the RESET pin, the device latches the states of IRQ1 and IRQ2 and places itself in the specified mode. While the RESET pin is low, all pins are configured as single-chip mode. Table A-3 shows the states of IRQ1 and IRQ2 for each mode entry. High voltage VTST = 2 x VDD is required to select modes other than single-chip mode. Table A-3. Mode Select Summary
Modes Single-chip (user) mode Boot-strap mode RESET PC6/IRQ1 VSS or VDD VTST PC7/IRQ2 VSS or VDD VDD
NON-DISCLOSURE
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
MC68HC705L5
SINGLE-CHIP MODE RESET VDD VSS VTST IRQ1 VDD VSS
IRQ2
VDD VSS
Freescale Semiconductor, Inc...
Figure A-3. Mode Entry Diagram
A.8.2 Single-Chip Mode (SCM)
In this mode, all address and data bus activity occurs within the MCU. Thus, no external pins are required for these functions. The single-chip mode allows the maximum number of I/O pins for on-chip peripheral functions, for example, ports A through E, and LCD drivers.
A.8.3 Bootstrap Mode
In this mode, the reset vector is fetched from a 496-byte internal bootstrap ROM at $3E00-$3FEF. The bootstrap ROM contains a small program which loads a program into the internal RAM and then passes control to that program at location $00C0 or executes the EPROM programming sequence and dumps EPROM contents. Since these modes are not normal user modes, all of the privileged control bits are accessible. This allows the bootstrap mode to be used for self test of the device.
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General Release Specification 187
NON-DISCLOSURE
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VTST = 2 x VDD
REQUIRED
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED A.9 Memory Map
The MC68HC705L5 contains a 8,192-byte EPROM, 496 bytes of bootstrap ROM, and 256 bytes of RAM. An additional 16 bytes of EPROM are provided for user vectors at $3FF0-$3FFF. The MCU's memory map is shown in Figure A-4.
$0000
$0000 I/O 64 BYTES DUAL-MAPPED I/O REGISTERS 16 BYTES $000F $0010
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$003F $0040 RAM 256 BYTES $00C0 $00FF $013F $0140 UNUSED $0FFF $1000 EPROM 8 KBYTES $2FFF $3000 UNUSED $3DFF $3E00 BOOTSTRAP ROM 496 BYTES $3FDF $3FE0 $3FEF $3FF0 $3FFF $003F STACK 64 BYTES
I/O 48 BYTES
NON-DISCLOSURE
TEST VECTORS USER VECTORS
Figure A-4. Memory Map
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
MC68HC705L5
A.10 Boot ROM
Boot ROM is 496 bytes of mask ROM positioned at $3E00-$3FEF. This ROM contains bootstrap loader programs and reset/interrupt vectors in the bootstrap mode. The bootstrap loader programs include: * * * EPROM programming and verification Dumping EPROM contents Loading programs into the internal RAM
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A.11 EPROM
The 8-Kbyte EPROM is positioned at $1000-$2FFF, and the additional 16 bytes of EPROM are located at $3FF0-$3FFF for user vectors. The erased state of EPROM is read as $FF and EPROM power is supplied from the VPP pin and the VDD pin. The program control register (PCR) is provided for EPROM programming and testing. The functions of EPROM depend on the device mode. In user mode, ELAT and PGM bits in the PCR are available for user programming, and the remaining test bits become read-only bits. The VPP pin should be tied to 5 volts or programming voltage.
A.11.1 Programming Sequence
To program the MC68HC705L5, execute this sequence: * * * * * Set the ELAT bit Write the data to the address to be programmed Set the PGM bit Delay for an appropriate amount of time Clear the PGM bit and the ELAT bit
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General Release Specification 189
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*
Executing programs in the internal RAM
REQUIRED
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED
Clearing the PGM bit and the ELAT bit may be done on a single CPU write.
NOTE:
It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should be equal to VDD during normal operations.
A.11.2 Program Control Register
A program control register is provided for EPROM programming.
Address: $000D Bit 7 Read: R Write: Reset: 0 R 0 = Reserved 0 0 0 0 0 0 R R R R R ELAT PGM 6 5 4 3 2 1 Bit 0
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Figure A-5. Program Control Register (PCR) Bits 7-3 -- Reserved These bits are reserved and read as logic 0 in user mode. Bit 2 -- Reserved This bit is not used and always reads as logic 0. ELAT -- EPROM LATch control 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming (Writes to EPROM cause address and data to be latched.) EPROM is in programming mode and cannot be read if ELAT is logic 1. This bit should not be set when no programming voltage is applied to the VPP pin. PGM -- EPROM ProGraM command 0 = Programming power switched off from EPROM array 1 = Programming power switched on to EPROM array If ELAT 1, then PGM = 0.
General Release Specification 190 MC68HC705L5 For More Information On This Product, Go to: www.freescale.com MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
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MC68HC705L5
A.12 COP Watchdog Timer
The MC68HC705L5 does not have a COP watchdog timer. For this reason, the COPE and COPC bits in timebase control register 2 (address: $0011) has no meaning. These bits are not used and always read as logic 0. Also or the same reason, COP watchdog timer reset does not occur on the MC68HC705L5.
Freescale Semiconductor, Inc...
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General Release Specification 191
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REQUIRED
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED A.13 LCD 1/2 Duty and 1/2 Bias Timing Diagram
DUTY = 1/2 BIAS = 1/2 (VLCD1 = VLCD2 = VDD-VLCD/2, VLCD3 = VDD-VLCD) 1FRAME BP0 VDD VLCD1, 2 VLCD3 VDD VLCD1, 2 VLCD3 VDD VLCD1, 2 VLCD3 VDD VLCD1, 2 VLCD3 +VLCD +VLCD/2 0 -VLCD/2 -VLCD +VLCD BP1-FPx (ON) +VLCD/2 0 -VLCD/2 -VLCD +VLCD +VLCD/2 0 -VLCD/2 -VLCD +VLCD +VLCD/2 0 -VLCD/2 -VLCD
BP1
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FPx (XX10)
FPy (XX00)
BP0-FPx (OFF)
NON-DISCLOSURE
BP0-FPy (OFF)
BP1-FPy (OFF)
Figure A-6. CD 1/2 Duty and 1/2 Bias Timing Diagram
General Release Specification 192 MC68HC705L5 For More Information On This Product, Go to: www.freescale.com
MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
MC68HC705L5
A.14 Electrical Specifications
This section contains parametric and timing information for the MC68HC705L5.
A.14.1 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
Freescale Semiconductor, Inc...
The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. Keep VIn and VOUT within the range VSS (VIn or VOUT) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating Symbol VDD VLCD1 VLCD2 VLCD3 VIn VIn VOut I TJ Tstg Value -0.3 to +7.0 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VDD + 0.3 VSS -0.3 to 2 x VDD + 0.3 VSS -0.3 to VDD + 0.3 12.5 +150 -55 to +150 Unit
Supply voltage
V
Input voltage Boot-strap mode IRQ1 pin only Output voltage Current drain per pin excluding VDD and VSS Operating junction temperature Storage temperature range
V V V mA C C
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to A.15.2 5.0-Volt DC Electrical Characteristics and A.15.3 3.3-Volt DC Electrical Characteristics for guaranteed operating conditions.
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General Release Specification 193
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REQUIRED
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED A.14.2 Operating Temperature Range
Characteristic Operating temperature range MC68HC705L5 (standard) Symbol TA Value TL to TH 0 to +70 Unit C
A.14.3 Thermal Characteristics
Characteristic Thermal resistance 80-pin plastic quad flat pack Symbol JA Value 120 Unit C/W
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A.15 Recommended Operating Conditions
Rating(1) (fOP = 2.1 MHz) (fOP = 1.0 MHz) Supply voltage Symbol VDD VDD VLCD1 VLCD2 VLCD3 Fast clock oscillation frequency External capacitance (fOSC = 3.52 MHz) Slow clock oscillation frequency External capacitance (fXOSC = 32.768 kHz) fOSC C1 C2 fXOSC CX1 CX2 -- -- -- -- -- -- Min 4.5 3.0 Typ 5.0 -- Max 5.5 5.5 Unit V V V V V MHz pF MHz pF
VDD - 1/3 VLCD VDD - 2/3 VLCD VDD - 3/3 VLCD 3.52 33 33 32.768 18 22 4.2 -- -- -- -- --
NON-DISCLOSURE
1. +3.0 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted
A.15.1 EPROM Programming Voltage
Characteristics(1) EPROM programming voltage
1. VDD = 5.0 Vdc, VSS = 0 Vdc, TA = 25
oC
Symbol VPP
Min 12.0
Typ 12.5
Max 13.0
Unit V
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
MC68HC705L5
A.15.2 5.0-Volt DC Electrical Characteristics
Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 5.0 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Symbol VOL VOH VOH Min -- VDD -0.1 VDD -0.8 Typ -- -- -- Max 0.1 -- -- Unit V
V
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Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fOP = 2.1 MHz) Wait (fOP = 2.1 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 5.0 V, TA = +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 5.0 V) PA0-PA7 PB0-PB7 PC0-PC7 LCD pin output impedance FP0-FP26 BP0-BP3
VIH VIL
0.8 x VDD VSS
-- --
VDD 0.2 x VDD
V V
IDD
-- -- -- --
6.0 3.0 3.0 17.0 --
12.0 6.0 10.0 -- 1.0
mA mA A A A A A A k k
IIn
--
IIn
40 40 160 -- --
150 150 500 10 5
340 340 1000 20 18
Zo, FP Zo, BP
1. +4.5 VDD +5.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 4.2 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current measured with output transistor turned off and VIn = 0 V.
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General Release Specification 195
NON-DISCLOSURE
AGREEMENT
Output low voltage (VDD = 5.0 V) (ILoad = 0.8 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7
VOL
--
--
0.4
V
REQUIRED
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED A.15.3 3.3-Volt DC Electrical Characteristics
Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (VDD = 3.5 V) (ILoad = -0.4 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Output low voltage (VDD = 3.5 V) (ILoad = 0.8 mA) PA0-PA7, PC0-PC5, PD1-PD7, PE0-PE7 Input high voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input low voltage PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Supply current(2), (3), (4), (5) Run (fOP = 1.0 MHz) Wait (fOP = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 3.0 V, TA= +25 oC Input current(6) (with pullups disabled) PA0-PA7, PB0-PB7, PC0-PC7, RESET, OSC1, XOSC1 Input current(6) (with pullups enabled, VDD = 3.3 V) PA0-PA7 PB0-PB7 PC0-PC7 LCD pin output impedance FP0-FP26 BP0-BP3 Symbol VOL VOH VOH Min -- VDD -0.1 VDD -0.8 Typ -- -- -- Max 0.1 -- -- Unit V
V
Freescale Semiconductor, Inc...
AGREEMENT
VOL
--
--
0.4
V
VIH VIL
0.8 x VDD VSS
-- --
VDD 0.2 x VDD
V V
IDD
-- -- -- --
1.8 0.8 2.0 8.0 --
8.0 5.0 10.0 -- 1.0
mA mA A A A A A A k k
NON-DISCLOSURE
IIn
--
IIn
20 20 60 -- --
80 80 300 10 5
230 230 760 20 18
Zo, FP Zo, BP
1. +3.0 VDD < +4.5 Vdc, VSS = 0 Vdc, TL TA TH, unless otherwise noted. All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only. 2. Run (Operating) IDD, wait IDD; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD; all ports configured as inputs; VIL = 0.2 V; VIH = VDD -0.2 V 4. Stop IDD measured with OSC1 = VSS. 5. Wait IDD is affected linearly by the OSC2 capacitance. 6. Input current measured with output transistor turned off and VIn = 0 V.
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
MC68HC705L5
A.15.4 3.3-Volt and 5.0-Volt Control Timing
Characteristic(1) Frequency of oscillation (OSC) Crystal External Clock Internal operating frequency(2), crystal or external clock (fOSC/2) VDD = 4.5 V to 5.5 V VDD = 3.0 V to 5.5 V Symbol fOSC Min -- dc Max 4.2 4.2 Unit MHz
fOP
-- --
2.1 1.0
MHz
Freescale Semiconductor, Inc...
tcyc tRL tRESL tTH, tTL tILIH tILIL tOH, tOL
480 1.0 1.5 4.0 284 284 see note 110
-- -- -- -- -- -- -- --
ns s tcyc tcyc ns ns tcyc ns
RESET pulse width (when bus clock active) Timer Resolution Input capture (TCAP) pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period(3) OSC1 pulse width (external clock input)
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General Release Specification 197
NON-DISCLOSURE
1. +3.0 VDD +5.5 Vdc, VSS = 0 Vdc,TL TA TH, unless otherwise noted. 2. The system clock divider configuration (SYS1-SYS0 bits) should be selected such that the internal operating frequency (fOP) does not exceed value specified in fOP for a given fOSC. 3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc.
AGREEMENT
Cycle time (fast OSC selected) VDD = 4.5 V to 5.5 V VDD = 3.0 V to 5.5 V
REQUIRED
Freescale Semiconductor, Inc. MC68HC705L5 REQUIRED A.16 MC Order Number
Table A-4 shows the MC order number for the available package type. Table A-4. MC Order Number
Package Type 80-pin plastic quad flat pack (QFP) Operating Temperature Range 0 C to +70 C MC Order Number
MC68HC705L5FU
NON-DISCLOSURE
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MC68HC(7)05L5 -- Rev. 2.0 MOTOROLA
Freescale Semiconductor, Inc.
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