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19-5664; Rev 1; 12/10
Parallel-Interface Elapsed Time Counter
General Description
The DS1318 parallel-interface elapsed time counter (ETC) is a 44-bit counter that maintains the amount of time that the device operates from main and/or backup power or during an external event. The internal frequency of the counter clock is 4.096kHz, which provides a 244s resolution and a maximum count of over 136 years. A built-in power-sense circuit detects power failures, automatically switches to the backup supply, and controls the timer. If an external event timer is desired, the control input EXT can control the counter operation. An open-drain output provides an interrupt, and a square-wave output provides a programmable square wave. The DS1318 is accessed through a bytewide parallel interface, and operates over the industrial temperature range. Byte-Wide Parallel Interface 44-Bit Binary Counter Provides Timer with 244s Resolution Automatic Power-Fail Detect and Switch Circuitry Selects Power Source from the Primary Power and the Battery, and Write Protects the Internal Registers Internal Power-Fail Circuit Allows Timer to Provide Primary or Battery Operation Times Timer can Alternately Provide an Event Timer of Either an Active-High or Active-Low Pulse Interrupt Output Generated Periodically or When the Upper 32 Bits of the Counter Match an Alarm Register Square-Wave Output with 16 Selectable Frequencies from 32.768kHz to 0.5Hz
Features
DS1318
Applications
Power Meters Industrial Controls Servers
+3.3V Operation Industrial Temperature Range: -40C to +85C Underwriters Laboratories (UL) Recognized
Ordering Information
PART DS1318E+ DS1318E+T&R TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 24 TSSOP 24 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel.
Typical Operating Circuit
TOP VIEW VCC RPU 0.1F VCC SQW EXT X1 X2 GND EXT A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12
Pin Configuration
+
IRQ WE CPU OE CE A3-A0 DQ-DQ7 GND
DS1318
VBAT X1 EXTERNAL COUNTER ENABLE (EVENT TIMER)
DS1318
X2
24 23 22 21 20 19 18 17 16 15 14 13
VCC VBAT IRQ SQW WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3
TSSOP (4.4mm)
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Parallel-Interface Elapsed Time Counter DS1318
ABSOLUTE MAXIMUM RATINGS
Voltage Range on any Pin Relative to Ground ......-0.3V to +6.0V Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Lead Temperature (soldering, 10s) .................................+260C Soldering Temperature (reflow) .......................................+260C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP (multilayer board) Junction-to-Ambient Thermal Resistance (JA) ............72C/W Junction-to-Case Thermal Resistance (JC) .................13C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Supply Voltage Battery Voltage Logic 1 Voltage Logic 0 Voltage SYMBOL VCC VBAT VIH VIL (Note 3) (Note 3) (Note 3) (Note 3) CONDITIONS MIN 3.0 1.6 0.7 x VCC -0.5 TYP 3.3 3.3 MAX 3.6 3.7 VCC + 0.5 +0.3 x VCC UNITS V V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Logic 0 Output Current (VOL = 0.15 x VCC) Logic 1 Output Current (VOH = 0.85 x VCC) SQW, INT Logic 0 Output (VOL = 0.15 x VCC) Input Leakage I/O Leakage Active Supply Current Standby Current Battery Input-Leakage Current Power-Fail Voltage SYMBOL I OL I OH I OLSI ILI ILO ICCA ICCS IBATLKG VPF (Note 3) 2.70 (Note 4) (Note 5) (Note 6) (Note 7) 100 10 -1 CONDITIONS MIN 3 1 5 1 +1 10 150 100 2.97 TYP MAX UNITS mA mA mA A A mA A nA V
2
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Parallel-Interface Elapsed Time Counter
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBAT = 3.7V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Battery Input Current (ENOSC = 1) Battery Input Current (ENOSC = 0) SYMBOL IBAT IBATDR (Note 8) (Note 8) CONDITIONS MIN TYP 750 MAX 1100 100 UNITS nA nA
DS1318
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Read Cycle Time Address Access Time CE to DQ Low-Z CE Access Time CE Data Off-Time OE to DQ Low-Z OE Access Time OE Data Off-Time Output Hold from Address Write Cycle Time Address Setup Time WE Pulse Width CE Pulse Width Data Setup Time Data Hold Time Address Hold Time WE Data Off-Time Write Recovery Time Oscillator Stop Flag (OSF) Delay SYMBOL tRC tAA tCEL tCEA tCEZ t OEL t OEA t OEZ tOH tWC tAS tWEW tCEW tDS tDH tAH tWEZ tWR t OSF (Note 9) 10 4 5 80 0 40 70 40 0 0 30 0 70 30 0 80 30 CONDITIONS MIN 80 80 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
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Parallel-Interface Elapsed Time Counter DS1318
Read Cycle Timing
tRC
A0-A4 tAA CE tCEA tCEL OE tOEZ tCEZ tOH
tOEA
tOEL DQ0-DQ7 VALID
Write Cycle Timing, Write-Enable Controlled
tWC
A0-A4 tAS CE tAS WE tWEZ DQ0-DQ7 DATA OUTPUT
VALID tAH
VALID
tWEW
tWR
tDS
tDH DATA INPUT DATA INPUT
Write Cycle Timing, Chip-Enable Controlled
tWC
A0-A4 tAS CE tAS WE
VALID tCEW tAH
VALID
tWR
tDS DQ0-DQ7 DATA INPUT
tDH DATA INPUT
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Parallel-Interface Elapsed Time Counter
Power-Up/Power-Down Timing
DS1318
VCC VPF(MAX) VPF(MIN)
tVCCF
tVCCR tREC
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40C to +85C) (Note 2)
PARAMETER Recovery at Power-Up VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; V PF(MIN) to VPF(MAX) SYMBOL tREC t VCCF t VCCR (Note 10) 300 0 CONDITIONS MIN TYP MAX 150 UNITS ms s s
CAPACITANCE
(TA = +25C)
PARAMETER Capacitance on All Input Pins Capacitance on IRQ, SQW, and DQ Pins SYMBOL CIN CIO CONDITIONS MIN TYP MAX 10 10 UNITS pF pF
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Parallel-Interface Elapsed Time Counter DS1318
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Output Load Including Scope and Jig Input and Output Timing Measurement Reference Levels Input-Pulse Rise and Fall Times 0 to 2.7V 25pF + 1TTL Gate VCC / 2 4ns TEST CONDITION
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in write protection. Limits at -40C are guaranteed by design and not production tested. All voltages are referenced to ground. OE, CE, WE, EXT, and A3-A0. DQ7-DQ0, SQW, and IRQ, when the outputs are high impedance. Outputs open. Specified with parallel bus inactive. Measured with a 32,768kHz crystal attached to the X1 and X2 pins. The parameter tOSF is the period of time that the oscillator must be stopped for the OSF flag to be set over the voltage range of 0V VCC VCC(MAX) and 1.3V VBAT 3.7V. Note 10: This delay applies only if the oscillator is enabled and running. If the ENOSC bit is 0, tREC is disabled, and the device is immediately accessible. If CE and OE are low on power-up, the DQ outputs are active. Valid data out is not available until after tREC. Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
IBAT vs. TEMPERATURE VBAT = 3.0V
DS1318 toc01
IBAT vs. VBAT
VCC = 0 800 SUPPLY CURRENT (nA) 750 700 650 600 550
DS1318 toc02
OSCILLATOR FREQUENCY vs. VOLTAGE
32768.45 32768.40 FREQUENCY (Hz) 32768.35 32768.30 32768.25 32768.20 32768.15 32768.10 32768.05 32768.00
DS1318 toc03
850 VCC = 0 800 SUPPLY CURRENT (nA)
850
32768.50
750
700
650
600 -40 -20 0 20 40 60 80 TEMPERATURE (C)
500 1.5 1.9 2.3 2.7 3.1 3.5 VBACKUP (V)
2.0
2.5
3.0 INPUT VOLTAGE (V)
3.5
4.0
6
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Parallel-Interface Elapsed Time Counter
Functional Diagram
X1 X2 CLOCK CONTROL CIRCUITRY EXT 4,096Hz SQUARE-WAVE RATE SELECTOR AND PRESCALER SQW 32,768Hz 32,768Hz CRYSTAL OSCILLATOR AND PRESCALER COUNTER 4,096Hz
DS1318
BUFFERED COUNTER REGISTERS, CONTROL AND STATUS REGISTERS VCC VBAT VCC LEVEL DETECT, POWER SWITCH, AND WRITE PROTECT SUBSECONDS0 SUBSECONDS1 SECONDS0 SECONDS1 SECONDS2 SECONDS3 CE OE WE A3-A0 DQ7-DQ0 BYTE-WIDE RAM INTERFACE INTERNAL DIVIDERS AND COUNTERS TRANSFER ENABLE (TE) SUBSECONDS0 SUBSECONDS1 SECONDS0 SECONDS1 SECONDS2 SECONDS3 ALARM0 ALARM1 ALARM2 ALARM3 CONTROL A CONTROL B STATUS PF/ALMF MUX IRQ
DS1318
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Parallel-Interface Elapsed Time Counter DS1318
Pin Description
PIN 1 2 3, 12 4 5-8 9, 10, 11, 13-17 18 19 20 21 22 23 24 NAME X1 X2 GND EXT A3-A0 DQ0-DQ7 CE OE WE SQW IRQ VBAT VCC FUNCTION Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a 12.5pF specified load capacitance (CL). X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, X2, is left unconnected if an external oscillator is connected to X1. Ground. This pin must be connected to ground for proper operation. External Counter-Enable Input Address Bus Inputs Bidirectional Data Pins Chip-Enable Input, Active Low Output-Enable Input, Active Low Write-Enable Input, Active Low Square-Wave Output Interrupt Output. This active-low open-drain pin requires a pullup resistor. Battery/Backup Power-Supply Input DC Power for Primary Power Supply
Table 1. Operation Modes for Power-Supply Conditions
VCC CE VIH VCC > VPF VIL VIL VIL VSO < VCC < VPF VCC < VSO < VPF X X OE X X VIL VIH X X WE X VIL VIH VIH X X DQ0-DQ7 High-Z DIN DOUT High-Z High-Z High-Z A0-A4 X AIN AIN AIN X X MODE Deselect Write Read Read Deselect Data POWER Standby Active Active Active CMOS Standby Battery Current
Detailed Description
The parallel-interface ETC contains a 44-bit up counter that maintains the amount of time the counter is enabled. The resolution of the timer is 244s. A control register selects which events enable and disable the counter. The counter is double-buffered into two register sets, and the TE bit controls the updating of the user-readable copy. The counter can be used to maintain the cumulative amount of time the primary power source or the battery powers the device. In this mode, the counter starts when the internal power-switching circuit enables the selected power source and stops when the circuit enables the other source. The counter can also be used as an external event timer. In this mode, the counter starts when the signal EXT tog8
gles to the active sate and stops when it toggles to the inactive state. The active state of the EXT signal is configurable as high or low. EXT is ignored and the counter is disabled while the device is in power fail. The interrupt output pin provides two maskable interrupt sources. A 32-bit alarm register allows an interrupt to be generated whenever the upper 32 bits of the counter match the alarm register. A periodic interrupt can also be generated from once every 244s to once every 1/12,097,152Hz (24.27 days). The alarm and interrupt output operate when the device is operating from either supply. Table 1 shows the factors that control the device operation. VSO is the battery switchover voltage and is the lesser of VBAT and VPF. While the device is operating from the battery with the oscillator running, the battery
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Parallel-Interface Elapsed Time Counter DS1318
Table 2. Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL fO ESR CL 12.5 MIN TYP 32.768 50 MAX UNITS kHz k pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
RTC
LOCAL GROUND PLANE (LAYER 2)
COUNTDOWN CHAIN
CRYSTAL
X1
X2
CL1
CL2 RTC REGISTERS
NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA (UPPER LEFT QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE DEVICE PACKAGE.
X1
X2
GND
CRYSTAL
Figure 1. Oscillator Circuit Showing Internal Bias Network
Figure 2. Layout Example
input current is IBAT. The oscillator consumes most of the current. If the oscillator is disabled, the data in the registers remain static, and the battery input current is IBATDR, which is primarily due to the leakage of the static memory cells. The DS1318 uses a standard parallel byte-wide interface to access the register map. Table 1 summarizes the modes of operation at various power-supply conditions.
An external 32.768kHz oscillator can also drive the DS1318. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is left unconnected.
Clock Accuracy
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 2 shows a typical PC board layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for more detailed information.
Oscillator Circuit
The DS1318 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 2 specifies several crystal parameters for the external crystal, and Figure 1 shows a functional schematic of the oscillator circuit. An enable bit in the control register controls the oscillator. Oscillator startup times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within one second.
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Parallel-Interface Elapsed Time Counter DS1318
Table 3. Address Map
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch BIT 7 SS3 SS11 S7 S15 S23 S31 ALM7 ALM15 ALM23 ALM31 TE PRS3 OSF BIT 6 SS2 SS10 S6 S14 S22 S30 ALM6 ALM14 ALM22 ALM30 ENOSC PRS2 UIP BIT 5 SS1 SS9 S5 S13 S21 S29 ALM5 ALM13 ALM21 ALM29 CCFG1 PRS1 0 BIT 4 SS0 SS8 S4 S12 S20 S28 ALM4 ALM12 ALM20 ALM28 CCFG0 PRS0 0 BIT 3 0 SS7 S3 S11 S19 S27 ALM3 ALM11 ALM19 ALM27 EPOL SRS3 0 BIT 2 0 SS6 S2 S10 S18 S26 ALM2 ALM10 ALM18 ALM26 SQWE SRS2 0 BIT 1 0 SS5 S1 S9 S17 S25 ALM1 ALM9 ALM17 ALM25 PIE SRS1 PF BIT 0 SQWS SS4 S0 S8 S16 S24 ALM0 ALM8 ALM16 ALM24 AIE SRS0 ALMF FUNCTION Subseconds0 Subseconds1 Seconds0 Seconds1 Seconds2 Seconds3 Alarm0 Alarm1 Alarm2 Alarm3 ControlA ControlB Status RANGE 00-F0h 00-FFh 00-FFh 00-FFh 00-FFh 00-FFh 00-FFh 00-FFh 00-FFh 00-FFh 00-FFh 00-FFh --
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
Counter Operation
The binary time information is obtained by reading the appropriate register bytes. Registers 02h through 05h contain the time in seconds from an arbitrary reference time determined by the user. Registers 00h and 01h contain the fractional seconds count. A buffered copy of the clock registers (A0-A5), updated every 244s, allows the user to read and write the registers while the internal registers continue to increment. However, it is possible to read or write inconsistent data, or for a write to corrupt the current buffered read copy, if an update occurs during the read or write. Several methods may be used to ensure that the data is accurate. The clock registers can be read, with the least-significant byte (LSB) being read once at the beginning and again after the other registers have been read (i.e., A2-A5, A2). If the LSB register data has changed, the registers should be re-read until the LSB register data matches. If the subseconds0 register is used, the user never has more than 244s to read all the registers before a mismatch occurs. In addition, if the routine used to read the registers takes approximately 1.95ms to read the registers, it is possible that the subseconds0 register could roll over to the same value as previously read. Other methods use the TE and UIP bits to synchronize accessing the clock registers to ensure that the data are valid. These methods are discussed in later sections.
Alarm
To use the alarm function, the user writes registers 06h through 09h with a time in seconds. When the current time in seconds becomes equal to the alarm value, the ALMF bit in the status register (0Ch) is set to 1. If the AIE bit in control register A is set to 1 by the user, then the IRQ pin is driven low when the ALMF bit is set to 1. The alarm and IRQ output operate when the device is running from either supply.
Periodic Flag
Writing a non-zero value into the periodic flag rateselect bits in control register B enables the periodic flag operation. The periodic flag is set to logic 1 when the internal counter reaches the selected value. Writing the PF bit to 0 resets the periodic flag. If the flag is not reset, it remains high. Once the PF bit is set, the internal counter continues counting, and attempts to set the PF bit again when the count again matches the selected rate value. Clearing the PF bit has no effect on the internal counter. If the PIE bit in control register A is set to 1, the IRQ output goes low when the PF bit is set. The periodic flag and IRQ output operates when the device is running from either supply. Note that writing to the subseconds or seconds registers affects the setting of the PF flag and IRQ output. The square-wave output uses a separate prescaler and is not affected by changes to the subseconds or seconds bits.
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Parallel-Interface Elapsed Time Counter
Control Register A (0Ah)
BIT 7 TE BIT 6 ENOSC BIT 5 CCFG1 BIT 4 CCFG0 BIT 3 EPOL BIT 2 SQWE BIT 1 PIE BIT 0 AIE
DS1318
Special-Purpose Registers
The DS1318 has three additional registers (control A, control B, and status) that control the clock, alarms, square wave, and interrupt output. The subseconds0 register has a square-wave synchronization (SQWS) bit in the bit 0 location. Writing the SQWS bit to 1 clears the square-wave prescaler and holds it in reset. Only the frequencies below 4096Hz are reset. Writing the bit back to 0 takes the prescaler out of reset and starts the square wave running. Bit 7: Transfer Enable (TE). When TE is set to logic 1, the DS1318 continues to update the user copy of the time value as it receives 4,096Hz clock pulses from the oscillator. To ensure reading valid time data from the part, the user should set TE to logic 0 before reading registers 00-05h. TE must be enabled (logic 1) for at least 244s to ensure that a transfer occurs. Note that because of the 244s restriction, sequential values of the subseconds0 register cannot be read when TE is used. It is possible that TE could be set to logic 0 while a transfer is taking place. In that case, the buffered data could be invalid. To prevent this, the UIP bit, described later, should be used. To write data to the clock registers, the user should set TE to logic 0, write the registers, and set TE to logic 1. Bit 6: Enable Oscillator (ENOSC). When ENOSC is set to logic 1, the DS1318 crystal oscillator becomes enabled. Actual startup time for the oscillator depends on many external variables and is not a specified parameter. Bits 5, 4: Clock Configuration 1, 0 (CCFG1, CCFG0). These bits determine which of the four possible modes the DS1318 uses to clock its timekeeping registers:
CCFG1 0 0 CCFG0 0 1 MODE Always clocks the registers (normal mode) Clocks when the EXT pin is "active" and VCC is greater than VPF (event-timer mode, depends on EPOL bit) Clocks registers when part is running on VCC Clocks registers when part is running on VBAT
Bit 3: External Polarity (EPOL). This bit controls the polarity on the EXT pin input when the CCFG1 and CCFG0 bits are equal to 0 and 1, respectively. When EPOL is set to logic 1, the registers count when the EXT pin is 1. When EPOL is set to logic 0, the registers count when the EXT pin is logic 0. Bit 2: Square-Wave Enable (SQWE). When SQWE is set to logic 1, a frequency determined by the SRSx bits in control register B (0Bh) is output on the SQW pin. When SQWE is logic 0, the SQW pin is always 0. When the part is in power-fail, the SQW pin is always highimpedance. The square-wave output uses a separate prescaler from the one used by PF, IRQ, UIP, and the up counter. The SQWS bit in control register A can be used to synchronize the square-wave output to within 244s of the other events. Bit 1: Periodic Interrupt Enable (PIE). When PIE is set to logic 1, the DS1318 sets the IRQ pin low whenever the PF flag is set to 1. When PIE is 0, the PF flag does not affect the IRQ pin. Bit 0: Alarm Interrupt Enable (AIE). When AIE is set to logic 1, the DS1318 sets the IRQ pin low whenever the ALMF flag is set to 1. When AIE is 0, the ALMF flag does not affect the IRQ pin.
1 1
0 1
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Parallel-Interface Elapsed Time Counter DS1318
Control Register B (0Bh)
BIT 7 PRS3 BIT 6 PRS2 BIT 5 PRS1 BIT 4 PRS0 BIT 3 SRS3 BIT 2 SRS2 BIT 1 SRS1 BIT 0 SRS0
Bits 7 to 4: Periodic Rate Select (PRS3-PRS0). When the oscillator is enabled (ENOSC = 1) the PF flag is set at the rates determined by the following table: Periodic Flag Frequency When ENOSC = 1
PRS3 PRS2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PRS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PRS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PERIODIC FLAG FREQUENCY Periodic Flag Not Set 4096Hz 2048Hz 1024Hz 512Hz 256Hz 128Hz 8Hz 4Hz 2Hz 1Hz 1/64Hz (Once per 1.067 Minutes) 1/4096Hz (Once per 1.138 Hours) 1/65536Hz (Once per 1.318 Days) 1/524288Hz (Once per 0.8669 Weeks) 1/2097152Hz (Once per 24.27 Days)
Bits 3 to 0: Square-Wave Rate Select (SRS3-SRS0). When the oscillator is enabled (ENOSC = 1) and running, and the square-wave pin is enabled (SQWE = 1), the SQW pin outputs a square-wave signal determined by the SRS bits according to the following table: Square-Wave Output Frequency When SQWE = 1, ENOSC = 1
SRS3 SRS2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SRS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SRS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SQUARE-WAVE OUTPUT FREQUENCY (Hz) 32,768 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 0.5
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Parallel-Interface Elapsed Time Counter
Status Register (0Ch)
BIT 7 OSF BIT 6 UIP BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 PF BIT 0 ALMF
DS1318
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is or was stopped for some period of time and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) 3) 4) The voltage present on both V CC and V BAT is insufficient to support oscillation. The ENOSC bit is turned off in battery-backed mode. External influences on the crystal (i.e., noise, leakage, etc.)
Bit 1: Periodic Flag (PF). The periodic flag bit is set to 1 at the rate determined by the PRS bits in register 0Bh. If the PF bit is already 1 when the selected frequency attempts to set it to 1 again, no change occurs. The user must clear the PIF flag faster than the part attempts to set it to see the desired PF rate. If the PIE bit in register 0Ah is also set to logic 1, the IRQ pin is driven low in response to PF transitioning to 1. Any write to the status register while this flag is active clears the bit to 0. Bit 0: Alarm Flag (ALMF). A logic 1 in the alarm flag bit indicates that the contents of the seconds registers matched the contents of the alarm registers. If the AIE bit in register 0Ah is also set to logic 1, the IRQ pin is driven low in response to ALMF transitioning to 1. Any write to the status register while this flag is active clears the bit to 0.
Any write to the status register while this flag is active clears the bit to 0. Bit 6: Update-In-Progress Flag (UIP). A logic 1 in the update-in-progress bit indicates that the internal clock registers may be in the process of updating the user registers. Writing to any seconds or subseconds registers when this bit is logic 1 may cause a collision with the internal update and corrupt one or more of the user registers until the next update occurs. If the UIP bit is read and is logic 0, the user has at least 60s to write to the device without the possibility of causing a collision with the internal update. The internal timekeeping update is gated by the falling edge of UIP. Reading the subseconds and or seconds registers while UIP is logic 1 may result in reading inconstant values. If the UIP bit is read and is logic 0, the user has at least 60s to read from the device without the possibility of getting inconstant values.
UIP vs. Update Timing
8kHz
4kHz
UIP 60s
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Parallel-Interface Elapsed Time Counter DS1318
Chip Information
PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 24 TSSOP PACKAGE CODE U24+2 OUTLINE NO. 21-0066 LAND PATTERN NO. 90-0118
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Parallel-Interface Elapsed Time Counter
Revision History
REVISION NUMBER 0 REVISION DATE 2/04 Initial release Added the UL recognized bullet to the Features section; added lead(Pb)-free parts to the Ordering Information table; updated the Absolute Maximum Ratings section to include lead temperature and soldering temperature information; added the Package Thermal Characteristics section; changed the battery voltage parameter symbol from VCC to VBAT in the Recommended DC Operating Conditions table; changed VBACKUP to VBAT in the DC Electrical Characteristics table globals and Note 9; added the Package Information table DESCRIPTION PAGES CHANGED --
DS1318
1
12/10
1, 2, 3, 5, 6, 14
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
(c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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