View W83115RG-BW_4989909.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Winbond Clock Generator W83115RG-BW W83115WG-BW For INTEL Broadwater Chipset
Date:
Dec./2006
Revision: 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR W83115RG-BW/W83115WG-BW Datasheet Revision History
PAGES DATES VERSION WEB VERSION MAIN CONTENTS
1 2 3 4 5 6 7 8 9 10
n.a. 1,3-5,16 2,3 6
03/06/2006 04/06/2006 05/18/2006 06/06/2006 12/13/2006
0.5 0.51 0.6 0.61 1.0
n.a. n.a. n.a. n.a. n.a.
All of the versions before 0.50 are for internal use. Modify some description in blue text. Add DOTSEL& hardware trapping pin. Change default value about DOT96_SEL. All of the versions before 1.0 are preliminary version
-I-
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 3 PIN DESCRIPTION..................................................................................................................... 4 FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7 I2C CONTROL AND STATUS REGISTERS............................................................................... 8 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 8. 8.1 8.2 8.3 8.4 9. 9.1 Register 0: ( Default : X1h )......................................................................................................8 Register 1: ( Default : 83h) .......................................................................................................9 Register 2: ( Default : FFh )......................................................................................................9 Register 3: ( Default : FFh )....................................................................................................10 Register 4: ( Default : FFh).....................................................................................................11 Register 5: ( Default : 00h ) ....................................................................................................12 Register 6: ( Default : 0Ch ) ...................................................................................................13 Register 7: Winbond Chip ID - Project Code Register ( Default : 04h )...............................14 Register 8: ( Default : 0Ch ) ...................................................................................................14 Register 9: ( Default : 25h ) ....................................................................................................15 Register 10: ( Default : D0h ) .................................................................................................15 Register 11: ( Default : 7Ah )..................................................................................................16 Register 12: ( Default : 7Ah )..................................................................................................16 Register 13: ( Default : 10h ) ..................................................................................................16 Register 14: ( Default : 04h ) ..................................................................................................17 Register 15: ( Default : 0Bh )..................................................................................................17 Register 16: ( Default : 30h ) ..................................................................................................18 Register 17: ( Default : 0Bh )..................................................................................................18 Register 18: ( Default : 00h ) ..................................................................................................18 Register 19: ( Default : 30h ) ..................................................................................................19 Block Write protocol ...............................................................................................................20 Block Read protocol ...............................................................................................................20 Byte Write protocol .................................................................................................................20 Byte Read protocol.................................................................................................................20 ABSOLUTE MAXIMUM RATINGS .......................................................................................21 - II -
ACCESS INTERFACE .............................................................................................................. 20
SPECIFICATIONS .................................................................................................................... 21
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
9.2 9.3 9.4 9.5 9.6 9.7 10. 11. 12. General Operating Characteristics ........................................................................................21 Skew Group timing clock........................................................................................................22 Low Power Differential Electrical Characteristics..................................................................22 PCI Electrical Characteristics.................................................................................................22 48M Electrical Characteristics................................................................................................23 REF Electrical Characteristics ...............................................................................................23
ORDERING INFORMATION..................................................................................................... 24 HOW TO READ THE TOP MARKING...................................................................................... 24 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 25
- III -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
1. GENERAL DESCRIPTION
The W83115RG-BW/W83115WG-BW is a Clock Synthesizer for Intel Broadwater series chipsets. W83115RG-BW/ W83115WG-BW provides all clocks required for the high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and SRC clocks setting, support SATA and DOT clock outputs, all clocks are externally selectable with smooth transitions. The W83115RG-BW/W83115WG-BW provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% down type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83115RG-BW/W83115WG-BW accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
* * * * * * * * * * * * * * 2 pair push-pull Differential clock outputs for CPU. 7 pair push-pull Differential clock outputs for SRC. 1 pair push-pull Differential clock outputs for CPU/SRC selectable. 1 pair push-pull Differential clock outputs for DOT/SRC selectable. 5 PCI clock outputs, 1 free running. 1 48 MHz clock output for USB. 1 14.318MHz REF clock output. Smooth frequency switch with selections from 100 to 400MHz. Step-less frequency programming. I2C 2-wire serial interface and support byte read/write and block read/write. -0.5% down type spread spectrum in H/W and software select mode. Programmable S.S.T. scale to reduce EMI in M/N mode. Programmable registers to enable/disable each output and select modes. Programmable clock outputs slew rate control and skew control.
* 56 pins TSSOP/SSOP package.
-1-
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
3. PIN CONFIGURATION
PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/LTE PCI3 PCI4/SRC5_EN PCI_F0/ITP_EN GNDPCI VDD48 USB_48/FSA GND48 VDD96IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDDA SRCT1/SE1 SRCC1/SE2 GND VDDIO SRCT2/SATAT SRCC2/SATAC GNDSRC SRCT3/CR#_C SRCC3/CR#_D VDDSRCIO SRCT4 SRCC4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
SCLK SDATA FSC/TEST_SEL/REF0 VDDREF XIN XOUT GNDREF FSB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1 CPUC1 VDDCPUIO VOUT CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRCIO SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5
#: Active low
-2-
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
4. BLOCK DIAGRAM
S A TA LO O P U SB LO O P C P U LO O P Spread S pectrum X IN XOUT X TA L OSC D ivider & S ync D ivider S A TA T SA TA C
D O TT D O TC 48M H z
REF 0
3 3 VC O CLK
C P U T 0:2 C P U C 0:2
P C IE LO O P S pread Spectrum
M /N /R atio ROM
D ivider & S nyc
9 9
S R C T 0:8 S R C C 0:8
FS(A:C ) C R #_(A :F) C K_PW R G D ITP _E N S R C 5_E N
2
S E1,2 P C I 0:4,F0
Latch &POR
6
PC I_STO P # C P U_S TO P # PD #
C ontrol Logic &C onfig R egister
S D A TA S C LK
I2C Interface
-3-
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
5. PIN DESCRIPTION
PIN PIN NAME TYPE DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/LTE PCI3 PCI4/SRC5_EN PCIF0/ITP_EN GNDPCI VDD48 USB_48/FSA GND48 VDD96IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDDA SRCT1/SE1 SRCC1/SE2 GND VDDIO SRCT2/SATAT SRCC2/SATAC GNDSRC SRCT3/CR#_C SRCC3/CR#_D VDDSRCIO
I/O PWR I/O I/O OUT I/O I/O PWR PWR I/O PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR I/O I/O PWR
PCI0 clock output or CLKREQ# control for either SRC0 or SRC2 pair Power supply for PCI PCI1 clock output or CLKREQ# control for either SRC1 or SRC4 pair PCI2 clock output and LTE strap PCI3 clock output PCI4 clock output and SRC5 enable strap (1=select SRC5 pair) PCIF0 free running clock output, ITP enable strap (1=select ITP pair) Ground pin Power supply for USB_48 48MHz USB clock and FSA CPU frequency select Ground pin Low voltage I/O power supply 0.8V clock outputs for DOTT or SRCT0 0.8V clock outputs for DOTC or SRCC0 Ground pin Power supply for core 0.8V clock outputs for SRCT1 or 3.3V SE clock output 0.8V clock outputs for SRCC1 or 3.3V SE clock output Ground pin Low voltage I/O power supply 0.8V clock outputs for SRCT2 or SATAT 0.8V clock outputs for SRCC2 or SATAC Ground pin
0.8V clock output for SRCT3 or CLKREQ# control for either SRC0 or SRC2 pair 0.8V clock output for SRCC3 or CLKREQ# control for either SRC1 or SRC4 pair
Low voltage I/O power supply
-4-
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
PIN DESCRIPTION, continued.
PIN
PIN NAME
TYPE
DESCRIPTION
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
SRCT4 SRCC4 CPU_STOP#/SRCC5 PCI_STOP#/SRCT5 VDDSRC SRCC6 SRCT6 GNDSRC SRCC7/CR#_E SRCT7/CR#_F VDDSRCIO CPUC2_ITP/SRCC8 CPUT2_ITP/SRCT8 VOUT VDDCPUIO CPUC1 CPUT1 GNDCPU CPUC0 CPUT0 VDDCPU CK_PWRGD/PD# FSB/TEST_MODE GNDREF XOUT
OUT OUT I/O I/O PWR OUT OUT PWR I/O I/O PWR OUT OUT PWR PWR OUT OUT PWR OUT OUT PWR IN IN PWR OUT
0.8V clock outputs for SRCT4 0.8V clock outputs for SRCC4 CPU_STOP# or 0.8V clock output for SRCC5 PCI_STOP# or 0.8V clock output for SRCT5 Power supply for core 0.8V clock output for SRCC6 0.8V clock output for SRCT6 Ground pin 0.8V clock output for SRCC7 or CLKREQ# control for SRC6 pair 0.8V clock output for SRCT7 or CLKREQ# control for SRC8 pair Low voltage I/O power supply for SRC 0.8V clock output for CPUC2_ITP or SRCC8 0.8V clock output for CPUT2_ITP or SRCT8 Integrated linear regulator voltage control Low voltage I/O power supply for CPU 0.8V clock outputs for CPUC1 0.8V clock outputs for CPUT1 Ground pin 0.8V clock outputs for CPUC0 0.8V clock outputs for CPUT0 Power supply for core Notifies CK505 to sample latched input or power down mode FSB CPU frequency select or entry to test mode input Ground pin Crystal output at 14.318MHz nominally with internal loading capacitors (18pF).
-5-
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
PIN DESCRIPTION, continued.
PIN
PIN NAME
TYPE
DESCRIPTION
52 53 54 55 56
XIN VDDREF
FSC/TEST_SEL/REF0
IN PWR I/O I/O IN
Crystal input with internal loading capacitors (18pF) and feedback resistors. Power supply for REF 14.318MHz REF clock and FSC CPU frequency select or test_sel Serial data of I2C 2-wire control interface. Serial clock of I2C 2-wire control interface.
SDATA SCLK
-6-
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [2:0] value or software programming at SSEL [4:0] (Register 13 bit 7 ~ 3). If FS [2:0] no any external circuit to modify power on status the Gray shading is Hardware default frequency.
BIT 7 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT 6 BIT 5 BIT 4 BIT 3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHZ) 266.68 133.34 200.01 166.68 333.36 100.00 400.01 233.33 266.97 133.93 200.90 166.86 333.72 100.90 400.91 233.86 266.68 133.34 200.01 166.68 333.36 100.00 400.01 233.33 266.97 133.93 200.90 166.86 333.72 100.90 400.91 233.86 SRC (MHZ) 100.00 100.00 100.00 100.01 100.01 100.00 100.00 100.00 100.12 100.45 100.45 100.12 100.12 100.90 100.23 100.23 100.00 100.00 100.00 100.01 100.01 100.00 100.00 100.00 100.12 100.45 100.45 100.12 100.12 100.90 100.23 100.23 SATA (MHZ) 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI (MHZ) 33.33 33.33 33.33 33.34 33.34 33.33 33.33 33.33 33.37 33.48 33.48 33.37 33.37 33.63 33.41 33.41 33.33 33.33 33.33 33.34 33.34 33.33 33.33 33.33 33.37 33.48 33.48 33.37 33.37 33.63 33.41 33.41
-7-
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7. I2C CONTROL AND STATUS REGISTERS
PWD: Power on default value
7.1
BIT
Register 0: ( Default : X1h )
AFFECTED PIN/ FUNCTION NAME(S) PWD AFFECTED PIN / FUNCTION DESCRIPTION TYPE
7 6 5
FSC FSB FSA
X X X 0 : Legacy mode 1 : iMAT mode, Sticky 1 Set via SMBus or dynamically by combination of PWRDWN, CPUSTOP_N and PCISTOP_N. Sticky 1 : Mean that once written to a `1' cannot be cleared until power is removed. Activate PCIELOOP 1 : Enable 0 : Disable Sync SRC clock to CPU 1 : Async, SRC come from PCIELOOP 0 : Sync, SRC come from CPULOOP Sync SATA clock to SRCs 1 : Async, SATA fix at 100M 0 : Sync, SATA follow SRC clocks Save last configuration status in power down mode 1 : Save final configuration 0 : Clear final configuration & return to power on default. Frequency table select bits. Latch
4
IAMT_EN
0
R/W
3
PCIELOOP_EN
0
R/W
2
SRC_SYNC_N
0
R/W
1
FIX_SATA
0
R/W
0
PD_RESTORE
1
R/W
-8-
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.2
BIT
Register 1: ( Default : 83h)
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
DOT96_SEL
1
Select SRC0 or DOT96 0 : SRC0 1 : DOT96 (Default) Down spread or center spread to total 0.5% for CPULOOP 1: Center 0: Down Down spread or center spread to total 0.5% for PCIELOOP 1: Center 0: Down PLL3 quick configuration bits <3:0> See Table2. & Set Reg0-bit3 = 1 prior to selecting these bits except 0000 & 0001. Sync PCI clock to CPU 0 : Async, PCI fix at 33.33M 1 : PCI follow SRC clocks
R/W
6
PLL1_SST_CEN_SEL
0
R/W
5 4 3 2 1 0
PLL3_SST_CEN_SEL PLL3_QCFB<3> PLL3_QCFB<2> PLL3_QCFB<1> PLL3_QCFB<0> FIX_PCI_N
0 0 0 0 1 1
R/W
R/W
R/W
7.3
BIT
Register 2: ( Default : FFh )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
REFEN
1
REF output control 1: Output enable 0: Output disable USB48 output control 1: Output enable 0: Output disable PCIF5 output control 1: Output enable 0: Output disable PCI4 output control 1: Output enable 0: Output disable
R/W
6
USB48EN
1
R/W
5
PCIF5EN
1
R/W
4
PCIEN<4>
1
R/W
-9-
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
Register 2: ( Default : FFh ), continued.
BIT
AFFECTED PIN/ FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
3
PCIEN<3>
1
2
PCIEN<2>
1
1
PCIEN<1>
1
PCI3 output control 1: Output enable 0: Output disable PCI2 output control 1: Output enable 0: Output disable PCI1 output control 1: Output enable 0: Output disable PCI0 output control 1: Output enable 0: Output disable
R/W
R/W
R/W
0
PCIEN<0>
1
R/W
7.4
BIT
Register 3: ( Default : FFh )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
SRCEN<11>
1
6
SRCEN<10>
1
5
SRCEN<9>
1
SRC11 output control 1: Output enable 0: Output disable SRC10 output control 1: Output enable 0: Output disable SRC9 output control 1: Output enable 0: Output disable SRC8 or CPU2_ITP output control 1: Output enable 0: Output disable SRC7 output control 1: Output enable 0: Output disable SRC6 output control 1: Output enable 0: Output disable SRC5 output control 1: Output enable 0: Output disable SRC4 output control 1: Output enable 0: Output disable
R/W
R/W
R/W
4
SRCEN<8>
1
R/W
3
SRCEN<7>
1
R/W
2
SRCEN<6>
1
R/W
1
SRCEN<5>
1
R/W
0
SRCEN<4>
1
R/W
- 10 -
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.5
BIT
Register 4: ( Default : FFh)
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
SRCEN<3>
1
6
SRCEN<2>
1
5
SRCEN<1>
1
4
SRCEN<0>
1
3
CPUEN<1>
1
2
CPUEN<0>
1
1
SS1_EN
1
0
SS3_EN
1
SRC3 output control 1: Output enable 0: Output disable SRC2 or SATA output control 1: Output enable 0: Output disable SRC1 output control 1: Output enable 0: Output disable SRC0 or DOT96 output control 1: Output enable 0: Output disable CPU1 output control 1: Output enable 0: Output disable CPU0 output control 1: Output enable 0: Output disable Spread spectrum enable for CPULOOP 1: Enable 0: Disable Spread spectrum enable for PCIELOOP 1: Enable 0: Disable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
- 11 -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.6
BIT
Register 5: ( Default : 00h )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
CR#_A_EN
0
6
CR#_A_SEL
0
5
CR#_B_EN
0
4
CR#_B_SEL
0
3
CR#_C_EN
0
2
CR#_C_SEL
0
1
CR#_D_EN
0
Enable CR#_A (clock request) feature 1: Enable =>configure PCI0/CR#_A as input pin, CR#_A. =>Set Reg2-Bit0 to 0, disable PCI0 clock output, prior to activate this feature 0 : Disable keep PCI0/CR#_A as output pin, PCI0. Select SRC0 or SRC2 to be controlled by CR#_A. 1: SRC2 0: SRC0 Enable CR#_B (clock request) feature 1: Enable =>configure PCI1/CR#_B as input pin, CR#_B. =>Set Reg2-Bit1 to 0, disable PCI1 clock output, prior to activate this feature 0 : Disable keep PCI1/CR#_B as output pin, PCI1. Select SRC1 or SRC4 to be controlled by CR#_B. 1: SRC4 0: SRC1 Enable CR#_C (clock request) feature 1: Enable =>configure SRC3T/CR#_C as input pin, CR#_C. =>Set Reg4-Bit7 to 0, disable SRC3 clock output, prior to activate this feature 0 : Disable keep SRC3T/CR#_C as output pin, SRC3T. Select SRC2 or SRC0 to be controlled by CR#_C. 1: SRC2 0: SRC0 Enable CR#_D (clock request) feature 1: Enable =>configure SRC3C/CR#_D as input pin, CR#_D. =>Set Reg4-Bit7 to 0, disable SRC3 clock output, prior to activate this feature 0 : Disable, Keep SRC3C/CR#_D as output pin,SRC3C. Select SRC4 or SRC1 to be controlled by CR#_D. 1: SRC4 0: SRC1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
CR#_D_SEL
0
R/W
- 12 -
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.7
BIT
Register 6: ( Default : 0Ch )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
CR#_E_EN
0
6
CR#_F_EN
0
5
CR#_G_EN
0
4
CR#_H_EN
0
Enable CR#_E (clock request) feature for SRC6 1: Enable =>configure SRC7C/CR#_E as input pin, CR#_E. =>Set Reg3-Bit3 to 0, disable SRC7 clock output, prior to activate this feature 0 : Disable keep SRC7C/CR#_E as output pin, SRC7C. Enable CR#_F (clock request) feature for SRC8 1: Enable =>configure SRC7T/CR#_F as input pin, CR#_F. =>Set Reg3-Bit3 to 0, disable SRC7 clock output, prior to activate this feature 0 : Disable keep SRC7T/CR#_F as output pin, SRC7C. Enable CR#_G (clock request) feature for SRC9 1: Enable =>configure SRC11C/CR#_G as input pin, CR#_G. =>Set Reg3-Bit7 to 0, disable SRC11 clock output, prior to activate this feature 0 : Disable, keep SRC11C/CR#_G as output pin, SRC11C. Enable CR#_H (clock request) feature for SRC10 1: Enable =>configure SRC11T/CR#_H as input pin, CR#_H. =>Set Reg3-Bit7 to 0, disable SRC11 clock output, prior to activate this feature 0:Disable, keep SRC11T/CR#_H as output pin, SRC11T.
R/W
R/W
R/W
R/W
3 2 1
Reserved Reserved SRC1_FR_N
1 1 0 SRC1 free running control 1 : Stoppable with PCI_STOP# assertion 0 : Free running SRCs free running control 1 : Stoppable with PCI_STOP# assertion 0 : Free running
R/W R/W R/W
0
SRCs_FR_N
0
R/W
- 13 -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.8
BIT
Register 7: Winbond Chip ID - Project Code Register ( Default : 04h )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
CHIP_ID [7] CHIP_ID [6] CHIP_ID [5] CHIP_ID [4] CHIP_ID [3] CHIP_ID [2] CHIP_ID [1] CHIP_ID [0]
0 0 0 0 0 1 0 0
Winbond Chip ID. W83115RG/WG-BW Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
R R R R R R R R
7.9
BIT
Register 8: ( Default : 0Ch )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1
DEVICE_ID [3] DEVICE_ID [2] DEVICE_ID [1] DEVICE_ID [0] Reserved Reserved SE1EN
0 0 0 0 1 1 0 Single-ended pin17 output enable 1 : Enable 0 : Disable Single-ended pin18 output enable 1 : Enable 0 : Disable R/W R/W R/W 0001 : 64TSSOP 0000 : 56TSSOP R
0
SE2EN
0
R/W
- 14 -
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.10 Register 9: ( Default : 25h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
PCIF5_FR_N
0
6 5 4
LTE_RB Reserved TEST_SEL
0 1 0
PCIF5 free running control 1 : Stoppable with PCI_STOP# assertion 0 : Free running LTE pin strap value 0 : allow over-clocking 1 : forbid over-clocking
R/W
Latch R/W
3 2 1 0
TEST_ENTRY IO_RAIL<2> IO_RAIL<1> IO_RAIL<0>
0 1 0 1
Allow to select output status 0 : All outputs are tri-state 1 : All outputs are REF/N besides REF clock Allow to entry test mode 0 : Normal operation 1 : Entry test mode Programmable VDDXXX_IO 111 : 1.0V 110 : 0.9V 101 : 0.8V 100 : 0.7V others : 0.6V
R/W
R/W
R/W
7.11 Register 10: ( Default : D0h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
NVAL<8> NVAL<9> NVAL<10> MVAL<4> MVAL<3> MVAL<2> MVAL<1> MVAL<0>
1 1 0 1 0 0 0 0 Programmable M divisor for CPU frequency. Default value follow FS=2 (01_0000 = 16) R/W Programmable N divisor value for CPU frequency. Bit 7 ~0 are defined in the Register 11. R/W
- 15 -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.12 Register 11: ( Default : 7Ah )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
NVAL<7> NVAL<6> NVAL<5> NVAL<4> NVAL<3> NVAL<2> NVAL<1> NVAL<0>
0 1 1 1 1 0 1 0
Programmable N divisor for CPU frequency. The bit 8,9,10 is defined in Register 10. Default value follow FS=2 (011_0111_1010 =894-4)
R/W
7.13 Register 12: ( Default : 7Ah )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
N3VAL<7> N3VAL<6> N3VAL<5> N3VAL<4> N3VAL<3> N3VAL<2> N3VAL<1> N3VAL<0>
0 1 1 1 1 0 1 0
Programmable N divisor for SRC frequency. SRC programmable range is 115M ~ 86M.
R/W
7.14 Register 13: ( Default : 10h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
SSEL<4> SSEL<3> SSEL<2> SSEL<1> SSEL<0> EN_SSEL Reserved ITP_EN
0 0 0 1 0 0 0 0 Select SRC8 or CPU2_ITP clock 0: to select the SRC8 clock 1: to select the CPU2_ITP clock Enable software table selection FS[4:0]. 0 = Hardware table setting (Jump mode). 1 = Software table setting through Bit7~3 . (Jumpless mode) R/W R/W R/W Software frequency table selection through I2C R/W
- 16 -
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.15 Register 14: ( Default : 04h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3
Reserved Reserved SATA_SSC_EN PCIEMN_EN CPUMN_EN
0 0 0 0 0 Enable spread spectrum to SATA with -0.5%, only valid in SRCs over-clocking mode. 1 : Enable 0 : Disable Enable programming PCIE frequency Enable programming CPU frequency Software PCISTOP function 0 : Stop all STOPPABLE PCI,PCIF and SRC clock with no glitches. 1 : Resume all STOPED PCI,PCIF and SRC clock with no glitches. Configure the input/output function of SRC5T/PCISTOP_N and SRC5C/PCISTOP_N 1 : Output feature, SRC5. 0 : Input feature, PCISTOP_N & CPUSTOP_N. Frequency table select bit.
R/W R/W
R/W R/W
2
SW_PCISTOP_N
1
R/W
1
SRC5_EN
0
Latch R
Latch R
0
FSD
0
7.16 Register 15: ( Default : 0Bh )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
SPH VAL1<3> SPH VAL1<2> SPH VAL1<1> SPH VAL1<0> SPL VAL1<3> SPL VAL1<2> SPL VAL1<1> SPL VAL1<0>
0 0 0 0 1 0 1 1 Spread Spectrum Down Counter bit 3 ~ bit 0 for CPULOOP. 2's complement representation. Ex: 1 -> 1111 ; 2 -> 1110 ; 7 -> 1001 ; 8 -> 1000 Spread Spectrum Up Counter bit 3 ~ bit 0 for CPULOOP . R/W
- 17 -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.17 Register 16: ( Default : 30h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
INV_CPU INV_SRC SPCNT1<5> SPCNT1<4> SPCNT1<3> SPCNT1<2> SPCNT1<1> SPCNT1<0>
0 0 1 1 0 0 0 0
Invert the CPUCLKT1/0 phase 0: Default 1: Inverse Invert the SRCCLKT phase 0: Default 1: Inverse
R/W R/W
Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us
R/W
7.18 Register 17: ( Default : 0Bh )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved Reserved SPL VAH3<5> SPL VAH3<4> SPL VAH3<3> SPL VAH3<2> SPL VAH3<1> SPL VAH3<0>
0 0 0 0 1 0 1 1 Spread Spectrum DOWN Counter bit5 ~ bit 0 for PCIEXLOOP. 2's complement representation. Ex: 1 -> 111111 ; 2 -> 111110 ; 7 ->111001 ; 8 -> 111000
R/W R/W
7.19 Register 18: ( Default : 00h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved Reserved SPH VAH3<5> SPH VAH3<4> SPH VAH3<3> SPH VAH3<2> SPH VAH3<1> SPH VAH3<0>
0 0 0 0 0 0 0 0 Spread Spectrum UP Counter bit5 ~ bit 0 for PCIEXLOOP. 2's complement representation. Ex: 1 -> 111111 ; 2 -> 111110 ; 7 -> 111001 ; 8 -> 111000
R/W R/W
- 18 -
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.20 Register 19: ( Default : 30h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
INV_PCI
0
Invert the PCICLK phase 0: Default 1: Inverse Invert the USB48M phase 0: Default 1: Inverse
R/W
6 5 4 3 2 1 0
INV_USB48 SPCNT3<5> SPCNT3<4> SPCNT3<3> SPCNT3<2> SPCNT3<1> SPCNT3<0>
0 1 1 0 0 0 0
R/W
Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us
R/W
TABLE 2 : PIN17,18 (SRCT1/SE1, SRCC1/SE2) FREQ CONFIGURATION BASED ON PCIELOOP
R1B4 R1B3 R1B2 R1B1 PIN17 (MHZ) PIN18 (MHZ) SPREAD (%) CLOCK TYPE COMMENT
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
100 100 100 100 100 100 100 24.576 24.576 98.304 27 25 -
100 100 100 100 100 100 100 24.576 98.304 98.304 27 25 -
-
Differential PCIELOOP disable
0.5% down Differential SRC1 follow SRCs 0.5% down Differential SRC1 come from PCIELOOP 1% down Differential SRC1 come from PCIELOOP 1.5% down Differential SRC1 come from PCIELOOP 2% down Differential SRC1 come from PCIELOOP 2.5% down Differential SRC1 come from PCIELOOP Non Non Non Non Non Single End Single End Single End Single End Single End -
- 19 -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
8. ACCESS INTERFACE
The W83115RG-BW/W83115WG-BW provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83115RG-BW/W83115WG-BW is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. The register number is increased by one if using byte data read/write protocol. Example: In block mode, byte number of program register is 1 In byte mode, byte number of program register is 2 (Byte number of block mode +1)
8.1
Block Write protocol
8.2
Block Read protocol
## In block mode, the command code must filled 8'h00
8.3
Byte Write protocol
8.4
Byte Read protocol
- 20 -
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER RATING
Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Absolute VDDIO Core Supply Voltage Absolute VDDIO I/O Supple Voltage Operating VDDIO Core Supply Voltage Operating VDDIO I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model)
-0.5V to +4.6V - 0.5V to + 4.6V 3.135V to 3.465V 3.135V to 3.465V -0.5V to +3.8V - 0.5V to + 3.8V 0.7V to 0.9V 0.7V to 0.9V - 65C to + 150C - 55C to + 125C 0C to + 70C 2000V
9.2
General Operating Characteristics
PARAMETER
SYMBOL
VDD= 3.3V 5 %, TA = 0C to +70C,
MIN MAX UNITS TEST CONDITIONS
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance
VIL VIH VOL VOH Idd Cin Cout Lin 2.4 2.0
0.8 0.4
Vdc Vdc Vdc Vdc CPU = 100 to 400 MHz PCI = 33.3 Mhz with load
350 5 6 7
mA pF pF nH
- 21 -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
9.3 Skew Group timing clock
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDD = 3.3V 5 %, TA = 0C to +70C, Cl=10pF CPU pair to CPU pair Skew SRC pair to SRC pair Skew PCI to PCI Skew 100 100 250 ps ps ps Measure Crossing point Measure Crossing point Measured at 1.5V
9.4
Low Power Differential Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDIO= 0.8V 5 %, TA = 0C to +70C, Test load, Cl=2pF Rising Edge Slew rate Falling Edge Slew rate Absolute crossing point Voltages Voltage High Voltage Low CPU Cycle to Cycle jitter SRC Cycle to Cycle jitter DOT Cycle to Cycle jitter Duty Cycle 45 -300 85 125 250 55 2.5 2.5 300 8 8 550 1150 V/ns V/ns mV mV mV ps ps ps % Measure Differential waveform Measure Differential waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform Measure Differential waveform Measure Differential waveform
9.5
PCI Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 250 55 ps ps ps % mA mA mA mA Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
- 22 -
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
9.6 48M Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 500 55 ps ps ps % mA mA mA mA Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
9.7
REF Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDD= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 29 27 45 -29 -23 500 500 2000 2000 1000 55 ps ps ps % mA mA mA mA Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
- 23 -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
10. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83115RG-BW W83115WG-BW
56 PIN SSOP 56 PIN TSSOP
Commercial, 0C to +70C Commercial, 0C to +70C
11. HOW TO READ THE TOP MARKING
W83115RG-BW 28051234 622GCABA W83115WG-BW 28051234 622LCABA
1st line: Winbond logo and the type number: W83115RG-BW/W83115WG-BW 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 604 G C A BA 622: packages made in '2006, week 22 G: assembly house ID; O means OSE, G means GR, L means Lingsen C: Internal use code A: IC revision BA: mask version All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
- 24 -
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
12. PACKAGE DRAWING AND DIMENSIONS
56 PIN SSOP-300mil
.035 .045
.045 .055 0.40/0.50 DIA
SYMBOL
DIMENSION IN MM
DIMENSION IN INCH
E
END VIEW
HE
A A1 A2 b c D HE E e L L1 Y
MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8
MAX. 0.110 0.016 0.092 0.0135 0.010
TOP VIEW
SEE DETAIL "A"
c
D
A2
A
Y SEATING PLANE e
SIDE VIEW A1
0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8
b
PARTING LINE
c
0
0
L L1
DETAIL"A"
56 PIN TSSOP-240mil
- 25 -
Publication Release Date: December, 2006 Revision 1.0
W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
- 26 -

▲Up To Search▲

Price & Availability of W83115RG-BW

	To Download W83115RG-BW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .