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High Voltage, Latch-up Proof, 4-Channel Multiplexer ADG5404
FEATURES
Latch-up proof 8 kV HBM ESD rating Low on resistance (<10 ) 9 V to 22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at 15 V, 20 V, +12 V, and +36 V VSS to VDD analog signal range
FUNCTIONAL BLOCK DIAGRAM
ADG5404
S1 S2 D S3 S4 1 OF 4 DECODER A0 A1 EN
09203-001
Figure 1.
APPLICATIONS
Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems
GENERAL DESCRIPTION
The ADG5404 is a complementary metal-oxide semiconductor (CMOS) analog multiplexer, comprising four single channels. The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. The ADG5404 is designed on a trench process, which guards against latch-up. A dielectric trench separates the P and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. The ADG5404 switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines, A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up. A dielectric trench separates the P and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. Low RON. Dual-Supply Operation. For applications where the analog signal is bipolar, the ADG5404 can be operated from dual supplies of up to 22 V. Single-Supply Operation. For applications where the analog signal is unipolar, the ADG5404 can be operated from a single-rail power supply of up to 40 V. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V. No VL logic power supply required.
2. 3.
4.
5. 6.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
ADG5404 TABLE OF CONTENTS
Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 15 V Dual Supply ....................................................................... 3 20 V Dual Supply ....................................................................... 4 +12 V Single Supply ..................................................................... 5 +36 V Single Supply ..................................................................... 6 Continuous Current per Channel, S or D ................................. 7 Absolute Maximum Ratings............................................................ 8 ESD Caution...................................................................................8 Pin Configurations and Function Descriptions ............................9 Truth Table .....................................................................................9 Typical Performance Characteristics ........................................... 10 Test Circuits..................................................................................... 14 Terminology .................................................................................... 17 Trench Isolation.............................................................................. 18 Applications Information .............................................................. 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
7/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG5404 SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C
-40C to +85C
-40C to +125C VDD to VSS
Unit V typ max typ max typ max nA typ
Test Conditions/Comments
9.8 11 0.35 0.7 1.2 1.6 0.05 0.25 0.1 0.4 0.1 0.4
14
16
VS = 10 V, IS = -10 mA; see Figure 23 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA
0.9 2
1.1 2.2
VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = VS = 10 V, VD = 10 V; see Figure 24 VS = VS = 10 V, VD = 10 V; see Figure 24 VS = VD = 10 V; see Figure 25
0.75 2 2
3.5 12 12 2.0 0.8
nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ A max V min/max
0.002 0.1 5 187 242 160 204 125 145 45 220 -78 -58 0.009 53 -0.7 19 92 132 45 55 0.001
VIN = VGND or VDD
285 247 168
330 278 183 12
RL = 300 , CL = 35 pF VS = 10 V; see Figure 30 RL = 300 , CL = 35 pF VS = 10 V; see Figure 32 RL = 300 , CL = 35 pF VS = 10 V; see Figure 32 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 31 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 RL = 1k , 15 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V
70 1 9/22
Guaranteed by design; not subject to production test.
Rev. 0 | Page 3 of 20
ADG5404
20 V DUAL SUPPLY
VDD = 20 V 10%, VSS = -20 V 10%, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C
-40C to +85C
-40C to +125C VDD to VSS
Unit V typ max typ max typ max nA typ
Test Conditions/Comments
9 10 0.35 0.7 1.5 1.8 0.05 0.25 0.1 0.4 0.1 0.4
13
15
VS = 15 V, IS = -10 mA; see Figure 23 VDD = +18 V, VSS = -18 V VS = 15 V, IS = -10 mA
0.9 2.2
1.1 2.5
VS = 15 V, IS = -10 mA VDD = +22 V, VSS = -22 V VS = 15 V, VD = 15 V; see Figure 24 VS = 15 V, VD = 15 V; see Figure 24 VS = VD = 15 V; see Figure 25
0.75 2 2
3.5 12 12 2.0 0.8
nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ V min/max
0.002 0.1 5 175 224 148 185 120 142 40 290 -78 -58 0.008 54 -0.6 18 88 129 50 70 0.001
VIN = VGND or VDD
262 222 159
301 250 173 10
RL = 300 , CL = 35 pF VS = +10 V; see Figure 30 RL = 300 , CL = 35 pF VS = 10 V; see Figure 32 RL = 300 , CL = 35 pF VS = 10 V; see Figure 32 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 31 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 RL = 1 k, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = -22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V
110 9/22
Guaranteed by design; not subject to production test.
Rev. 0 | Page 4 of 20
ADG5404
+12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD VDD
1
25C
-40C to +85C
-40C to +125C 0 V to VDD
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max V min/max
Test Conditions/Comments
19 22 0.4 0.8 4.4 5.5 0.02 0.25 0.05 0.4 0.05 0.4
27
31
VS = 0 V to 10 V, IS = -10 mA; see Figure 23 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA
1 6.5
1.2 7.5
VS = 0 V to 10 V, IS = -10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = VD = 1 V/10 V; see Figure 25
0.75 2 2
3.5 12 12 2.0 0.8
0.002 0.1 5 266 358 260 339 135 162 125 92 -78 -58 0.075 43 -1.36 22 105 140 40 50
VIN = VGND or VDD
446 423 189
515 485 210 45
RL = 300 , CL = 35 pF VS = +8 V; see Figure 30 RL = 300 , CL = 35 pF VS = 8 V; see Figure 32 RL = 300 , CL = 35 pF VS = 8 V; see Figure 32 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 31 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 1MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 RL = 1k , 6 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V
65 9/40
Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 20
ADG5404
+36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD VDD
1
25C
-40C to +85C
-40C to +125C 0 V to VDD
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max V min/max
Test Conditions/Comments
10.6 12 0.35 0.7 2.7 3.2 0.05 0.25 0.1 0.4 0.1 0.4
15
17
VS = 0 V to 30 V, IS = -10 mA; see Figure 23 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = -10 mA
0.9 3.8
1.1 4.5
VS = 0 V to 30 V, IS = -10 mA VDD =39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V; see Figure 24 VS = 1 V/30 V, VD = 30 V/1 V; see Figure 24 VS = VD = 1 V/30 V; see Figure 25
0.75 2 2
3.5 12 12 2.0 0.8
0.002 0.1 5 196 256 170 214 130 172 52 280 -78 -58 0.03 47 -0.85 18 89 128 80 100
VIN = VGND or VDD
276 247 167
314 273 176 13
RL = 300 , CL = 35 pF VS = 18 V; see Figure 30 RL = 300 , CL = 35 pF VS = 18 V; see Figure 32 RL = 300 , CL = 35 pF VS = 18 V; see Figure 32 RL = 300 , CL = 35 pF VS1 = VS2 = 18 V; see Figure 31 VS = 18 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 1MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 RL = 1k , 18 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V
130 9/40
Guaranteed by design; not subject to production test.
Rev. 0 | Page 6 of 20
ADG5404
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5.
Parameter CONTINUOUS CURRENT, S OR D VDD = +15 V, VSS = -15 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = +20 V, VSS = -20 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 12 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 36 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) 25C 85C 125C Unit
165 290 176 282 114 203 149 263
96 141 101 146 72 112 89 133
49 57 51 58 42 53 48 56
mA max mA max mA max mA max mA max mA max mA max mA max
Rev. 0 | Page 7 of 20
ADG5404 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 6.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, Sx or D Pins Continuous Current, S or D 2 Operating Temperature Range Storage Temperature Range Junction Temperature Thermal Impedance, JA 16-Lead TSSOP, JA Thermal Impedance (4-Layer Board) 16-Lead LFCSP, JA Thermal Impedance (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free
1
Rating 48 V -0.3 V to +48 V +0.3 V to -48 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 515 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% -40C to +125C -65C to +150C 150C 112.6C/W 30.4C/W 260(+0/-5)C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
2
Overvoltages at the Sx and D pins are clamped by internal diodes. Limit current to the maximum ratings given. See Table 5.
Rev. 0 | Page 8 of 20
ADG5404 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16 EN 15 A0 13 NC 14 A1
VSS 1
A0 EN VSS S1 S2 D NC
1 2 3 4 5 6 7 14 A1 13 GND
PIN 1 INDICATOR
12 GND 11 VDD 10 S3 9 S4
NC 2 S1 3 S2 4
ADG5404
TOP VIEW (Not to Scale)
ADG5404
TOP VIEW (Not to Scale)
12 VDD
10 S4 9 8
NC
09203-002
NC = NO CONNECT
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. TSSOP LFCSP 1 15 2 16 3 4 5 6 7 to 9 10 11 12 13 14 1 3 4 6 2, 5, 7, 8, 13 9 10 11 12 14 EP Mnemonic A0 EN VSS S1 S2 D NC S4 S3 VDD GND A1 Exposed Pad Description Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the Ax logic inputs determine the on switches. Most Negative Power Supply Potential. Source Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. No Connection. Source Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
TRUTH TABLE
Table 8.
EN 0 1 1 1 1
1
A1 X1 0 0 1 1
A0 X1 0 1 0 1
S1 Off On Off Off Off
S2 Off Off On Off Off
S3 Off Off Off On Off
S4 Off Off Off Off On
X = don't care.
Rev. 0 | Page 9 of 20
09203-003
NC
NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
NC 8
NC 7
NC 5
D6
11 S3
ADG5404 TYPICAL PERFORMANCE CHARACTERISTICS
16 TA = 25C 14 12 VDD = +10V VDD = +9V VSS = -10V VSS = -9V VDD = +11V VSS = -11V
12
TA = 25C VDD = 32.4V VSS = 0V
10
ON RESISTANCE ()
ON RESISTANCE ()
VDD = 36V VSS = 0V
8
10 8 6 4 VDD10 +13.5V = VSS = -13.5V VDD = +15V VSS = -15V VDD = +16.5V VSS = -16.5V
6
VDD = 39.6V VSS = 0V
4
2
2 0 -20
0
-15
-10
-5
0 VS, VD (V)
5
10
15
20
09203-029
0
5
10
15
20
25
30
35
40
45
VS, VD (V)
Figure 4. RON as a Function of VD (VS), Dual Supply
12 VDD = +18V VSS = -18V
ON RESISTANCE ()
Figure 7. RON as a Function of VD (VS), Single Supply
18 16 14
10
ON RESISTANCE ()
8 VDD = +20V VSS = -20V VDD = +22V VSS = -22V
12 10 8 6 4
TA = +125C TA = +85C TA = +25C TA = -40C
6
4
2
2
-20
-15
-10
-5
0 VS, VD (V)
5
10
15
20
25
09203-030
-5
0 VS, VD (V)
5
10
15
Figure 5. RON as a Function of VD (VS), Dual Supply
25
TA = 25C VDD = +10V VSS = 0V VDD = 10.8V VSS = 0V
Figure 8. RON as a Function of VD (VS) for Different Temperatures, 15 V Dual Supply
16 14 12
20
VDD = +9V VSS = 0V
ON RESISTANCE ()
ON RESISTANCE ()
TA = +125C
10 8 6 4
15
VDD = 11V VSS = 0V VDD = 13.2V VSS = 0V
TA = +85C TA = +25C TA = -40C
10
VDD = 12V VSS = 0V
5
2
-5
0
5
10
15
20
VS, VD (V)
VS, VD (V)
Figure 6. RON as a Function of VD (VS), Single Supply
Figure 9. RON as a Function of VD (VS) for Different Temperatures, 20 V Dual Supply
Rev. 0 | Page 10 of 20
09203-024
0
2
4
6
8
10
12
14
09203-027
0
VDD = +20V VSS = -20V 0 -20 -15 -10
09203-023
0 -25
TA = 25C
VDD = +15V VSS = -15V 0 -15 -10
09203-028
ADG5404
30 VDD = 12V VSS = 0V
1.0
25
VDD = +20V VSS = -20V VBIAS = +15V/-15V
ID, IS (ON) + + ID (OFF) - + IS (OFF) + -
0.5
TA = +125C
20 TA = +85C 15 TA = +25C TA = -40C
LEAKAGE CURRENT (nA)
ON RESISTANCE ()
0
-0.5
IS (OFF) - + ID, IS (ON) - -
10
-1.0 ID (OFF) + - -1.5
5
09203-025
0
2
4
6 VS, VD (V)
8
10
12
0
25
50
75
100
125
TEMPERATURE (C)
Figure 10. RON as a Function of VD (VS) for Different Temperatures, 12 V Single Supply
16 14 TA = +125C TA = +85C TA = +25C TA = -40C
Figure 13. Leakage Currents vs. Temperature, 20 V Dual Supply
0.6 VDD = 12V VSS = 0V VBIAS = 1V/10V ID, IS (ON) + +
0.4
LEAKAGE CURRENT (nA)
12
ID (OFF) - + 0.2 IS (OFF) + -
ON RESISTANCE ()
10 8 6 4 2 0
0
-0.2
IS (OFF) - + ID, IS (ON) - -
-0.4
VDD = 36V VSS = 0V
09203-026
ID (OFF) + -
10 15 20 VS, VD (V) 25 30 35 40
0
5
0
25
50
75
100
125
TEMPERATURE (C)
Figure 11. RON as a Function of VD (VS) for Different Temperatures, 36 V Single Supply
1.0 VDD = +15V VSS = -15V VBIAS = +10V/-10V 0.5 ID, IS (ON) + + ID (OFF) - + IS (OFF) + - 0
Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply
1.0
VDD = 36V VSS = 0V VBIAS = 1V/30V IS (OFF) + -
ID, IS (ON) + + ID (OFF) - +
0.5
LEAKAGE CURRENT (nA)
LEAKAGE CURRENT (nA)
0
-0.5
IS (OFF) - + ID, IS (ON) - -
-0.5
IS (OFF) - + ID, IS (ON) - -
-1.0
ID (OFF) + -
-1.0
ID (OFF) + -
-1.5
09203-032
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 12. Leakage Currents vs. Temperature, 15 V Dual Supply
Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. 0 | Page 11 of 20
09203-034
-1.5
-2.0
09203-031
-0.6
09203-033
0
-2.0
ADG5404
0 -10 -20 TA = 25C VDD = +15V VSS = -15V
CHARGE INJECTION (pC)
450
TA = 25C
400 350 300 250 200 150 100 50 -20
VDD = +15V VSS = -15V VDD = 12V VSS = 0V VDD = +20V VSS = -20V VDD = 36V VSS = 0V
OFF ISOLATION (dB)
-30 -40 -50 -60 -70 -80 -90
09203-019
1k
10k
100k
1M
10M
100M
1G
-10
0
10 VS (V)
20
30
40
FREQUENCY (Hz)
Figure 16. Off Isolation vs. Frequency, 15 V Dual Supply
0 -10 -20
TA = 25C VDD = +15V VSS = -15V
Figure 19. Charge Injection vs. Source Voltage
350 300 VDD = +12V, VSS = 0V 250 VDD = +36V, VSS = 0V
CROSSTALK (dB)
-30
TIME (ns)
-40 -50 -60 -70 -80 -90
09203-016
200 VDD = +15V, VSS = -15V VDD = +20V, VSS = -20V 100
150
50 0 -40
100k
1M
10M
100M
1G
-20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (C)
Figure 17. Crosstalk vs. Frequency, 15 V Dual Supply
0 -0.5 -1.0
INSERTION LOSS (dB)
Figure 20. Transition Time vs. Temperature
0 -10 -20 -30 TA = 25C VDD = +15V VSS = -15V NO DECOUPLING CAPACITORS
TA = 25C VDD = +15V VSS = -15V
-1.5
ACPSRR (dB)
-2.0 -2.5 -3.0 -3.5 -4.0 -4.5
09203-020
-40 -50 -60 -70 -80 -90 DECOUPLING CAPACITORS
10k
100k
1M
10M
100M
10k
100k FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 18. On Response vs. Frequency, 15 V Dual Supply
Figure 21. ACPSRR vs. Frequency, 15 V Dual Supply
Rev. 0 | Page 12 of 20
09203-017
-5.0 1k
-100 1k
09203-022
-100 10k
09203-021
-100
ADG5404
0.10 0.09 0.08 0.07 LOAD = 1k TA = 25C VDD = 12V, VSS = 0V, VS = 6V p-p
THD + N (%)
0.06 0.05 0.04 VDD = 36V, VSS = 0V, VS = 18V p-p 0.03 0.02 0.01 0 0 VDD = 15V, VSS = 15V, VS = 15V p-p VDD = 20V, VSS = 20V, VS = 20V p-p 5 10 FREQUENCY (MHz) 15 20
09203-018
Figure 22. THD + N vs. Frequency, 15 V Dual Supply
Rev. 0 | Page 13 of 20
ADG5404 TEST CIRCUITS
VDD
0.1F VSS
0.1F
NETWORK ANALYZER 50 Sx 50 VS
D
VDD
VSS
V
Sx
D
IDS
GND
RL 50
VOUT
VS
09203-005
OFF ISOLATION = 20 log
VOUT VS
Figure 23. On Resistance
Figure 26. Off Isolation
VDD
0.1F
VSS
0.1F NETWORK ANALYZER 50
VDD Sx
VSS
VS
D
IS (OFF) A
VS
ID (OFF) Sx D A
VD
09203-006
GND
RL 50
VOUT
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 24. Off Leakage
Figure 27. Bandwidth
VDD 0.1F
VSS 0.1F
NETWORK ANALYZER VOUT RL 50
VDD S1
VSS
D S2
RL 50
VS
ID (ON) NC Sx D A VD
09203-007
GND
NC = NO CONNECT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT VS
Figure 25. On Leakage
Figure 28. Channel-to-Channel Crosstalk
Rev. 0 | Page 14 of 20
09203-010
09203-009
09203-008
ADG5404
VDD 0.1F VSS 0.1F AUDIO PRECISION VDD Sx IN D VIN GND RL 1k VS V p-p VSS
RS
VOUT
Figure 29. THD + Noise
0.1F
VDD VSS
0.1F ADDRESS DRIVE (VIN) VS1 3V 50% 0V 50%
VIN
VDD VSS S1 A1 S2 A0 S3 S4
2.4V EN GND D RL 300
09203-011
VS4 VOUT CL 35pF
VOUT
90% 90%
09203-012
tTRANSITION
tTRANSITION
Figure 30. Address to Output Switching Times
0.1F
VDD VSS
0.1F
VIN
300
A1 A0
VDD VSS S1 S2 S3 S4
D GND
VS1
ADDRESS DRIVE (VIN)
3V 0V
2.4V
EN
VOUT
tBBM
Figure 31. Break-Before-Make Time Delay
Rev. 0 | Page 15 of 20
09203-013
RL 300
CL 35pF
VOUT
80%
80%
ADG5404
0.1F
VDD VSS
0.1F ENABLE DRIVE (VIN) 3V 50% 0V 50%
VDD VSS S1 A1 S2 A0 S3 S4
EN VIN 300 GND D RL 300
VS
VOUT OUTPUT
0.9VOUT
0.9VOUT
VOUT
CL 35pF
0V
tOFF (EN)
Figure 32. Enable-to-Output Switching Delay
VDD
VSS VOUT VOUT QINJ = CL x VOUT VOUT CL 1nF VIN
VDD RS VS
Sx
VSS
D
SW OFF SW ON
SW OFF
DECODER GND
EN
Figure 33. Charge Injection
Rev. 0 | Page 16 of 20
09203-015
A1 A2
VIN
SW OFF
SW OFF
09203-014
tON (EN)
ADG5404 TERMINOLOGY
IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, which is measured with reference to ground. CD (Off) The off switch drain capacitance, which is measured with reference to ground. CD, CS (On) The on switch capacitance, which is measured with reference to ground. CIN The digital input capacitance. tTRANSITION The delay time between the 50% and 90% points of the digital input and switch-on condition when switching from one address state to another. tON (EN) The delay between applying the digital control input and the output switching on. See Figure 32. tOFF (EN) The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. ACPSRR (AC Power Supply Rejection Ratio) The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the part's ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.
Rev. 0 | Page 17 of 20
ADG5404 TRENCH ISOLATION
In the ADG5404, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction-isolated switches, are eliminated, and the result is a completely latch-up proof switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon-controlled rectifier (SCR) type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch.
NMOS PMOS
P-WELL
N-WELL
TRENCH BURIED OXIDE LAYER HANDLE WAFER
09203-004
Figure 34. Trench Isolation
Rev. 0 | Page 18 of 20
ADG5404 APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5404 high voltage multiplexer allows single-supply operation from 9 V to 40 V and dual-supply operation from 9 V to 22 V. The ADG5404, as well as three other ADG54xx family members, ADG5412/ADG5413 and ADG5436, achieve an 8 kV human body model ESD rating that provides a robust solution and eliminates the need for separate protection circuitry designs in some applications.
Rev. 0 | Page 19 of 20
ADG5404 OUTLINE DIMENSIONS
5.10 5.00 4.90
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 0.65 BSC 1.05 1.00 0.80 0.15 0.05 COPLANARITY 0.10 1.20 MAX
0.20 0.09 8 0
0.30 0.19
SEATING PLANE
0.75 0.60 0.45
061908-A
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 35. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
PIN 1 INDICATOR
4.10 4.00 SQ 3.90 0.65 BSC
0.35 0.30 0.25
13 12 EXPOSED PAD 1 16
PIN 1 INDICATOR
4 9 8 5
2.70 2.60 SQ 2.50
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.45 0.40 0.35
0.25 MIN
BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADG5404BRUZ ADG5404BRUZ-REEL7 ADG5404BCPZ-REEL7
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
012909-B
Package Option RU-14 RU-14 CP-16-17
Z = RoHS Compliant Part.
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09203-0-7/10(0)
Rev. 0 | Page 20 of 20

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