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Quad, Current-Output, Serial-Input 16-/14-Bit DACs AD5544/AD5554
FEATURES
AD5544 16-bit resolution AD5554 14-bit resolution 2 mA full-scale current 20%, with VREF = 10 V 2 s settling time VSS BIAS for zero-scale error reduction @ temp midscale or zero-scale reset Four separate, 4-Q multiplying reference inputs SPI(R)-compatible 3-wire interface Double buffered registers enable Simultaneous multichannel change Internal power ON reset Compact SSOP-28 package
FUNCTIONAL BLOCK DIAGRAM
VREFA B C D D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 VDD RFBA INPUT REGISTER R DAC A REGISTER R DAC A IOUTA AGNDA RFBB 16 INPUT REGISTER R DAC B REGISTER R DAC B IOUTB AGNDB RFBC INPUT REGISTER R DAC C REGISTER R DAC C IOUTC AGNDC CS CLK EN DAC A B C D 2:4 DECODE INPUT REGISTER R DAC D REGISTER R DAC D RFBD IOUTD AGNDD POWERON RESET
SDO
SDI
APPLICATIONS
Automatic test equipment Instrumentation Digitally controlled calibration
AD5544
AGNDF
00943-0-001
DGND
RS
MSB
LDAC
VSS
Figure 1.
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current-output, digital to-analog converters are designed to operate from a single 5 V supply. The applied external reference input voltage (VREF) determines the full-scale output current. Integrated feedback resistors (RFB) provide temperature-tracking, full-scale voltage outputs when combined with an external I-to-V precision amplifier.
INL (LSB)
1.0 0.5 0 -0.5 -1.0 1.0 0.5 0 -0.5 -1.0 1.0 0.5 0 -0.5 -1.0 1.0 0.5 0
00943-0-002
DAC A
DAC B
A double-buffered serial-data interface offers high speed, 3-wire, SPI- and microcontroller-compatible inputs using serialdata-in (SDI), a chip-select (CS), and clock (CLK) signals. In addition, a serial-data-out pin (SDO) allows for daisy-chaining when multiple packages are used. A common, level-sensitive, load-DAC strobe (LDAC) input allows the simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power ON reset forces the output voltage to zero at system turn ON. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to half-scale code when MSB = 1. The AD5544/AD5554 are packaged in the compact SSOP-28.
DAC C
DAC D
-0.5 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE (Decimal)
Figure 2. AD5544 INL vs. Code Plot (TA = 25C)
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD5554/AD5554 TABLE OF CONTENTS
Specifications..................................................................................... 3 AD5544 Electrical Characteristics ............................................. 3 AD5554 Electrical Characteristics ............................................. 4 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ........................................... 10 Circuit Operation ........................................................................... 14 D/A Converter ............................................................................ 14 Serial Data Interface....................................................................... 16 Power On Reset .......................................................................... 17 Applications ................................................................................ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
12/04--Rev. 0 to Rev. A Updated Format...................................................................... Universal Change to Electrical Characteristics Tables .......................................4 Change to Pin Description Table.......................................................10 Addition of Power Supply Sequence Section...................................19 Addition of Layout and Power Supply Bypassing Section .............19 Addition of Grounding Section.........................................................19 Addition of Figure 32..........................................................................19 4/00--Revision 0: Initial Version
Rev. A | Page 2 of 20
AD5544/AD5554 SPECIFICATIONS
AD5544 ELECTRICAL CHARACTERISTICS
VDD = 5 V 10%, VSS = 0 V, IOUTX = virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE1 Resolution Relative Accuracy Differential Nonlinearity Output Leakage Current Full-Scale Gain Error Full-Scale Tempco2 Feedback Resistor REFERENCE INPUT VREFX Range Input Resistance Input Resistance Match Input Capacitance2 ANALOG OUTPUT Output Current Output Capacitance2 LOGIC INPUT AND OUTPUT Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance2 Logic Output Low Voltage Logic Output High Voltage INTERFACE TIMING2, 3 Clock Width High Clock Width Low CS to Clock Setup Clock to CS Hold Clock to SDO Prop Delay Load DAC Pulse Width Data Setup Data Hold Load Setup Load Hold SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Negative Supply Current Power Dissipation Power Supply Sensitivity Symbol N INL DNL IOUTX IOUTX GFSE TCVFS RFBX VREFX RREFX RREFX CREFX IOUTX COUTX VIL VIH IIL CIL VOL VOH tCH tCL tCSS tCSH tPD tLDAC tDS tDH tLDS tLDH VDD RANGE IDD ISS PDISS PSS Condition 1 LSB = VREF/216 = 153 V when VREF = 10 V Min Typ Max 16 4 1.5 10 20 3 8 +15 8 Unit Bits LSB LSB nA nA mV ppm/C k V k % pF mA pF V V A pF V V ns ns ns ns ns ns ns ns ns ns V A A mW %/%
Data = 0000H, TA = 25C Data = 0000H, TA = TA max Data = FFFFH VDD = 5 V 4 -15 4 Channel-to-channel
0.75 1 6
6 1 5
Data = FFFFH Code-dependent
1.25 80
2.5
0.8 2.4 1 10 0.4 4 25 25 0 25 2 25 20 20 5 25 4.5 Logic inputs = 0 V Logic inputs = 0 V, VSS = -5 V Logic inputs = 0 V VDD = 5% 50 0.001
IOL = 1.6 mA IOH = 100 A
20
5.5 250 1 1.25 0.006
Rev. A | Page 3 of 20
AD5554/AD5554
Parameter AC CHARACTERISTICS4 Output Voltage Settling Time Output Voltage Settling Time Reference Multiplying BW DAC Glitch Impulse Feedthrough Error Crosstalk Error Digital Feedthrough Total Harmonic Distortion Output Spot Noise Voltage Symbol tS tS BW - 3 dB Q VOUTX/VREFX VOUTA/VREFB Q THD eN Condition To 0.1% of full scale, data = 0000H to FFFFH to 0x0000 To 0.0015% of full scale, data = 0000H to FFFFH to 0000H VREFX = 100 mV rms, data = FFFFH, CFB = 15 pF VREFX = 10 V, data 0000H to 8000H to 0000H Data = 0000H, VREFX = 100 mV rms, f = 100 kHz Data = 0000H, VREFB = 100 mV rms, adjacent channel, f = 100 kHz CS = 1, and fCLK = 1 MHz VREF = 5 V p-p, data = FFFFH, f = 1 kHz f = 1 kHz, BW = 1 Hz Min Typ 1 2 2 12 -65 -90 5 -90 7 Max Unit s s MHz nV-s dB dB nV-s dB nVHz
1
All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25 C. These parameters are guaranteed by design and not subject to production testing. 3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 4 All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.
2
AD5554 ELECTRICAL CHARACTERISTICS
VDD = 5 V 10%, VSS = 0 V, IOUTX = virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless otherwise noted. Table 2.
Parameter STATIC PERFORMANCE1 Resolution Relative Accuracy Differential Nonlinearity Output Leakage Current Full-Scale Gain Error Full-Scale Tempco2 Feedback Resistor REFERENCE INPUT VREFX Range Input Resistance Input Resistance Match Input Capacitance2 ANALOG OUTPUT Output Current Output Capacitance2 LOGIC INPUT AND OUTPUT Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance2 Logic Output Low Voltage Logic Output High Voltage Symbol N INL DNL IOUTX IOUTX GFSE TCVFS RFBX VREFX RREFX RREFX CREFX IOUTX COUTX VIL VIH IIL CIL VOL VOH Condition 1 LSB = VREF/214 = 610 V when VREF = 10 V Min Typ Max 14 1 1 10 20 10 8 +15 8 Unit Bits LSB LSB nA nA mV ppm/C k V k % pF mA pF V V A pF V V
Data = 0000H, TA = 25C Data = 0000H, TA = TA Max Data = 3FFFH VDD = 5 V 4 -15 4 Channel-to-channel
2 1 6
6 1 5
Data = 3FFFH Code-dependent
1.25 80
2.5
0.8 2.4 1 10 0.4 4
IOL = 1.6 mA IOH = 100 A
Rev. A | Page 4 of 20
AD5544/AD5554
Parameter INTERFACE TIMING2, 3 Clock Width High Clock Width Low CS to Clock Setup Clock to CS Hold Clock to SDO Prop Delay Load DAC Pulse Width Data Setup Data Hold Load Setup Load Hold SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Negative Supply Current Power Dissipation Power Supply Sensitivity AC CHARACTERISTICS4 Output Voltage Settling Time Output Voltage Settling Time Reference Multiplying BW DAC Glitch Impulse Feedthrough Error Crosstalk Error Digital Feedthrough Total Harmonic Distortion Output Spot Noise Voltage Symbol tCH tCL tCSS tCSH tPD tLDAC tDS tDH tLDS tLDH VDD RANGE IDD ISS PDISS PSS tS tS BW - 3 dB Q VOUTX/VREFX VOUTA/VREFB Q THD eN Condition Min 25 25 0 25 2 25 20 20 5 25 4.5 Logic inputs = 0 V Logic inputs = 0 V, VSS = -5 V Logic inputs = 0 V VDD = 5% To 0.1% of full scale, data = 0000H to 3FFFH to 0000H To 0.0015% of full scale, data = 0000H to 3FFFH to 0000H VREFX = 100 mV rms, data = 3FFFH, CFB = 15 pF VREFX = 10 V, data 0000H to 2000H to 0000H Data = 0000H, VREFX = 100 mV rms, f = 100 kHz Data = 0000H, VREFB = 100 mV rms, adjacent channel, f = 100 kHz CS = 1, and fCLK = 1 MHz VREF= 5 V p-p, data = 3FFFH, f = 1 kHz f = 1 kHz, BW = 1 Hz 50 0.001 Typ Max Unit ns ns ns ns ns ns ns ns ns ns V A A mW %/% s s MHz nV-s dB dB nV-s dB nVHz
20
5.5 250 1 1.25 0.006
1 2 2 12 -65 -90 5 -90 7
1
All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25C. These parameters are guaranteed by design and not subject to production testing. 3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 4 All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.
2
Rev. A | Page 5 of 20
AD5554/AD5554 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VDD to GND VSS to GND VREF to GND Logic Input and Output to GND V(IOUT) to GND AGNDX to DGND Input Current to Any Pin Except Supplies Package Power Dissipation Thermal Resistance 28-Lead Shrink Surface-Mount (RS-28) Maximum Junction Temperature (TJ Max) Operating Temperature Range: Model A Storage Temperature Range Lead Temperature: RS-28 (Vapor Phase, 60 secs) RS-28 (Infrared, 15 secs) Rating -0.3 V, +8 V +0.3 V, -7 V -18 V, +18 V -0.3 V, +8 V -0.3 V, VDD+ 0.3 V -0.3 V, + 0.3 V 50 mA (TJ Max - TA)/JA JA 100C/W 150C -40C to +85C -65C to +150C 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 20
AD5544/AD5554 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGNDA 1 IOUTA 2 VREF A 3 RFBA 4 MSB 5 RS 6 VDD 7
28 27 26 25
AGNDD IOUTD VREFD RFBD DGND VSS
AD5544/ AD5554
24 23
22 AGNDF TOP VIEW CS 8 (Not to Scale) 21 LDAC 20 19 18 17 16 15
CLK 9 SDI 10 RFBB 11 VREF B 12 IOUTB 13 AGNDB 14
SDO NC RFBC VREFC IOUTC AGNDC
00943-0-005
NC = NO CONNECT
Figure 3. AD5544/AD5554 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Name AGNDA IOUTA VREFA RFBA MSB RS Function DAC A Analog Ground. DAC A Current Output. DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin. Establish voltage output for DAC A by connecting to external amplifier output. MSB Bit. Set pin during a reset pulse (RS) or at system power ON if tied to ground or VDD. Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD5544 and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB = 0. Register Data = 8000H for AD5544 and 2000H. Positive Power Supply Input. Specified range of operation 5 V 10%. Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input register when CS/LDAC returns high. Does not effect LDAC operation. Clock Input. Positive edge clocks data into shift register. Serial Data Input. Input data loads directly into the shift register. Establish voltage output for DAC B by connecting to external amplifier output. DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin. DAC B Current Output. DAC B Analog Ground. DAC C Analog Ground. DAC C Current Output. DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin. Establish voltage output for DAC C by connecting to external amplifier output. No Connect. Leave pin unconnected. Serial Data Output. Input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD5544 and 17 clock pulses for AD5554 after input at the SDI pin. Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous active low input. See Table 5 and Table 6 for operation. High Current Analog Force Ground. Negative Bias Power Supply Input. Specified range of operation: -5.5 V to +0.3 V. Digital Ground Pin. Establish Voltage Output for DAC D by Connecting to External Amplifier Output. DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin. DAC D Current Output. DAC D Analog Ground.
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VDD CS CLK SDI RFBB VREFB IOUTB AGNDB AGNDC IOUTC VREFC RFBC NC SDO LDAC AGNDF VSS DGND RFBD VREFD IOUTD AGNDD
Rev. A | Page 7 of 20
AD5554/AD5554
SDI A1 A0 D15 D14 D13 D12 D11 D10 D1 D0 INPUT REG LD
CLK
CS
tCSS
tDS
tDH
tCH
tCL
tCSH
LDAC
tLDS tPD
SDO
tLDH
tLDAC
00943-0-003
Figure 4. AD5544 Timing Diagram
SDI
A1
A0
D13
D12
D11
D10
D09
D08
D1
D0 INPUT REG LD
CLK
CS
tCSS
tDS
tDH
tCH
tCL
tCSH
tLDS
LDAC
tLDH
tPD
SDO
tLDAC
00943-0-004
Figure 5. AD5554 Timing Diagram
Table 5. AD55441 Control-Logic Truth Table
CS H L L L CLK X L LDAC H H H H H L H RS H H H H H H H H L L MSB X X X X X X X X 0 H Serial Shift Register Function No Effect No Effect Shift-Register-Data Advanced One Bit No Effect No Effect No Effect No Effect No Effect No Effect No Effect Input Register Function Latched Latched Latched Latched Selected DAC Updated with Current SR Contents Latched Latched Latched Latched Data = 0000H Latched Data = 8000H DAC Register Latched Latched Latched Latched Latched Transparent Latched Latched Latched Data = 0000H Latched Data = 8000H
+
H L X X X X X
+
H H H H H
+
H H
1
For the AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.
Rev. A | Page 8 of 20
AD5544/AD5554
Table 6. AD55541 Control-Logic Truth Table
CS H L L L CLK X L LDAC H H H H H L H RS H H H H H H H H L L MSB X X X X X X X X 0 H
3
Serial Shift Register2 Function No Effect No Effect Shift-Register-Data Advanced One Bit No Effect No Effect No Effect No Effect No Effect No Effect No Effect
Input Register2 Function Latched Latched Latched Latched Selected DAC Updated with Current Shift-Register Contents4 Latched Latched Latched Latched Data = 0000H Latched Data = 2000H
DAC Register Latched Latched Latched Latched Latched Transparent Latched Latched Latched Data = 0000H Latched Data = 2000H
+2
H L X X X X X
+2
H H H H H
+
H H
1 2
For the AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin. positive logic transition. + 3 X = don't care. 4 At power on both the input register and the DAC register are loaded with all zeros.
Table 7. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
Bit Position Data Word MSB B17 A1 B16 A0 B15 D15 B14 D14 B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0
1
Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line's positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (Bits D15 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0. Any extra bits clocked into the AD5544 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 8. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
Bit Position Data Word MSB B15 A1 B14 A0 B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0
1
Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line's positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (Bits D13 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0. Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 9. Address Decode
A1 0 0 1 1 A0 0 1 0 1 DAC Decoded DAC A DAC B DAC C DAC D
Rev. A | Page 9 of 20
AD5554/AD5554 TYPICAL PERFORMANCE CHARACTERISTICS
0.50 0.25 0 -0.25 -0.50 0.50 0.25 0
DAC A
0.75 0.50 0.25 0 -0.25 -0.50 -0.75 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 0.75 0.50 0.25 0 -0.25 -0.50 -0.75
DAC A
DAC B
DNL (LSB)
-0.25 -0.50 0.50 0.25 0 -0.25 -0.50 0.50 0.25 0 -0.25 -0.50 0 8192
DNL (LSB)
DAC B
DAC C
DAC C
DAC D
DAC D
16384 24576 32768 40960 49152 57344 65536 CODE (Decimal)
00943-0-006
0
2048
4096
6144 8192 10240 12288 14336 16384 CODE (Decimal)
Figure 6. AD5544 DNL vs. Code, TA = 25C
1.0 0.5 0 -0.5 -1.0 1.0 0.5 0 -0.5
Figure 8. AD5554 DNL vs. Code, TA = 25C
2.0
DAC A
INTEGRAL NONLINEARITY ERROR (LSB)
1.5 1.0 0.5 0 -0.5
VDD = 5V VREF = 10V TA = 25C
F000H
8000H
DAC B
7FFFH
INL (LSB)
-1.0 1.0 0.5 0 -0.5 -1.0 1.0 0.5 0
00943-0-007
0FFFH -1.0 -1.5 -2.0 -1500
00943-0-009
DAC C
-1000
0 -500 500 OP AMP OFFSET VOLTAGE (V)
1000
1500
DAC D
Figure 9. AD5544 Integral Nonlinearity Error vs. Op Amp Offset
-0.5 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE (Decimal)
Figure 7. AD5554 INL vs. Code, TA = 25C
Rev. A | Page 10 of 20
00943-0-008
AD5544/AD5554
0.75
10.0
INTEGRAL NONLINEARITY ERROR (LSB)
0.50
VDD = 5V VREF = 10V TA = 25C 3000H
7.5 5.0
VDD = 5V VREF = 10V TA = 25C
0.25 2000H 0 1FFFH
GAIN ERROR (LSB)
00943-0-010
2.5 0 -2.5 -5.0
-0.25
0FFFH
-0.50
-7.5
-0.75 0 -2000 -1500 -1000 -500 500 1000 OP AMP OFFSET VOLTAGE (V)
1500
2000
-10.0 -1500
-1000
0 -500 500 OP AMP OFFSET VOLTAGE (V)
1000
1500
Figure 10. AD5554 Integral Nonlinearity Error vs. Op Amp Offset
Figure 13. AD5544 Gain Error vs. Op Amp Offset
1.00
4 VDD = 5V VREF = 10V TA = 25C 8000H 3 2 VDD = 5V VREF = 10V TA = 25C
DIFFERENTIAL NONLINEARITY ERROR (LSB)
0.75 0.50
GAIN ERROR (LSB)
1 0 -1 -2 -3 -4
0.25 0
F000H
0FFFH -0.25 -0.50 -0.75
00943-0-011
-1.00 -1000
-750
0 -500 -250 250 500 OP AMP OFFSET VOLTAGE (V)
750
1000
-5 -1500
-1000
0 -500 500 OP AMP OFFSET VOLTAGE (V)
1000
1500
Figure 11. AD5544 Differential Nonlinearity Error vs. Op Amp Offset
Figure 14. AD5554 Gain Error vs. Op Amp Offset
0.3
30
VDD = 5V VREF = 10V TA = 25C 2000H
DIFFERENTIAL NONLINEARITY ERROR (LSB)
0.2
SS = 120 UNITS VDD = 5V VREF = 10V TA = -40C TO +85C 20
FREQUENCY
0.1
3000H
0 0FFFH -0.1 ACCURACY DEGRADATION DUE TO EXTERNAL OP AMP INPUT OFFSET VOLTAGE SPECIFICATION.
00943-0-012
10
-0.2
-0.3 -1500
0
-1000
0 -500 500 OP AMP OFFSET VOLTAGE (V)
1000
1500
0
0.5 1.0 FULL-SCALE TEMPCO (ppm/C)
1.5
Figure 12. AD5554 Differential Nonlinearity Error vs. Op Amp Offset
Figure 15. AD5544 Full-Scale Tempco (ppm/C)
Rev. A | Page 11 of 20
00943-0-015
00943-0-014
00943-0-013
AD5554/AD5554
50 SS = 180 UNITS VDD = 5V VREF = 10V TA = -40C TO +85C
40
FREQUENCY
30
VDD = 5V VREF = 10V TA = 25C AV = -343 1LSB = 52mV
VOUT (10V/DIV)
VOUT (50mV/DIV)
20
10
1s/DIV
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 FULL-SCALE ERROR TEMPCO (ppm/C) 1.8
00943-0-016
Figure 16. AD5554 Full-Scale Tempco (ppm/C)
Figure 19. AD5544 Small Signal Settling Time
7FFFH
8000H
VDD = 5V VREF = 10V TA = 25C CS (5V/DIV)
10000 VDD = 5V VREF = 10V TA = 25C 5555H
FFFFH 1000 8000H 0000H
VOUT (50mV/DIV)
IDD (A)
100
00943-0-017
100ns/DIV
00943-0-019
10 1k 10k 100k 1M CLOCK FREQUENCY (Hz) 10M 100M
Figure 17. AD5544 Midscale Transition
Figure 20. AD5544 Power Supply Current vs. Clock Frequency
0000H
FFFFH
VDD = 5V VREF = 10V TA = 25C
10000
CS (5V/DIV)
VDD = 5V VREF = 10V TA = 25C
1555H
3FFFH 1000 2000H 0000H
VOUT (5V/DIV)
IDD (A)
100
00943-0-018
2s/DIV
10 1k 10k 100k 1M CLOCK FREQUENCY (Hz) 10M 100M
00943-0-021
Figure 18. AD5544 Large Signal Settling Time
Figure 21. AD5554 Power Supply Current vs. Clock Frequency
Rev. A | Page 12 of 20
00943-0-020
AD5544/AD5554
100 90 80 400 70 VDD = 5V 10% TA = 25C 600 VDD = 5V VREF = 10V TA = 25C
500
PSRR (dB)
IDD (A)
00943-0-022
60 50 40
300
200
100 30 20 100 0 0 1 2 3 4 5 LOGIC INPUT VOLTAGE (V)
00943-0-024
1k
10k 100k CLOCK FREQUENCY (Hz)
1M
Figure 22. AD5544/AD5554 Power Supply Rejection vs. Frequency
Figure 24. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage
55 54 53 VDD = 5V VREF = 10V LOGIC = VDD
SUPPLY CURRENT (A)
52 51 50 49 48 47 46 -50
00943-0-023
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 23. AD5544/AD5554 Power Supply Current vs. Temperature
Rev. A | Page 13 of 20
AD5554/AD5554 CIRCUIT OPERATION
The AD5544 and AD5554 contain four, 16-bit and 14-bit, current-output, digital-to-analog converters, respectively. Each DAC has its own independent multiplying reference input. Both the AD5544 and the AD5554 use a 3-wire, SPI compatible, serial data interface, with a configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDAC strobe enables four channel simultaneous updates for hardware synchronized output voltage changes. resistance of 5 k, 30%. On the other hand, the DAC outputs IOUTA, B, C, D are code-dependent and produce various output resistances and capacitances. The choice of external amplifier should take into account the variation in impedance generated by the AD5544/AD5554 on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance, dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor (CFB) may be needed to provide a critically damped output response for step changes in reference input voltages. Figure 26 and Figure 27 show the gain vs. frequency performance at various attenuation settings using a 23 pF external feedback capacitor connected across the IOUTX and RFBX terminals for AD5544 and AD5554, respectively. In order to maintain good analog performance, power supply bypassing of 0.01 F, in parallel with 1 F, is recommended. Under these conditions, a clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not suitable for this application due to the higher ripple voltage and PSS frequency-dependent characteristics. It is best to derive the AD5544/AD5554's 5 V supply from the system's analog supply voltages. Do not use the digital 5 V supply (see Figure 28).
FFFFH B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ZS
D/A CONVERTER
Each part contains four current-steering R-2R ladder DACs. Figure 25 shows a typical equivalent DAC. Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin connects to the output of the external amplifier. The IOUTX terminal connects to the inverting input of the external amplifier. The AGNDX pin should be Kelvinconnected to the load point requiring full 16-bit accuracy. These DACs are designed to operate with both negative or positive reference voltage. The VDD power pin is only used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the internal 5 k feedback resistor. If users attempt to measure the value of RFB, power must be applied to VDD in order to achieve continuity. An additional VSS bias pin is used to guard the substrate during high temperature applications, minimizing zero-scale leakage currents that double every 10C. The DAC output voltage is determined by VREF and the digital data (D) in the following equations:
VOUT = - VREF x
VOUT = - VREF x
D (For AD5544 ) 65536
D (For AD5554 ) 16384
(1) (2)
GAIN (12dB/DIV)
VDD VREFX 2R R 2R R 2R R R S2 5k S1 IOUTX AGNDF AGNDX FROM OTHER DACS AGND
00943-0-025
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
RFBX
Figure 26. AD5554 Reference Multiplying Bandwidth vs. Code
3FFFH B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ZS VDD = 5V VREF = 100mV rm s TA = 25C CF = 23pF 1k 10k 100k FREQUENCY (Hz) 1M 10M
VSS
DGND
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY. SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED.
Figure 25. Typical Equivalent DAC Channel
These DACs are also designed to accommodate ac reference input signals. Both the AD5544 and the AD5554 accommodate input reference voltages in the range of -12 V to +12 V. The reference voltage inputs exhibit a constant nominal input
GAIN (12dB/DIV)
100
Figure 27. AD5554 Reference Multiplying Bandwidth vs. Code
Rev. A | Page 14 of 20
00943-0-027
00943-0-026
Note that the output polarity is opposite to the VREF polarity for dc reference voltages.
VDD = 5V VREF = 100mV rm s TA = 25C
AD5544/AD5554
15V 2R ANALOG POWER SUPPLY
+
R
5V
VDD
AD5544
VREFX 2R RR 2R 2R R R S2 5k 15V S1 IOUTX AGNDF AGNDX FROM OTHER DACS AGND VSS DIGITAL INTERFACE CONNECTIONS OMITTED. FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED. DGND
00943-0-028
RFBX
VCC A1 VOUT VEE
+
LOAD
Figure 28. Recommended Kelvin-Sensed Hookup
Rev. A | Page 15 of 20
AD5554/AD5554 SERIAL DATA INTERFACE
The AD5544/AD5554 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. Serial data of AD5544 and AD5554 is clocked into the serial input register in an 18-bit and 16-bit data-word format respectively. MSB bits are loaded first. Table 6 defines the 18 data-word bits for AD5544. Table 7 defines the 16 data-word bits for AD5554. Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data setup and data hold time requirements specified in the interface timing specifications. data can only be clocked in while the CS chip select pin is active low. For AD5544, only the last 18 bits clocked into the serial register will be interrogated when the CS pin returns to the logic high state, extra data bits are ignored. For AD5554, only the last 16 bits clocked into the serial register will be interrogated when the CS pin returns to the logic high state. Since most microcontrollers output serial data in 8-bit bytes, three right justified data bytes can be written to the AD5544. Keeping
CS EN CLK
the CS line low between the first, second, and third byte transfers will result in a successful serial register update. Similarly, two right justified data bytes can be written to the AD5554. Keeping the CS line low between the first and second byte transfer will result in a successful serial register update. Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new data to the target DAC register, determined by the decoding of address Bits A1 and A0. For AD5544, Table 5, Table 7, Table 9, and Figure 4 define the characteristics of the software serial interface. For AD5554, Table 6, Table 8, Table 9, and Figure 5 define the characteristics of the software serial interface. Figure 29 and Figure 30 show the equivalent logic interface for the key digital control pins for the AD5544. AD5554 has a similar configuration, except it has 14 data bits. Two additional pins, RS and MSB, provide hardware control over the preset function and DAC register loading.
VREFA B C D
AD5544
VDD
SDI
SDO
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1
16
RFBA INPUT REGISTER R DAC A REGISTER R DAC A IOUTA AGNDA
RFBB INPUT REGISTER R DAC A B C D 2:4 DECODE RFBC INPUT REGISTER R DAC C REGISTER R DAC C IOUTC AGNDC DAC B REGISTER R DAC B IOUTB AGNDB
RFBD INPUT REGISTER R DAC D REGISTER R DAC D IOUTD AGNDD SET MSB SET MSB
POWERON RESET
AGNDF
DGND
MSB
LDAC
RS
VSS
Figure 29. System Level Digital Interfacing
Rev. A | Page 16 of 20
00943-0-029
AD5544/AD5554
If these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all input and DAC registers to either the zero-code state (MSB = 0) or the halfscale state (MSB = 1).
TO INPUT REGISTER A B C D
electrolytic capacitors should also be applied at VDD to minimize any transient disturbance and filter any low frequency ripple (see Figure 32). Users should not apply switching regulators for VDD due to the power supply rejection ratio degradation over frequency.
AD5544/AD5554
VDD C3 10F C4 10F VSS +
VDD
CS
ADDRESS DECODER
C1 0.1F C2 0.1F
AGNDX VSS
EN CLK SDI SDO SHIFT REGISTER
00943-0-030
19TH/17TH CLOCK
Figure 32. Power Supply Bypassing and Grounding Connection Figure 30. AD5544/AD5554 Equivalent Logic Interface
Grounding
The DGND and AGNDX pins of the AD5544/AD5554 refer as digital and analog ground references. To minimize the digital ground bounce, the DGND terminal should be joined remotely at a single point to the analog ground plane (see Figure 32).
POWER ON RESET
When the VDD power supply is turned on, an internal reset strobe forces all the input and DAC registers to the zero-code state or half-scale state, depending on the MSB pin voltage. The VDD power supply should have a smooth positive ramp without drooping in order to have consistent results, especially in the region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on the power-on reset performance. The DAC register data will stay at a zero or half-scale setting until a valid serial register data load takes place.
APPLICATIONS
The AD5544/AD5554 are inherently 2-quadrant multiplying D/A converters. That is, they can be easily set up for unipolar output operation. The full-scale output polarity is the inverse of the reference-input voltage. In some applications it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished using an additional external amplifier (A2) configured as a summing amplifier (see Figure 33). In this circuit the first and second amplifiers (A1 and A2) provide a total gain of 2 which increases the output voltage span to 20 V. Biasing the external amplifier with a 10 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = -10 V) to midscale (VOUT = 0 V) to full-scale (VOUT = 10 V). D (3) VOUT - 1 x - VREF (For AD5544 ) 32768 D (4) VOUT - 1 x - VREF (For AD5554 ) 8192
10k 10k 10V VREF 5k A2 VOUT
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zeners connected to ground (DGND) and VDD, as shown in Figure 31.
VDD 5k
00943-0-031
DIGITAL INPUTS
DGND
Figure 31. Equivalent ESD Production Circuits
Power Supply Sequence
As standard practice, it is recommended to power VDD, VSS, and ground prior to any reference. The ideal power up sequence is AGNDX, DGND, VDD, VSS, VREFX, and digital inputs. A noncompliance power up sequence may elevate the reference current, but the devices resume normal operation once VDD and VSS are powered-up.
Layout and Power Supply Bypassing
It is good practice to employ a compact, minimum-lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 F to 0.1 F disc or chip ceramic capacitors. Low-ESR 1 F to 10 F tantalum or
AD588
-10V < VOUT < +10V VDD VREFX ONE CHANNEL RFBX IOUTX A1 AGNDX
00943-0-033
AD5544
VSS AGNDF
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
Figure 33. Four-Quadrant Multiplying Application Circuit
Rev. A | Page 17 of 20
00943-0-033
DGND
AD5544/AD5554 OUTLINE DIMENSIONS
10.50 10.20 9.90
28
15
5.60 5.30 5.00
1 14
8.20 7.80 7.40
2.00 MAX
1.85 1.75 1.65
0.10 COPLANARITY 0.25 0.09
0.05 MIN
0.65 BSC
0.38 0.22
SEATING PLANE
8 4 0
0.95 0.75 0.55
COMPLIANT TO JEDEC STANDARDS MO-150AH
Figure 34. 28-Lead SSOP (RS-28) Dimensions Shown in Inches and (Millimeters)
ORDERING GUIDE
Model AD5544ARS AD5554BRS AD5544EVAL RES Bit 16 14 INL LSB 4 1 DNL LSB 1.5 1 Temperature Range -40C to +85C -40C to +85C Package Description SSOP-28 SSOP-28 Evaluation Board Package Option RS-28 RS-28
Rev. A | Page 18 of 20
AD5544/AD5554 NOTES
Rev. A | Page 19 of 20
AD5544/AD5554 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00943-0-12/04(A)
Rev. A | Page 20 of 20

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