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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13734-9E
16-bit Microcontroller
CMOS
F2MC-16LX MB90330A Series
MB90333A/F334A/F335A/V330A
DESCRIPTION
The MB90330A series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but also HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. While inheriting the AT architecture of the F2MC family, the instruction set supports the C language and extended addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURES
* Clock * Built-in oscillation circuit and PLL clock frequency multiplication circuit * Oscillation clock * The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz) * Clock for USB is 48 MHz * Machine clock frequency of 6 MHz, 12 MHz, or 24 MHz selectable * Minimum execution time of instruction : 41.7 ns (6 MHz oscillation clock, 4-time multiplied : machine clock 24 MHz and at operating VCC = 3.3 V). * The maximum memory space : 16 Mbytes * 24-bit addressing (Continued)
For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development.
http://edevice.fujitsu.com/micom/en-support/
Copyright(c)2004-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.7
MB90330A Series
(Continued) * Bank addressing * Instruction system * Data types : Bit, Byte, Word and Long word * Addressing mode (23 types) * Enhanced high-precision computing with 32-bit accumulator * Enhanced Multiply/Divide instructions with sign and the RETI instruction * Instruction system compatible with high-level language (C language) and multi-task * Employing system stack pointer * Instruction set symmetry and barrel shift instructions * Program Patch Function (2 address pointer) * 4-byte instruction queue * Interrupt function * Priority levels are programmable * 32 interrupts function * Data transfer function * Extended intelligent I/O service function (EI2OS) : Maximum of 16 channels * DMAC : Maximum 16 channels * Low Power Consumption Mode * Sleep mode (with the CPU operating clock stopped) * Time-base timer mode (with the oscillator clock and time-base timer operating) * Stop mode (with the oscillator clock stopped) * CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles) * Watch mode (with 32 kHz oscillator clock and watch timer operating) * Package * LQFP-120P (FPT-120P-M24 : 0.40 mm pin pitch) * LQFP-120P (FPT-120P-M21 : 0.50 mm pin pitch) * Process : CMOS technology * Operation guaranteed temperature : - 40 C to + 85 C (0 C to + 70 C when USB is in use)
2
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MB90330A Series
PRODUCT LINEUP
Part number Type ROM capacity RAM capacity Emulator-specific power supply * MB90V330A For evaluation No 28 Kbytes Yes MB90F334A Built-in Flash memory 384 Kbytes 24 Kbytes MB90F335A Built-in Flash memory 512 Kbytes 30 Kbytes MB90333A Built-in MASK ROM 256 Kbytes 16 Kbytes
CPU functions
Number of basic instructions : 351 instructions Minimum instruction execution time : 41.7 ns/at oscillation of 6 MHz (When 4 times are used : Machine clock of 24 MHz) Addressing type : 23 types Program Patch Function : For 2 address pointers Maximum memory space : 16 Mbytes I/O Ports (CMOS) 94 ports Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable It can also be used for I/O serial Built-in special baud-rate generator Built-in 4 channels 16-bit reload timer operation Built-in 3 channels 16-bit free run timer x 1 channel Output compare x 4 channels Input capture x 4 channels 8/16-bit PPG timer (8-bit mode x 6 channels, 16-bit mode x 3 channels) 16-bit PWC timer x 1 channel 16 channels (input multiplex) 8-bit resolution or 10-bit resolution can be set. Conversion time : 7.16 s at minimum (24 MHz machine clock at maximum) 8 channels Interrupt factor : "L""H" edge/"H""L" edge/"L" level/"H" level selectable 3 channels 1 channel 1 channel USB function (correspond to USB Full Speed) USB HOST function For multi-bus/non-multi-bus 16 ports (excluding UTEST and I/O for I2C) Sleep mode/Time-base timer mode/Stop mode/CPU intermittent mode/ Watch mode CMOS 3.3 V 0.3 V (at maximum machine clock 24 MHz)
Ports
UART
16-bit reload timer
Multi-functional timer
8/10-bit A/D converter
DTP/External interrupt I2C Extended I/O serial interface USB External bus interface Withstand voltage of 5 V Low Power Consumption Mode Process Operating voltage
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. 4 DS07-13734-9E
MB90330A Series
PACKAGES AND PRODUCT MODELS
Package FPT-120P-M24 (LQFP-0.40 mm) FPT-120P-M21 (LQFP-0.50 mm) PGA-299C-A01 (PGA) : Yes x : No Note : For detailed information on each package, refer to " PACKAGE DIMENSIONS". x x x MB90333A MB90F334A MB90F335A MB90V330A x x
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MB90330A Series
Pin no.
Pin name
I/O Circuit type*
Function This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports.
P24 to P27
117 to 120 A20 to A23
D
When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins. When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins. Function as ch.0 to ch.3 output pins for the 8-bit PPG timer. General purpose input/output port.
PPG0 to PPG3 P30 1 A00 TIN1 P31 2 A01 TOT1 P32 3 A02 TIN2 P33 4 A03 TOT2 5 to 8 P34 to P37 A04 to A07 P40 9 A08 TIN0 P41 10 A09 TOT0 P42 11 A10 SIN0 P43 12 A11 SOT0 P44 17 A12 SCK0 G G G G G D D D D D
Function as the external address pin in non-multi-bus mode. Function as an event input pin for 16-bit reload timer ch.1. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as the output pin for 16-bit reload timer ch.1. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as an event input pin for 16-bit reload timer ch.2. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as the output pin for 16-bit reload timer ch.2. General purpose input/output port. Function as the external address pin in non-multi-bus mode. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as an event input pin for 16-bit reload timer ch.0. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as the output pin for 16-bit reload timer ch.0. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as a data input pin for UART ch.0. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as a data output pin for UART ch.0. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as a clock I/O pin for UART ch.0. (Continued)
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MB90330A Series
Pin no.
Pin name P45
I/O Circuit type* G
Function General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as a data input pin for UART ch.1. General purpose input/output port.
18
A13 SIN1 P46
19
A14 SOT1 P47
G
Function as the external address pin in non-multi-bus mode. Function as a data output pin for UART ch.1. General purpose input/output port.
20
A15 SCK1 P50 ALE P51 RD P52
G
Function as the external address pin in non-multi-bus mode. Function as a clock I/O pin for UART ch.1. General purpose input/output port. Function as the address latch enable signal pin in external bus mode. General purpose input/output port. Function as the read strobe output pin in external bus mode. General purpose input/output port. Function as the data write strobe output pin on the lower side in external bus mode. This pin functions as a general-purpose I/O port when the WRE bit in the EPCR register is "0". General purpose input/output port. Function as the data write strobe output pin on the higher side in bus width 16-bit external bus mode. This pin functions as a general-purpose I/O port when the WRE bit in the EPCR register is "0". General purpose input/output port. Function as the hold request input pin in external bus mode. This pin functions as a general-purpose I/O port when the HDE bit in the EPCR register is "0". General purpose input/output port. Function as the hold acknowledge output pin in external bus mode. This pin functions as a general-purpose I/O port when the HDE bit in the EPCR register is "0". General purpose input/output port. Function as the external ready input pin in external bus mode. This pin functions as a general-purpose I/O port when the RYE bit in the EPCR register is "0". General purpose input/output port. Function as the machine cycle clock output pin in external bus mode. This pin functions as a general-purpose I/O port when the CKE bit in the EPCR register is "0". General purpose input/output port. (With stand voltage of 5 V) Function as external interrupt ch.0 and ch.1 input pins. (Continued)
81 82
L L
83
WRL P53
L
84
WRH P54
L
85
HRQ P55
L
86
HAK P56
L
91
RDY P57
L
92
CLK P60, P61 INT0, INT1
L
21, 22
C
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MB90330A Series
Pin no.
Pin name P62
I/O Circuit type* C
Function General purpose input/output ports. (Withstand voltage of 5 V) Function as an external interrupt ch.2 input pin. Extended I/O serial interface data input pin. General purpose input/output port. (Withstand voltage of 5 V)
23
INT2 SIN P63
24
INT3 SOT P64
C
Function as an external interrupt ch.3 input pin. Extended I/O serial interface data output pin. General purpose input/output port. (Withstand voltage of 5 V)
25
INT4 SCK P65
C
Function as an external interrupt ch.4 input pin. Extended I/O serial interface clock input/output pin. General purpose input/output port. (Withstand voltage of 5 V)
26
INT5 PWC P66 INT6 SCL0 P67
C
Function as an external interrupt ch.5 input pin. Function as the PWC input pin. General purpose input/output port. (Withstand voltage of 5 V) Function as an external interrupt ch.6 input pin. Function as the ch.0 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) Function as an external interrupt ch.7 input pin. Function as the ch.0 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. Function as input pins for analog ch.0 to ch.7. General purpose input/output port. Function as input pins for analog ch.8 to ch.15. General purpose input/output port. Function as a data input pin for UART ch.2. General purpose input/output port. Function as a data output pin for UART ch.2. General purpose input/output port. Function as a clock I/O pin for UART ch.2. General purpose input/output port. Function as a data input pin for UART ch.3. General purpose input/output port. Function as a data output pin for UART ch.3. General purpose input/output port. Function as a clock I/O pin for UART ch.3. General purpose input/output port. (Withstand voltage of 5 V) Function as the external trigger input pin when the A/D converter is being used. Function as the external clock input pin when the free-run timer is being used. (Continued)
27
C
28
INT7 SDA0
C
39 to 46 48 to 55 29 30 31 32 33 34
P70 to P77 AN0 to AN7 P80 to P87 AN8 to AN15 P90 SIN2 P91 SOT2 P92 SCK2 P93 SIN3 P94 SOT3 P95 SCK3 P96 ADTG FRCK
I I D D D D D D
35
C
10
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MB90330A Series
(Continued) Pin no. Pin name PA0 to PA3 IN0 to IN3 PA4 to PA7 OUT0 to OUT3 PB0 64 SCL1 PB1 65 SDA1 PB2 66 SCL2 PB3 67 68 69, 70 71 73 74 77 78 80 36 37 38 87 to 89 15, 75, 79, 105 16, 47, 72, 76, 106 SDA2 PB4 PB5, PB6 PPG4, PPG5 UTEST DVM DVP HVM HVP HCON AVcc AVRH AVss MD2 to MD0 Vcc Vss C C D C K K K K E J B C C C I/O Circuit type* C C Function General purpose input/output port. (Withstand voltage of 5 V) Function as the input capture ch.0 to ch.3 trigger inputs. General purpose input/output port. (Withstand voltage of 5 V) Function as the output compare ch.0 to ch.3 event output pins. General purpose input/output port. (Withstand voltage of 5 V) Function as the ch.1 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) Function as the ch.1 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) Function as the ch.2 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) Function as the ch.2 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) General purpose input/output port. Function as ch.4 and ch.5 output pins for the 8-bit PPG timer. USB test pin. Connect this to a pull-down resistor during normal usage. USB function D- pin. USB function D+ pin. USB HOST D- pin. USB HOST D+ pin. External pull-up resistor connect pin. A/D converter power supply pin. A/D converter external reference power supply pin. A/D converter power supply pin. Operation mode select input pin. Power supply pin. Power supply pin (GND).
56 to 59 60 to 63
* : For circuit information, refer to " I/O CIRCUIT TYPE".
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MB90330A Series
I/O CIRCUIT TYPE
Type A
X1 X1A X0 X0A
Circuit
Remarks * High-rate oscillation feedback resistor, approx.1 M * Low-rate oscillation feedback resistor, approx.10 M * With standby control CMOS hysteresis input CMOS hysteresis input
Clock input
Standby control signal
B
C
* CMOS hysteresis input * N-ch open drain output
N-ch
Nout
CMOS hysteresis input Standby control signal D
P-ch Pout
N-ch
Nout
CMOS hysteresis input Standby control signal E
P-ch N-ch Pout Nout
* CMOS output * CMOS hysteresis input (With input interception function at standby) Notes : * Share one output buffer because both output of I/O port and internal resource are used. * Share one input buffer because both input of I/O port and internal resource are used. CMOS output
F
R
CMOS hysteresis input with pull-up resistor
CMOS hysteresis input (Continued)
12
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MB90330A Series
Type G
P-ch
Circuit
Remarks * CMOS output * CMOS hysteresis input (With input interception function at standby) With open drain control signal
Pout
Open drain control signal
N-ch
Nout
CMOS hysteresis input Standby control signal H
CTL R P-ch Pout
* CMOS output * CMOS input (With input interception function at standby) * With input pull-up register control
N-ch
Nout
CMOS input Standby control signal I * CMOS output * CMOS hysteresis input (With input interception function at standby) * Analog input (The A/D converter analog input is enabled when the corresponding bit in the analog input enable register (ADER) is 1.) Notes: * Because the output of the I/O port and the output of internal resources are used combinedly, one output buffer is shared. * Because the input of the I/O port and the input of internal resources are used combinedly, one input buffer is shared. A/D converter (AVRH) voltage input pin
P-ch P-ch N-ch N-ch
P-ch
Pout
N-ch
Nout
CMOS hysteresis input Standby control signal A/D converter analog input
J
AVRH input A/D converter analog input enable signal (Continued)
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MB90330A Series
(Continued) Type K D + input D - input
D+
Circuit USB I/O pin
Remarks
Differential input
D-
Full D + output Full D - output Low D + output Low D - output Direction Speed
L
P-ch N-ch Pout Nout
* CMOS output * CMOS input * With standby control
CMOS input Standby control signal
14
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MB90330A Series
HANDLING DEVICES
1. Preventing latch-up and turning on power supply
Latch-up may occur on CMOS IC under the following conditions: * If a voltage higher than VCC or lower than VSS is applied to input and output pins. * A voltage higher than the rated voltage is applied between VCC pin and VSS pin. * If the AVCC power supply is turned on before the VCC voltage. Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as VCC and the digital power supply). If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating.
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open.
3. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS.
4. About the attention when the external clock is used
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub clock or stop mode. When suing an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. * Using external clock
X0
OPEN
X1
5. Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC pin and VSS pin near this device.
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MB90330A Series
BLOCK DIAGRAM
X0, X1 X0A,X1A RST MD0 to MD2
Clock control circuit Interrupt controller RAM ROM
F2MC-16LX CPU
8/16-bit PPG timer ch.0 to ch.5* Input capture ch.0 to ch.3
PPG0 to PPG5
SIN0 to SIN3 SOT0 to SOT3 SCK0 to SCK3 SCL0 to SCL2 SDA0 to SDA2 AVCC AVRH AVSS AN0 to AN15 ADTG TOT0 to TOT2 TIN0 to TIN2 DVP DVM HVP HVM HCON UTEST INT0 to INT7
UART/SIO ch.0 to ch.3
IN0 to IN3
Internal data bus
I2C ch.0 to ch.2
16-bit free-run timer
FRCK
8/10-bit A/D converter 16-bit reload timer ch.0 to ch.2 USB (Function) (HOST)
External interrupt
Output compare ch.0 to ch.3 16-bit PWC
OUT0 to OUT3
PWC SIN SOT SCK
SIO DMAC
I/O port (port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)
P00 P07
P10 P17
P20 P27
P30 P37
P40 P47
P50 P57
P60 P67
P70 P77
P80 P87
P90 P96
PA0 PB0 PA7 PB6
* : Channel for use in 8-bit mode. 3 channels (ch.1, ch.3, ch.5) are used in 16-bit mode. Note : I/O ports share pins with peripheral function (resources) . For details, refer to " PIN ASSIGNMENT" and " PIN DESCRIPTION". Note also that pins used for peripheral function (resources) cannot serve as I/O ports.
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MB90330A Series
MEMORY MAP
Memory map of MB90330A series (1/3) Single chip mode (with ROM mirror function)
MB90V330A
FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H
MB90F334A
ROM (FF bank) ROM (FE bank) ROM (FD bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H
MB90F335A
ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H
MB90333A
ROM (FF bank) ROM (FE bank) ROM (FD bank)
ROM (FB bank) ROM (FA bank) ROM (F9 bank)
ROM (FB bank)
ROM 008000H (image of FF bank) 007FFFH Peripheral area 007900H 007100H RAM area (28 Kbytes) 000100H 0000FBH Peripheral area 000000H Register
00FFFFH
ROM 008000H (image of FF bank) 007FFFH Peripheral area 007900H
00FFFFH
ROM 008000H (image of FF bank) 007FFFH Peripheral area 007900H
00FFFFH
ROM 008000H (image of FF bank) 007FFFH Peripheral area 007900H
00FFFFH
006100H RAM area (24 Kbytes) 000100H 0000FBH Peripheral area 000000H 000000H Register 000100H 0000FBH
RAM area (30 Kbytes)
004100H RAM area (16 Kbytes)
Register
000100H 0000FBH
Register
Peripheral area 000000H
Peripheral area
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MB90330A Series
Memory map of MB90330A series (3/3) External ROM external bus mode
MB90V330A
FFFFFFH FFFFFFH
MB90F334A
FFFFFFH
MB90F335A
FFFFFFH
MB90333A
External area
External area
External area
External area
008000H 007FFFH 007900H 007100H
Peripheral area External area
008000H 007FFFH 007900H
Peripheral area External area
008000H 007FFFH 007900H
Peripheral area
008000H 007FFFH 007900H
Peripheral area External area
006100H RAM area (28 Kbytes) RAM area (24 Kbytes) 000100H 0000FBH Peripheral area Peripheral area 000000H 000000H Register 000100H 0000FBH
RAM area (30 Kbytes)
004100H RAM area (16 Kbytes) 000100H 0000FBH Register
000100H 0000FBH
Register
Register
Peripheral area 000000H
Peripheral area
000000H
Notes: * When the ROM mirror function register has been set, the mirror image data at higher addresses ("FF8000H to FFFFFFH") of bank FF is visible from the higher addresses ("008000H to 00FFFFH") of bank 00. * The ROM mirror function is effective for using the C compiler small model. * The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00. * When the C compiler small model is used, the data table mirror image can be shown at "008000H to 00FFFFH" by storing the data table at "FF8000H to FFFFFFH". Therefore, data tables in the ROM area can be referred without declaring the far addressing with the pointer. * MB90F335A has the larger size of RAM area than MB90V330A, so that the emulation memory area needs to be set in the tools for a larger size of emulation area than 007100H. For details of setting, please refer to "Notes on Debug Environment Setting for MB90330A Series" by clicking "Application note" at the following URL. http://edevice.fujitsu.com/micom/en-support/ * 3 cycles are required to access to the emulation memory area (007100H to 0078FFH), which is 1 cycle more than to the mounted RAM area. 20 DS07-13734-9E
MB90330A Series
I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H Register abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB DDRB Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 7 Data Register Port 8 Data Register Port 9 Data Register Port A Data Register Prohibited Port B Data Register Port B Direction Register Prohibited DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 RDR0 RDR1 ADER0 ADER1 SMR0 SCR0 SIDR0 SODR0 SSR0 UTRLR0 UTCR0 Port 0 Direction Register Port 1 Direction Register Port 2 Direction Register Port 3 Direction Register Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Port 7 Direction Register Port 8 Direction Register Port 9 Direction Register Port A Direction Register Port 4 Output Pin Register Port 0 Pull-up Resistance Register Port 1 Pull-up Resistance Register Analog Input Enable Register 0 Analog Input Enable Register 1 Serial Mode Register 0 Serial Control Register 0 Serial Input Data Register 0 Serial Output Data Register 0 Serial Status Register 0 UART Prescaler Reload Register 0 UART Prescaler Control Register 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 (open drain control) Port 0 (PULL-UP) Port 1 (PULL-UP) Port 7, 8, A/D Port 7, 8, A/D 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB R/W R/W Port B Port B - XXXXXXXB - 0 0 0 0 0 0 0B Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - XXXXXXXB XXXXXXXXB
UART0
0 0 0 0 1 0 0 0B Communication 0 0 0 0 0 0 0 0B Prescaler (UART0) 0 0 0 0 - 0 0 0B (Continued)
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MB90330A Series
Address 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H to 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H
Register abbreviation SMR1 SCR1 SIDR1 SODR1 SSR1 UTRLR1 UTCR1 SMR2 SCR2 SIDR2 SODR2 SSR2 UTRLR2 UTCR2 SMR3 SCR3 SIDR3 SODR3 SSR3 UTRLR3 UTCR3
Register Serial Mode Register 1 Serial Control Register 1 Serial Input Data Register 1 Serial Output Data Register 1 Serial Status Register 1 UART Prescaler Reload Register 1 UART Prescaler Control Register 1 Serial Mode Register 2 Serial Control Register 2 Serial Input Data Register 2 Serial Output Data Register 2 Serial Status Register 2 UART Prescaler Reload Register 2 UART Prescaler Control Register 2 Serial Mode Register 3 Serial Control Register 3 Serial Input Data Register 3 Serial Output Data Register 3 Serial Status Register 3 UART Prescaler Reload Register 3 UART Prescaler Control Register 3 Prohibited
Read/ Write R/W R/W R W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R W R/W R/W R/W
Resource name
Initial Value 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B
UART1
XXXXXXXXB
0 0 0 0 1 0 0 0B 0 0 0 0 0 0 0 0B Communication Prescaler (UART1) 0 0 0 0 - 0 0 0B 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B UART2 XXXXXXXXB 0 0 0 0 1 0 0 0B 0 0 0 0 0 0 0 0B Communication Prescaler (UART2) 0 0 0 0 - 0 0 0B 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B UART3 XXXXXXXXB 0 0 0 0 1 0 0 0B 0 0 0 0 0 0 0 0B Communication Prescaler (UART3) 0 0 0 0 - 0 0 0B
ENIR EIRR ELVR ADCS0 ADCS1 ADCR0 ADCR1
ADMR PPGC0 PPGC1 PPGC2
DTP/Interrupt Enable Register DTP/Interrupt Source Register Request Level Setting Register Lower Request Level Setting Register Upper A/D Control Status Register Lower A/D Control Status Register Upper A/D Data Register Lower A/D Data Register Upper Prohibited A/D Conversion Channel Selection Register PPG0 Operation Mode Control Register PPG1 Operation Mode Control Register PPG2 Operation Mode Control Register
R/W R/W R/W R/W R/W R/W R/W R/W
DTP/External Interrupt
8/10-bit A/D Converter
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 - - - - - 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 1 0 1 XXXB
R/W R/W R/W R/W
8/10-bit A/D Converter PPG ch.0 PPG ch.1 PPG ch.2
0 0 0 0 0 0 0 0B 0X0 0 0XX1B 0X0 0 0 0 0 1B 0X0 0 0XX1B (Continued)
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MB90330A Series
Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H
Register abbreviation ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 HCNT0 HCNT1 HIRQ HERR HSTATE HFCOMP
Register Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Interrupt Control Register 05 Interrupt Control Register 06 Interrupt Control Register 07 Interrupt Control Register 08 Interrupt Control Register 09 Interrupt Control Register 10 Interrupt Control Register 11 Interrupt Control Register 12 Interrupt Control Register 13 Interrupt Control Register 14 Interrupt Control Register 15 Host Control Register 0 Host Control Register 1 Host Interruption Register Host Error Status Register Host State Status Register SOF Interrupt FRAME Compare Register Retry Timer Setting Register Host Address Register EOF Setting Register FRAME Setting Register Host Token End Point Register Prohibited
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial Value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B
Interrupt Controller
0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B XX 0 1 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
HRTIMER HADR HEOF HFRAME HTOKEN
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
USB HOST
0 0 0 0 0 0 0 0B XXXXXX 0 0B X 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXX 0 0 0B 0 0 0 0 0 0 0 0B 1 0 1 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Continued)
UDCC
UDC Control Register
USB Function
DS07-13734-9E
27
MB90330A Series
Address 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH 0000EEH 0000EFH 0000F0H 0000F1H 0000F2H 0000F3H 0000F4H 0000F5H 0000F6H 0000F7H
Register abbreviation EP0C EP1C EP2C EP3C EP4C EP5C TMSP UDCS UDCIE EP0IS EP0OS EP1S EP2S EP3S EP4S EP5S EP0DT EP1DT EP2DT EP3DT
Register EP0 Control Register EP1 Control Register EP2 Control Register EP3 Control Register EP4 Control Register EP5 Control Register Time Stamp Register UDC Status Register UDC Interrupt Enable Register EP0I Status Register EP0O Status Register EP1 Status Register EP2 Status Register EP3 Status Register EP4 Status Register EP5 Status Register EP0 Data Register EP1 Data Register EP2 Data Register EP3 Data Register
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W, R R/W R/W R/W, R R/W R R/W, R R R/W, R R R/W, R R R/W, R R R/W, R R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial Value 0 1 0 0 0 0 0 0B XXXX 0 0 0 0B 0 0 0 0 0 0 0 0B 0 1 1 0 0 0 0 1B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXX0 0 0B XX0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 1 0 XXX 1 XXB 0 XXXXXXXB 1 0 0 XX 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 XB XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
USB Function
28
DS07-13734-9E
MB90330A Series
Address 0000F8H 0000F9H 0000FAH 0000FBH 0000FCH to 0000FFH 000100H to #H 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H #H to 0078FFH 007900H 007901H 007902H 007903H 007904H 007905H 007906H 007907H 007908H 007909H 00790AH 00790BH 00790CH to 00790FH
Register abbreviation EP4DT EP5DT
Register EP4 Data Register EP5 Data Register
Read/ Write R/W R/W R/W R/W Prohibited
Resource name
Initial Value XXXXXXXXB
USB Function
XXXXXXXXB XXXXXXXXB XXXXXXXXB
RAM Area Program Address Detection Register ch.0 Lower PADR0 Program Address Detection Register ch.0 Middle Program Address Detection Register ch.0 Upper Program Address Detection Register ch.1 Lower PADR1 Program Address Detection Register ch.1 Middle Program Address Detection Register ch.1 Upper Unused Area PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PPG Reload Register Lower ch.0 PPG Reload Register Upper ch.0 PPG Reload Register Lower ch.1 PPG Reload Register Upper ch.1 PPG Reload Register Lower ch.2 PPG Reload Register Upper ch.2 PPG Reload Register Lower ch.3 PPG Reload Register Upper ch.3 PPG Reload Register Lower ch.4 PPG Reload Register Upper ch.4 PPG Reload Register Lower ch.5 PPG Reload Register Upper ch.5 Prohibited (Continued) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Address Match Detection
PPG ch.0 PPG ch.1 PPG ch.2 PPG ch.3 PPG ch.4 PPG ch.5
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MB90330A Series
(Continued) Address 007910H 007911H 007912H 007913H 007914H 007915H 007916H 007917H 007918H 007919H 00791AH 00791BH 00791CH 00791DH 00791EH 00791FH 007920H 007921H 007922H 007923H 007924H 007925H 007926H 007927H 007928H to 007FFFH * Explanation on read/write R/W : Readable / Writable R : Read only W : Write only * Explanation on initial values 0 : Initial value is "0". 1 : Initial value is "1". X : Initial value is undefined. : Initial value is undefined (None) . : Initial value of this bit is "1" or "0". Note : No I/O instruction can be used for registers located between 007900H and 007FFFH. 30 DS07-13734-9E Register abbreviation IPCP0 IPCP1 IPCP2 IPCP3 OCCP0 OCCP1 OCCP2 OCCP3 DBAPL DBAPM DBAPH DMACS DIOAL DIOAH DDCTL DDCTH Register Input Capture Data Register Lower ch.0 Input Capture Data Register Upper ch.0 Input Capture Data Register Lower ch.1 Input Capture Data Register Upper ch.1 Input Capture Data Register Lower ch.2 Input Capture Data Register Upper ch.2 Input Capture Data Register Lower ch.3 Input Capture Data Register Upper ch.3 Output Compare Register Lower ch.0 Output Compare Register Upper ch.0 Output Compare Register Lower ch.1 Output Compare Register Upper ch.1 Output Compare Register Lower ch.2 Output Compare Register Upper ch.2 Output Compare Register Lower ch.3 Output Compare Register Upper ch.3 DMA Buffer Address Pointer Lower 8-bit DMA Buffer Address Pointer Middle 8-bit DMA Buffer Address Pointer Upper 8-bit DMA Control Register DMA I/O Register Address Pointer Lower 8-bit DMA I/O Register Address Pointer Upper 8-bit DMA Data Counter Lower 8-bit DMA Data Counter Upper 8-bit Prohibited Read/ Write R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMAC Output Compare ch.2/ch.3 Output Compare ch.0/ch.1 Input Capture ch.2/ch.3 Input Capture ch.0/ch.1 Resource name Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
MB90330A Series
INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT 9 instruction Exceptional treatment USB Function1 USB Function2 USB Function3 USB Function4 USB HOST1 USB HOST2 I2C ch.0 DTP/External interrupt ch.0/ch.1 I2C ch.1 DTP/External interrupt ch.2/ch.3 I2C ch.2 DTP/External interrupt ch.4/ch.5 PWC/Reload timer ch.0 DTP/External interrupt ch.6/ch.7 Input capture ch.0/ch.1 Reload timer ch.1 Input capture ch.2/ch.3 Reload timer ch.2 Output compare ch.0/ch.1 PPG ch.0/ch.1 Output compare ch.2/ch.3 PPG ch.2/ch.3 UART (Send completed) ch.2/ch.3 PPG ch.4/ch.5 UART (Reception completed) ch.2/ch.3 A/D converter/Free-run timer UART (Send completed) ch.0/ch.1 Extended serial I/O UART (Reception completed) ch.0/ch.1 Time-base timer/Watch timer Flash memory status Delay interrupt output module x x x x x x x x x EI2OS DMAC support x x x x x x x x x x x x x 0, 1 2 to 6* x x x x x x x x x x 14 x 7 x 8 x x x x x 11 x 10 15 13 9 12 x x x
2
Interrupt vector Number*1 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 09H 0AH 0BH
Interrupt control register Priority Address ICR Address High
08H FFFFDCH FFFFD8H FFFFD4H FFFFD0H
0CH FFFFCCH 0DH FFFFC8H 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH
1CH FFFF8CH
Low
(Continued) DS07-13734-9E 31
MB90330A Series
(Continued) : Available, EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal. With a stop request). : Available (The interrupt request flag is cleared by the interrupt clear signal.) : Available when any interrupt source sharing ICR is not used. x : Unavailable *1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority. *2 : ch.2 and 3 can also be used during USB HOST operation. Notes : * If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests when using the EI2OS. * The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (ICR). * If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the DMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to "0" in the appropriate resource, and take measures by software polling. * Content of USB interruption factor USB interrupt factor USB function 1 USB function 2 USB function 3 USB function 4 USB HOST1 USB HOST2 End Point1-5 * SUSP SOF BRST WKUP CONF SPK DIRQ CNNIRQ URIRQ RWKIRQ SOFIRQ CMPIRQ
Details End Point0-IN End Point0-OUT
* : Endpoints 1 and 2 can also be used during USB HOST operation.
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USB
1. USB Function
The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol. * Feature of USB function * Correspond to USB Full Speed * Full speed (12 Mbps) is supported. * The device status is auto-answer. * Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16 * Toggle check by data synchronization bit * Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these 3 commands can be processed the same way as the class vendor commands). * The class vendor commands can be received as data and responded via firmware. * Supports up to 6 EndPoints (EndPoint0 is fixed to control transfer) * 2 transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for EndPoint 0) * Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint 0)
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MB90330A Series
2. USB HOST
USB HOST provides the minimal host operations required and is a function that enables data to be transferred to and from a device without PC intervention. * Feature of USB HOST * Automatic detection of Low Speed/Full Speed transfer * Low Speed/Full Speed transfer support * Automatic detection of connection and cutting device * Reset sending function support to USB-bus * Support of IN/OUT/SETUP/SOF token * In-token handshake packet automatic transmission (excluding STALL) * Out-token handshake packet automatic detection * Supports a maximum packet length of 256 bytes. * Error (CRC error/toggle error/time-out) various supports * Wake-Up function support * Restrictions of USB HOST USB HOST HUB support Bulk transfer Transfer Control transfer Interrupt transfer Isochronous transfer Transfer speed PRE packet support SOF packet support CRC error Error Toggle error Time-out Maximum packet < receive data Detection of connection and cutting of device Transfer speed detection : Supported x : Not supported * : It corresponds to Full Speed only, and the HUB supports up to one step. Low Speed Full Speed x x *
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MB90330A Series
SECTOR CONFIGURATION OF FLASH MEMORY
* Sector configuration of 3Mbit flash memory 3 Mbits flash memory is located in F9H to FFH bank on the CPU memory map.
Flash Memory CPU address Writer address *
Prohibited
SA0 (64 Kbytes) SA1 (64 Kbytes) SA2 (64 Kbytes) F80000H F8FFFFH F90000H F9FFFFH FA0000H FAFFFFH FB0000H FBFFFFH FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H FF7FFFH FF8000H FF9FFFH FFA000H FFBFFFH FFC000H FFFFFFH 00000H 0FFFFH 10000H 1FFFFH 20000H 2FFFFH 30000H 3FFFFH 40000H 4FFFFH 50000H 5FFFFH 60000H 6FFFFH 70000H 77FFFH 78000H 79FFFH 7A000H 7BFFFH 7C000H 7FFFFH
Prohibited
SA3 (64 Kbytes) SA4 (64 Kbytes) SA5 (32 Kbytes) SA6 (8 Kbytes) SA7 (8 Kbytes) SA8 (16 Kbytes)
* : The writer address is relative to the CPU address when data is programmed into flash memory by a parallel programmer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses.
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MB90330A Series
* Sector configuration of 4Mbit flash memory 4 Mbits flash memory is located in F8H to FFH bank on the CPU memory map.
Flash Memory
SA0 (64 Kbytes) SA1 (64 Kbytes) SA2 (64 Kbytes) SA3 (32 Kbytes) SA4 (8 Kbytes) SA5 (8 Kbytes) SA6 (16 Kbytes) SA7 (64 Kbytes) SA8 (64 Kbytes) SA9 (64 Kbytes) SA10 (32 Kbytes) SA11 (8 Kbytes) SA12 (8 Kbytes) SA13 (16 Kbytes)
CPU address Writer address *
F80000H F8FFFFH F90000H F9FFFFH FA0000H FAFFFFH FB0000H FB7FFFH FB8000H FB9FFFH FBA000H FBBFFFH FBC000H FBFFFFH FC0000 FCFFFF FD0000 FDFFFF FE0000H FEFFFFH FF0000H FF7FFFH FF8000H FF9FFFH FFA000H FFBFFFH FFC000H FFFFFFH 00000H 0FFFFH 10000H 1FFFFH 20000H 2FFFFH 30000H 37FFFH 38000H 39FFFH 3A000H 3BFFFH 3C000H 3FFFFH 40000H 4FFFFH 50000H 5FFFFH 60000H 6FFFFH 70000H 77FFFH 78000H 79FFFH 7A000H 7BFFFH 7C000H 7FFFFH
* : The writer address is relative to the CPU address when data is programmed into flash memory by a parallel programmer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses.
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ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage*
1
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 4.5 VSS + 4.0 VSS + 4.5 +2.0 20 10 43 4 15/4.5 100 50 - 10 - 43 -4 -15/-4.5 - 100 - 50 340 + 85 + 150 + 125
Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW C C C *9 *9
Remarks
AVCC AVRH
VCC AVCC*2 AVCC AVR 0 V*3 *4 N-ch open-drain (Withstand voltage of 5 V I/O)*5 USB I/O *4 USB I/O *6 *6 Other than USB I/O*7 USB I/O*7 *8 USB-IO (Full speed/ Low speed) *8
Input voltage*1
VI
VSS - 0.3 - 0.5
Output voltage*1 Maximum clamp current Total maximum clamp current "L" level maximum output current
VO ICLAMP ICLAMP IOL1 IOL2 IOLAV1
VSS - 0.3 - 0.5 - 2.0 - 40 - 55 - 55
"L" level average output current "L" level maximum total output current "L" level average total output current "H" level maximum output current
IOLAV2 IOL IOLAV IOH1 IOH2 IOHAV1
Other than USB I/O*7 USB I/O*7 *8 USB-IO (Full speed/ Low speed) *8
"H" level average output current "H" level maximum total output current "H" level average total output current Power consumption Operating temperature Storage temperature
IOHAV2 IOH IOHAV Pd TA Tstg
USB I/O
*1 : The parameter is based on VSS = AVSS = 0.0 V. *2 : Be careful not to let AVCC exceed VCC, for example, when the power is turned on. *3 : Be careful not to let AVRH exceed AVcc. *4 : VI and VO must not exceed Vcc + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *5 : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST (Continued) DS07-13734-9E 37
MB90330A Series
(Continued) *6 : * Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to P87, P90 to P95, PB5, PB6 * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than P60 to P67, P96, PA0 to PA7, PB0 to PB4, DVP, DVM, HVP, HVM, UTEST, HCON * Sample recommended circuits: * Input/output equivalent circuits Protective diode Limiting resistance +B input (0 V to 16 V)
N-ch VCC P-ch
R
*7 : A peak value of an applicable one pin is specified as a maximum output current. *8 : The average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *9 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB90330A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol Value Min 3.0 Power supply voltage VCC VIH VIHS1 Input "H" voltage VIHS2 VIHM VIHUSB VIL Input "L" voltage VILS VILM VILUSB Differential input sensitivity Differential common mode input voltage range Operating temperature VDI 2.7 1.8 0.7 VCC 0.8 VCC 0.8 VCC VCC - 0.3 2.0 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS 0.2 Max 3.6 3.6 3.6 VCC + 0.3 VCC + 0.3 VSS + 5.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 0.8 2.5 + 85 + 70 Unit V V V V V V V V V V V V V Remarks At normal operation (when using USB) At normal operation (when not using USB) Hold state of stop operation CMOS input pin CMOS hysteresis input pin N-ch open-drain (Withstand voltage of 5 V I/O)* MD pin input USB pin input CMOS input pin CMOS hysteresis input pin MD pin input USB pin input USB pin input
VCM
0.8 - 40
V C C
USB pin input When not using USB When using USB, at external bus operation
TA
0
* : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
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MB90330A Series
3. DC Characteristics
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin name Conditions Value Unit Min Typ Max VCC - 0.5 2.8 Vss 0 Vcc 3.6 Vss + 0.4 0.3 V V V V Remarks
Output "H" voltage
Output "L" voltage
Input leak current
Output pins other than P60 to P67, P96, VOH PA0 to PA7, PB0 to PB4, HVP, HVM, DVP, DVM HVP, HVM, DVP, DVM Output pins other than VOL HVP, HVM, DVP, DVM HVP, HVM, DVP, DVM Output pins other than P60 to P67, P96, PA0 to PA7, IIL PB0 to PB4, HVP, HVM, DVP, DVM HVP, HVM, DVP, DVM
IOH = - 4.0 mA RL = 15 k 5% IOL = 4.0 mA RL = 1.5 k 5% VCC = 3.3 V, Vss < VI < VCC
- 10
+ 10
A
-5 25
50 0.1 75 65 70 60
+5 100 10 85 75 80 70
A k A mA MB90F334A MB90F335A
VCC = 3.3 V, Pull-up RPULL P00 to P07, P10 to P17 TA = + 25 C resistance Open drain P60 to P67, P96, output ILIOD PA0 to PA7, PB0 to PB4 current VCC = 3.3 V, Internal frequency 24 MHz, At normal operating At USB operating (USTP = 0) ICC VCC = 3.3 V, Internal frequency 24 MHz, At normal operating At non-operating USB (USTP = 1) VCC = 3.3 V, Power ICCS Internal frequency 24 MHz, VCC supply At sleep mode current VCC = 3.3 V, Internal frequency 24 MHz, At timer mode ICTS VCC = 3.3 V, Internal frequency 3 MHz, At timer mode VCC = 3.3 V, Internal frequency 8 kHz, ICCL At sub clock operation, (TA = +25 C)
mA MB90333A mA MB90F334A MB90F335A
mA MB90333A
27
40
mA
3.5
10
mA
1
2
mA
25
150
A (Continued)
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MB90330A Series
(Continued) (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin name Conditions VCC = 3.3 V, Internal frequency 8 kHz, At sub clock, At sleep operating, (TA = + 25 C) VCC ICCT VCC = 3.3 V, Internal frequency 8 kHz, Watch mode, (TA = + 25 C) TA = + 25 C, At stop Other than AVcc, AVss, Vcc, Vss RST DVP, DVM HVP, HVM Value Min Typ Max Unit Remarks
ICCLS Power supply current
10
50
A
1.5
40
A
ICCH Input capacitance Pull-up resistor USB I/O output impedance CIN Rup ZUSB
25 3
1 5 50
40 15 100 14
A pF k
Note : P60 to P67, P96, PA0 to PA7, and PB0 to PB4 are N-ch open-drain pins usually used as CMOS.
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MB90330A Series
4. AC Characteristics
(1)Clock input timing Parameter (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) SymPin name bol fCH fCL Clock cycle time tHCYL tLCYL PWH PWL PWHL PWLL tcr tcf fCP fCPL tCP tCPL X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Value Min 6 166.7 10 3 42 Typ 6 32.768 166.7 30.5 15.2 8.192 122.1 Max 24 41.7 5 24 333 Unit Remarks
MHz When oscillator is used MHz External clock input kHz ns ns s ns s ns At external clock A reference duty ratio is 30% to 70%. When oscillator is used External clock input
Clock frequency
Input clock pulse width
Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time
MHz When main clock is used kHz When sub clock is used ns s When main clock is used When sub clock is used
* Clock Timing
tHCYL 0.8 VCC
X0
0.2 VCC PWH tcf PWL tcr
tLCYL 0.8 VCC
X0A
0.2 VCC PWHL tcf PWLL tcr
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* PLL operation guarantee range
Relation between power supply voltage and internal operation clock frequency PLL operation guarantee range
3.6
Power voltage VCC (V)
3.0 2.7
Normal Operation Assurance Range
3 6 12 24
Internal clock FCP (MHz)
Note : When the USB is used, operation is guaranteed at voltages between 3.0 V and 3.6 V.
Relation between internal operation clock frequency and external clock frequency
24
Multiplied by 4
Internal clock FCP (MHz)
12
Multiplied by 2
6
External clock Multiplied by 1
3
6
24
External clock Fc (MHz)
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MB90330A Series
The AC standards assume the following measurement reference voltages. * Input signal waveform * Output signal waveform Hysteresis input pin
0.8 VCC 0.2 VCC
Output pin
2.4 V 0.8 V
Hysteresis input/other than MD input pin
0.7 VCC 0.3 VCC
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(2)Clock output timing (VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Value Unit Remarks Min Max tCP tCP/2 - 15 CLKCLK tCHCL CLK VCC = 3.0 V to 3.6 V tCP/2 - 20 tCP/2 - 64 Note : tCP : Refer to " (1) Clock input timing". tCP/2 + 15 tCP/2 + 20 tCP/2 + 64 ns ns ns ns At fcp = 24 MHz At fcp = 12 MHz At fcp = 6 MHz
Parameter Cycle time
Symbol Pin name tCYC CLK
Conditions
tCYC tCHCL 2.4 V 2.4 V 0.8 V
CLK
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MB90330A Series
(3) Reset Pin name (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Value Conditions Unit Remarks Min Max At normal operating, At time base timer mode, At main sleep mode, At PLL sleep mode At stop mode, At sub clock mode, At sub sleep mode, At watch mode
Parameter
Symbol
500 Reset input time tRSTL RST Oscillation time of oscillator* + 500 ns
ns
s
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. It takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a ceramic oscillator, and 0 milliseconds on an external clock.
* During normal operation, time-base timer mode, main sleep mode and PLL sleep mode
tRSTL
RST
0.2 Vcc 0.2 Vcc
* During stop mode, sub clock mode, sub-sleep mode and watch mode
tRSTL
RST
0.2 Vcc 0.2 Vcc
X0
90% of amplitude
Internal operation clock
Oscillation time of oscillator
500 ns
Oscillation stabilization wait time
Execute instruction
Internal reset
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(4) Power-on reset (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to +85 C) Parameter Power supply rising time Power supply shutdown time Symbol Pin name Conditions tR tOFF VCC VCC 1 ms Value Min 0.05 Max 30 Unit ms Waiting time until power-on Remarks
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Notes : * VCC must be lower than 0.2 V before the power supply is turned on. * The above standard is a value for performing a power-on reset. * In the device, there are internal registers which is initialized only by a power-on reset. When the initialization of these items is expected, turn on the power supply according to the standards. * Sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.
VCC
The rising edge should be 50 mV/ms or less.
1.8 V VSS
RAM data hold
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MB90330A Series
(5) UART0, UART1, UART2, UART3 I/O extended serial timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time SCKSOT delay time Valid SINSCK SCKvalid SIN hold time Serial clock H pulse width Serial clock L pulse width SCKSOT delay time Valid SINSCK SCKvalid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx, SINx SCKx, SINx External shift clock mode output pin is : CL = 80 pF + 1TTL Internal shift clock mode output pin is : CL = 80 pF + 1TTL Conditions Value Min 8 tCP - 80 100 60 4 tCP 4 tCP 60 60 Max + 80 150 Unit ns ns ns ns ns ns ns ns ns
Notes : * Above rating is the case of CLK synchronous mode. * CL is a load capacitance value on pins for testing. * tCP : Refer to " (1) Clock input timing".
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* Internal shift clock mode
SCK
0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
SCK
0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
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MB90330A Series
* Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied. *Timing definition
SDA
tLOW tSUDAT tHDSTA tBUS
SCL
tHDSTA tHDDAT tHIGH tSUSTA tSUSTO
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MB90330A Series
(10) Bus read timing Symbol (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Value Pin name Conditions Unit Remarks Min Max tCP/2 - 15 ALE pulse width tLHLL ALE tCP/2 - 20 tCP/2 - 35 Valid addressALEtime ALEAddress valid time Valid addressRDtime Valid addressvalid data input RD pulse width RDvalid data input RDdata hold time RDALEtime RDaddress valid time Valid addressCLKtime RDCLKtime ALERDtime tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL Address, ALE ALE, Address RD, Address Address/ data RD RD, Data RD, Data RD, ALE Address, RD Address, CLK RD, CLK RD, ALE tCP/2 - 17 tCP/2 - 40 tCP/2 - 15 tCP - 25 3 tCP/2 - 25 3 tCP/2 - 20 0 tCP/2 - 15 tCP/2 - 10 tCP/2 - 17 tCP/2 - 17 tCP/2 - 15 5 tCP/2 - 55 5 tCP/2 - 80 3 tCP/2 - 55 3 tCP/2 - 80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns At fcp = 6 MHz At fcp = 6 MHz At fcp = 24 MHz At fcp = 12 MHz At fcp = 6 MHz At fcp = 24 MHz At fcp = 12 MHz At fcp = 6 MHz
Parameter
Note : tCP : Refer to " (1) Clock input timing".
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MB90330A Series
tAVCH 2.4 V
tRLCH 2.4 V
CLK
tRHLH
ALE
2.4 V tLHLL
2.4 V 0.8 V tRLRH
2.4 V
RD
2.4 V tAVLL tLLAX tLLRL 0.8 V
In multiplex mode
A23 to A16
2.4 V 0.8 V
tAVRL
tRLDV
tRHAX 2.4 V 0.8 V
tAVDV
tRHDX 0.7 VCC 0.7 VCC
AD15 to AD00
2.4 V
2.4 V
Address
0.8 V 0.8 V 0.3 VCC
Read data
0.3 VCC tRHAX
In non-multiplex mode
A23 to A00
2.4 V 0.8 V tRLDV tAVDV
2.4 V 0.8 V
tRHDX 0.7 VCC 0.7 VCC
D15 to D00
Read data
0.3 VCC 0.3 VCC
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(13) Hold timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Parameter Pin floating HAK time HAK pin valid time Symbol tXHAL tHAHV Pin name HAK HAK Conditions Value Min 30 tCP Max tCP 2 tCP Unit ns ns
Notes : * It takes one cycle or more for HAK to change after the HRQ pin is captured. * tCP : Refer to " (1) Clock input timing".
HAK
0.8 V tXHAL 2.4 V
2.4 V tHAHV
High-Z
2.4 V 0.8 V
Each pin
0.8 V
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MB90330A Series
Notes : * About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input circuit model
R
Analog input
C
Comparator During sampling : ON MB90333A MB90F334A MB90F335A MB90V330A R 1.9 k (Max) 1.9 k (Max) 1.9 k (Max) 1.9 k (Max) C 32.3 pF (Max) 25.0 pF (Max) 25.0 pF (Max) 32.3 pF (Max)
Note : The values are reference values.
* To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between the external impedance and minimum sampling time (External impedance = 0 k to 100 k)
MB90333A/ MB90V330A
(External impedance = 0 k to 20 k)
MB90333A/ MB90V330A MB90F334A MB90F335A
100 90 80 70 60 50 40 30 20 10 0
MB90F334A MB90F335A
0
5
10
15
20
25
30
35
20 18 16 14 12 10 8 6 4 2 0
External impedance [k]
External impedance [k]
0
1
2
3
4
5
6
7
8
Minimum sampling time [s]
Minimum sampling time [s]
* If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.
* About errors As |AVRH| becomes smaller, values of relative errors grow larger.
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MB90330A Series
A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter. Linearity error : The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics. Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FFH 3FEH 3FDH Digital output Actual conversion value 0.5 LSB {1 LSB x (N - 1) + 0.5 LSB}
004H 003H 002H 001H AVSS Analog input 0.5 LSB AVRH Actual conversion value Theoretical characteristics VNT (Measured value)
Total error for digital output N = 1 LSB (Theoretical value) =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVRH - AVss [V] 1024
[LSB]
VOT (Theoretical value) = AVss + 0.5 LSB [V] VFST (Theoretical value) = AVRH - 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
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(Continued) Linearity error
3FFH 3FEH 3FDH Digital output Actual conversion value {1 LSB x (N - 1) + VOT } N+1 VFST (Measured value)
Differential linearity error
Theoretical characteristics Actual conversion value
Digital output
N V (N + 1) T (Measured value) VNT (Measured value) N-2 Actual conversion value AVRH
004H 003H 002H 001H AVSS
VNT (Measured value) Actual conversion value Theoretical characteristics VOT (Measured value) Analog input AVRH
N-1
AVSS
Analog input
Linearity error of = digital output N
VNT - {1 LSB x (N - 1) + VOT} 1 LSB - 1 [LSB] [V]
[LSB]
Differential linearity error V (N + 1) T - VNT = 1 LSB of digital output N 1 LSB = VFST - VOT 1022
VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH"
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MB90330A Series
* Load condition (Full Speed)
ZUSB DVP/HVP
RS = 27
Testing point
CL = 50 pF ZUSB DVM/HVM RS = 27
Testing point
CL = 50 pF
* Load condition (Low Speed)
ZUSB
HVP
RS = 27
Testing point
CL = 50 pF to 150 pF ZUSB RS = 27
HVM
Testing point
CL = 50 pF to 150 pF
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MB90330A Series
MEMO
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MB90330A Series
MEMO
70
DS07-13734-9E
MB90330A Series
MEMO
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MB90330A Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

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