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| 19-5336; Rev 0; 6/10 TION KIT EVALUA BLE ILA AVA Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Features S S S S S S S S S S S S S S IEEE 802.3af/at Compliant Up to 40W for Single-Port PSE Applications Integrated Power MOSFET and Sense Resistor Supports 54V Single-Supply Operation PD Detection and Classification I2C-Compatible, 2-Wire Serial Interface Instantaneous Readout of Port Current Through I2C Interface Programmable Current Limit for Class 5 PDs High-Capacitance Detection for Legacy Devices Supports Both DC and AC Load Removal Detections Current Foldback and Duty-Cycle-Controlled Current Limit LED Indicator for Port Status Direct Fast-Shutdown Control Capability Space-Saving, 28-Pin TQFN (5mm x 5mm) Power Package General Description The MAX5971B is a single-port power controller designed for use in IEEEM 802.3af/at-compliant power-sourcing equipment (PSE). This device provides powered device (PD) discovery, classification, current limit, and DC and AC load-disconnect detections. The MAX5971B supports both fully automatic operation and software programmability, and features an integrated power MOSFET and sense resistor. The device supports detection and classification operation from a single 54V supply. In addition, it supports 2-event classification and new Class 5 classification of high-power PDs. The MAX5971B provides up to 40W to a single port (Class 5 enabled) and still provides high-capacitance detection for legacy PDs. The device provides four operating modes to suit different system requirements. By default, auto mode allows the device to operate automatically at its default settings without any software. Semiautomatic mode automatically detects and classifies a device connected to the port after initial software activation, but does not power the port until instructed to by software. Manual mode allows total software control of the device and is useful for system diagnostics. Shutdown mode terminates all port activities and securely turns off power to the port. The IC features an I2C-compatible, 2-wire serial interface, and is fully software-configurable and programmable. The device provides instantaneous readout of port current through the I2C interface. The device's extensive programmability enhances system flexibility, enables field diagnosis and allows for uses in other, non standard applications. The device provides input undervoltage lockout (UVLO), input undervoltage detection, input overvoltage lockout, overtemperature protection, output voltage slew-rate limit during startup, and LED status indication. The MAX5971B programmability includes startup timeout, overcurrent timeout, and load-disconnect detection timeout. The device is available in a space-saving, 28-pin TQFN (5mm x 5mm) power package and is rated for the extended (-40NC to +85NC) temperature range. MAX5971B Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5971BETI+ 28 TQFN-EP* -40NC to +85NC +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Typical Operating Circuit PSE OUTPUT -54V VEE VEE_DIG LED PWMEN MAX5971B LEGACY MIDSPAN OSC EN SDA SCL AD0 INT DET ILIM1 ILIM2 AGND OUT OUTP Applications Single-Port PSE End-Point Applications Single-Port PSE Power Injectors (Midspan Applications) Switches/Routers SERIAL INTERFACE IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VEE, unless otherwise noted.) AGND, DET, LED ..................................................-0.3V to +80V OUT .......................................................-0.3V to (AGND + 0.3V) OUTP ........................................................-6V to (AGND + 0.3V) VEE_DIG ................................................................-0.3V to +0.3V OSC .........................................................................-0.3V to +6V EN, PWMEN, MIDSPAN, LEGACY, ILIM1, ILIM2 ....-0.3V to +4V INT, AD0, SCL, SDA ................................................-0.3V to +6V Maximum Current into INT and SDA ..................................80mA Maximum Current into LED ................................................40mA Maximum Current into OUT ........................Internally Regulated Continuous Power Dissipation (TA = +70NC) 28-Pin TQFN (derate 34.5mW/NC above +70NC)......2758mW Package Thermal Resistance (Note 1) BJA ...............................................................................29NC/W BJC .................................................................................2NC/W Operating Temperature Range .......................... -40NC to +85NC Storage Temperature Range............................ -65NC to +150NC Junction Temperature .....................................................+150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAGND - VEE = 32V to 60V, TA = -40NC to +85NC, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND - VEE = +54V, TA = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER POWER SUPPLIES Operating Voltage Range Supply Current CURRENT LIMIT Class 0, 1, 2, 3 or ICUT = 000 Maximum ILOAD allowed during current-limit conditions, VOUT = 0V (Note 3) Class 4 or ICUT = 001 Class 5 if ILIM1 = VEE, ILIM2 = unconnected or ICUT = 101 Class 5 if ILIM1 = unconnected, ILIM2 = VEE or ICUT = 110 Class 5 if ILIM1 = VEE, ILIM2 = VEE or ICUT = 111 Foldback Initial OUT Voltage Foldback Final OUT Voltage Minimum Foldback Current-Limit Threshold VFLBK_ST VFLBK_END ITH_FB VAGND - VOUT below which the current limit starts folding back VAGND - VOUT below which the current limit reaches ITH_FB VOUT = VAGND 400 684 807 420 720 850 441 756 893 mA 855 900 945 VAGND IEE VAGND - VEE VOUT = VEE, all logic inputs unconnected, measured at AGND in power mode 32 2.5 60 4 V mA SYMBOL CONDITIONS MIN TYP MAX UNITS Current Limit ILIM 902 950 27 10 166 998 V V mA 2 ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C ELECTRICAL CHARACTERISTICS (continued) (VAGND - VEE = 32V to 60V, TA = -40NC to +85NC, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND - VEE = +54V, TA = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER OVERCURRENT Class 0, 1, 2, 3 or ICUT = 000 Class 4 or ICUT = 001 Overcurrent threshold allowed for t P tFAULT, VOUT = 0V (Note 3) Class 5 if ILIM1 = VEE, ILIM2 = unconnected or ICUT = 101 Class 5 if ILIM1 = unconnected, ILIM2 = VEE or ICUT = 110 Class 5 if ILIM1 = VEE, ILIM2 = VEE or ICUT = 111 INTERNAL POWER DMOS On-Resistance Power-Off OUT Leakage Current SUPPLY MONITORS VEE Undervoltage Lockout VEE Undervoltage Lockout Hysteresis VEE Overvoltage Lockout VEE Overvoltage Lockout Hysteresis VEE Undervoltage Thermal Shutdown Threshold Thermal Shutdown Hysteresis OUTPUT MONITOR OUT Input Current Idle Pullup Current at OUT Short to VEE Detection Threshold Short to VEE Detection Threshold Hysteresis IBOUT IDIS DCNTH DCNHY VOUT = VAGND, probing phases OUTP discharge current, detection and classification off, port shutdown, VOUTP = VAGND - 2.8V VOUT - VEE, VOUT decreasing, enabled during detection 200 1.5 2.0 220 6 265 2.5 FA FA V mV VEE_UVLO VAGND - VEE, VAGND increasing 28.5 3 62.5 1 VEE_UV event bit sets if: VAGND - VEE < VEE_UV, VEE increasing Port is shut down and device resets if the junction temperature exceeds this limit, temperature increasing Temperature decreasing 40 150 20 V V V V V Port is shutdown if: VAGND - VEE < VEE_ VEE_UVLOH UVLO - VEE_UVLOH VEE_OV VEE_OVH VEE_UV TSHD TSHDH VAGND - VEE > VEE_OV, VAGND increasing IOUT_LEAK Measured from OUT to VEE, IOUT = 100mA TA = +25NC TA = +85NC 0.5 0.6 0.9 1.3 10 I FA 351 602 710 370 634 748 389 666 785 mA 752 792 832 SYMBOL CONDITIONS MIN TYP MAX UNITS MAX5971B Overcurrent Threshold ICUT 794 836 878 VEN = VEE, VOUT = VAGND NC NC _______________________________________________________________________________________ 3 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B ELECTRICAL CHARACTERISTICS (continued) (VAGND - VEE = 32V to 60V, TA = -40NC to +85NC, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND - VEE = +54V, TA = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER LOAD DISCONNECT DC Load-Disconnect Threshold AC Load-Disconnect Threshold (Note 4) Triangular Wave Peak-to-Peak Voltage Amplitude OSC Pullup/Pulldown Currents ACD_EN Threshold IDCTH IACTH AMPTRW IOSC VACD_EN Minimum load current allowed before disconnect (DC disconnect active), VOUT = 0V Current into DET, for IDET < IACTH the port powers off (AC disconnect active) Measured at DET, referred to AGND Measured at OSC VOSC - VEE > VACD_EN to activate AC disconnect Time from IRSENSE < IDCTH (DC disconnect active) or IDET < IACTH (AC disconnect active) to gate shutdown (Note 5) VAGND - VDET during the first detection phase VAGND - VDET during the second detection phase VDET = VAGND during detection, measure current through DET If VAGND - VOUT < VDCP after the first detection phase a short circuit to AGND is detected. First point measurement current threshold for open condition (Note 6) Detection rejects lower values Detection rejects higher values VAGND - VDET during classification VDET = VAGND, during classification measure current through DET 32 16 65 20 80 19 5 115 3.85 26 270 7.5 130 4 32 330 10 145 4.2 39 380 mA SYMBOL CONDITIONS MIN TYP MAX UNITS FA V FA mV Load-Disconnect Timer DETECTION Detection Probe Voltage (First Phase) Detection Probe Voltage (Second Phase) Current-Limit Protection tDISC 300 400 ms VDPH1 VDPH2 IDLIM 3.8 9 1.50 4 9.3 1.75 4.2 9.6 2.00 V V mA Short-Circuit Threshold VDCP 1 V Open-Circuit Threshold Resistor Detection Window Resistor Rejection Window CLASSIFICATION Classification Probe Voltage Current-Limit Protection ID_OPEN RDOK RDBAD 20 26.5 15.5 FA kI kI VCL IClLIM V mA 4 ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C ELECTRICAL CHARACTERISTICS (continued) (VAGND - VEE = 32V to 60V, TA = -40NC to +85NC, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND - VEE = +54V, TA = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER SYMBOL CONDITIONS Class 0, Class 1 Classification current thresholds between classes Class 1, Class 2 Class 2, Class 3 Class 3, Class 4 Class 4 upper limit (Note 7) MIN 5.5 13.0 21 31 45 8 55 TYP 6.5 14.5 23 33 48 MAX 7.5 16.0 25 35 51 10 80 V mA mA UNITS MAX5971B Classification Current Thresholds ICL Mark Event Voltage Mark Event Current Limit VMARK IMARK_LIM VAGND - VDET during mark event VDET = VAGND during mark event measure current through DET DIGITAL INPUTS/OUTPUTS (Voltages Referenced to VEE) Digital Input Low Digital Input High Internal Input Pullup Current Open-Drain Output Low Voltage Open-Drain Leakage LED Output Low Voltage LED Output Leakage PWM Frequency PWM Duty Cycle TIMING Startup Time Fault Time Detection Reset Time Detection Time Midspan Mode Detection Delay Classification Time Mark Event Time VEEUVLO Turn-On Delay Restart Timer Watchdog Clock Period tDLY tRESTART tSTART tFAULT tME tDET tDMID tCLASS Time allowed for classification Time allowed for mark event Time VAGND must be above the VEEUVLO thresholds before the device operates Time the device waits before turning on after an overcurrent fault (Note 8) Rate of decrement of the watchdog time 7 Time during which a current limit set to 420mA is allowed, starts when power is turned on (Note 8) Maximum allowed time for an overcurrent condition set by ICUT after startup (Note 8) Time allowed for the port voltage to reset before detection starts Maximum time allowed before detection is completed 2 2.2 19 9 5.2 16 x tFAULT 164 50 50 60 60 80 70 70 90 330 2.4 23 11 ms ms ms ms s ms ms ms ms ms VIL VIH IPU VOL IOL VLED_LOW ILED_LEAK Pullup current to internal digital supply to set default values ISINK = 10mA Open-drain high impedance ILED = 10mA, PWM disabled, port power-on PWM disabled, shutdown mode, VLED = 60V 25 6.25 2.4 3 5 7 0.4 2 0.8 10 0.8 V V FA V FA V FA kHz % _______________________________________________________________________________________ 5 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B ELECTRICAL CHARACTERISTICS (continued) (VAGND - VEE = 32V to 60V, TA = -40NC to +85NC, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND - VEE = +54V, TA = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER Resolution Range LSB Step Size Gain Error ADC Absolute Accuracy Integral Nonlinearity Differential Nonlinearity Serial Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time for a START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition (Sr) Data Hold Time Data in Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed INL DNL fSCL tBUF SYMBOL CONDITIONS MIN TYP 9 1.507 2.95 MAX UNITS Bits A mA ADC PERFORMANCE (Power-On Mode) TA = +25NC TA = -40NC to +85NC IOUT = 400mA 130 136 0.3 0.3 2 4 142 1.7 1.7 400 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 0.6 150 % LSB LSB LSB kHz s s s s s ns ns TIMING CHARACTERISTICS (For 2-Wire Fast Mode) tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tR tF tSU,STO CB tSP (Note 9) (Note 9) (Note 9) (Note 9) 300 250 ns ns s 400 50 pF ns Note 2: This device is production tested at TA = +25C. Limits to TA = -40C to +85C are guaranteed by design. Note 3: Default thresholds are set by the classification result in auto mode. The thresholds are manually software programmable through the ICUT Register (R2Ah[2:0]). If ILIM1 and ILIM2 are both unconnected, Class 5 detection is disabled. See the Class 5 PD Classification section and Table 3 for details and settings. Note 4: Default value. The AC load-disconnect threshold can be programmed through the AC_TH register (R23h[2:0]). Note 5: Default value. The load-disconnect time, tDISC can be programmed through the TDISC register (R16h[1:0]). Note 6: RDOK = (VOUT2 - VOUT1)/(IDET2 - IDET1). VOUT1, VOUT2, IDET2, and IDET1 represent the voltage at OUT and the current at DET during phase 1 and 2 of the detection, respectively. Note 7: If Class 5 is enabled, this value is the classification current threshold from Class 4 to Class 5. Note 8: Default values. The startup, fault, and restart timers can be programmed through the TSTART (R16h[5:4]), TFAULT (R16h[3:2]), and RSRT (R16h[7:6]) registers, respectively. Note 9: Guaranteed by design. Not subject to production testing. 6 ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Typical Operating Characteristics (TA = +25C, unless otherwise noted.) ANALOG SUPPLY CURRENT vs. INPUT VOLTAGE MAX5971B toc01 MAX5971B ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX5971B toc02 VEE UNDERVOLTAGE LOCKOUT vs. TEMPERATURE MAX5971B toc03 2.7 MEASURED AT AGND 2.7 MEASURED AT AGND 30.0 29.5 29.0 28.5 28.0 27.5 SUPPLY CURRENT (mA) 2.5 SUPPLY CURRENT (mA) 2.6 2.6 2.5 2.4 2.4 2.3 32 36 40 44 48 52 56 60 VAGND - VEE (V) 2.3 -40 -15 10 35 60 85 TEMPERATURE (C) UNDERVOLTAGE LOCKOUT (V) 27.0 -40 -15 10 35 60 85 TEMPERATURE (C) VEE OVERVOLTAGE LOCKOUT vs. TEMPERATURE MAX5971B toc04 INTERNAL FET RESISTANCE vs. TEMPERATURE MAX5971B toc05 64.0 63.5 OVERVOLTAGE LOCKOUT (V) 63.0 62.5 62.0 61.5 61.0 60.5 60.0 -40 -15 10 35 60 1000 FET RESISTANCE (m) 85 800 600 400 200 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C) FOLDBACK CURRENT-LIMIT THRESHOLD vs. OUTPUT VOLTAGE MAX5971B toc06 DC DISCONNECT THRESHOLD vs. TEMPERATURE MAX5971B toc07 800 700 600 IRSENSE (mA) 500 400 300 200 100 0 0 10 20 VAGND - VOUT (V) 30 7.4 DC DISCONNECT THRESHOLD (mA) 7.2 7.0 6.8 6.6 6.4 -40 -15 10 35 60 CLASS 4 CLASS 0, 1, 2, 3 40 85 TEMPERATURE (C) _______________________________________________________________________________________ 7 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) OVERCURRENT TIMEOUT (240 TO 138) MAX5971B toc08 SHORT-CIRCUIT RESPONSE TIME MAX5971B toc09 VAGND - VOUT 20V/div 0V 0V VAGND - VOUT 20V/div IOUT 200mA/div 0mA 20ms/div 0mA 20ms/div IOUT 200mA/div SHORT-CIRCUIT TRANSIENT RESPONSE MAX5971B toc10 EN TO OUT TURN-OFF DELAY MAX5971B toc11 VAGND - VOUT 20V/div 0V VAGND - VOUT 20V/div 0V IOUT 200mA/div VEN 5V/div 100s/div 0mA IOUT 5A/div 0mA 10s/div 0V ZERO-CURRENT DETECTION WAVEFORM WITH DC DISCONNECT ENABLED MAX5971B toc12 ZERO-CURRENT DETECTION WAVEFORM WITH AC DISCONNECT ENABLED MAX5971B toc13 VAGND - VOUT 20V/div 0V 0V VAGND - VOUT 20V/div IOUT 100mA/div 0mA 100ms/div 0mA 100ms/div IOUT 100mA/div 8 ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) OVERCURRENT RESTART DELAY MAX5971B toc14 STARTUP WITH A VALID PD MAX5971B toc15 VAGND - VOUT 20V/div 0V VAGND - VOUT 20V/div 0V IOUT 200mA/div 0mA 400ms/div 0mA 100ms/div IOUT 100mA/div DETECTION WITH INVALID PD (25k TO 10F) MAX5971B toc16a DETECTION WITH INVALID PD (15k) MAX5971B toc16b VAGND - VOUT 1V/div 0V VAGND - VOUT 5V/div 0V IOUT 1mA/div 0mA 40ms/div 0mA 100ms/div IOUT 1mA/div DETECTION WITH INVALID PD (33k) MAX5971B toc16c DETECTION WITH INVALID PD (OPEN CIRCUIT) MAX5971B toc16d VAGND - VOUT 5V/div 0V 0V VAGND - VOUT 5V/div 0mA 100ms/div IOUT 1mA/div 0mA 100ms/div IOUT 1mA/div _______________________________________________________________________________________ 9 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) STARTUP IN MIDSPAN WITH A VALID PD MAX5971B toc17 DETECTION IN MIDSPAN WITH INVALID PD (15k) MAX5971B toc18a VAGND - VOUT 20V/div 0V 0V VAGND - VOUT 5V/div IOUT 100mA/div 0mA 100ms/div 0mA 400ms/div IOUT 1mA/div DETECTION IN MIDSPAN WITH INVALID PD (33k) MAX5971B toc18b DETECTION IN OUTPUT SHORTED TO AGND MAX5971B toc19 VAGND - VOUT 5V/div 0V 0V VAGND - VOUT 5V/div 0mA 400ms/div IOUT 1mA/div IOUT 1mA/div 0mA 40ms/div CLASSIFICATION WITH DIFFERENT PD CLASSES (0 TO 3) MAX5971B toc20a CLASSIFICATION WITH DIFFERENT PD CLASSES (4 AND 5) MAX5971B toc20b VAGND - VOUT 10V/div 0V 0V VAGND - VOUT 10V/div CLASS 3 CLASS 2 CLASS 1 CLASS 0 IOUT 10mA/div 0mA CLASS 5 CLASS 4 IOUT 20mA/div 0mA 40ms/div 40ms/div 10 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) STARTUP USING 2-EVENT CLASSIFICATION WITH A VALID PD MAX5971B toc21 MAX5971B LED DETECTION FAULT WITH PWM ENABLED MAX5971B toc22a VAGND - VOUT 20V/div 0V 0V VAGND - VOUT 10V/div 0mA IOUT 500mA/div IOUT 100mA/div 0mA 0V 100ms/div 200ms/div VAGND - VLED 20V/div LED DETECTION FAULT WITH PWM DISABLED MAX5971B toc22b LED OVERCURRENT FAULT WITH PWM ENABLED MAX5971B toc23a LED OVERCURRENT FAULT WITH PWM DISABLED MAX5971B toc23b 0V VAGND - VOUT 10V/div 0V VAGND - VOUT 50V/div IOUT 500mA/div 0V VAGND - VOUT 50V/div IOUT 500mA/div 0mA IOUT 500mA/div 0mA 0mA VAGND - VLED 20V/div 0V 200ms/div 0V 200ms/div VAGND - VLED 20V/div 0V 200ms/div VAGND - VLED 20V/div LED PWM TIMING: MINIMUM DUTY CYCLE (DEFAULT) MAX5971B toc24a LED PWM TIMING: MAXIMUM DUTY CYCLE (PROGRAMMABLE) MAX5971B toc24b VAGND - VOUT 50V/div OV OV VAGND - VOUT 50V/div OmA IOUT 500mA/div OmA IOUT 500mA/div VAGND - VLED 20V/div OV 10s/div OV 10s/div VAGND - VLED 20V/div ______________________________________________________________________________________ 11 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Pin Configuration AGND OSC N.C. N.C. N.C. 16 LED I.C. 15 14 13 12 EN LEGACY VEE_DIG AD0 INT SCL SDA 11 10 9 8 1 VEE 2 VEE 3 VEE 4 ILIM1 5 ILIM2 6 PWMEN 7 MIDSPAN TOP VIEW 21 N.C. 22 DET 23 N.C. 24 OUTP 25 OUT 26 OUT 27 N.C. 28 20 19 18 17 MAX5971B + *EP THIN QFN *CONNECT TO VEE. Pin Description PIN 1, 2, 3 NAME VEE FUNCTION Analog Low-Side Supply Input. Bypass with an external 100V, 47FF capacitor in parallel with a 100V, 0.1FF ceramic capacitor between AGND and VEE. Class 5 Current-Limit Digital Adjust 1. Referenced to VEE. ILIM1 is internally pulled up to the digital supply. Use ILIM1 with ILIM2 to enable Class 5 operation and to adjust the Class 5 current-limit value. See the Electrical Characteristics table and Table 3 in the Class 5 PD Classification section for details. Class 5 Current-Limit Digital Adjust 2. Referenced to VEE. ILIM2 is internally pulled up to the digital supply. Use ILIM2 with ILIM1 to enable Class 5 operation and to adjust the Class 5 current-limit value. See the Electrical Characteristics table and Table 3 in the Class 5 PD Classification section for details. PWM Control Logic Input. Referenced to VEE. PWMEN is internally pulled up to the digital supply. Leave unconnected to enable the internal PWM to drive the LED pin. Force low to disable the internal PWM. Detection Collision Avoidance Logic Input. Referenced to VEE. MIDSPAN is internally pulled up to the digital supply. Leave unconnected to activate the detection collision avoidance circuitry for midspan PSE systems. Force low to disable this function for an end-point PSE system. The MIDSPAN logic level latches after the device is powered up or after a reset condition. 2-Wire Serial Interface Input/Output Data Line. Referenced to VEE. Connect to VEE if the I2C interface is not used. 4 ILIM1 5 ILIM2 6 PWMEN 7 MIDSPAN 8 SDA 12 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Pin Description (continued) PIN 9 10 11 12 13 NAME SCL INT AD0 VEE_DIG LEGACY FUNCTION 2-Wire Serial Interface Input Clock Line. Referenced to VEE. Connect to VEE if the I2C interface is not used. Open-Drain Interrupt Output. Referenced to VEE. INT is pulled low whenever an interrupt is sent to the microcontroller. See the Interrupt section for details. Connect to VEE if the I2C interface is not used. Address Input. Referenced to VEE. AD0 is used to form the lower part of the device address. See the Device Address section and Table 5 for details. Connect to VEE if the I2C interface is not used. Digital Low-Side Supply Input. Connect to VEE externally. Legacy Detection Logic Input. Referenced to VEE. LEGACY is internally pulled up to the digital supply. Leave unconnected to activate the legacy PD detection. Force low to disable this function. The LEGACY logic level latches after the device is powered up or after a reset condition. Enable Input. Referenced to VEE. EN is internally pulled up to the digital supply. Leave unconnected to enable the device. Force low for at least 40Fs to reset the device. The MIDSPAN, OSC, and LEGACY states latch-in when the reset condition is removed (low-to-high transition). Bypass EN to VEE with a 1nF ceramic capacitor. Internally Connected. Connect I.C. to VEE. No Connection. Not internally connected. Leave N.C. unconnected. LED Indicator Open-Drain Output. Referenced to VEE. LED can sink 10mA and can drive an external LED directly. Blinking functionality is provided to signal different conditions (see the PWM and LED Signals section). Connect LED to AGND externally (see Figures 15 and 16) or to an external supply (if available) through a series resistance. AC-Disconnect Triangular Wave Output. Bypass with a 100nF (Q10% tolerance) external capacitor to VEE to enable the AC disconnect function. Connect OSC to VEE to disable the AC disconnect function and to activate the DC disconnect function. The OSC state latches after the device is powered up or after a reset condition. High-Side Supply Input Detection/Classification Voltage Output. DET is used to set the detection and classification probe voltages and for the AC current sensing when using the AC disconnect function. To use the AC disconnect function, place a 1kI and 0.47FF RC series in parallel with the external protection diode to OUTP (see Figure 16). Port Pullup Output. OUTP is used to pull up the port voltage to AGND when needed. If AC disconnect is used, connect OUTP to the anode of the AC-blocking diode. If AC disconnect is not used, connect OUTP to OUT (see Figures 15 and 17). Bypass OUTP to AGND with a 100V, 0.1FF ceramic capacitor. Integrated MOSFET Output. If DC disconnect is used, connect the port output to OUTP (see Figures 15 and 17). If the AC disconnect function is used, connect OUT to the cathode of the AC-blocking diode (see Figure 16). Exposed Pad. Connect EP to VEE externally. See the Layout Procedure section for details. MAX5971B 14 15 16, 18, 20, 22, 24, 28 EN I.C. N.C. 17 LED 19 OSC 21 AGND 23 DET 25 OUTP 26, 27 -- OUT EP ______________________________________________________________________________________ 13 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Simplified Diagram ADO SCL SDA OSC CURRENT SENSING SERIAL PORT INTERFACE (SPI) EN TRIANGLE WAVE GENERATOR VOLTAGE PROBING AND CURRENT-LIMIT CONTROL AGND DET OSC STATUS MONITOR OUTP DETECTION AND CLASSIFICATION CONTROL VOLTAGE SENSING FOLDBACK CONTROL OUT LEGACY MIDSPAN REGISTER FILE PORT STATE MACHINE (SM) 9-BIT ADC AC DISCONNECT ENABLE INT CENTRAL LOGIC UNIT (CLU) A=1 POWER ENABLE AGND ANALOG BIAS AND SUPPLY MONITOR INTERNAL SUPPLIES VOLTAGE REFERENCES CURRENT REFERENCES AC DISCONNECT SIGNAL (ACD) AC DETECTOR ACD REFERENCE CURRENT GATEDRIVE CONTROL INTERNAL MOSFET VEE LED THRESHOLD SETTINGS PWM CURRENT-LIMIT, OVERCURRENT, AND OPENCIRCUIT SENSING, AND FOLDBACK CONTROL INTERNAL RSENSE CLASS 5 ENABLE/DISABLE, OVERCURRENT AND CURRENT-LIMIT CONTROL ILIM1 ILIM2 MAX5971B PWMEN Detailed Description The MAX5971B is a single-port power controller designed for use in IEEE 802.3af/802.3at-compliant PSE. This device provides PD discovery, classification, current limit, and DC and AC load-disconnect detections. The MAX5971B supports both fully automatic operation and software programmability, and features an integrated power MOSFET and sense resistor. The device also supports new Class 5 and 2-event classification for detection and classification of high-power PDs. The MAX5971B provides up to 40W to a single port (Class 5 enabled), and still provides high-capacitance detection for legacy PDs. The MAX5971B features an I2C-compatible, 2-wire serial interface, and is fully software configurable and programmable. The device provides instantaneous readout 14 of port current through the I2C interface. The MAX5971B provides input undervoltage lockout (UVLO), input undervoltage detection, input overvoltage lockout, overtemperature protection, output voltage slew-rate limit during startup, and LED status indication. The MAX5971B programmability includes startup timeout, overcurrent timeout, and load-disconnect detection timeout. The MAX5971B is reset by any of the following conditions: 1) Power-Up. Reset condition is cleared once VEE rises above the UVLO threshold. 2) Hardware Reset. Reset occurs once the EN input is driven low (> 40Fs, typ) any time after power-up. The device exits the reset condition once the EN input is driven high again. Reset _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C 3) Software Reset. To initiate a software reset, write a logical 1 to the RESET_IC register (R1Ah[4]) any time after power-up. Reset clears automatically and all registers are set to their default states. 4) Thermal Shutdown. The device enters thermal shutdown at 150NC. The device exits thermal shutdown and is reset once the temperature drops below 130NC. At the end of a reset event, the MAX5971B latches in the state of MIDSPAN, LEGACY, and OSC. During normal operation, changes to the MIDSPAN and LEGACY inputs are ignored, and these inputs can be changed at any time prior to the end of a reset state. Changes to OSC input during normal operation can impact device functionality. Therefore, OSC is only changed while the device is held in a reset state (or powered down), and OSC then latches in when the reset state ends (other schematic modifications may be needed, see Figures 15 and 16). Set RESET_P (R1Ah[0]) high anytime during normal operation to turn off port power and clear the port event and status registers. Port reset does not initiate a global device reset. In midspan mode, the device adopts cadence timing during the detection phase. When cadence timing is enabled and a failed detection occurs, the port waits between 2s and 2.4s before attempting to detect again. Midspan mode is activated by setting MIDSPAN high and then powering or resetting the device. Alternatively, midspan mode is software enabled by setting BCKOFF (R15h[0], Table 22) to a logical 1. By default, the MIDSPAN input is internally pulled high, enabling cadence timing. Force MIDSPAN low to disable this function. The MAX5971B provides four operating modes to suit different system requirements. By default, auto mode allows the device to operate automatically at its default settings without any software. Semiautomatic mode automatically detects and classifies a device connected to the port after initial software activation, but does not power up the port until instructed to by software. Manual mode allows total software control of the device and is useful for system diagnostics. Shutdown mode terminates all activities and securely turns off power to the port. Switching between auto, semiautomatic, and manual mode does not interfere with the operation of the output port. When the port is set into shutdown mode, all port operations are immediately stopped and the port remains idle until shutdown mode is exited. Auto (Automatic) Mode By default, the MAX5971B enters auto mode after the reset condition is cleared. To manually place the MAX5971B into auto mode from any other mode, set P_M[1:0] (R12h[1:0]) to [11] during normal operation (see Tables 18 and 19). In auto mode, the MAX5971B performs detection and classification, and powers up the port automatically if a valid PD is connected to the port. If a valid PD is not connected at the port, the MAX5971B repeats the detection routine continuously until a valid PD is connected. When entering auto mode, the DET_EN and CLASS_EN bits (R14h[0] and R14h[4], Table 21) are set to high and stay high unless changed by software. Using software to set DET_EN and/or CLASS_EN low causes the MAX5971B to skip detection and/or classification. As a protection, disabling the detection routine in auto mode does not allow the corresponding port to power up, unless the DET_BY bit (R23h[4], Table 32) is set to 1. Semiautomatic (Semi) Mode The MAX5971B is put into semiautomatic mode by setting P_M[1:0] (R12h[1:0]) to [10] during normal operation (see Tables 18 and 19). In semi mode, the MAX5971B, upon request, performs detection and/or classification repeatedly but does not power up the port. To power the port, set the PWR_ON bit (R19h[0], Table 26) to 1. This immediately terminates the detection/classification routine and turns on power to the port. DET_EN and CLASS_EN (R14h[0] and R14h[4], Table 21) default to low in semiautomatic mode. Use software to set DET_EN (R14h[0]) to 1 to start the detection routine and CLASS_EN (R14h[4]) to 1 to enable classification routine. They are reset every time the software commands a power-off of the port, either through a reset event or by writing a 1 to the PWR_OFF bit (R19h[4]). In any other case, the status of the bits is left unchanged (including when the state machine turns off the power when a load disconnect or a fault condition is encountered). Manual Mode The MAX5971B is placed in manual mode by setting P_M[1:0] (R12h[1:0]) to [01] during normal operation (see Tables 18 and 19). Manual mode allows the software to dictate the sequence of operation. Write a 1 to both R14h[0] (DET_EN) and R14h[4] (CLASS_EN) to start detection and classification operations, respectively, and in that priority order. In manual mode, after 15 MAX5971B Port Reset Midspan Mode Operation Modes ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B execution, the command is cleared from the register(s). PWR_ON has highest priority. Setting PWR_ON to 1 at any time causes the device to immediately enter the powered mode. Setting DET_EN and CLASS_EN to 1 at the same time causes detection to be performed first. Once in the powered state, the device ignores DET_EN or CLASS_EN commands. When switching to manual mode from another mode, DET_EN and CLASS_EN default to low. These bits become pushbutton rather than configuration bits. Writing 1 to these bits while in manual mode commands the device to execute one cycle of detection and/or classification. They are reset back to 0 at the end of the execution. Shutdown Mode To put the MAX5971B into shutdown mode, set P_M[1:0] (R12h[1:0]) to [00] during normal operation (see Table 18 and Table 19). Putting the MAX5971B into shutdown mode immediately turns off port power, clears the event and status bits, and halts all port operations. In shutdown mode the serial interface is still fully active, however, all DET_EN, CLASS_EN, and PWR_ON commands are ignored. During normal operation, the MAX5971B probes the output for a valid PD. A valid PD has a 25kI discovery signature characteristic as specified in the IEEE 802.3af/802.3at standard. Table 1 shows the IEEE 802.3at specification for a PSE detecting a valid PD signature. After each detection cycle, the MAX5971B sets DET_ END (R04h[0] and R05h[0]) to 1 and reports the detection results in the detection status bits, DET_ST[2:0] (R0Ch[2:0], see Table 13). The DET_END registers are reset to 0 when read through the CoR (clear-on-read) register R05h[0], or after a reset event. During detection, the MAX5971B keeps the internal MOSFET off and forces two probe voltages through DET. The current through DET is measured as well as the voltage at OUT. A two-point slope measurement is used, as specified by the IEEE 802.3af/802.3at standard, to verify the device connected to the port. By default, The MAX5971B load stability check is disabled. Set LSC_EN (R29h[4], Table 35) to 1 to enable the load stability check. The MAX5971B implements appropriate settling times to reject 50Hz/60Hz power-line noise coupling. An external diode, in series with the DET input, restricts PD detection to the first quadrant as specified by the IEEE 802.3af/802.3at standard. To prevent damage to non-PD devices, and to protect itself from an output short circuit, the MAX5971B limits the current into DET to less than 2mA (max) during PD detection. In midspan mode, after every failed detection cycle, the MAX5971B waits at least 2.0s before attempting another detection cycle. The first detection, however, still happens immediately after exiting a reset condition. High-Capacitance Detection High-capacitance detection for legacy PDs is both software and pin programmable (LEGACY). To use software to enable high-capacitance detection, set CLC_EN (R23h[5]) to 1 during normal operation. Alternatively, the status of the LEGACY input is latched and written to CLC_EN during power-up or after reset condition is cleared. The LEGACY input is internally pulled PD Detection Table 1. PSE PI Detection Modes Electrical Requirements (IEEE 802.3at) PARAMETER Open-Circuit Voltage Short-Circuit Current Valid Test Voltage Voltage Difference Between Test Points Time Between Any Two Test Points Slew Rate Accept Signature Resistance Reject Signature Resistance Open-Circuit Resistance Accept Signature Capacitance Reject Signature Capacitance Signature Offset Voltage Tolerance Signature Offset Current Tolerance 16 SYMBOL VOC ISC VVALID DVTEST tBP VSLEW RGOOD RBAD ROPEN CGOOD CBAD VOS IOS 10 0 0 2.0 12 19 < 15 500 150 2.8 1 2 0.1 26.5 > 33 MIN MAX 30 5 10 UNITS V mA V V ms V/Fs kI kI kI nF FF V FA This timing implies a 500Hz maximum probing frequency ADDITIONAL INFORMATION In detection mode only In detection mode only _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C high, enabling high-capacitance detection. Unless highcapacitance detection is needed, connect LEGACY to VEE to disable this function. If high-capacitance detection is enabled, PD signature capacitances up to 47FF (typ) are accepted. current exceeds 51mA, the MAX5971B does not power the PD, but returns to idle state before attempting a new detection cycle. Class 5 PD Classification The MAX5971B supports high power beyond the IEEE 802.3at standard by providing an additional classification (Class 5) if needed. To enable Class 5 detection and select the corresponding current-limit/overcurrent thresholds, ILIM1 and ILIM2 must be set based on the combinations detailed in Table 3. Once Class 5 is enabled, during classification, if the MAX5971B detects currents in excess of the Class 4 upper limit threshold, the PD is classified as a Class 5 powered device. The PD is guaranteed to be classified as a Class 5 device for any classification current from 51mA up to the classification current-limit threshold. The Class 5 overcurrent threshold and current limit is set with ILIM1 and ILIM2. ILIM1 and ILIM2 are both referenced to VEE and are internally pulled up to the digital supply. Leave ILIM1 and ILIM2 unconnected to disable Class 5 detection and to be fully compliant to IEEE 802.3at standard classification. Class 5 detection is enabled, and the corresponding overcurrent threshold and current limit is adjusted, by connecting one or both to VEE (see Table 3). 2-Event PD Classification If the result of the first classification event is Class 0 through Class 3, then only a single classification event occurs as shown in Figure 1. However, if the result is Class 4 or Class 5 (when enabled), the device performs a second classification event as shown in Figure 2. Between the classification cycles, the MAX5971B performs a first and second mark event as required by the IEEE 802.3at standard, forcing a -9.3V probing voltage at DET. MAX5971B During PD classification, the MAX5971B forces a probe voltage (-18V, typ) at DET and measures the current into DET. The measured current determines the class of the PD. After each classification cycle, the MAX5971B sets CL_END (R04h[4] and R05h[4]) to 1 and reports the classification results in the classification status bits, CLASS[2:0] (R0Ch[6:4], see Table 13). The CL_END registers are reset to 0 when read through the CoR (clearon-read) register, R05h, or after a reset event. If ILIM1 and ILIM2 are both left unconnected, the MAX5971B classifies the PD based on Table 33.9 of the IEEE 802.3at standard (see Table 2). If the measured Powered Device Classification (PD Classification) Table 2. PSE Classification of a PD (Table 33.9 of the IEEE 802.3at Standard) MEASURED ICLASS (mA) 0 to 5 > 5 and < 8 8 to 13 > 13 and < 16 16 to 21 > 21 and < 25 25 to 31 > 31 and < 35 35 to 45 > 45 and < 51 CLASSIFICATION Class 0 Can be Class 0 or 1 Class 1 Either Class 1 or 2 Class 2 Either Class 2 or 3 Class 3 Either Class 3 or 4 Class 4 Either Class 4 or Invalid Table 3. Class 5 Overcurrent Threshold and Current-Limit Settings ILIM1 CONFIGURATION Unconnected VEE Unconnected VEE ILIM2 CONFIGURATION Unconnected Unconnected VEE VEE OVERCURRENT THRESHOLD (mA) Class 5 disabled 748 792 836 CURRENT LIMIT (mA) Class 5 disabled 850 900 950 ______________________________________________________________________________________ 17 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B 80ms 150ms tDET(1) 150ms tDET(2) 19ms tCLASS t 0V -4V -9.3V -18V -54V VOUT Figure 1. Detection, Classification, and Port Power-Up Sequence 9ms 80ms 150ms tDET(1) 150ms tDET(2) 19ms tCLASS(1) 19ms tCLASS(2) t 0V -4V -9.3V 9ms -18V -54V VOUT Figure 2. Detection, 2-Event Classification, and Port Power-Up Sequence 18 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C When the MAX5971B enters a powered state, the tFAULT and tDISC timers are reset. When the startup timer (tSTART) has timed out, the device enters a normal powered condition, allowing power delivery to the PD. PGOOD (R10h[4], Table 16) is set to 1 when the device enters the normal Power condition. PGOOD immediately resets to 0 whenever the power to the port is turned off. The power-good change bits, PG_CHG ([R02h[4] and R03h[4], Table 9) are set both when the port powers up and when it powers down. PWR_EN (R10h, Table 16) is set to 1 when the port powers up and resets to 0 when a port shuts down. Set PWR_OFF (R19h[4], Table 26) to 1 to immediately turn off power to the port. The MAX5971B has an internal sense resistor, RSENSE (see the Functional Diagram), connected between the source of the internal MOSFET and VEE to monitor the load current. Under normal operating conditions, the current through RSENSE (IRSENSE) never exceeds the threshold ILIM. If IRSENSE exceeds ILIM, an internal current-limiting circuit regulates the gate voltage of the internal MOSFET, limiting the current. During transient conditions, if IRSENSE exceeds ILIM by more than 2A, a fast pulldown circuit activates to quickly recover from the current overshoot. In the normal powered state, the MAX5971B checks for overcurrent conditions, as determined by ICUT = ~88% of ILIM. The tFAULT counter sets the maximum-allowed continuous overcurrent period. This timer is incremented both in startup and in normal powered state, but under different conditions. During startup it increases when IRSENSE exceeds ILIM, while in the normal powered state the counter increases when IRSENSE exceeds ICUT. It decreases at a slower pace when IRSENSE drops below ILIM or ICUT. A slower decrement for the tFAULT counter allows for detection of repeated short-duration overcurrent events. When the counter reaches the tFAULT limit, Powered State the MAX5971B powers down the port and asserts the IMAX_FLT bits (R06h[0] and R07h[0]). For a continuous overstress, a fault occurs exactly after a period of tFAULT. The timing is software programmable through the timing register (R16h, Table 23). After a power-off due to an overcurrent fault, the tFAULT timer is not immediately reset but starts decrementing. The MAX5971B allows the port to be powered on only when the tFAULT counter reaches zero. This feature sets an automatic port power duty-cycle protection to the internal MOSFET to avoid overheating. Through programmable registers, the MAX5971B allows the rate of decrement to be adjusted or for the restart timeout to be disabled entirely (see Tables 23 and 24). In the normal powered state, the ILIM and ICUT thresholds are set automatically according to the classification result (see Table 4 for classification results based on detection current, and the Electrical Characteristics table for the corresponding thresholds). The thresholds can also be set manually by programming the ICUT register (R2Ah[2:0]). During startup, ILIM is always set to 420mA regardless of the detected class. The ICUT register determines the maximum current limit allowed for the MAX5971B during the powered state. The ICUT bits (R2Ah[2:0]) allow manual programming of the current limit (ILIM) and overcurrent (ICUT) thresholds (see Tables 36 and 37). The ICUT register can be written to directly through the I2C interface when the automatic ICUT programming bit, CL_DISC (R17h[2]), is set to 1 (see Table 4). In this case, the current limit of the port is configured regardless of the status of the classification. By setting the CL_DISC bit to 0 (default), the MAX5971B automatically sets the ICUT register based upon the classification result (see Tables 4, 36, and 37 in the Register Map and Description section). MAX5971B Overcurrent Protection The ICUT Register Table 4. Automatic ICUT Programming CL_DISC (R17h[2]) 1 0 0 0 0 0 PORT CLASSIFICATION RESULT Any 0, 1, 2, 3 4 5 5 5 ILIM1 SETTING -- -- -- VEE Unconnected VEE ILIM2 SETTING -- -- -- Unconnected VEE VEE RESULTING ICUT REGISTER BITS (R2Ah[2:0]) User programmed ICUT = 000 ICUT = 001 ICUT = 101 ICUT = 110 ICUT = 111 CURRENT LIMIT (mA) -- 420 720 850 900 950 19 ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B During startup and normal operation, an internal circuit senses the port voltage and reduces the current-limit value and the overcurrent threshold when (VAGND VOUT) < 27V. The foldback function helps to reduce the power dissipation on the internal MOSFET. The current limit eventually reduces down to ITH_FB (166mA, typ) when (VAGND - VOUT) < 10V (see Figure 3). The MAX5971B internally generates digital supplies (referenced to VEE) to power the internal logic circuitry. All logic inputs and outputs are referenced to VEE. See the Electrical Characteristics table for digital input thresholds. If digital logic inputs are driven externally, the nominal digital logic level is 3.3V. The MAX5971B contains an open-drain logic output (INT) that goes low when an interrupt condition exists. The interrupt register (R00h, Table 7) contains the interrupt flag bits and the interrupt mask register (R01h, Table 8) determines which events can trigger an interrupt. When an event occurs, the appropriate interrupt event register bits (in R02h through R0Bh) and the corresponding interrupt (in R00h) are set to 1 and INT is asserted low (unless masked). IRSENSE Foldback Current Digital Logic As a response to an interrupt, the controller can read the status of the event register(s) to determine the cause of the interrupt and take appropriate action. Each interrupt event register is paired with a clear-on-read (CoR) register. When an interrupt event register is read through the corresponding CoR register, the interrupt register is reset to 0. INT remains low and the interrupt is not reset when the interrupt event register is read through the read-only addresses. For example, to clear a supply event fault, read R0Bh (CoR) not R0Ah (read only, see Table 12). Use the CLR_INT bit (R1Ah[7]) to clear an interrupt, or the RESET_IC (R1Ah[4]) or RESET_P (R1Ah[0]) bit to initiate a software reset (see Table 27). The MAX5971B contains both undervoltage and overvoltage protection features. Table 12 in the Register Map and Description section shows a detailed list of the undervoltage and overvoltage protection features. An internal VEE undervoltage lockout (VEE_UVLO) circuit keeps the port off and the MAX5971B in reset until VAGND - VEE exceeds 28.5V (typ) for more than 2.5ms. An internal VEE overvoltage (VEE_OV) circuit shuts down the port when VAGND - VEE exceeds 62.5V (typ). The MAX5971B also features a VEE undervoltage interrupt (VEE_UV) that triggers when VAGND - VEE drops below Undervoltage and Overvoltage Protection Interrupt ILIM ITH_FB 10V 27V VAGND - VOUT Figure 3. Foldback Current Characteristics 20 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C 40V (typ). A fault latches into the supply event register VEE_UV (R0Ah[2] and R0Bh[2], Table 12) but the MAX5971B does not power down the port in this case. Force OSC to VEE and power or reset the device to activate DC load-disconnect monitoring. DCD_EN (R13h[0]) is set to 1 to enable DC load disconnect. If IRSENSE (the current across RSENSE) falls below the DC load-disconnect threshold, IDCTH, for more than tDISC, the device turns off port power and sets LD_DISC in the fault event registers (R06h[4] and R07h[4]) to 1. The MAX5971B features AC load-disconnect monitoring. Bypass OSC with a 100nF (Q10% tolerance) external capacitor to VEE and power or reset the device to automatically enable AC disconnect. ACD_EN (R13h[4]) is set to 1 to enable AC disconnect (the bypass from OSC to VEE must be in place as well). When AC disconnect is enabled, a blocking diode in series to OUT and an RC circuit in parallel to the DET diode must be used, as shown in the typical operating circuit of Figure 16. The AC disconnect uses an internal triangle-wave generator to supply the probing signal. Then the resulting DC Disconnect Monitoring 4VP-P amplitude wave is forced on DET. The common mode of the output signal probed on DET is 5V below AGND. If the AC current peak at DET falls below IACTH for more than tDISC, the device powers down the port and asserts LD_DISC (R06h[4] and R07h[4]). The AC loaddisconnect threshold (IACTH) is programmable using the AC_TH[2:0] bits (R23h[2:0], see Table 32 for settings). The MAX5971B includes a multifunction LED driver to inform the user of the port status. LED is an open-drain, multifunction output referenced to VEE and can sink 10mA (typ) while driving an external LED. The LED is turned on when the port is connected to a valid PD and powered. If the port is not powered or is disconnected, the LED is off. For two other conditions, the MAX5971B blinks a code to communicate the port status. A series of two flashes indicates an overcurrent fault occurred during port power-on, and has a timing characteristic detailed by Figure 4. A series of five flashes indicates that during detection an invalid low or high discovery signature resistance was detected, and has a timing characteristic detailed by Figure 5. MAX5971B PWM and LED Signals AC Disconnect Monitoring PORT POWERED ON PORT POWERED DOWN, DUE TO OVERCURRENT FAULT PORT POWERED ON AGAIN LED ON LED OFF LED ON LED OFF LED ON LED OFF LED ON 223ms 74ms 223ms 74ms Figure 4. LED Code Timing for Overcurrent Fault During Port Power-On INVALID HIGH OR LOW DISCOVERY SIGNATURE RESISTANCE DETECTED LED ON LED OFF LED ON LED OFF LED ON LED OFF LED ON LED OFF LED ON LED OFF 74ms 223ms 74ms 223ms 74ms 223ms 74ms 223ms 74ms 1.4s SEQUENCE REPEATS Figure 5. LED Code Timing for Detection Fault Due to High- or Low-Discovery Signature Resistance ______________________________________________________________________________________ 21 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C The MAX5971B also contains an internal square wave, PWM signal generator. The PWM runs at a typical frequency of 25kHz with a default duty cycle of 6.25%. The duty cycle is programmable from 6.25% up to 25% through the PWM_TH[1:0] bits (R24h[5:4], Tables 33 and 34). PWMEN is used to enable or disable the PWM. PWMEN is internally pulled up to the digital supply, and can be left unconnected to enable the internal PWM. When enabled, the LED pulses are driven by the PWM to reduce the power dissipation and increase the system efficiency. Force PWMEN low to disable the internal PWM; LED is then driven directly. If the MAX5971B die temperature reaches +150NC (typ), an overtemperature fault is generated and the device shuts down. The die temperature must cool down below 130NC (typ) to remove the overtemperature fault condition. After a thermal shutdown condition clears, the device is reset. The R1Eh and R1Fh registers control the watchdog operation. The watchdog function, when enabled, allows the MAX5971B to automatically take over control and securely shut down the power to the port in case of software/firmware crashes. See the Register Map and Description section for register configuration and settings (Tables 29, 30, and 31). The MAX5971B is programmable to one of four unique slave addresses. To program the device address, connect AD0 to VEE, SCL, SDA or to an external VCC supply referenced to VEE. This external VCC (at AD0) MAX5971B must exceed the digital input logic-high threshold (VCC > 2.4V, see Table 5), but should not exceed 5.5V. An external regulated 3.3V or 5V supply is recommended for VCC. The MAX5971B operates as a slave that sends and receives data through an IC-compatible 2-wire interface. The interface uses a serial-data line (SDA) and a serial-clock line (SCL) to achieve communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX5971B, and generates the SCL clock that synchronizes the data transfer (see Figure 6). The MAX5971B SDA line operates as both an input and an output. A pullup resistor, typically 4.7kI, may be required on SDA. The MAX5971B SCL line operates only as an input. A pullup resistor may be required (typically 4.7kI) on SCL if there are multiple masters, or if the master in a single-master system has an open-drain SCL output. I2C-Compatible Serial Interface Thermal Shutdown Watchdog Table 5. Programmable Device Address Settings AD0 VEE VCC SCL SDA DEVICE ADDRESS A7 0 0 0 0 A6 1 1 1 1 A5 0 0 0 0 A4 0 0 0 0 A3 0 0 0 0 A2 0 0 1 1 A1 0 1 0 1 Device Address (AD0) SDA tSU,STA tHD,DAT tHD,STA tSU,STO tBUF tSU,DAT tLOW SCL tHD,STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION Figure 6. 2-Wire Serial Interface Timing Details 22 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Serial-Addressing Each transmission consists of a START condition sent by a master, followed by the MAX5971B 7-bit slave address plus R/W bit, a register address byte, one or more data bytes, and finally a STOP condition. START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master finishes communicating with the slave, the master issues a STOP condition by transitioning SDA from low to high while SCL is high. The stop condition frees the bus for another transmission (see Figure 7). Bit Transfer Each clock pulse transfers one data bit (Figure 8). The data on SDA must remain stable while SCL is high. Acknowledge The acknowledge bit is a clocked 9th bit (Figure 9), which the recipient uses to handshake receipt of each byte of data. Thus each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the clock pulse. When the master transmits to the MAX5971B, the device generates the acknowledge bit. When the MAX5971B transmits to the master, the master generates the acknowledge bit. MAX5971B SDA SCL S START P STOP Figure 7. START and STOP Conditions SDA SCL DATA LINE STABLE; CHANGE OF DATA VALID DATA ALLOWED Figure 8. Bit Transfer START CONDITION SCL SDA BY TRANSMITTER S SDA BY RECEIVER 1 2 CLOCK PULSE FOR ACKNOWLEDGEMENT 8 9 Figure 9. Acknowledge ______________________________________________________________________________________ 23 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Slave Address The MAX5971B has a 7-bit long slave address (Figure 10). The bit following the 7-bit slave address (bit 8) is the R/W bit, which is low for a write command and high for a read command. The upper five bits of the slave address cannot be changed and are always [01000]. Using the AD0 input, the lowest two bits can be programmed to assign the MAX5971B one of 4 unique slave addresses (see Table 5). The MAX5971B monitors the bus continuously, waiting for a START condition followed by the MAX5971B's slave address. When a MAX5971B recognizes its slave address, it acknowledges and is then ready for continued communication. Global Addressing and Alert Response Protocol The global address call is used in writing mode to write the same register to multiple devices (address 0x60). In read mode (address 0x61), the global address call is used as the alert response address. When responding to a global call, the MAX5971B puts out on the data line its own address whenever its interrupt is active (as does every other device connected to the SDA line that has an active interrupt). After every bit transmitted, the MAX5971B checks that the data line effectively corresponds to the MAX5971B data it is delivering. If it is not, it then backs off and frees the data line. This litigation protocol always allows the part with the lowest address to complete the transmission. The microcontroller then responds to that interrupt and takes proper action. The MAX5971B does not reset its own interrupt at the end of the alert response protocol. The microcontroller has to do it by clearing the event register through their CoR addresses or activating the CLR_INT pushbutton (R1Ah[7]). General Call In compliance with the I2C specification, the MAX5971B responds to the general call through the global address 30h. Message Format for Writing the MAX5971B A write to the MAX5971B comprises the device slave address transmission with the R/W bit set to 0, followed by at least one byte of information. The first byte of information is the command byte (Figure 11). The command byte determines which register of the MAX5971B is written to by the next byte, if received. If the MAX5971B detects a STOP condition after receiving the command byte but before receiving any data, then the MAX5971B takes no further action beyond storing the command byte. MSB SDA SCL 0 1 0 0 0 X LSB X R/W ACK Figure 10. Slave Address CONTROL BYTE STORED ON STOP CONDITION ACKNOWLEDGE FROM THE MAX5971B S SLAVE ADDRESS R/W 0 ACK CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 CONTROL BYTE ACKNOWLEDGE FROM THE MAX5971B ACK P Figure 11. Write Format: Control Byte Received 24 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Any bytes received after the command byte are data bytes. The first data byte goes into the internal register of the MAX5971B selected by the command byte (Figure 12). The control byte address then autoincrements, if possible (see Table 6), and then waits for the next data byte or a STOP condition. If multiple data bytes are transmitted before a STOP condition is detected, these bytes are stored in subsequent MAX5971B internal registers as the control byte address autoincrements (Figure 13). If the control byte address can no longer increment, any subsequent data sent continues to write to that address. Message Format for Reading A read command for the MAX5971B comprises the device slave address transmission with the R/W bit set to 1, followed by at least one byte of information. As with a write command, the first byte of information is the command byte. The MAX5971B then reads using the internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. This pointer autoincrements after reading each data byte using the same rules as for a write, though the master now sends the acknowledge bit after each read receipt (Figure 14). When performing read-after-write verification, remember to reset the command byte's address because the stored control byte address autoincrements after the write. ACKNOWLEDGE FROM THE MAX5971B CONTROL BYTE STORED ON STOP CONDITION ACKNOWLEDGE FROM THE MAX5971B S SLAVE ADDRESS R/W 0 ACK CONTROL BYTE ACK DATA BYTE (1 BYTE) WORD ADDRESS AUTOINCREMENT ACK P CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 D7 D6 D5 D4 D3 D2 D1 D0 MAX5971B Figure 12. Write Format: Control and Single Data Byte Written ACKNOWLEDGE FROM THE MAX5971B CONTROL BYTE STORED ON STOP CONDITION ACKNOWLEDGE FROM THE MAX5971B S SLAVE ADDRESS R/W 0 ACK CONTROL BYTE ACK DATA BYTE (n BYTES) WORD ADDRESS AUTOINCREMENT REPEAT FOR n BYTES ACK P CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 13. Write Format: Control and n Data Bytes Written ACKNOWLEDGE FROM THE MAX5971B CONTROL BYTE STORED ON STOP CONDITION ACKNOWLEDGE FROM THE MAX5971B S SLAVE ADDRESS R/W 0 ACK CONTROL BYTE ACK DATA BYTE (n BYTES) WORD ADDRESS AUTOINCREMENT REPEAT FOR n BYTES ACK P CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 D7 D6 ACKNOWLEDGE FROM THE MASTER D5 D4 D3 D2 D1 D0 Figure 14. Read Format: Control and n Data Bytes Read ______________________________________________________________________________________ 25 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Operation with Multiple Masters When the MAX5971B operates on a 2-wire interface with multiple masters, a master reading the MAX5971B should use repeated starts between the write that sets the MAX5971B's address pointer, and the read(s) that take the data from the location(s). It is possible for master 2 to take over the bus after master 1 has set up the MAX5971B's address pointer but before master 1 has read the data. If master 2 subsequently resets the MAX5971B's address pointer, then master 1's read may be from an unexpected location. Command Address Autoincrementing Address autoincrementing allows the MAX5971B to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. The command address stored in the MAX5971B generally increments after each data byte is written or read (Table 6). The MAX5971B is designed to prevent MAX5971B overwrites on unavailable register addresses and unintentional wraparound of addresses. Register Map and Description The MAX5971B contains a bank of volatile registers that store its settings and status. The device features an I2Ccompatible, 2-wire serial interface, allowing the registers to be fully software configurable and programmable. In addition to this, several registers are also pin programmable to allow the MAX5971B to operate in auto mode and still be partially configurable even without the assistance of software. The Interrupts Registers (R00h to R01h) Interrupt Register (R00h) The interrupt register (R00h, Table 7) summarizes the event register status and is used to send an interrupt signal to the controller. On power-up or after a reset condition, interrupt (R00h) is set to a default value of 00h. INT goes low to report an interrupt event if any one of the active interrupt bits is set to 1 (active high) and it is not masked by the interrupt mask register (R01h, Table 8). INT does not go low to report an interrupt if the corresponding mask bit (R01h) is set. Writing a 1 to CLR_INT (R1Ah[7], Table 27) clears all interrupt and events registers (resets to low). INT_EN (R17h[7], Table 25) is a global interrupt enable and writing a 0 to INT_EN disables the INT output, putting it into a state of high impedance. Table 6. Autoincrement Rules COMMAND BYTE ADDRESS RANGE 0x00 to 0x37 0x37 AUTOINCREMENT BEHAVIOR Command address autoincrements after byte read or written Command address remains at 0x37 after byte written or read Table 7. Interrupt Register ADDRESS = 00h SYMBOL SUP_INT Reserved IMAX_INT CL_INT DET_INT LD_INT PG_INT PE_INT BIT NO. 7 6 5 4 3 2 1 0 TYPE R R R R R R R R DESCRIPTION Interrupt signal for supply faults. SUP_INT is the logic OR of all the active bits in the supply event register (R0Ah/R0Bh, Table 12). Reserved Interrupt signal for current-limit violations. IMAX_INT reports the status of IMAX_FLT (bit 0) in the fault event register (R06h/R07h, Table 11). Interrupt signal for completion of classification. CL_INT reports the status of CL_END (bit 4) in the detect event register (R04h/R05h, Table 10). Interrupt signal for completion of detection. DET_INT reports the status of DET_END (bit 0) in the detect event register (R04h/R05h, Table 10). Interrupt signal for load disconnection. LD_INT reports the status of LD_DISC (bit 4) in the fault event register (R06h/R07h, Table 11). Interrupt signal for PGOOD (R10h[4]) status changes. PG_INT reports the status of PG_CHG (bit 4) in the power event register (R02h/R03h, Table 9). Interrupt signal for power enable status change. PEN_INT reports the status of PWEN_CHG (bit 0) in the power event register (R02h/R03h, Table 9). 26 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Interrupt Mask Register (R01h) The interrupt mask register (R01h, Table 8) contains MASK_ bits that mask the corresponding interrupt bits in register R00h (active high). Setting MASK_ bits low individually disables the corresponding interrupt signal. When masked (set low), the corresponding bits are still set in the interrupt register (R00h) but the masking bit (R01h) suppresses the generation of an interrupt signal (INT). On power-up or a reset condition, the interrupt mask register is set to a default state of A4h. The Event Registers (R02h to R08h) Power Event Register (R02h/R03h) The power event register (R02h/R03h, Table 9) records changes in the power status of the port. On power-up or after a reset condition, the power event register is set to a default value of 00h. Any change in PGOOD (R10h[4]) sets PG_CHG to 1. Any change in PWR_EN (R10h[0]) sets PWEN_CHG to 1. PG_CHG and PWEN_CHG trigger on the edges of PGOOD and PWR_EN and do not depend on the actual logic status of the bits. The power event register has two addresses. When read through the R02h address, the content of the register is left unchanged. When read through the CoR R03h address, the register content is reset to the default state. MAX5971B Table 8. Interrupt Mask Register ADDRESS = 01h SYMBOL MASK7 Reserved MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 BIT NO. 7 6 5 4 3 2 1 0 TYPE R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Interrupt mask bit 7. A logic-high enables the SUP_INT interrupts. A logic-low disables the SUP_FLT interrupts. Reserved Interrupt mask bit 5. A logic-high enables the IMAX_INT interrupts. A logic-low disables the IMAX_FLT interrupts. Interrupt mask bit 4. A logic-high enables the CL_INT interrupts. A logic-low disables the CL_END interrupts. Interrupt mask bit 3. A logic-high enables the DET_INT interrupts. A logic-low disables the DET_END interrupts. Interrupt mask bit 2. A logic-high enables the LD_INT interrupts. A logic-low disables the LD_DISC interrupts. Interrupt mask bit 1. A logic-high enables the PG_INT interrupts. A logic-low disables the PG_INT interrupts. Interrupt mask bit 0. A logic-high enables the PE_INT interrupts. A logic-low disables the PE_INT interrupts. Table 9. Power Event Register ADDRESS = SYMBOL Reserved Reserved Reserved PG_CHG Reserved Reserved Reserved PWEN_CHG BIT NO. 7 6 5 4 3 2 1 0 02h TYPE -- -- -- R -- -- -- R 03h R/W -- -- -- CoR -- -- -- CoR Reserved Reserved Reserved PGOOD change event for the port Reserved Reserved Reserved Power enable change event for the port 27 DESCRIPTION ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Detect Event Register (R04h/R05h) The detect event register (R04h/R05h, Table 10) records detection/classification events for the port. On power-up or after a reset condition, the detect event register is set to a default value of 00h. DET_END and CL_END are set high whenever detection/classification is completed. As with the other event registers, the detect event register has two addresses. When read through the R04h address, the content of the register is left unchanged. When read through the CoR R05h address, the register content is reset to the default state. Fault Event Register (R06h/R07h) The fault event register (R06h/R07h, Table 11) records load removal and overcurrent events for the port. On power-up or after a reset condition, the fault event register is set to MAX5971B a default value of 00h. LD_DISC is set to 1 whenever the port shuts down due to detection of load removal. IMAX_FLT is set to 1 when the port shuts down due to an extended overcurrent event after a successful startup. As with the other events registers, the fault event register has two addresses. When read through the R06h address, the content of the register is left unchanged. When read through the CoR R07h address, the register content is reset to the default state. Reserved Registers (R08h/R09h) Registers R08h/R09h are at this time reserved. Writing to this register has no effect (the address autoincrement still updates) and any attempt to read this register returns all zeros. Table 10. Detect Event Register ADDRESS = SYMBOL Reserved Reserved Reserved CL_END Reserved Reserved Reserved DET_END BIT NO. 7 6 5 4 3 2 1 0 04h TYPE -- -- -- R -- -- -- R 05h R/W -- -- -- CoR -- -- -- CoR Reserved Reserved Reserved Classification completed on the port Reserved Reserved Reserved Detection completed on the port DESCRIPTION Table 11. Fault Event Register ADDRESS = SYMBOL Reserved Reserved Reserved LD_DISC Reserved Reserved Reserved IMAX_FLT BIT NO. 7 6 5 4 3 2 1 0 06h TYPE -- -- -- R -- -- -- R 07h TYPE -- -- -- CoR -- -- -- CoR Reserved Reserved Reserved Disconnect on the port Reserved Reserved Reserved Overcurrent on the port DESCRIPTION 28 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Supply Event Register (R0Ah/R0Bh) The MAX5971B continuously monitors the power supplies and sets the appropriate bits in the supply event register (R0Ah/R0Bh, Table 12). On power-up or after a reset condition, the supply event register is set to a default value of 00h. VEE_OV is set to 1 whenever VEE exceeds its overvoltage threshold. VEE_UV is set to 1 whenever VEE falls below its undervoltage threshold. A thermal shutdown circuit monitors the temperature of the die and resets the MAX5971B if the temperature exceeds +150NC. TSD is set to 1 after the MAX5971B returns to normal operation. When VEE is below its UVLO threshold, the MAX5971B is in reset mode and securely holds the port off. When VEE rises above its UVLO threshold, the device comes out of reset and the VEE_UVLO bit in the supply event register is set to 1. As with any of the other event registers, the supply event register has two addresses. When read through the R0Ah address, the content of the register is left unchanged. When read through the CoR R0Bh address, the register content is reset to the default state. MAX5971B The Status Registers (R0Ch to R11h) Port Status Register (R0Ch) The port status register (R0Ch, Table 13) records the results of the port detection and classification at the end of each phase in three encoded bits. On power-up or after a reset condition, the port status register is set to a default value of 00h. Tables 14 and 15 show the detection and classification result decoding charts, respectively. For CLC_EN = 0 (R23h[5]), the detection result is shown in Table 13. When CLC_EN = 1, the MAX5971B allows valid detection of high capacitive loads of up to 47FF, typ. As a protection, when POFF_CL (R12h[3], Table 18) is set to 1, the MAX5971B prohibits turning on power to the port that returns a status 111 after classification. Table 12. Supply Event Register ADDRESS = SYMBOL TSD Reserved Reserved VEE_UVLO VEE_OV VEE_UV Reserved Reserved BIT NO. 7 6 5 4 3 2 1 0 0Ah TYPE R -- -- R R R -- -- 0Bh TYPE CoR -- -- CoR CoR CoR -- -- Overtemperature shutdown Reserved Reserved VEE undervoltage lockout condition VEE overvoltage condition VEE undervoltage condition Reserved Reserved DESCRIPTION Table 13. Port Status Register ADDRESS = 0Ch SYMBOL Reserved CLASS Reserved DET_ST BIT NO. 7 6 5 4 3 2 1 0 TYPE -- R R R -- R R R Reserved CLASS[2] CLASS[1] CLASS[0] Reserved DET[2] DET[1] DET[0] DESCRIPTION ______________________________________________________________________________________ 29 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Table 14. Detection Result Decoding Chart DET_ST[2:0] (ADDRESS = 0Ch) 000 001 010 011 100 101 110 111 DETECTED None DCP HIGH CAP RLOW DET_OK RHIGH OPEN DCN DESCRIPTION Detection status unknown (default) Positive DC supply connected at the port (VAGND - VOUT_ < 1V) High capacitance at the port (> 8.5FF, typ) Low resistance at the port (RDET < 15kI) Detection pass (15kI > RDET > 33kI) High resistance at the port (RDET > 33kI) Open port (IDET < 20FA) Negative DC bias on the port (VOUT - VEE < 2V) Table 15. Classification Result Decoding Chart CLASS[2:0] (ADDRESS = 0Ch) 000 001 010 011 100 101 110 111 CLASS RESULT Unknown 1 2 3 4 5 0 Class FAIL Table 16. Power Status Register ADDRESS = 10h SYMBOL Reserved Reserved Reserved PGOOD Reserved Reserved Reserved PWR_EN BIT NO. 7 6 5 4 3 2 1 0 TYPE -- -- -- R -- -- -- R Reserved Reserved Reserved Power-good condition on the port Reserved Reserved Reserved Power is enabled on the port DESCRIPTION Reserved Registers (R0Dh to R0Fh) Registers R0Dh to R0Fh are unconnected; writing to them has no effect (address autoincrement still functions) and a read always returns logical zeros. Power Status Register (R10h) The power status register (R10h, Table 16) records the current status of port power. On power-up or after a reset condition, the port is initially unpowered and the power 30 status register is set to its default value of 00h. PGOOD (R10h[4]) is set to 1 at the end of the power-up startup period. PGOOD is reset to 0 whenever a fault condition occurs. PWR_EN (R10h[0]) is set to 1 when the port power is turned on. PWR_EN resets to 0 as soon as the port turns off. Any transition of PGOOD and PWR_EN bits set the corresponding bit in the power event register (R02h/R03h, Table 9). _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Pin Status Register (R11h) The pin status register (R11h, Table 17) records the state of the OSC, LEGACY, and MIDSPAN pins. The states of OSC, LEGACY, and MIDSPAN are latched into the corresponding bits after a power-up or reset condition clears. Therefore, the default state of the pin status register depends on those inputs (0000 to xxx1). Changes to those inputs during normal operation are ignored and do not change the register contents. Configuration Registers (R12h to R17h) Mode Register (R12h) The mode register (R12h, Table 18) contains two bits that set the MAX5971B mode of operation. Table 19 details how to set the mode of operation for the device. On a power-up or after a reset condition, the mode register is set to a default value of 03h. Use software to program the mode of operation. The software port specific reset using RESET_P (R1Ah[0], Table 27) does not affect the mode register. Setting POFF_CL (R12h[3]) to 1 prevents power-up after a classification failure. MAX5971B Table 17. Pin Status Register To ADDRESS = 11h SYMBOL Reserved Reserved Reserved Reserved OSC LEGACY MIDSPAN Reserved BIT NO. 7 6 5 4 3 2 1 0 TYPE -- -- -- -- R R R -- Reserved Reserved Reserved Reserved OSC input latched-in status LEGACY input latched-in status MIDSPAN input latched-in status Reserved DESCRIPTION Table 18. Mode Register ADDRESS = 12h SYMBOL Reserved Reserved Reserved Reserved POFF_CL Reserved P_M BIT NO. 7 6 5 4 3 2 1 0 TYPE -- -- -- -- R/W -- R/W R/W Reserved Reserved Reserved Reserved A logic-high prevents power-up after a classification failure (I > 50mA, valid only in auto mode) Reserved MODE[1] for the port MODE[0] for the port DESCRIPTION Table 19. Port Operating Mode Status MODE 00 01 10 11 DESCRIPTION Shutdown Manual Semiautomatic Auto (Automatic) ______________________________________________________________________________________ 31 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Disconnect Enable Register (R13h) The disconnect enable register (R13h, Table 20) is used to enable AC and DC load-disconnect detection. On power-up or after a reset condition, this register is reset to a default value of 000x to 000x, where the status latched in from the OSC input determines if AC or DC disconnect is set (see the AC/DC Disconnect Monitoring sections for details). Setting DCD_EN (R13h[0]) to 1 enables the DC load-disconnect detection feature. Setting ACD_EN (R13h[4]) to 1 enables the AC load-disconnect feature. If enabled, the load-disconnect detection starts during power mode and after startup when the PGOOD bit (R10h[4], Table 16) goes high. Detection and Classification Enable Register (R14h) The detection and classification enable register (R14h, Table 21) is used to enable detection and classification routines for the port. On a power-up or after a reset condition, this register is set to a default value of FFh (which corresponds to the default auto mode). Setting DET_EN (R14h[0]) and CLASS_EN (R14h[4]) to 1 enables load detection and classification, respectively. Detection always has priority over classification. For classification without detection, set the DET_EN bit to 0 and the CLASS_EN bit to 1. When entering auto mode, R14h defaults to FFh. When entering semi or manual modes, R14h defaults to 00h. In manual mode, R14h works like a pushbutton. Set the bits high to launch the corresponding routine. The bit then clears after one complete detection or classification cycle finishes. MAX5971B Table 20. Disconnect Enable Register ADDRESS = 13h SYMBOL Reserved Reserved Reserved ACD_EN Reserved Reserved Reserved DCD_EN BIT NO. 7 6 5 4 3 2 1 0 TYPE -- -- -- R/W -- -- -- R/W Reserved Reserved Reserved Enable AC disconnect detection on the port Reserved Reserved Reserved Enable DC disconnect detection on the port DESCRIPTION Table 21. Detection And Classification Enable Register ADDRESS = 14h SYMBOL Reserved Reserved Reserved CLASS_EN Reserved Reserved Reserved DET_EN BIT NO. 7 6 5 4 3 2 1 0 TYPE -- -- -- R/W -- -- -- R/W Reserved Reserved Reserved Enable classification on the port Reserved Reserved Reserved Enable detection on the port DESCRIPTION 32 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Backoff Enable Register (R15h) The backoff enable register (R15h, Table 22) is used to control cadence timing (midspan) for the port. On a power-up or after a reset condition, this register is set to a default value of 0000 to 000x where x is the latched in value of the MIDSPAN input. Setting BCKOFF (R15h[0]) to 1 enables cadence timing where the port backs off and waits 2.2s (typ) after each failed load detection. The IEEE 802.3af/at standard requires a PSE that delivers power through the spare pairs (midspan) to have cadence timing (see the Midspan Mode section for details). Timing Register (R16h) The timing register (R16h, Table 23) is used to program the restart, startup, overcurrent, and load-disconnect timers for the port. On a power-up or after a reset condition, the timing register is set to a default value of 00h. To program the timer values, set the bits in R16h to scale the tDISC, tFAULT, tSTART, and tRESTART to a multiple of their nominal value specified in the Electrical Characteristics table. TDISC[1:0] (R16h[1:0]) is used to program the loaddisconnect detection time (tDISC). The device turns off power to the port if it fails to provide a minimum power maintenance signal for longer than the programmed load-disconnect detection time. TFAULT[1:0] (R16h[3:2]) programs the overcurrent fault time (tFAULT). Fault time is the time allowed for the port to remain in an overcurrent state both during startup and normal operation (see the Overcurrent Protection section). TSTART[1:0] (R16h[5:4]) programs the startup timer (tSTART). Startup time is the time the port is allowed to be in current limit during startup. RSTR[1:0] programs the discharge rate of the TFAULT counter (tRESTART) and effectively sets the time the port remains off after an overcurrent fault. When the MAX5971B shuts down a port due to an extended overcurrent condition (either during startup or normal operation), if RSTR_EN (R17h[6]) is set high, the part does not allow the port to power back on before the restart timer (tRESTART) returns to zero. This effectively sets a minimum duty cycle that protects the external MOSFET from overheating during a prolonged output overcurrent condition. MAX5971B Table 22. Backoff Enable Register ADDRESS = 15h SYMBOL Reserved Reserved Reserved Reserved Reserved Reserved Reserved BCKOFF BIT NO. 7 6 5 4 3 2 1 0 TYPE -- -- -- -- -- -- -- R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Enable cadence timing on the port DESCRIPTION Table 23. Timing Register ADDRESS = 16h SYMBOL RSTR[1] RSTR[0] TSTART[1] TSTART[0] TFAULT[1] TFAULT[0] TDISC[1] TDISC[0] BIT NO. 7 6 5 4 3 2 1 0 TYPE R/W R/W R/W R/W R/W R/W R/W R/W Restart timer programming bit 1 Restart timer programming bit 0 Startup timer programming bit 1 Startup timer programming bit 0 Overcurrent timer programming bit 1 Overcurrent timer programming bit 0 Load-disconnect timer programming bit 1 Load-disconnect timer programming bit 0 33 DESCRIPTION ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Table 24. Timer Values for Timing Register BIT [1:0] (ADDRESS = 16h) 00 01 10 11 tRESTART 16 x tFAULT 32 x tFAULT 64 x tFAULT 0 x tFAULT tDISC tDISC nominal (350ms, typ) 1/4 x tDISC nominal 1/2 x tDISC nominal 2 x tDISC nominal tSTART tSTART nominal (60ms, typ) 1/2 x tSTART nominal 2 x tSTART nominal 4 x tSTART nominal tFAULT tFAULT nominal (60ms, typ) 1/2 x tFAULT nominal 2 x tFAULT nominal 4 x tFAULT nominal Table 25. Miscellaneous Configurations 1 Register ADDRESS = 17h SYMBOL INT_EN RSTR_EN Reserved Reserved Reserved CL_DISC OUT_ISO HP_TIME BIT NO. 7 6 5 4 3 2 1 0 TYPE R/W R/W -- -- -- R/W R/W R/W A logic-high enables INT functionality A logic-high enables the autorestart protection timer (set by the RSRT[1:0] bits) Reserved Reserved Reserved A logic-high enables current-limit programming regardless of the classification result through the ICUT[2:0] register A logic-high forces DET to a high-impedance state. Does not interfere with other circuit operation. A logic-high enables the higher current limit for Type 2 PDs during startup. DESCRIPTION Miscellaneous Configuration 1 Register (R17h) The miscellaneous configuration 1 register (R17h, Table 25) is used for several functions that do not cleanly fit within one of the other configuration categories. On a power-up or after a reset condition, this register is set to a default value of 0xC0h. Therefore, by default, INT_EN (R17h[7]) and RSTR_EN (R17h[6]) are set to 1, enabling both INT functionality and the autorestart protection timer. Setting CL_DISC (R17h[2] to 1 enables current-limit programming regardless of the classification result through the ICUT[2:0] register (R2Ah). Setting OUT_ISO (R17h[1]) to 1, forces DET to a high-impedance state. Setting HP_TIME high enables the higher current limits needed for type 2 PDs even during startup (during the time after port power-up but before tSTART has expired). Pushbutton Registers (R18h to R1Ah) Reserved Register (R18h) Register R18h is at this time reserved. Writing to this register has no effect (the address autoincrement still updates) and any attempt to read this register returns all zeros. Power Enable Pushbutton Register (R19h) The power enable pushbutton register (R19h, Table 26) is used to manually power the port on or off. On a power-up or after a reset condition, this register is set to a default value of 0x00h. Setting PWR_ON (R19h[0]) to 1 turns on power to the port. PWR_ON commands are ignored when the port is already powered and during shutdown. During detection or classification, if a 1 is written to PWR_ON, the MAX5971B gracefully terminates the detection/classification routine and turns on power to the port. The MAX5971B also ignores PWR_ON commands when operating in auto mode. Setting PWR_OFF (R19h[4]) to 1 turns off power to the port. PWR_OFF commands are ignored when the port is already off and during shutdown. After the appropriate command is executed (port power on or off), the PWR_ON/PWR_OFF bit resets back to 0. Global Pushbutton Register (R1Ah) The global pushbutton register (R1Ah, Table 27) is used to manually clear interrupts and to initiate global and port resets. On a power-up or after a reset condition, this register is set to a default value of 0x00h. Writing a 1 to 34 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Table 26. Power Enable Pushbutton Register ADDRESS = 19h SYMBOL Reserved Reserved Reserved PWR_OFF Reserved Reserved Reserved PWR_ON BIT NO. 7 6 5 4 3 2 1 0 TYPE -- -- -- R/W -- -- -- R/W Reserved Reserved Reserved A logic-high powers off the port Reserved Reserved Reserved A logic-high powers on the port DESCRIPTION MAX5971B Table 27. Global Pushbutton Register ADDRESS = 1Ah SYMBOL CLR_INT Reserved Reserved RESET_IC Reserved Reserved Reserved RESET_P BIT NO. 7 6 5 4 3 2 1 0 TYPE R/W -- -- R/W -- -- -- R/W A logic-high clears all interrupts Reserved Reserved A logic-high resets the entire device Reserved Reserved Reserved A logic-high resets the port DESCRIPTION Table 28. ID Register ADDRESS = 1Bh SYMBOL BIT NO. 7 6 ID_CODE 5 4 3 2 REV 1 0 TYPE R R R R R R R R ID_CODE[4] ID_CODE[3] ID_CODE[2] ID_CODE[1] ID_CODE[0] REV [2] REV [1] REV [0] DESCRIPTION CLR_INT (R1Ah[7]) clears all the event registers and the corresponding interrupt bits in the interrupt register (R00h, Table 7). Writing a 1 to RESET_IC (R1Ah[4]) causes a global software reset, after which all registers are set back to default values (after reset condition clears). Writing a 1 to RESET_P (R1Ah[0]) turns off power to the port and resets only the port status and event registers. After the appropriate command is executed, the bits in the global pushbutton register all reset to 0. General Registers (R1Bh to R1Fh) ID Register (R1Bh) The ID register (R1Bh, Table 28) keeps track of the device ID number and revision. The MAX5971B's ID code is stored in ID_CODE[4:0] (R1Bh[7:3]) and is 10000. Contact the factory for the value of the revision code stored in REV[2:0] (R1Bh[2:0]) that corresponds to the device lot number. ______________________________________________________________________________________ 35 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C SMODE Register (R1Ch) The SMODE register (R1Ch, Table 29) contains the port hardware control flag. On a power-up or after a reset condition, this register is set to a default value of 0x00h. Enable the SMODE function by setting EN_WHDOG (R1Fh[7], Table 31) to 1. The SMODE bit goes high when the watchdog counter reaches zero and the port switches over to hardware-controlled mode. SMODE also goes high each and every time the software tries to power on a port, but is denied since the port is in hardware mode. Reserved Register (R1Dh) Register R1Dh is at this time reserved. Writing to this register is not recommended as it is internally connected. If the software needs to do a large batch write command using the address autoincrement function, write a code of 0x00h to this register to safely autoincrement past it, and then continue the write commands as normal. Watchdog Register (R1Eh) The watchdog register (R1Eh, Table 30) is used to configure the watchdog timer duration. On a power-up or after a reset condition, this register is set to a default MAX5971B value of 0x00h. Set EN_WHDOG (R1Fh[7], Table 31) to 1 to enable the watchdog function. When activated, the watchdog timer counter, WDTIME[7:0] (R1Eh[7:0]), continuously decrements toward zero once every 164ms. Use software to initially set WDTIME[7:0] to a nonzero value. Then, once the watchdog function is active the software must continue to set the watchdog register to a nonzero value before the decrementing value stored in the register reaches zero. Once the counter reaches zero (also called watchdog expiry), the MAX5971B enters hardware-controlled mode and the port shifts to an operating mode set by the HWMODE bit (R1Fh[0], Table 31). In this way, the hardware can gracefully manage the port power during a software crash, system crash or switchover condition. While in hardware-controlled mode, the MAX5971B ignores all requests to turn the power on and the flag SMODE indicates that the hardware has taken control of the MAX5971B operation. In addition, the software is not allowed to change the mode of operation in hardwarecontrolled mode. Table 29. SMODE Register ADDRESS = 1Ch SYMBOL Reserved Reserved Reserved Reserved Reserved Reserved Reserved SMODE BIT NO. 7 6 5 4 3 2 1 0 TYPE -- -- -- -- -- -- -- CoR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Port hardware control flag DESCRIPTION Table 30. Watchdog Register ADDRESS = 1Eh SYMBOL BIT NO. 7 6 5 WDTIME 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W WDTIME[7] WDTIME[6] WDTIME[5] WDTIME[4] WDTIME[3] WDTIME[2] WDTIME[1] WDTIME[0] DESCRIPTION 36 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Switch Mode Register (R1Fh) The switch mode register (R1Fh, Table 31) is used to enable the watchdog timer, interrupt, and watchdog expiry port state. On a power-up or after a reset condition, this register is set to a default value of 0x00h. Set EN_WHDOG (R1Fh[7], Table 31) to 1 to enable the watchdog function. When the watchdog counter reaches zero, the hardware-controlled mode activates and sets the port to the operating mode determined by the HWMODE bit (R1Fh[0]). A 0 in HWMODE places the port into shutdown mode by setting the P_M[1:0] bits (R12h[1:0]) to 00. A 1 in HWMODE places the port into auto mode by setting the P_M[1:0] bits to 11. If WD_INT_EN is set to 1, an interrupt is sent if the SMODE bit is set. the software needs to do a large batch write command using the address autoincrement function, write a code of 0x00h to these registers to safely autoincrement past them, and then continue the write commands as normal. Program Register (R23h) The program register (R23h, Table 32) is used to enable large capacitor detection, skipping detection in AUTO mode and for setting the AC disconnect threshold. On a power-up or after a reset condition, this register is set to a default value of 00x0 to 0100. CLC_EN (R23h[5]) enables the large capacitor detection feature. The CLC_EN register can be programmed directly by the software or by using the LEGACY input (see the High Capacitance Detection section). When CLC_EN = 1 the device can recognize a capacitor load up to 47FF, typ. If the CLC_EN = 0, the MAX5971B performs normal detection. DET_BY (R23h[4]) is used to allow the port to power when skipping the detection routine in auto mode. When DET_BY is set to 0 (default), the port cannot power up if the port detection sequence was bypassed in auto MAX5971B Special and Reserved Registers (R20h to R2Fh) Reserved Registers (R20h to R22h, R25h to R28h, and R2Bh to R2Fh) These registers are reserved. Writing to these registers is not recommended as they are internally connected. If Table 31. Switch Mode Register ADDRESS = 1Fh SYMBOL EN_WHDOG WD_INT_EN Reserved Reserved Reserved Reserved Reserved HWMODE BIT NO. 7 6 5 4 3 2 1 0 R/W R/W R/W -- -- -- -- -- R/W Enables interrupt on SMODE bit Reserved Reserved Reserved Reserved Reserved Port switches to auto mode if logic-high and to shutdown mode if logic-low when watchdog timer expires DESCRIPTION A logic-high enables the watchdog function Table 32. Program Register ADDRESS = 23h SYMBOL Reserved CLC_EN DET_BY Reserved AC_TH BIT NO. 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W -- R/W R/W R/W DESCRIPTION Internally connected. For a write command, always write a zero to this bit. Large capacitor detection enable Enables skipping detection in auto mode Reserved AC_TH[2] AC_TH[1] AC_TH[0] 37 ______________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B mode. When DET_BY is set to 1 however, the MAX5971B can power the port without doing the detection routine. AC_TH[2:0] (R23h[2:0]) allows direct programming of the AC disconnect threshold. The threshold is defined as a current since the comparator verifies that the peak current pulses sensed at the DET input exceeds a preset threshold. The current threshold is defined as follows: IAC_TH = 85.28FA + 10.64FA x NAC_TH where NAC_TH is the decimal value of AC_TH[2:0]. The default NAC_TH is 4 (AC_TH[2:0] = 100) which corresponds to a default IAC_TH of ~128FA. PWM Register (R24h) The PWM register (R24h, Table 33) is used to program the PWM duty cycle. On a power-up or after a reset condition, this register is set to a default value of 0x00h. PWM_TH[1:0] (R24h[5:4]) is used to set the PWM duty cycle. The default PWM_TH[1:0] value of 00 corresponds to a 6.25% duty cycle, while the maximum PWM_TH[1:0] value of 11 corresponds to a 25% duty cycle (see Table 34). Table 33. PWM Register ADDRESS = 24h SYMBOL Reserved Reserved PWM_TH BIT NO. 7 6 5 4 3 Reserved 2 1 0 R/W -- -- R/W R/W R/W R/W R/W R/W Internally connected. For a write command, always write a zero to this bit. Reserved Reserved PWM_TH[1] PWM_TH[0] DESCRIPTION Table 34. PWM Duty-Cycle Settings PWM_TH[1:0] 00 01 10 11 DUTY CYCLE (%) 6.25 12.5 18.75 25.0 38 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Miscellaneous Configurations 2 Register (R29h) The miscellaneous configurations 2 register (R29h, Table 35) is used to enable the load stability safety check (see the PD Detection section). On a power-up or after a reset condition, this register is set to a default value of 0x00h. ICUT Register (R2Ah) The ICUT register (R2Ah, Table 36) is used to adjust the device current limit and corresponding overcurrent thresholds. On a power-up or after a reset condition, this register is set to a default value of 0x00h. The MAX5971B can automatically set the ICUT register (see Table 4) or ICUT[2:0] can be manually written to by the software (see Table 37) to manually adjust the current-limit and overcurrent thresholds. MAX5971B Table 35. Miscellaneous Configurations 2 Register ADDRESS = 29h SYMBOL Reserved Reserved Reserved LSC_EN Reserved Reserved Reserved Reserved BIT NO. 7 6 5 4 3 2 1 0 R/W -- -- -- R/W R/W R/W -- -- Reserved Reserved Reserved Enables the load stability safety check Internally connected. For a write command, always write a zero to this bit. Reserved Reserved DESCRIPTION Table 36. ICUT Register ADDRESS = 2Ah SYMBOL Reserved Reserved Reserved Reserved Reserved ICUT BIT NO. 7 6 5 4 3 2 1 0 R/W -- -- -- -- -- R/W R/W R/W Reserved Reserved Reserved Reserved Reserved ICUT[2] ICUT[1] ICUT[0] DESCRIPTION Table 37. ICUT Current-Limit Threshold Settings ICUT_[2:0] 000 001 010, 011, 100 101 110 111 TYPICAL CURRENT-LIMIT THRESHOLD (mA) 420 720 Not Used 850 900 950 TYPICAL OVERCURRENT THRESHOLD (mA) 370 634 Not Used 748 792 836 ______________________________________________________________________________________ 39 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Current Readout Registers (R30h to R37h) Port Current Registers (R30h to R31h) The port current registers (R30h to R31h, Tables 38 and 39) provide port current readout during classification and normal power mode. On a power-up or after a reset condition, these registers are both set to a default value of 0x00h. The port current readout has 9 bits of overall resolution. The MAX5971B has 8-bit registers, so the data is split between 2 consecutive registers. R30h[7:0] contains the highest 8 bits (MSB) and R31h[0] contains the lowest bit (LSB). To avoid the LSB register changing while reading the MSB, the register contents are frozen if the addressing byte points to either of the current readout registers. When the port is powered, the port output current can be calculated as: IOUT = NIPD x 2.95mA During classification, the port current is: ICLASS = NIPD x 0.0975mA where NIPD is the decimal value of the 9-bit port current readout. The ADC saturates both at full scale and at zero, resulting in poor current readout accuracy near the top and bottom codes. Reserved Registers (R32h to R37h) Registers R32h to R37h are unconnected; writing to them has no effect (address autoincrement still functions) and a read always returns logical zeros. Table 38. Port Current Register (MSB) ADDRESS = 30h SYMBOL BIT NO. 7 6 5 IPD 4 3 2 1 0 R/W R R R R R R R R IPD[8] (MSB) IPD[7] IPD[6] IPD[5] IPD[4] IPD[3] IPD[2] IPD[1] DESCRIPTION Table 39. Port Current Register (LSB) ADDRESS = 31h SYMBOL Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD BIT NO. 7 6 5 4 3 2 1 0 R/W -- -- -- -- -- -- -- R Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD[0] (LSB) DESCRIPTION 40 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Table 40. Register Summary ADDR REGISTER NAME INTERRUPTS 00h 01h Interrupt Interrupt Mask R R/W SUP_INT MASK7 Reserved Reserved IMAX_INT MASK5 CL_INT MASK4 DET_INT MASK3 LD_INT MASK2 PG_INT MASK1 PE_INT MASK0 0000 to 0000 1010 to 0100 0000 to 0000 0000 to 0000 0000 to 0000 -- 0000 to 0000 0000 to 0000 -- -- -- 0000 to 0000 0000 to xxx1 0000 to 0011 000x to 000x 0001 to 0001 0000 to 000x 0000 to 0000 1100 to 0000 R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE MAX5971B EVENTS 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh Power Event Power Event CoR Detect Event Detect Event CoR Fault Event Fault Event CoR Startup Event Startup Event CoR Supply Event Supply Event CoR R CoR R CoR R CoR R CoR R CoR Reserved Reserved Reserved Reserved TSD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PG_CHG CL_END LD_DISC Reserved VEE_UVLO Reserved Reserved Reserved Reserved VEE_OV Reserved Reserved Reserved Reserved VEE_UV Reserved PWEN_CHG Reserved Reserved Reserved Reserved DET_END IMAX_FLT Reserved Reserved STATUS 0Ch 0Dh 0Eh 0Fh 10h 11h Port Status Reserved Reserved Reserved Power Status Pin Status R -- -- -- R R Reserved Reserved Reserved Reserved Reserved Reserved CLASS[2] Reserved Reserved Reserved Reserved Reserved CLASS[1] Reserved Reserved Reserved Reserved Reserved CLASS[0] Reserved Reserved Reserved PGOOD Reserved Reserved Reserved Reserved Reserved Reserved OSC DET_ST[2] DET_ST[1] DET_ST[0] Reserved Reserved Reserved Reserved LEGACY Reserved Reserved Reserved Reserved MIDSPAN Reserved Reserved Reserved PWR_EN Reserved CONFIGURATION 12h 13h 14h 15h 16h 17h Operating Mode Disconnect Enable Det/Class Enable Backoff Enable Timing Configuration Miscellaneous Configurations 1 R/W R/W R/W R/W R/W R/W Reserved Reserved Reserved Reserved RSRT[1] INT_EN Reserved Reserved Reserved Reserved RSRT[0] RSRT_EN Reserved Reserved Reserved Reserved TSTART[1] Reserved Reserved ACD_EN CLASS_EN Reserved POFF_CL Reserved Reserved Reserved Reserved Reserved Reserved Reserved P_M[1] Reserved Reserved Reserved P_M[0] DCD_EN DET_EN BCKOFF TDISC[0] HP_TIME TSTART[0] TFAULT[1] TFAULT[0] TDISC[1] Reserved Reserved CL_DISC OUT_ISO ______________________________________________________________________________________ 41 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Table 40. Register Summary (continued) ADDR REGISTER NAME PUSHBUTTONS 18h 19h 1Ah Reserved Power Enable Global -- W W Reserved Reserved CLR_INT Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWR_OFF RESET_IC Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWR_ON RESET_P -- 0000 to 0000 0000 to 0000 1000 to 0xxx 0000 to 0000 -- 0000 to 0000 0000 to 0000 -- -- -- 00x0 to 0100 0000 to 0000 -- -- -- -- 0000-0000 0000 to 0000 -- -- -- -- -- R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE GENERAL 1Bh 1Ch 1Dh 1EH 1FH ID SMODE Reserved Watchdog Switch Mode R CoR -- R/W R/W ID_CODE[4] ID_CODE[3] ID_CODE[2] ID_CODE[1] ID_CODE[0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved REV [2] Reserved Reserved REV [1] Reserved Reserved REV [0] SMODE Reserved WDTIME[7] WDTIME[6] WDTIME[5] WDTIME[4] WDTIME[3] WDTIME[2] WDTIME[1] WDTIME[0] EN_WHDOG WD_INT_EN Reserved Reserved Reserved Reserved Reserved HWMODE SPECIAL/RESERVED 20H 21H 22H 23H 24h 25h 26h 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH Reserved Reserved Reserved Program PWM Reserved Reserved Reserved Reserved Miscellaneous Configurations 2 ICUT Reserved Reserved Reserved Reserved Reserved -- -- -- R/W R/W -- -- -- -- R/W R/W -- -- -- -- -- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CLC_EN Reserved Reserved Reserved DET_BY Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AC_TH[0] Reserved Reserved Reserved Reserved Reserved Reserved ICUT[0] Reserved Reserved Reserved Reserved Reserved AC_TH[2] AC_TH[1] Reserved Reserved Reserved Reserved Reserved Reserved ICUT[2] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ICUT[1] Reserved Reserved Reserved Reserved Reserved Reserved PWM_TH[1] PWM_TH[0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LSC_EN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 42 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Table 40. Register Summary (continued) ADDR REGISTER NAME CURRENT READOUT 30H 31H 32H 33H 34H 35H 36H 37H Port Current (MSB) Port Current (LSB) Reserved Reserved Reserved Reserved Reserved Reserved R R -- -- -- -- -- -- IPD[8] Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD[7] Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD[6] Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD[5] Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD[4] Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD[3] Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD[2] Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD[1] IPD[0] Reserved Reserved Reserved Reserved Reserved Reserved 0000 to 0000 0000 to 0000 -- -- -- -- -- -- R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE MAX5971B Applications Information Careful PCB layout is critical to achieve high efficiency and low EMI. Follow these layout guidelines for optimal performance. 1) Place the high-frequency input bypass capacitor (0.1FF ceramic capacitor from AGND to VEE) and the output bypass capacitor (0.1FF ceramic capacitor from AGND to OUTP) as close as possible to the MAX5971B. 2) Use large SMT component pads for power dissipating devices, such as the MAX5971B and the external diodes in the high-power path. Layout Procedure 3) Use short, wide traces whenever possible for highpower paths. 4) Use the MAX5971B Evaluation Kit as a design and layout reference. 5) The EP must be soldered evenly to the PCB ground plane (VEE) for proper operation and power dissipation. Use multiple vias beneath the EP for maximum heat dissipation. A 1.0mm to 1.2mm pitch is the recommended spacing for these vias and should be plated (1oz copper) with a small barrel diameter (0.30mm to 0.33mm). 1N4448 10mH SMJ58A 0.1F 100V 2.2MI PSE OUTPUT 47F 100V 0.1F 100V LED LED AGND OUT OUTP 5.1kI EN 1N4448 MAX5971B DET ILIM1 -54V 1nF VEE VEE_DIG LEGACY MIDSPAN OSC SDA SCL 1kI ILIM2 PWMEN AD0 INT -54V 1kI SERIAL INTERFACE Figure 15. Typical Operating Circuit 1 (DC Load Removal Detection, Internal PWM Enabled for LED Indication, and Class 5 Detection Enabled) ______________________________________________________________________________________ 43 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B 1N4448 10mH SMJ58A 0.1F 100V 2.2MI PSE OUTPUT 47F 100V 0.1F 100V LED LED AGND OUT OUTP EN 5.1kI 1N4448 MAX5971B DET 0.47F 100V 1nF -54V VEE VEE_DIG LEGACY 1kI ILIM1 -54V 1kI MIDSPAN OSC ILIM2 PWMEN 1kI 0.1F SDA SCL AD0 INT SERIAL INTERFACE Figure 16. Typical Operating Circuit 2 (AC Load Removal Detection, Internal PWM Enabled for LED Indication, and Class 5 Detection Enabled) 47F 100V 0.1F 100V SMJ58A 0.1F 100V 2.2MI PSE OUTPUT -54V VEE VEE_DIG EN AGND OUT OUTP 1nF LED PWMEN LEGACY MAX5971B DET ILIM1 ILIM2 1N4448 MIDSPAN OSC SDA SCL AD0 INT SERIAL INTERFACE Figure 17. Typical Operating Circuit 3 (IEEE 802.3at Compliant, Minimal Application Circuit with DC Load Removal Detection and No LED Indication) 44 _____________________________________________________________________________________ Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 28 TQFN-EP PACKAGE CODE T2855+6 OUTLINE NO. 21-0140 LAND PATTERN NO. 90-0026 MAX5971B ______________________________________________________________________________________ 45 Single-Port, 40W, IEEE 802.3af/at, PSE Controller with I2C MAX5971B Revision History REVISION NUMBER 0 REVISION DATE 6/10 Initial release DESCRIPTION PAGES CHANGED -- Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 46 (c) Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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