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| Pletronics, Inc. 19013 36 Ave. West PO Box 2607 Lynnwood, Washington 98036 U.S.A. T: 1-425-776-1880 F: 1-425-776-2760 E: ple-sales@pletronics.com www.pletronics.com th Effective January 1, 2008 The LV11xxBY and the LV11xxBW devices are discontinued. These were discontinued because the components needed to make these parts are no longer available. For the LV11xxBY Use the LV99xxDV oscillator and a 3.3V LDO. The board space required will be similar. For the LV11xxBW Use the LV77xxDW oscillator, this is a smaller footprint and superior performance Pl tronics, Inc. . 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products LV1145B LVDS Series Low Voltage Differential Signal Output with Enable/Disable 6 Pad Leadless Surface Mount Oscillator Standard Specifications Overall Frequency Stability Operating Temperature Range Operable Supply Voltage (Vcc) High Level Output Voltage Low Level Output Voltage Differential Output Voltage Offset Voltage Output Leakage Current Supply Current (Icc) Enabled Supply Current (Icc) Disabled Symmetry (DC) Rise and Fall Time (Tr & Tf) RMS Jitter Enable / Disable Pin: 1.50 MHz - 650.00 MHz Consult factory for higher frequencies 50 PPM, 25 PPM and 20 PPM over Operating Temp. Range 0 to +80C is standard, can be extended to - 40 to +85C 3.3 V 5% standard, 5.0 V 10% also available 1.43 V typical and 1.60 V maximum with output enabled (100 ohm load) See Test circuit #6 0.90 V minimum and 1.10 V typical with output enabled (100 ohm load) See TC #6 247 V minimum, 330 V typical and 454 V maximum with output enabled (100 ohm load) See TC #6 1.125 V minimum, 1.25 V typical and 1.375 V maximum with output enabled (100 ohm load) See TC #6 10 uA maximum with output disabled 50 mA max < 200 MHz, 60 mA max < 500 MHz, 70 mA max 500 MHz and above 20 mA max < 200 MHz, 30 mA max < 500 MHz, 40 mA max 500 MHz and above 45/55% measured at 0C <= Ta <= 70C, 40/60% measured at Ta < 0C and Ta > 70C 1.0 nS max at 20% to 80% output swing (100 ohm load) See Test circuit #6 and Waveform #2 1.0 pS max at12 kHz to 20 MHz from the output The Enable / Disable pin has an internal pull up and if the pin is not connected the oscilaltor is enabled. Pletronics strongly recommends connecting the Enable / Disable pin to Vcc, if the oscillator is to be enabled at all times. In the disable condition, the output becomes a high impedance. High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Output Enable Time Output Disable Time 0.7 Vcc minimum at Enable / Disable Pin 0.3 Vcc maximum at Enable / Disable Pin -20 uA maximum at Enable / Disable Pin = 0.7 Vcc -200 uA maximum at Enable / Disable Pin = 0 V 200 nS maximum 200 nS maximum Part Numbering Guide Portions of the part number that appear after the frequency may not be marked on part (C of C provided) Packaging Tube or 24mm tape 16mm pitch LV11 45 B V - 70.0M - XXX (Internal Code or blank) Model LV11 = E/D Pin 2 LV33 = E/D Pin 1 & 2 LV37 = E/D Pin 1 Frequency Stability 45 = 50 PPM 44 = 25 PPM 20 = 20 PPM Frequency in MHz Special Specifications (choose all that apply) E: Extended Operating Temp Range (-40 to +85C) V: Supply Voltage of 3.3 volts 5% Y: Supply Voltage of 5.0 volts 10%, Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned. Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load Jun 2004 Pl tronics, Inc. (425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com 5 PECL, LVDS, OCXO Page 1 - 7 Pl tronics, Inc. . 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products LV1145B LVDS Series Mechanical: inches (mm) not to scale Solder Pads Due to part size and factory abilities, part marking may vary from lot to lot and may contain our part number or an internal code. 0.200 (5.08) 0.400 (10.16) MAX 6 4 5 6 3 2 1 1 2 3 0.560 (14.23) MAX 0.125 (3.17) MAX 0.200 (5.08) 0.055 (1.4) 0 .145 (3.68) LV1145B PIN 1 2 3 4 5 6 SIGNAL N.C. E/D GND VoD+ VoDVcc LV3345B PIN 1 2 3 4 5 6 SIGNAL E/D E/D GND VoD+ VoDVcc LV3745B PIN 1 2 3 4 5 6 SIGNAL E/D N.C. GND VoD+ VoDVcc 1.50 - 650.0 MHz 120.0 - 650.0 MHz (5.0 Vcc - May not be available) 180.0 - 650.0 MHz (3.3 Vcc) See page 6 for Layout Guidelines Jun 2004 5A Pl tronics, Inc. (425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com 0.118 0.228 (5.8) (3.0) 5 4 Pl tronics, Inc. . 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products PECL and LVDS Layout Guidelines SUGGESTED PCB LAYOUTS Solder Pad Layout which accommodates all PECL surface mount devices 0.200 (5.08) 0 .185 (4.7) 0 .087 (2.2) 'B Pkg' 5 x7 TOP SIDE BYPASS BOTTOM SIDE BYPASS 0.055 0.100 (1.4) (2.54) The output line should be designed with proper characteristic impedance. Pletronics recommends laying out for the larger 'B package' with pads long enough to accept the smaller 5 x 7mm device. This permits the best option for alternate sources of device. Pletronics also recommends connecting Pin 1 and Pin 2 together on the models with Q & QN OUT on pins 4 & 5. This allows having E/D on either pin 1 or pin 2. MULTI LAYER BYPASS For Optimum Jitter Performance, Pletronics recommends: A ground plane under the device with any other signals below the ground plane Minimize other RF signals near device No large transient signals (both current and voltage) should be routed under the device Do not layout near a large magnetic field such as a high frequency switching power supply Do not place near piezoelectric buzzers or mechancial fans Reflow Cycle for lead free processing 250 Temperature C 200 150 100 215C 10C 50 Seconds 175C 10C 120 to 160 Seconds 260C max 10 Seconds max T Rise= 4 Degree/second max Mar 2004 Pl tronics, Inc. (425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com 6 PECL, LVDS, OCXO Page 1 - 7 Pl tronics, Inc. . 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products PECL and LVDS Layout Guidelines Continued PECL Terminations: Suggested Terminations for 50 ohm impedance matched termination Vcc Vcc R1 Vcc Out Oscillator GND Vcc Out Oscillator GND Thevenin Equivalent Termination Vcc 5.0 V 3.3 V 2.5 V R1 82 ohm 130 ohm 249 ohm R2 130 ohm 82 ohm 61.9 ohm 50 ohm Vcc - 2.00 V R2 Simple termination for NON impedance matched termination Vcc Vcc Out Oscillator GND R load Vcc 5.0 V 3.3 V 2.5 V R load 274 ohm 147 ohm 86.6 ohm LVDS Terminations: Vcc Vcc Q Out Oscillator GND QN Out 100 ohm Design PCB traces for 50 ohm characteristic impedance Mixed System Power Supply: PECL ECL LVDS To use multiple supply voltages requires level translation. Direct circuit connection is not valid. Mixed supply voltages are allowed. No translation is necessary. (ECL is returned to the most positive supply and this is common to all circuits) Mixed supply voltages are allowed. LVDS signal levels are power supply independent. 3.3 V LVDS oscillators properly interface 2.5 V Logic Arrays for example. Mar 2004 6A Pl tronics, Inc. (425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com |
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