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ISL55033
Data Sheet September 11, 2008 FN6346.0
400MHz Slew Rate Enhanced Rail-to-Rail Output Gain Block
The ISL55033 is a triple rail-to-rail output gain block with a -3dB bandwidth of 400MHz and slew rate of 2350V/s into a 150 load. The ISL55033 has a fixed gain of +2. The inputs are capable of sensing ground. The outputs are capable of swinging to 0.45V to either rail through a 150 resistor connected to V+/2. The ISL55033 is designed for general purpose video applications. The part includes a fast-acting global disable/power-down circuit. The ISL55033 is available in a 12 Ld TQFN package. Operation is specified over the -40C to +85C temperature range.
Features
* 400MHz -3dB Bandwidth * 2350V/sTyp Slew Rate, RL = 150 to V+/2 * Single-Supply Operation From +3V to +5.5V * Rail-to-Rail Output * Input Ground Sensing * Fast 25ns Disable Time * Pb-Free (RoHS compliant)
Applications
* Video Amplifiers * Set-Top Boxes * Video Distribution
Ordering Information
PART NUMBER ISL55033IRTZ ISL55033IRTZ-T13* ISL55033EVAL1Z PART MARKING 5033 5033 TEMP RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
Pinout
ISL55033 (12 LD TQFN) TOP VIEW
V+_OUTPUT 10
-40 to +85 12 LdTQFN L12.3x3A -40 to +85 12 LdTQFN L12.3x3A
EN 11 V+ 12
Coming Soon
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
-+
-+
IN+_1
1
9
OUTPUT_1
IN+_2
2
8
OUTPUT_2
-+
IN+_3
3
7
OUTPUT_3
4 GND_IN-(1,2,3)
5 GND_PWR
6 GND_OUTPUT
AV EACH CHANNEL EQUALS +2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL55033
Absolute Maximum Ratings (TA = +25C)
Supply Voltage from V+ to GND . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn-On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/s EN Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . V+ + 0.3V to GND - 0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2,500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1,500V
Thermal Information
Thermal Resistance (Note 1) JA (C/W) 12 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . . +57 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = 5V, TA = +25C, RL = 1k to V+/2, VIN = 0.1VDC, Unless Otherwise Specified. CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT
DESCRIPTION
INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN Output Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current Input Resistance Input Capacitance (Note 2) Measured from -40C to +85C VIN = 0V -8.5 -9 -1 -3 -6 7 0.5 9 mV V/C A M pF
OUTPUT CHARACTERISTICS ACL ROUT VOH Closed Loop Gain Output Resistance Positive Output Voltage Swing VOUT = 0.5V to 4V, RL = 150 AV = +2 RL = 1k to 2.5V RL = 150 to 2.5V VOL Negative Output Voltage Swing RL = 1k to 2.5V RL = 150 to 2.5V ISC (source) ISC (sink) Output Short Circuit Current Output Short Circuit Current RL = 10 to GND, VIN = 1.5V RL = 10 to + 2.5V, VIN = 0V 50 50 4.7 4.5 1.97 1.99 30 4.75 4.55 27 130 50 200 2.014 V/V m V V mV mV mA mA
POWER SUPPLY PSRR IS-ON IS-OFF ENABLE tEN tDS VIH-ENB VIL-ENB Enable Time Disable Time ENABLE Pin Voltage for Power-Up ENABLE Pin Voltage for Shut-Down RL = 150, VIN = 0.5V RL = 150, VIN = 0.5V 250 25 0.8 2 ns ns V V Power Supply Rejection Ratio Supply Current - Enabled V+ = 3V to 5.5V, RL = Open VIN = 0.1V, RL = Open 65 18.5 275 83 21.3 486 24.5 900 dB mA A
Supply Current - All Amplifiers Disabled RL = Open
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FN6346.0 September 11, 2008
ISL55033
Electrical Specifications
PARAMETER IIH-ENB IIL-ENB V+ = 5V, TA = +25C, RL = 1k to V+/2, VIN = 0.1VDC, Unless Otherwise Specified. (Continued) CONDITIONS VEN = 5V VEN = 0V MIN (Note 3) 1 -10 TYP 7 2 MAX (Note 3) 15 10 UNIT A A
DESCRIPTION ENABLE Pin Input Current High ENABLE Pin Input for Current Low
AC PERFORMANCE BW BW Peak dG dP eN-OUT iN ISO X-TALK PSRR -3dB Bandwidth 0.1dB Bandwidth Peaking Differential Gain Differential Phase Output Voltage Noise Density Input Current Noise Density Off-State Isolation fO = 10MHz Channel-to-Channel Crosstalk, fO = 10MHz Power Supply Rejection Ratio fO = 10MHz VOUT = 100mVP-P, RL = 150, CL = 2pF, VIN = 1.0 VDC VOUT = 100mVP-P, RL = 150, CL = 2pF VOUT = 100mVP-P, RL = 150, CL = 3.2pF VIN = 0.1V to 2.0V, VOUT = 100mVP-P, f = 3.58MHz, RL = 150 f = 10kHz f = 10kHz VIN = 0.8VDC + 1VP-P, CL = 2pF, RL = 150 VIN = 0.8VDC + 1VP-P, CL = 2pF, RL = 150 VIN = 0.2VDC, VSOURCE = 1VP-P, CL = 2pF, RL = 150 400 60 1.5 0.012 0.11 35 2.9 -80 -65 -55 MHz MHz dB % nV/Hz pA/Hz dB dB dB
TRANSIENT RESPONSE SR tr, tf Large Signal Slew Rate 25% to 75% Rise Time, tr 20% to 80% Fall Time, tf 80% to 20% Rise Time, tr 20% to 80% Fall Time, tf 80% to 20% tr, tf, Small Signal OS tPD tS NOTES: 2. VOS is extrapolated from 2 output voltage measurements, with VIN = 62.5mV and VIN = 125mV, RL = 1k. 3. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Rise Time, tr 20% to 80% Fall Time, tf 80% to 20% Overshoot Propagation Delay 0.1% Settling Time 100mV step 100mV step; RL = 150 2V step VOUT = 100mVP-P, RL = 150, CL = 2pF VOUT = 2VP-P, RL = 150, CL = 2pF RL = 150, VOUT = 0.5V to 3.5V VOUT = 3VP-P, RL = 150, CL = 2pF 2350 0.8 0.7 0.6 0.6 0.55 0.55 13 1 65 V/s ns ns ns ns ns ns % ns ns
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FN6346.0 September 11, 2008
ISL55033 Typical Performance Curves
3 2 NORMALIZED GAIN (dB) 1 0 -1 -2 -3 -4 -5 V+ = 5V AV = +2 CL = 2pF VOUT = 100mVP-P VIN(DC) = 0.1V 1M 10M FREQUENCY (Hz) RL = 150 RL = 100 RL = 1k NORMALIZED GAIN (dB) RL = 499 8 CL = 9.2pF 6 CL = 7.8pF 4 2 0 -2 -4 -6 100M 1G V+ = 5V AV = +2 RL = 150 VOUT = 100mVP-P VIN(DC) = 0.1V 1M CL = 3.2pF CL = 2.0pF CL = 5.7pF CL = 4.3pF
-6 100k
-8 100k
10M FREQUENCY (Hz)
100M
1G
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD
1 0 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 V+ = 5V AV = +2 RL = 150 CL = 2pF VIN(DC) = 0.1V 1M VOUT = 1.5VP-P VOUT = 0.1VP-P VOUT = 0.5VP-P VOUT = 1.0VP-P
4 2 0 -2 -4
VIN DC = 2.3V VIN DC = 2.2V VIN DC = 2.0V VIN DC = 1.0V VIN DC = 0.1V
-9 100k
100M 10M FREQUENCY (Hz)
1G
-6 V+ = 5V AV = +2 R = 150 to GND -8 L CL = 2pF VOUTP-P = 100mV -10 1M 100M 100k 10M FREQUENCY (Hz)
1G
FIGURE 3. -3dB BANDWIDTH vs VOUT
FIGURE 4. GAIN vs FREQUENCY vs DC INPUT VOLTAGE
7 6 ALL CHANNELS 5 GAIN (dB) 4 3 V+ = 5V 2 AV = +2 RL = 150 CL = 2pF 1V OUT = 100mVP-P VIN(DC) = 0.1V 0 1M 10k 100k NORMALIZED GAIN (dB)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 10M 100M 1G -0.8 10k V+ = 5V AV = +2 RL = 150 CL = 2pF VOUT = 100mVP-P VIN(DC) = 0.1V 100k 1M FREQUENCY (Hz) 10M 100M
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY - ALL CHANNELS
FIGURE 6. 0.1 dB GAIN FLATNESS
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ISL55033 Typical Performance Curves (Continued)
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 10k 100k 1M FREQUENCY (Hz) 10M 100M V+ = 5V AV = +2 RL = 150 CL = 2pF VSOURCE = 1VP-P ALL INPUTS = +0.2V DC 0 -20 OFF- ISOLATION (dB) -40 -60 -80 -100 -120 -140 10k V+ = 5V AV = +2 RL = 150 CL = 2pF VIN = 0.8VDC+1VP-P ALL INPUTS = +0.8VDC
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 7. PSRR vs FREQUENCY
FIGURE 8. OFF-ISOLATION vs FREQUENCY
0 -10 CROSSTALK (dB) -20 -30 -40 -50 -60 -70 -80 10k 100k 1M 10M 100M 1G V+ = 5V +2 AV = +4 RL = 150 2pF CL = 3pF CHANNEL) = 4VPVOUT (DRIVEN CHANNEL) = 2VP-P
P ALL INPUTS = +0.8V DC
10000 OUTPUT VOLTAGE NOISE (nV/Hz)
1000
100
10 1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. CHANNEL-TO-CHANNEL CROSSTALK vs FREQUENCY
FIGURE 10. OUTPUT VOLTAGE NOISE DENSITY vs FREQUENCY
1000 INPUT CURRENT NOISE (pA/Hz)
5.5 5.0 4.5 4.0 3.0 2.5 2.0 1.5 1.0 0.5 0 V+ = 5V AV = +2 RL = 150 CL = 2pF VIN = 0.5V DISABLE
1.8 1.5 1.2 0.9 0.6 0.3 0 2.0
10
ENABLE
1 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz)
-0.5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TIME (s)
FIGURE 11. INPUT CURRENT NOISE DENSITY vs FREQUENCY
FIGURE 12. ENABLE/DISABLE TIMING
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FN6346.0 September 11, 2008
OUTPUT (V)
ENABLE (V)
100
3.5
VOUT
ISL55033 Typical Performance Curves (Continued)
0.62 0.60 SMALL SIGNAL (V) SMALL SIGNAL (V) 0.58 0.56 0.54 0.52 0.50 0.48 V+ = 5V AV = +2 RL = 150 CL = 2.0pF VOUT = 100mVP-P 3.0 2.5 2.0 1.5 1.0 0.5 0
V+ = 5V AV = +2 RL = 150 CL = 2.0pF VOUT = 2VP-P
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
TIME (ns)
TIME (ns)
FIGURE 13. SMALL SIGNAL STEP RESPONSE
FIGURE 14. LARGE SIGNAL (2VP-P) STEP RESPONSE
4.0 3.5 LARGE SIGNAL (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 V+ = 5V AV = +2 RL = 150 CL = 2.0pF VOUT = 3VP-P NORMALIZED GAIN (dB)
0.014 0.012 0.010 0.008 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.008 -0.01 TIME (ns) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 INPUT DC OFFSET (V) V+ = 5V AV = +2 RL = 150 CL = 2pF F = 3.58MHz VOUT = 100mVP-P
FIGURE 15. LARGE SIGNAL (3VP-P) STEP RESPONSE
FIGURE 16. DIFFERENTIAL GAIN
0.1 0.05 NORMALIZED PHASE ()
1000 V+ = 5V AV = +2 CL = 2.0pF VIN = 1.25V DC VSOURCE = 1VP-P
-0.05 -0.10 -0.15 -0.20 -0.25 -0.3 0
V+ = 5V AV = +2 RL = 150 CL = 2pF F = 3.58MHz VOUT = 100mVP-P
ZOUT ENABLED ()
0
100
10
1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 INPUT DC OFFSET (V)
0.1 100k
1M
10M 100M FREQUENCY (Hz)
1G
FIGURE 17. DIFFERENTIAL PHASE
FIGURE 18. ZOUT (ENABLED) vs FREQUENCY
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FN6346.0 September 11, 2008
ISL55033 Typical Performance Curves (Continued)
10000 1M
100k ZOUT DISABLED () 1000 ZIN () 10k
100
V+ = 5V AV = +2 CL = 2.0pF VIN = 1.25V DC VSOURCE = 1VP-P
1k
100
V+ = 5V AV = +2 RL = 150 CL = 3.0pF VIN = 1.25V DC VSOURCE = 1VP-P 1M 10M FREQUENCY (Hz) 100M 1G
10 100k
1M
10M 100M FREQUENCY (Hz)
1G
10 100k
FIGURE 19. ZOUT (DISABLED) vs FREQUENCY
FIGURE 20. ZIN vs FREQUENCY
24 20 SUPPLY CURRENT (mA) 16 12 8 4 RL = Open 0 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 SUPPLY VOLTAGE (V) 5 5.4 5.8
FIGURE 21. SUPPLY CURRENT vs SUPPLY VOLTAGE
7.25 CURRENT PER AMPLIFIER (mA) 7.20 7.15 7.10 7.05 7.00 6.95 6.90 6.85 6.80 -40 -20 0 20 40 60 80 100 120 MIN MAX DISABLED CURRENT (A) SAMPLE SIZE = 100 VS = 5V RL = 1k MEDIAN
720 MAX 670 620 570 520 MEDIAN 470 420 370 -40 MIN SAMPLE SIZE = 100 VS = 5V RL = 1k
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 22. ENABLED SUPPLY CURRENT vs TEMPERATURE
FIGURE 23. DISABLED SUPPLY CURRENT vs TEMPERATURE
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FN6346.0 September 11, 2008
ISL55033 Typical Performance Curves (Continued)
7 6 5 4 VOS(mV) 3 2 1 0 -1 -2 -3 -40 -20 0 20 40 60 80 100 120 MIN -2 -3 -4 -40 MIN MEDIAN MAX 3 SAMPLE SIZE = 100 VS = 5V RL = 150 VOS (mV) 2 1 0 -1 MEDIAN SAMPLE SIZE = 100 VS = 5V RL = 1k 4 MAX
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 24. OUTPUT OFFSET VOLTAGE VOS vs TEMPERATURE
FIGURE 25. OUTPUT OFFSET VOLTAGE VOS vs TEMPERATURE
-4.5 SAMPLE SIZE = 100 VS = 5V -5.0 IBIAS + (A) MAX PSRR (dB) 115 MAX 105 SAMPLE SIZE = 100 VS = 3V to 5.5V
-5.5 MEDIAN -6.0 MIN -6.5
95
85 MEDIAN 75 MIN
-7.0 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120
65 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 26. IBIAS vs TEMPERATURE
FIGURE 27. PSRR vs TEMPERATURE
4.61 4.60 4.59 4.58
160 SAMPLE SIZE = 100 VS = 5V RL = 150 155 150 145 VOUT (m V) MAX MEDIAN 140 135 130 125 120 MIN -40 -20 0 20 40 60 80 100 120 115 110 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN MAX SAMPLE SIZE = 100 VS = 5V RL = 150
4.57 VOUT (V) 4.56 4.55 4.54 4.53 4.52 4.51 4.50 TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 28. VOUT HIGH vs TEMPERATURE
FIGURE 29. VOUT LOW vs TEMPERATURE
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ISL55033 Typical Performance Curves (Continued)
4.78 4.77 4.76 VOUT (V) 4.75 MEDIAN 4.74 MIN 4.73 4.72 -40 24 22 -40 SAMPLE SIZE = 100 VS = 5V RL = 1k VOUT (mV) MAX 34 32 30 28 26 MIN MEDIAN SAMPLE SIZE = 100 VS = 5V RL = 1k
MAX
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 30. VOUT HIGH vs TEMPERATURE
FIGURE 31. VOUT LOW vs TEMPERATURE
Pin Descriptions
ISL55033 12 LD TQFN 1 2 3 4 5 6 7 8 9 10 11 12 PIN NAME IN+_1 IN+_2 IN+_3 GND IN-(1, 2, 3) GND_PWR GND_OUTPUT OUTPUT_3 OUTPUT_2 OUTPUT_1 V+_OUTPUT EN V+
V+ IN+ dV/dt CLAMP GND_PWR CIRCUIT 1 -+ V+ SUBSTRATE GND_PWR (1,2,3) ~1M -+ 500 CIRCUIT 2 EN
EQUIVALENT CIRCUIT Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 4 Circuit 4 Circuit 3 Circuit 3 Circuit 3 Circuit 4 Circuit 2 Circuit 4 Amplifier 1 Non-inverting Input Amplifier 2 Non-inverting Input Amplifier 3 Non-inverting Input
DESCRIPTION
Common input for Amplifiers 1, 2, 3 Inverting Inputs Power Supply Ground Output Power Supply Ground Amplifier 3 Output Amplifier 2 Output Amplifier 1 Output Output Power Supply Enable pin internal pull-down: Logic "1" selects the disabled state; Logic "0" selects the enabled state Positive Power Supply
V+ V+_OUT(1, 2, 3) V+_OUT(4, 5, 6) OUT(1, 2, 3) OUT(4, 5, 6) GND_PWR GND_OUT(1, 2, 3) GND_OUT(4, 5, 6) CIRCUIT 3
-+
GND_IN-(1,2,3)
GND_PWR(1,2,3) CIRCUIT 4
500k
THERMAL HEAT SINK PAD CIRCUIT 5
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FN6346.0 September 11, 2008
ISL55033
DECOUPLING CAPACITORS V+ V+_OUT
EN
GND_OUT(1,2,3) -+ IN+_1 IN+_2 IN+_3 RIN 1 RIN 2 -+ RIN 3 GND_IN(1, 2, 3) OUT_1 ROUT 1 -+ OUT_2 ROUT 2 OUT_3 ROUT 3
FIGURE 32. BASIC APPLICATION CIRCUIT
Application Information
General
The ISL55033 single supply, fixed gain, triple amplifier is intended for use in a variety of video and other high speed applications. The device features a ground-sensing PNP input stage and a bipolar rail-to-rail output stage. The three amplifiers have an internally fixed gain of 2, and share a single enable pin as shown in Figure 32.
employed to ensure the maximum rates-of-rise is not exceeded.
Single Supply Input/Output Considerations
For best performance, the input signal voltage range should be maintained between 0.1V to 2.1V. These input limits correspond to an output voltage range of 0.2V to 4.2V and define the limits of linear operation. Figure 4 shows the frequency response versus the input DC voltage level. Figures 16 and 17 show the differential gain-phase performance over the input range of 0V to 2.4V operating into a 150 load. The 0.1V to 2.1V input levels corresponds to a 0.2V to 4.2V output levels, which define the minimum and maximum range of output linear operation. Composite video with sync requires care to ensure that the negative sync tip voltage (typically -300mV) is properly level-shifted up into the ISL55033 input linear operating region of +0.1V to 2.1V. The high input impedance enables AC coupling using low values of coupling capacitance with relatively high input voltage divider resistances.
Ground Connections
For the best isolation performance and crosstalk rejection, all GND pins must connect directly to the GND plane. In addition, the electrically conductive thermal pad must also connect directly to ground.
Power Considerations
Separate V+ power supply and GND pins for the input and output stages are provided to maximize PSRR. Providing separate power pins provides a way to prevent high speed transient currents in the output stage from bleeding into the sensitive amplifier input and gain stages. To maximize crosstalk isolation, each power supply pin should have its own de-coupling capacitors connected as close to the pin as possible as shown in Figure 30 (0.1F in parallel with 1nF recommended). The ESD protection circuits use internal diodes from all pins to the V+ and ground pins. In addition, a dV/dt-triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 in Figure 32. The dV/dt triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be
EN and Power-Down States
The EN pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the EN pin. The power-down state is established within approximately 25ns, if a logic high (>2V) is placed on the EN pin. In the power-down state, supply current is reduced significantly by shutting the three amplifiers off. The output presents a relatively high impedance (~2k) to the output pin. Multiplexing several outputs together is possible using the enable/disable function as long as the application can tolerate the limited power-down output impedance.
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FN6346.0 September 11, 2008
ISL55033
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 40mA. Adequate thermal heat sinking of the parts is also required. as possible and output termination resistors as close to the receiving device as possible. * When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * A minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible. Avoid vias between the capacitor and the device because vias add unwanted inductance. Larger capacitors can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components, such as chip resistors and chip capacitors, is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners. Use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless controlled impedance (50 or 75) strip lines or microstrips are used. * Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC decoupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Input termination resistors should be as close to the input terminal
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to power supply ground through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the power ground pins through the substrate, the thermal pad must be tied to the power supply ground to prevent unwanted current flow through the thermal pad. Maximum AC performance is achieved if the thermal pad has good contact to the IC ground pins. Heat sinking requirements can be satisfied using thermal vias directly beneath the thermal pad to a heat dissipating layer of a square at least 1" on a side.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6346.0 September 11, 2008
ISL55033
Package Outline Drawing
L12.3x3A
12 LEAD THIN QUAD FLAT NO LEAD PLASTIC PACKAGE Rev 0, 09/07
3.00 A B 10 0.5 BSC 12 6 PIN #1 INDEX AREA
6 PIN 1 INDEX AREA 9 4X 1.45 3.00 1
7 3 0.10 M C A B (4X) 0.15 6 12X 0 . 4 0 . 1 4 4 0.25 +0.05 / -0.07
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X" 0.10 C BASE PLANE 1.45 ) SEATING PLANE 0.08 C
0 . 75 ( 2 . 8 TYP )
C
SIDE VIEW
(
0.6
C
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. 0 . 50
NOTES:
0 . 25
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
12
FN6346.0 September 11, 2008

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