View ADP3118_4798660.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3118
FEATURES
Optimized for low gate charge MOSFETs All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float output per Intel VRM 10 Meets CPU VR requirement when used with Analog Devices, Inc. Flex-Mode1 controller
GENERAL DESCRIPTION
The ADP3118 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, which are the two switches in a nonisolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 25 ns propagation delay and a 25 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3118 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3118 is specified over the commercial temperature range of 0C to 85C and is available in 8-lead SOIC and 8-lead LFCSP packages.
APPLICATIONS
Multiphase desktop CPU supplies Single-supply synchronous buck converters
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
VIN 12V
VCC
D1
4 1
ADP3118
BST CBST2 CBST1 DRVH RG
IN 2
8
Q1 TO INDUCTOR
DELAY SW
RBST
7
CMP
VCC 6 DRVL
CMP 1V CONTROL LOGIC
5
Q2
Figure 1.
1
Flex-ModeTM is protected by U.S. Patent 6683441.
(c)2008 SCILLC. All rights reserved. January 2008 - Rev. 2
Publication Order Number: ADP3118/D
05452-001
OD 3
DELAY
6
PGND
ADP3118 TABLE OF CONTENTS
Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Simplified Functional Block Diagram............................................1 Revision History................................................................................2 Specifications .....................................................................................3 Absolute Maximum Ratings ............................................................4 ESD Caution ..................................................................................4 Pin Configuration and Function Descriptions .............................5 Timing Characteristics .....................................................................6 Typical Performance Characteristics..............................................7 Theory of Operation.........................................................................9 Low-Side Driver ............................................................................ 9 High-Side Driver........................................................................... 9 Overlap Protection Circuit .......................................................... 9 Application Information ................................................................10 Supply Capacitor Selection........................................................10 Bootstrap Circuit ........................................................................10 MOSFET Selection .....................................................................10 High-Side (Control) MOSFETs ................................................10 Low-Side (Synchronous) MOSFETs.........................................11 PC Board Layout Considerations .............................................11 Outline Dimensions........................................................................13 Ordering Guide ...........................................................................13
REVISION HISTORY
01/08 - Rev 2: Conversion to ON Semiconductor 9/07--Rev. 0 to Rev. A Added LFCSP...................................................................... Universal Updated Outline Dimensions........................................................13 Changes to Ordering Guide...........................................................13 4/05--Revision 0: Initial Version
Rev. 2 | Page 2 of 14 | www.onsemi.com
ADP3118 SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 0C to 85C, unless otherwise noted.1 Table 1.
Parameter PWM INPUT Input Voltage High Input Voltage Low Input Current Hysteresis OD INPUT Input Voltage High Input Voltage Low Input Current Hysteresis Propagation Delay Times2 Symbol Conditions Min 2.0 -1 90 2.0 -1 90 tpdlOD tpdhOD HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times2 SW Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times2 Timeout Delay SUPPLY Supply Voltage Range Supply Current UVLO Voltage Hysteresis
1 2
Typ
Max
Unit V V A mV V V A mV ns ns k ns ns ns ns k k ns ns ns ns ns ns V mA V mV
0.8 +1 250
0.8 +1 250 20 40 2.2 1.0 10 25 20 25 25 10 2.0 1.0 10 20 16 12 30 190 150 35 55 3.5 2.5 40 30 40 35
See Figure 3 See Figure 3 BST - SW = 12 V BST - SW = 12 V BST - SW = 0 V BST - SW = 12 V, CLOAD = 3 nF, see Figure 4 BST - SW = 12 V, CLOAD = 3 nF, see Figure 4 BST - SW = 12 V, CLOAD = 3 nF, see Figure 4 BST - SW = 12 V, CLOAD = 3 nF, see Figure 4 SW to PGND
trDRVH tfDRVH tpdhDRVH tpdlDRVH
3.2 2.5 35 30 35 45
trDRVL tfDRVL tpdhDRVL tpdlDRVL
VCC = PGND CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 SW = 5 V SW = PGND
110 95 4.15
VCC ISYS
BST = 12 V, IN = 0 V VCC rising
2 1.5 350
13.2 5 3.0
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low.
Rev. 2 | Page 3 of 14 | www.onsemi.com
ADP3118 ABSOLUTE MAXIMUM RATINGS
Unless otherwise specified, all voltages are referenced to PGND. Table 2.
Parameter VCC BST BST to SW SW DC <200 ns DRVH DC <200 ns DRVL DC <200 ns IN, OD JA, SOIC 2-Layer Board 4-Layer Board JA, LFCSP_VD1 4-Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Range Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec)
1
Rating -0.3 V to +15 V -0.3 V to VCC + 15 V -0.3 V to +15 V -5 V to +15 V -10 V to +25 V SW - 0.3 V to BST + 0.3 V SW - 2 V to BST + 0.3 V -0.3 V to VCC + 0.3 V -2 V to VCC + 0.3 V -0.3 V to 6.5 V 123C/W 90C/W 50C/W 0C to 85C 0C to 150C -65C to +150C 300C 215C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
For LFCSP_VD, JA is measured per JEDEC STD with the exposed pad soldered to PCB.
Rev. 2 | Page 4 of 14 | www.onsemi.com
ADP3118 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BST 1 IN 2 OD 3
8
DRVH SW
05452-002
ADP3118
7
6 PGND TOP VIEW VCC 4 (Not to Scale) 5 DRVL
Figure 2. 8-Lead SOIC Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 Mnemonic BST IN OD VCC DRVL PGND SW Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with an ~1 F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. This pin is connected to the buck-switching node, close to the upper MOSFET's source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V. Buck Drive. Output drive for the upper (buck) MOSFET.
8
DRVH
Rev. 2 | Page 5 of 14 | www.onsemi.com
ADP3118 TIMING CHARACTERISTICS
OD
tpdlOD
tpdhOD
90% 10%
05452-004
DRVH OR DRVL
Figure 3. Output Disable Timing Diagram
IN tpdlDRVL DRVL tfDRVL tpdlDRVH trDRVL
tfDRVH tpdhDRVH trDRVH
DRVH - SW
VTH
VTH
tpdhDRVL SW 1V
05452-005
Figure 4. Timing Diagram--Timing Is Referenced to the 90% and 10% Points, Unless Otherwise Noted
Rev. 2 | Page 6 of 14 | www.onsemi.com
ADP3118 TYPICAL PERFORMANCE CHARACTERISTICS
24
IN
VCC = 12V CLOAD = 3nF 22
DRVH
FALL TIME (ns)
20
DRVL
18 DRVL 16
05452-006
14
0
25
50
75
100
125
JUNCTION TEMPERATURE (C)
Figure 5. DRVH Rise and DRVL Fall Times CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 8. DRVH and DRVL Fall Times vs. Temperature
40 35 30 TA = 25C VCC = 12V DRVH
IN
RISE TIME (ns)
25 20 15 10 5 2.0
DRVL
DRVL
05452-007
2.5
3.0
3.5
4.0
4.5
5.0
LOAD CAPACITANCE (nF)
Figure 6. DRVH Fall and DRVL Rise Times CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance
35 VCC = 12V CLOAD = 3nF
35 VCC = 12V TA = 25C 30 DRVH
30
DRVH
FALL TIME (ns)
RISE TIME (ns)
25 DRVL
25 DRVL 20
20
15
10
05452-008 05452-011
15
0
25
50
75
100
125
5 2.0
2.5
3.0
3.5
4.0
4.5
5.0
JUNCTION TEMPERATURE (C)
LOAD CAPACITANCE (nF)
Figure 7. DRVH and DRVL Rise Times vs. Temperature
Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance
Rev. 2 | Page 7 of 14 | www.onsemi.com
05452-010
DRVH
05452-009
DRVH
ADP3118
60 TA= 25C VCC = 12V CLOAD = 3nF
12 11 10
DRVL OUTPUT VOLTAGE (V)
TA = 25C CLOAD = 3nF
SUPPLY CURRENT, ICC (mA)
45
9 8 7 6 5 4 3 2
05452-014
30
15
05452-012
1 0 0 1 2 3 4 5 6 7 8 9 10 11 12
0
0
200
400
600
800
1000
1200
1400
FREQUENCY (kHz)
VCC VOLTAGE (V)
Figure 11. Supply Current vs. Frequency
Figure 13. DRVL Output Voltage vs. Supply Voltage
13 VCC = 12V CLOAD = 3nF fIN = 250kHz
SUPPLY CURRENT, ICC (mA)
12
11
10
05452-013
9
0
25
50
75
100
125
JUNCTION TEMPERATURE (C)
Figure 12. Supply Current vs. Temperature
Rev. 2 | Page 8 of 14 | www.onsemi.com
ADP3118 THEORY OF OPERATION
The ADP3118 is a dual-MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A more detailed description of the ADP3118 and its features follows (see Figure 1 for a block diagram). To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. The high-side driver's output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn-off to the Q2 turn-on, and by internally setting the delay from the Q2 turn-off to the Q1 turn-on. To prevent the overlap of the gate drives during the Q1 turn-off and the Q2 turn-on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 begins to turn off (after propagation delay). Before Q2 can turn on, the overlap protection circuit makes sure that SW has first gone high and then waits for the voltage at the SW pin to fall from VIN to 1 V. Once the voltage on the SW pin falls to 1 V, Q2 begins turn-on. If the SW pin has not gone high first, the Q2 turn-on is delayed by a fixed 150 ns. By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. If SW does not go below 1 V after 190 ns, DRVL turns on. This can occur if the current flowing in the output inductor is negative and is flowing through the high-side MOSFET body diode.
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground-referenced N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver's output is 180 out of phase with the PWM input. When the ADP3118 is disabled, the low-side gate is held low.
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST1. CBST2 and RBST are included to reduce the high-side gate drive voltage and to limit the switch node slew rate (referred to as a Boot-Snap circuit, see the Application Information section for more details). When the ADP3118 is starting up, the SW pin is at ground, so the bootstrap capacitor charges up to VCC through D1. When the PWM input goes high, the high-side driver begins to turn on the high-side MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1 turns on, the SW pin rises up to VIN, forcing the BST pin to VIN + VC (BST), which is enough gate-to-source voltage to hold Q1 on.
Rev. 2 | Page 9 of 14 | www.onsemi.com
ADP3118 APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3118, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 4.7 F, low ESR capacitor. Multilayer ceramic chip capacitors (MLCC) provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3118.
A small-signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage. The average forward current can be estimated by
IF(AVG) = QGATE x fMAX
(3)
where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be calculated using
I F ( PEAK ) = VCC - V D R BST
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST) and a diode, as shown in Figure 1. These components can be selected after the high-side MOSFET is chosen. The bootstrap capacitor must have a voltage rating that can handle twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitor values are determined by: Q C BST1 + C BST2 = 10 x GATE (1) VGATE
(4)
MOSFET SELECTION
When interfacing the ADP3118 to external MOSFETs, there are a few considerations that the designer should be aware of. These help to make a more robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short-time duration voltage ratings on the driver pins as well as the external MOSFET. It is also highly recommended to use a Boot-Snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs. If a simple bootstrap arrangement is used, make sure to include a proper snubber network on the SW node.
C BST1 C BST1 + C BST2
=
VGATE VCC - VD
(2)
where: QGATE is the total gate charge of the high-side MOSFET at VGATE. VGATE is the desired gate drive voltage (usually in the range of 5 V to 10 V, 7 V being typical). VD is the voltage drop across D1. Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
C BST1 = 10 x Q GATE VCC - V D Q GATE VGATE
HIGH-SIDE (CONTROL) MOSFETS
The high-side MOSFET is usually selected to be high speed to minimize switching losses (see the ADP3186 or ADP3188 data sheet for controller details). This usually implies a low gate resistance and low input capacitance/charge device. Yet, a significant source lead inductance can also exist. This depends mainly on the MOSFET package; it is best to contact the MOSFET vendor for this information. The ADP3118 DRVH output impedance and the input resistance of the MOSFETs determine the rate of charge delivery to the gate's internal capacitance. This determines the speed at which the MOSFETs turn on and off. However, due to potentially large currents flowing in the MOSFETs at the on and off times (this current is usually larger at turn off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high-side MOSFETs switch off. This creates a significant drain-source voltage spike across the internal die of the MOSFETs and can lead to a catastrophic avalanche. The mechanisms involved in this avalanche condition can be referenced in literature from the MOSFET suppliers.
CBST2 can then be found by rearranging Equation 1.
C BST2 = 10 x
- C BST1
For example, an NTD60N02 has a total gate charge of about 12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, one finds CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors should be used. RBST is used for slew-rate limiting to minimize the ringing at the switch node. It also provides peak current limiting through D1. An RBST value of 1.5 to 2.2 is a good choice. The resistor needs to be able to handle at least 250 mW due to the peak currents that flow through it.
Rev. 2 | Page 10 of 14 | www.onsemi.com
ADP3118
The MOSFET vendor should provide a maximum voltage slew rate at a drain current rating such that this can be designed around. Once the designer has this specification, determine the maximum current you expect to see in the MOSFET. This can be done with the following equation:
I MAX = I DC ( per phase ) + (VCC - VOUT ) x D MAX f MAX x L OUT
(5)
the proper switching time, so the state of the DRVL pin is monitored to go below one sixth of VCC. A delay is then added. Due to the Miller capacitance and internal delays of the lowside MOSFET gate, one must ensure that the Miller-to-input capacitance ratio is low enough and that the low-side MOSFET internal delays are not so large as to allow accidental turn on of the low-side when the high-side turns on. Contact sales for an updated list of recommended low-side MOSFETs.
where: DMAX is determined for the VR controller being used with the driver. This current is divided as equally as possible between MOSFETs if more than one is used (assume a worst-case mismatch of 30% for design margin). LOUT is the output inductor value. When producing a design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external MOSFETs as well as the PCB. However, it can be measured to determine if it is safe. If it appears that the dV/dt is too fast, an optional gate resistor can be added between DRVH and the high-side MOSFETs. This resistor slows down the dV/dt, but it increases the switching losses in the high-side MOSFETs. The ADP3118 has been optimally designed with an internal drive impedance that works with most MOSFETs to switch them efficiently yet minimizes dV/dt. However, some high speed MOSFETs may require this external gate resistor depending on the currents being switched in the MOSFET.
PC BOARD LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed circuit boards.
* * * * *
Trace out the high current paths and use short, wide (>20 mil) traces to make these connections. Minimize trace inductance between DRVH and DRVL outputs and MOSFET gates. Connect the PGND pin of the ADP3118 as closely as possible to the source of the lower MOSFET. Locate the VCC bypass capacitor as close as possible to the VCC and PGND pins. Use vias to other layers when possible to maximize thermal conduction away from the IC.
LOW-SIDE (SYNCHRONOUS) MOSFETS
The low-side MOSFETs are usually selected to have a low on resistance to minimize conduction losses. This usually implies a large input gate capacitance and gate charge. The first concern is to make sure the power delivery from the ADP3118's DRVL does not exceed the thermal rating of the driver (see the ADP3186 or ADP3188 data sheet for controller details). The next concern for the low-side MOSFETs is based on preventing them from inadvertently being switched on when the high-side MOSFET turns on. This occurs due to the draingate (Miller, also specified as Crss) capacitance of the MOSFET. When the drain of the low-side MOSFET is switched to VCC by the high-side turning on (at a rate of dV/dt), the internal gate of the low-side MOSFET is pulled up by an amount roughly equal to VCC x (Crss/Ciss). It is important to make sure this does not put the MOSFET into conduction. Another consideration is the nonoverlap circuitry of the ADP3118, which attempts to minimize the nonoverlap period. During the state of the high-side turning off to low-side turning on, the SW pin is monitored (as well as the conditions of SW prior to switching) to adequately prevent overlap. However, during the low-side turn off to high-side turn on, the SW pin does not contain information for determining
The circuit in Figure 15 shows how four drivers can be combined with the ADP3188 to form a total power conversion solution for generating VCC (CORE) for an Intel(R) CPU that is VRD 10.x-compliant. Figure 14 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the Layout and Component Placement section of the ADP3188 data sheet.
CBST1
CBST2
RBST
D1
CVCC
Figure 14. External Component Placement Example
Rev. 2 | Page 11 of 14 | www.onsemi.com
05452-015
ADP3118
VIN 12V C7 4.7F D2 1N4148
1 2 3
L1 370nH 18A R3 2.2 C8 12nF
2700F/16V/3.3A x 2 SANYO MV-WX SERIES
VIN RTN BST IN OD PGND 6 DRVL 5 C24 Q3 NTD110N02 Q4 NTD110N02 + C31 VCC SW 7 DRVH 8 Q1 NTD60N02 560F/4V x 8 L2 320nH/1.4m SANYO SEPC SERIES 5m EACH +
+ C1
+ C2
U2 ADP3118
C6 6.8nF
VCC (CORE) 0.8375V - 1.6V 95A TDC, 119A PK VCC (CORE) RTN
C5 4.7F R4 2.2 C11 4.7F Q5 NTD60N02 C12 12nF
4
D1 1N4148
1 2 3
D3 1N4148 BST IN OD PGND 6 DRVL 5 Q8 NTD110N02 VCC SW 7 DRVH 8
U3 ADP3118
C10 6.8nF
10F x 18 MLCC IN SOCKET
R1 10 C9 4.7F R5 2.2 C16 12nF
4
L3 320nH/1.4m
C3 100F R2 357k, 1%
1 2 3 1 4 5 6 7 8 9 10 PWRGD
+
Q7 NTD110N02
C4 1F
U1 ADP3188
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23
4
VID4 VID3 VID2 VID1 VID0 VID5 FBRTN SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 CSREF 16 C22 1nF 560pF 1.5nF 35.7k 84.5k CCS1 CCS2 RCS2 RCS1 RPH4 158k, 1% RPH2 RPH3 158k, RPH1 1% 158k, 158k, 1% 1% RSW41 RSW31 FB COMP C13 4.7F RSW21
3
D4 1N4148 BST IN OD VCC
1 2
U4 ADP3118
DRVH 8 SW 7 PGND 6 DRVL 5
C14 6.8nF
C15 4.7F Q9 NTD60N02
FROM CPU RSW1
L4 320nH/1.4m
CB
Figure 15. VRD 10-Compliant Power Supply Circuit
R6 2.2 C20 12nF Q11 NTD110N02
11 EN 12 DELAY 13 RT 14 RAMPADJ ILIMIT 15
Rev. 2 | Page 12 of 14 | www.onsemi.com
D5 1N4148
1 2 3
C211 1nF
470pF
CFB
Q12 NTD110N02
POWER GOOD
ENABLE
CA RB RA 1.21k 470pF 12.1k
22pF
CLDY 39nF
RLDY 470k
U5 ADP3118
BST IN OD
4
C16 6.8nF
DRVH 8 SW 7 PGND
6
C19 4.7F Q13 NTD60N02
RT 137k, 1%
L5 320nH/1.4m VCC DRVL 5 RTH1 100k, 5% NTC
C23 1nF
RLIM 150k, 1%
C17 4.7F
Q15 NTD110N02
Q16 NTD110N02
05452-016
NOTE: 1. FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE ADP3188 THEORY OF OPERATION SECTION.
ADP3118 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 16. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters (inches)
3.25 3.00 SQ 2.75
0.60 MAX 0.60 MAX
5 8
0.50 BSC
PIN 1 INDICATOR
TOP VIEW
2.95 2.75 SQ 2.55
(BOTTOM VIEW)
EXPOSED PAD
1
1.60 1.45 1.30 PIN 1 INDICATOR
4
0.90 MAX 0.85 NOM SEATING PLANE
12 MAX
0.70 MAX 0.65 TYP
0.50 0.40 0.30 0.05 MAX 0.01 NOM
1.89 1.74 1.59
Figure 17. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP3118JRZ1 ADP3118JRZ-RL1 ADP3118JCPZ-RL1
1
Temperature Range 0C to 85C 0C to 85C 0C to 85C
061507-B
0.30 0.23 0.18
0.20 REF
012407-A
Package Description 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
Package Option R-8 R-8 CP-8-2
Ordering Quantity 98 2,500 2,500
Z = RoHS Compliant Part.
Rev. 2 | Page 13 of 14 | www.onsemi.com
ADP3118
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any ON Semiconductor and products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
Rev. 2 | Page 14 of 14 | www.onsemi.com

▲Up To Search▲

Price & Availability of ADP3118

	To Download ADP3118 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .